PMC PM7351-BI Datasheet

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PMC-1980582 ISSUE 5 OCTAL SERIAL LINK MULTIPLEXER

PM7351 S/UNI-VORTEX

PM7351

S/UNI

VORTE

S/UNI-VORTEX

OCTAL SERIAL LINK MULTIPLEXER

DATA SHEET

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ISSUE 5: MARCH 2000

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REVISION HISTORY

Issue No. Issue Date Details of Change

Issue 5 March 2000 Changes marked with side bars.

Incorporated errata items and updated data sheet for Production Release.

Updated A.C. Timing Characteristics tH

RCLK

and tH

TCLK

and V

ODM

Issue 4 January

2000

Updated D.C. Characteristics R

Changes marked with side bars.

Matches functionality of PM7351 Rev B

Issue 3 June 1999 Changed the confidentiality notices for the

document’s public release.

Issue 2 April 1999 Changes in all areas from Issue 1.

Matches functionality of product PM7351-BI, Rev A

Issue 1 May ,1998 Preliminary Document

in.

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1 FEATURES .............................................................................................. 1

2 APPLICATIONS ....................................................................................... 3

3 REFERENCES......................................................................................... 4

4 APPLICATION EXAMPLES ..................................................................... 5

5 BLOCK DIAGRAM ................................................................................... 9

6 DESCRIPTION ...................................................................................... 10

7 PIN DIAGRAM ....................................................................................... 12

8 PIN DESCRIPTION................................................................................ 13

9 FUNCTIONAL DESCRIPTION............................................................... 29

9.1 CELL INTERFACE ...................................................................... 29

9.2 HIGH-SPEED SERIAL INTERFACES......................................... 34

9.3 CELL BUFFERING AND FLOW CONTROL ............................... 43

9.4 TIMING REFERENCE INSERTION AND RECOVERY ............... 46

9.5 JTAG TEST ACCESS PORT....................................................... 47

9.6 MICROPROCESSOR INTERFACE ............................................ 47

9.7 INTERNAL REGISTERS............................................................. 51

9.8 REGISTER MEMORY MAP ........................................................ 51

10 NORMAL MODE REGISTER DESCRIPTION ....................................... 55

11 TEST FEATURES DESCRIPTION .......................................................117

11.1 RAM BUILT-IN-SELF-TEST ...................................................... 120

11.2 JTAG TEST PORT .................................................................... 122

12 OPERATION ........................................................................................ 127

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12.1 DETERMINING THE VALUE FOR FREADY[5:0]...................... 127

12.2 INTERACTION BETWEEN BUS AND LVDS CONFIGURATIONS

.................................................................................................. 130

12.3 MINIMUM PROGRAMMING ..................................................... 134

12.4 JTAG SUPPORT ....................................................................... 135

12.5 MICROPROCESSOR INBAND COMMUNICATION ................. 141

13 FUNCTIONAL TIMING......................................................................... 144

14 ABSOLUTE MAXIMUM RATINGS....................................................... 147

15 D.C. CHARACTERISTICS................................................................... 148

16 MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS..... 152

17 A.C. TIMING CHARACTERISTICS...................................................... 156

18 ORDERING AND THERMAL INFORMATION...................................... 162

19 MECHANICAL INFORMATION ............................................................ 163

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LIST OF REGISTERS

METERS ................................................................................................ 56

............................................................................................................... 69

............................................................................................................... 70

INTERRUPT STATUS............................................................................ 71

CONTROL AND STATUS....................................................................... 73

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REGISTERS 0X080, 0X0A0, 0X0C0, 0X0E0, 0X100, 0X120, 0X140, 0X160:

RECEIVE HIGH SPEED SERIAL CONFIGURATION............................ 86

REGISTERS 0X081, 0X0A1, 0X0C1, 0X0E1, 0X101, 0X121, 0X141, 0X161:

RECEIVE HIGH-SPEED SERIAL CELL FILTERING

CONFIGURATION/STATUS................................................................... 88

REGISTERS 0X082, 0X0A2, 0X0C2, 0X0E2, 0X102, 0X122, 0X142, 0X162:

RECEIVE HIGH-SPEED SERIAL INTERRUPT ENABLES ................... 90

REGISTERS 0X083, 0X0A3, 0X0C3, 0X0E3, 0X103, 0X123, 0X143, 0X163:

RECEIVE HIGH-SPEED SERIAL INTERRUPT STATUS ...................... 92

RECEIVE HIGH-SPEED SERIAL HCS ERROR COUNT ...................... 94

REGISTERS 0X085, 0X0A5, 0X0C5, 0X0E5, 0X105, 0X125, 0X145, 0X165:

RECEIVE HIGH-SPEED SERIAL CELL COUNTER (LSB).................... 95

REGISTERS 0X086, 0X0A6, 0X0C6, 0X0E6, 0X106, 0X126, 0X146, 0X166:

RECEIVE HIGH-SPEED SERIAL CELL COUNTER .............................. 95

REGISTERS 0X087, 0X0A7, 0X0C7, 0X0E7, 0X107, 0X127, 0X147, 0X167:

RECEIVE HIGH-SPEED SERIAL CELL COUNTER (MSB)................... 96

REGISTERS 0X088, 0X0A8, 0X0C8, 0X0E8, 0X108, 0X128, 0X148, 0X168:

RECEIVE HIGH-SPEED SERIAL FIFO OVERFLOW............................ 97

REGISTERS 0X089, 0X0A9, 0X0C9, 0X0E9, 0X109, 0X129, 0X149, 0X169:

UPSTREAM ROUND ROBIN WEIGHT ................................................. 98

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REGISTERS 0X08A, 0X0AA, 0X0CA, 0X0EA, 0X10A, 0X12A, 0X14A, 0X16A:

LOGICAL CHANNEL BASE ADDRESS................................................. 99

LOGICAL CHANNEL ADDRESS RANGE / LOGICAL CHANNEL BASE

ADDRESS MSB................................................................................... 100

REGISTERS 0X08C, 0X0AC, 0X0CC, 0X0EC, 0X10C, 0X12C, 0X14C, 0X16C:

DOWNSTREAM LOGICAL CHANNEL FIFO CONTROL..................... 101

DOWNSTREAM LOGICAL CHANNEL FIFO INTERRUPT STATUS... 102

REGISTERS 0X08F, 0X0AF, 0X0CF, 0X0EF, 0X10F, 0X12F, 0X14F, 0X16F:

DOWNSTREAM LOGICAL CHANNEL FIFO READY LEVEL.............. 103

REGISTERS 0X090, 0X0B0, 0X0D0, 0X0F0, 0X110, 0X130, 0X150, 0X170:

TRANSMIT HIGH-SPEED SERIAL CONFIGURATION ....................... 104

REGISTERS 0X091, 0X0B1, 0X0D1, 0X0F1, 0X111, 0X131, 0X151, 0X171:

TRANSMIT HIGH-SPEED SERIAL CELL COUNT STATUS................ 106

REGISTERS 0X092, 0X0B2, 0X0D2, 0X0F2, 0X112, 0X132, 0X152, 0X172:

TRANSMIT HIGH-SPEED SERIAL CELL COUNTER (LSB) ............... 107

REGISTERS 0X093, 0X0B3, 0X0D3, 0X0F3, 0X113, 0X133, 0X153, 0X173:

TRANSMIT HIGH-SPEED SERIAL CELL COUNTER ......................... 107

TRANSMIT HIGH-SPEED SERIAL CELL COUNTER (MSB) .............. 108

REGISTERS 0X095, 0X0B5, 0X0D5, 0X0F5, 0X115, 0X135, 0X155, 0X175:

SERIAL LINK MAINTENANCE ............................................................ 109

REGISTERS 0X097, 0X0B7, 0X0D7, 0X0F7, 0X117, 0X137, 0X157, 0X177:

TRANSMIT BIT ORIENTED CODE ...................................................... 111

REGISTERS 0X098, 0X0B8, 0X0D8, 0X0F8, 0X118, 0X138, 0X158, 0X178: BIT

ORIENTED CODE RECEIVER ENABLE..............................................112

RECEIVE BIT ORIENTED CODE STATUS ..........................................113

REGISTERS 0X09C, 0X0BC, 0X0DC, 0X0FC, 0X11C, 0X13C, 0X15C, 0X17C:

UPSTREAM LINK FIFO CONTROL .....................................................114

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LIST OF FIGURES

FIG. 1 TYPICAL TARGET APPLICATION ........................................................... 5

FIG. 2 THREE STAGE MULTIPLEX ARCHITECTURE....................................... 7

FIG. 3 SCI-PHY/ANY-PHY CELL FORMAT....................................................... 32

FIG. 4 HIGH-SPEED SERIAL LINK DATA STRUCTURE ................................. 34

FIG. 5 LOOPBACKS ......................................................................................... 38

FIG. 6: CELL DELINEATION STATE DIAGRAM............................................... 42

FIG. 7 MICROPROCESSOR CELL FORMAT................................................... 50

FIG. 8 BOUNDARY SCAN ARCHITECTURE ................................................. 136

FIG. 9 TAP CONTROLLER FINITE STATE MACHINE ................................... 138

FIG. 10 UPSTREAM SCI-PHY INTERFACE TIMING ..................................... 144

FIG. 11 UPSTREAM ANY-PHY INTERFACE TIMING..................................... 145

FIG. 12 DOWNSTREAM ANY-PHY INTERFACE POLLING TIMING ............. 146

FIG. 13 DOWNSTREAM ANY-PHY INTERFACE TRANSFER TIMING.......... 146

FIG. 14 MICROPROCESSOR INTERFACE READ TIMING ........................... 153

FIG. 15 MICROPROCESSOR INTERFACE WRITE TIMING ......................... 155

FIG. 16 RSTB TIMING .................................................................................... 156

FIG. 17 RECEIVE SCI-PHY/ANY-PHY INTERFACE TIMING......................... 157

FIG. 18 TRANSMIT SCI-PHY INTERFACE TIMING....................................... 158

FIG. 19 JTAG PORT INTERFACE TIMING ..................................................... 160

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LIST OF TABLES

TABLE 1 SCI-PHY AND ANY-PHY COMPARISON .......................................... 33

TABLE 2 PREPENDED FIELDS....................................................................... 34

TABLE 3 : ASSIGNED BIT ORIENTED CODES .............................................. 41

TABLE 4: BOUNDARY SCAN REGISTER ..................................................... 123

TABLE 5 FROM NEAR-END DOWNSTREAM BUS TO FAR-END UPSTREAM BUS 131

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1 FEATURES

• Integrated analog/digital device that interfaces a high speed parallel bus to 8 bidirectional data streams, each transported over a high speed Low Voltage Differential Signal (LVDS) serial link.

• Works with its sister device, the S/UNI-DUPLEX, to satisfy a full set of system level requirements for backplane interconnect:

• Transports user data by providing the inter-card data-path.

• Inter-processor communication by providing an integrated inter-card

control channel.

• Exchanges flow control information (back-pressure) to prevent data loss.

• Provides embedded command and control signals across the backplane: system reset, error indications, protection switching commands, etc.

• Clock/timing distribution (system clocks as well as reference clocks such as 8 kHz timing references).

• Fault detection, redundancy, protection switching, and inserting/removing cards while the system is running (hot swap).

• Each S/UNI-VORTEX Interfaces to 8 S/UNI-DUPLEX devices (via the LVDS links) to create a point-to-multipoint serial backplane architecture.

• Up to 16 S/UNI-VORTEX devices (interfacing to a maximum of 128 S/UNIDUPLEXs) can reside on a single system bus.

• In the LVDS receive direction: accepts cell streams from the 8 LVDS links, multiplexing them into a single cell stream which is presented to the system bus as a single Utopia L2 compatible PHY.

• In the LVDS transmit direction: receives cell streams from the bus master, and routes the cells to the appropriate serial link.

• Cell read/write to the 8 LVDS links is available via the microprocessor port. Provides optional hardware assisted CRC32 calculation across cells to create an embedded inter-processor communication channel across the LVDS links.

• Optionally routes the embedded control channels from the 8 link's to/ from the system bus.

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• Under software control, the 8 LVDS links can be individually marked active or standby. This is used by the far end S/UNI-DUPLEXs to implement 1:1 protected systems.

• Error monitoring and cell counting on all links.

• Requires no external memories.

• Low power 3.3V CMOS technology.

• Standard 5 pin P1149 JTAG port.

• 304 ball SBGA, 31mm x 31mm.

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2 APPLICATIONS

• Single shelf or multi-shelf Digital Subscriber Loop Access Multiplexer (DSLAM).

• ATM, frame relay, IP switch.

• Multiservice access multiplexer.

• Universal Mobile Telecommunication System (UMTS) wireless base stations.

• UMTS wireless base station controllers.

• Multi-shelf access concentrators.

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3 REFERENCES

• PMC-Sierra; “Saturn Compatible Interface For ATM PHY Layer And ATM Layer Devices, Level 2”; PMC-940212; Dec. 8, 1995

• PMC-Sierra; “Saturn Interface Specification And Interoperability Framework For Packet And Cell Transfer Between Physical Layer And Link Layer Devices”, PMC-980902, Draft

• ATM Forum, “Universal Test & Operations PHY Interface for ATM (UTOPIA), Level 2”, Version 1.0, af-phy-0039.000, June 1995

• ITU-T Recommendation I.432.1, “B-ISDN user-network interface – Physical layer specification: General characteristics”, 08/96

• American National Standard for Telecommunications, “Network and Customer Installation Interfaces – Asymmetric Digital Subscriber Line (ADSL) Metallic Interface”, ANSI T1.413-1998, November, 1998

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4 APPLICATION EXAMPLES

When designing communication equipment such as access switches, multiplexers, wireless base stations, and base station controllers the equipment architect is faced with a common problem: how do I efficiently connect a large number of lower speed ports to a small number of high speed ports? Typically, a number of line-side ports (analog modems, xDSL modems ATM PHYs, or RF modems) are terminated on each line card. Numerous line cards are then slotted into one or more shelves and backplane traces or inter-shelf cables are used to connect the line cards to a centralized (often 1:1 protected) common card, hereafter referred to as the core card. The core card normally includes one or more high speed WAN up-link ports that transport traffic to and from a high speed broadband network.

A block diagram of a 1:1 redundant system is shown in Fig. 1.

Fig. 1 Typical Target Application

Modem or PHY

Modem

or PHY

Modem

or PHY

Modem

or PHY

Line Card #1

S/UNI-

DUPLEX

Line Card #N

S/UNI-

DUPLEX

S/UNI-

VORTEX

WAN Card

S/UNI-

VORTEX

WAN Card

Policing

OA&M

Policing

OA&M

Buffering

Discard

Scheduling

Buffering

Discard

Scheduling

OA&M

WAN

up-link

WAN

up-link

In this type of equipment the majority (perhaps all) user traffic goes from WAN port to line port, or from line port to WAN port. Although the individual ports on the line cards are often relatively low speed interfaces such as T1, E1, or xDSL, there may be many ports per line card and many line cards per system, resulting in hundreds or even thousands of lines terminating on a single WAN up-link. In the upstream direction (from line card to WAN up-link), the equipment must have capacity to buffer and intelligently manage bursts of upstream traffic simultaneously from numerous line cards.

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In the downstream direction the equipment must handle a similar issue, the “big pipe feeding little pipe” problem. When a large burst of traffic destined for a single line port is received at the high speed WAN port it must be buffered and managed as it queues up waiting for the much lower speed line port to clear.

The line cards are always the most numerous cards in this type of equipment. An individual line card, even if it terminates a few dozen low speed ports, does not generate or receive enough traffic to justify putting complex buffering and traffic management devices on it. The ideal architecture has low cost “dumb” line cards and a feature rich, “smart” core card. In order to enhance fault tolerance, the architecture should also inherently support 1:1 protection using a redundant core card and WAN up-link without significantly increasing line card complexity.

A system architecture that keeps buffering and traffic management off the line card will typically exhibit the following features:

1. Connection setup is simpler both in terms of programming and during execution because there is minimal or no requirement for line card intervention during the connection setup process.

2. In-service feature upgrades are simpler because feature complexity is limited to the common equipment.

3. Component costs are reduced, while system reliability increases due to reduced component count.

In this type of architecture there are often three stages of signal concentration or multiplexing, as shown in Fig. 2.

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Fig. 2 Three Stage Multiplex Architecture

Modem

Line Card #1

S/UNI-

DUPLEX

Line Card #2

S/UNI-

DUPLEX

Line Card #N

S/UNI-

DUPLEX

Stage 1 Stage 2 Stage 3

S/UNI-

VORTEX

S/UNI-

VORTEX

Policing

OA&M

Buffering

Discard

Scheduling

OA&M

WAN Card

WAN

up-link

The first stage resides on the line card and spans only those ports physically terminated by that card. Since it is confined to a single card, this first stage of multiplexing readily lends itself to a simple parallel bus based multiplex topology. The second stage of concentration occurs between the core card(s) and the line cards, including line cards that are on a separate shelf. This second stage is best served by a redundant serial point-to-point technology. The third stage of multiplexing is optional and resides on the core card. This third stage is used in systems with a large number of line cards that require several S/UNI-VORTEX devices to terminate the second stage of aggregation. Since the third stage of aggregation is confined to the core card, it lends itself readily to a parallel bus implementation. This three stage approach is implemented directly by the S/UNI-VORTEX and its sister device, the S/UNI-DUPLEX.

The S/UNI-DUPLEX acts as the line card’s bus master. It implements the first stage of multiplexing by routing traffic from the PHYs and transmitting the traffic simultaneously over two high speed (up to 200 Mbps) serial 4-wire LVDS links. One serial link attaches to the active core card, the other to the standby core

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card.1 In the downstream direction the S/UNI-DUPLEX demultiplexes traffic from the active core card’s LVDS serial link and routes this traffic to the appropriate PHYs. If the active core card (or its LVDS link) should fail, protection switching commands embedded in the spare LVDS link will direct the S/UNI-DUPLEX to start receiving its traffic from this spare link.

The S/UNI-VORTEX resides on the core card and terminates up to 8 LVDS links connected to 8 S/UNI-DUPLEX devices. The S/UNI-VORTEX implements the second stage of multiplexing. More than one S/UNI-VORTEX will be required if more than 8 links are required – as will be the case for a system with more than 8 line cards. The S/UNI-VORTEX device(s) share a high speed parallel bus with the core card’s traffic management and OA&M layers, as implemented by devices such as PMC-Sierra’s S/UNI-APEX and the S/UNI-ATLAS. This is the third stage of multiplexing.

A single core card implementation is also supported, of course.

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5 BLOCK DIAGRAM

TENB

TADR[11:0]

TDAT[15:0]

TPRTY

TSX

TCLK

TPA

VADR[4:0]

RANYPHY

RENB

RADR[4:0]

RDAT[15:0]

RPRTY

RSOP

RSX

RCLK

RPA

A[9:0]

RDB

WRB

CSB

ALE

INTB

RSTB

D[7:0]

Any-PHY

Transm it

Slave

SCI-PHY/

Any-PHY

Receive

Slave

Micro-

Processor

Inte rfac e

to all blocks

. . .

33 Cell

per-PHY

buffer

6 Cell

FIFO

2 Cell

FIFO

4 Cell

FIFO

K 8 X

Cell

Processor

K 8 X T

TXD0 +

TXD0 -

RXD0+ RXD0-

. . .

TXD7+

TXD7-

RXD7+ RXD7-

Clock

Synthesis

JTAG

Test Access

Port

REFCLK

TDO

TDI

TCK

TMS

TRS TB

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6 DESCRIPTION

The PM7351 S/UNI-VORTEX is a monolithic integrated circuit typically used with its sister device, the S/UNI-DUPLEX, to implement a point-to-point serial backplane interconnect architecture.

Up to sixteen S/UNI-VORTEX devices can reside on a common cell processing card along side a traffic management device. The traffic management device exchanges cells with the S/UNI-VORTEX via 16-bit SCI-PHY or Any-PHY interfaces. Flow control is effected across this interface via cell available signals generated by the S/UNI-VORTEX. In the downstream direction, the availability of a buffer for each logical channel can be polled by the traffic management device. In the upstream direction, an indication is provided whether there is one or more cells queued in the S/UNI-VORTEX for transfer.

Each S/UNI-VORTEX can be connected to eight line cards via 100 to 200 Mb/s serial links. Each upstream link has its own queue. If a queue becomes nearly full, a flow control indication is sent downstream. In the downstream direction, each logical channel has a dedicated cell buffer to avoid head of line blocking. The serialization of cells from the cell buffers is throttled by flow control information sent from the line card via the upstream high-speed link.

A microprocessor port provides access to internal configuration and monitoring registers. The port may also be used to insert and extract cells in support of a control channel.

LVDS INTERFACES, BOTH DIRECTIONS

• 8 independent 4-wire LVDS serial transceivers each operating at up to 200 Mbps across PCB or backplane traces, or across up to 10 meters of 4-wire twisted pair cabling for inter-shelf communications.

• Usable bandwidth (excludes system overhead) of 186 Mbps per direction per LVDS link.

• Full integrated LVDS clock synthesis and recovery. No external analog components are required.

LVDS RECEIVE DIRECTION

• Weighted round robin multiplex of cell streams from the 8 LVDS links into a single cell stream which is transferred to the parallel bus under control of the bus master.

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• LVDS link and S/UNI-VORTEX identifiers are added to each cell (along with the PHY identifier already added by S/UNI-DUPLEX) for use by ATM layer to identify the cell source.

• Back-pressure sent to far end to prevent overflow of receiver FIFO.

LVDS TRANSMIT DIRECTION

• Per PHY and microprocessor port back-pressure used on each of the 8 links to prevent overflow of downstream buffers.

• Device polling: provides Utopia-like TCA status for 264 PHYs (includes 8 control channels) based on back-pressure from the LVDS links.

• Cell transfer: Bus master adds a PHY address to each cell via a 12 bit identifier. S/UNI-Vortex decodes and accepts cells for its links based on software configured base addresses.

PARALLEL BUS INTERFACE:

• Both directions: 16 bit wide, 50 MHz max clock rate, bus slave.

• Cells transferred to the bus: Utopia L2 compatible with optional expanded

length cells. Appears as single PHY, with a cell prepend identifying the source PHY ID of each cell. Alternatively, Utopia L2 compliance is supported by placing the PHY ID inside the UDF/HEC fields of a standard ATM cell.

• Cells received from the bus: The Any-PHY bus is similar to Utopia L2 but with optional expanded length cells and expanded addressing capabilities. The S/UNI-VORTEX appears to the bus master as a 264 port multi-PHY device (8 links, each with 32 PHYs & communication channel). PHY address is added as cell prepend or optionally in HEC/UDF field when standard length cells are desired.

MICROPROCESSOR INTERFACE

• 8 bit data bus, 8 bit address bus.

• Provides read/write access to all configuration and status registers.

• Provides CRC32 calculation and cell transfer registers to support an

embedded microprocessor to microprocessor communication channel over the LVDS link.

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7 PIN DIAGRAM

The S/UNI-VORTEX is packaged in a 304-ball enhanced ball grid array (BGA) package having a body size of 31 mm by 31 mm and a ball pitch of 1.27 mm.

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8 PIN DESCRIPTION

Ball Name

RXD0+ RXD0RXD1+ RXD1RXD2+ RXD2RXD3+ RXD3RXD4+ RXD4RXD5+ RXD5RXD6+ RXD6RXD7+ RXD7-

TXD0+ TXD0TXD1+ TXD1TXD2+ TXD2TXD3+ TXD3TXD4+ TXD4TXD5+ TXD5TXD6+ TXD6TXD7+ TXD7-

Type

Diff.

LVDS

Input

Diff.

LVDS

Output

Ball

No. Function

High Speed LVDS Links

D3 E4 F3 G4 G3 H4

L2 P1 P2 U3 T4

The high-speed receive data (RXD0+/- - RXD7+/-) inputs present NRZ data from a serial backplane.

These are truly differential inputs offering superior common-mode noise rejection. They have sufficient sensitivity and common-mode range to support LVDS signals.

These inputs are high-impedance. An external resistor must be connected between the two pins of a signal pair to terminate the transmission line. D.C. or A.C. coupling may be used depending on the application.

V3 U4 Y3

C1 D2 D1 E2 E1 F2 K1 K2 N1 N2

The transmit differential data (TXD0+/- -TXD7+/-) outputs present NRZ encoded data to a serial backplane. These outputs are open drain current sinks which interface directly with twisted-pair cabling or board interconnect. D.C. or A.C. coupling may be used depending on the application.

As current sinks, these outputs must see a 100Ω reflected impedance between the pins in a signal pair to produce correct LVDS signal levels.

V2 Y1

AA1

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PM7351 S/UNI-VORTEX

Ball Name

Type

Ball

No. Function

REFCLK Input AB13 The reference clock input (REFCLK) must provide a

jitter-free reference clock. It is used as the reference clock by both clock recovery and clock synthesis circuits. Any jitter below 1 MHz is transferred directly to the TXDn+/- outputs. The high speed serial interface bit rate is eight times the REFCLK frequency.

RES RESK

Analog P4

A 4.75kΩ ±1% resistor must be connected between these two balls to achieve the correct LVDS output signal levels.

ATP0 ATP1

Analog K3K4The Analog Test Points (ATP) are provided for

production test purposes. In mission mode they are high impedance and should be connected to ground.

TX8K Input J23 The transmit 8 kHz timing reference (TX8K) input

allows a traceable signal to be transmitted to the far end of the high-speed serial links via TXD0+/- through TXD7+/-. A rising edge on TX8K is encoded in the next cell transmitted.

Although TX8K is targeted at a typical need of transporting an 8 kHz signal, its frequency is not constrained to 8 kHz. Any frequency less than the cell rate is permissible.

RX8K Output A14 The receive 8 kHz timing reference (RX8K) output

presents the timing extracted from one of the receive high-speed serial links.

The rising edge of RX8K is accurate to the nearest byte boundary of the high-speed serial link; therefore, a small amount of jitter is present. At a link rate of

155.52 Mb/s, the jitter is 63ns peak-to-peak.

Pulses on RX8K are always 16 high-speed serial link bit periods wide (two REFCLK periods).

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PM7351 S/UNI-VORTEX

Ball Name

Type

Ball

No. Function

Upstream (Receive) Bus

RANYPHY Input C15 The Receive Any-PHY configuration input determines

the protocol of the upstream cell interface.

If RANYPHY is logic low, the interface complies to the SCI-PHY specification. As such, all outputs have a single cycle latency.

If RANYPHY is logic high, the interface complies to the Any-PHY specification. Relative to SCI-PHY, all outputs have an additional cycle of latency.

RANYPHY is an asynchronous input and is expected to be held static.

RCLK Input D17 The Receive FIFO clock (RCLK) is used to read words

from the S/UNI-VORTEX upstream cell buffer. RCLK must cycle at a 52 MHz or lower instantaneous rate. RSOP, RPA, RPRTY and RDAT[15:0] are updated on the rising edge of RCLK. RENB and RADR[4:0] are sampled on the rising edge of RCLK.

RPA Output C18 The RPA signal indicates whether at least one cell is

queued for transfer.

Upon sampling a RADR[4:0] value that equals the value on VADR[4:0], the S/UNI-VORTEX drives the RPA with the cell availability status immediately if RANYPHY is logic low. If RANYPHY is logic high, RPA has an additional cycle of latency. RPA will be a one if at least one entire cell is available.

RPA is high-impedance when not polled.

RPA is updated on the rising edge of RCLK.

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PM7351 S/UNI-VORTEX

Ball Name

Type

Ball

No. Function

RENB Input A19 The active low read enable (RENB) output is used to

initiate the transfer of cells from the S/UNI-VORTEX to a traffic management device.

When RENB is sampled low and the S/UNI-VORTEX has been selected, a word is output on bus RDAT[15:0]. Selection occurs when RENB is last sampled high if the RADR[4:0] value equals the state of VADR[4:0]. RENB must be low for between 27 and 29 cycles to transfer an entire cell depending on whether the cell contains prepended words or the H5/UDF word.

If RANYPHY is logic low, valid data is driven immediately upon sampling RENB low. If RANYPHY is logic high, the RSX, RSOP, RDAT[15:0] and RPRTY outputs have an additional cycle of latency.

It is permissible to pause a cell transfer by deasserting RENB high. If RANYPHY is logic low, the S/UNIVORTEX’s address must be presented on RADR[4:0] the last cycle RENB is high to reselect the device. If RANYPHY is logic high, the cell transfer resumes unconditionally when RENB is asserted low again. In either case, a cell transfer must be completed before another device on the bus is selected.

The Any-PHY protocol supports autonomous deselection. If RANYPHY is logic high, the outputs become high impedance after the last word of a cell is transferred until the S/UNI-VORTEX is reselected. If RANYPHY is logic low, a subsequent cell is transferred (provided one is available) if RENB is held low beyond the end of a cell.

When RENB is sampled high or the S/UNI-VORTEX is not selected, no read is performed and outputs RDAT[15:0], RPRTY, RSX and RSOP become high impedance.

The RENB input is sampled on the rising edge of RCLK.

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PM7351 S/UNI-VORTEX

Ball Name

RADR[4] RADR[3] RADR[2] RADR[1] RADR[0]

VADR[4] VADR[3] VADR[2] VADR[1] VADR[0]

Ball

Type

No. Function

Input B16

C16 A17 B17 D16

Input B14

C14 A15 D14 B15

The RADR[4:0] signals are used to address up to sixteen S/UNI-VORTEX devices for the purposes of polling and selection for cell transfer.

When a RADR[4:0] value is sampled that equals the state of VADR[4:0], the RPA output is driven to indicate whether a cell is available for transfer. If RANYPHY is logic high, RPA has an additional cycle of latency.

If the RADR[4:0] value equals the state of VADR[4:0] when the RENB is last sampled high, the S/UNIVORTEX will initiate a cell transfer. If RANYPHY is logic low, the device must be reselected to resume a cell transferred that has been halted by deasserting RENB high.

The RADR[4:0] bus is sampled on the rising edge of RCLK.

The device identification address (VADR[4:0]) inputs are the most-significant bits of the upstream polling address space which this S/UNI-VORTEX occupies.

When the VADR[4:0] inputs match the value sampled on RADR[4:0] inputs, the S/UNI-VORTEX drives RPA to indicate the existence of queued cells. Otherwise, RPA is high impedance.

VADR[4:0] are expected to be held static.

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PM7351 S/UNI-VORTEX

Ball Name

Type

Ball

No. Function

RSOP Output B18 The Receive Start of Packet (RSOP) marks either the

first or second word of the cell on the RDAT[15:0] bus. When RSOP is high and RANYPHY is low, the first word of the cell structure is present on the RDAT[15:0] stream. When RSOP and RANYPHY are both high, the second word of the cell structure is present on the RDAT[15:0] stream.

RSOP is updated on the rising edge of RCLK and considered valid only when the S/UNI-VORTEX device was selected after the polling process and the RENB signal is sampled low. If RANYPHY is logic low RSOP is driven immediately upon sampling RENB low, but it has an additional cycle latency when RANYPHY is logic high. RSOP becomes high impedance upon sampling RENB high or if the S/UNIVORTEX device is not selected for transfer.

When RANYPHY is high, autonomous deselection occurs after the last word of a cell resulting in setting RSOP high-impedance until reselection.

RSX Output C17 The Receive Start of Transfer (RSX) is only active

when the RANYPHY input is logic high. When RANYPHY is logic low, RSX is low during cell transfers or high-impedance otherwise.

RSX marks the start of the cell on the RDAT[15:0] bus. When RSX is high, the first word of the cell structure is present on the RDAT[15:0] stream.

RSX is updated on the rising edge of RCLK and considered valid only when the RENB signal was sampled low in the previous cycle and the S/UNIVORTEX device was selected after the polling process. RSX becomes high impedance (with a cycle latency) upon sampling RENB high or if the S/UNIVORTEX device is not selected for transfer.

When RANYPHY is high, autonomous deselection occurs after the last word of a cell resulting in setting RSX high-impedance until reselection.

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PM7351 S/UNI-VORTEX

Ball Name

RDAT[15] RDAT[14] RDAT[13] RDAT[12] RDAT[11] RDAT[10] RDAT[9] RDAT[8] RDAT[7] RDAT[6] RDAT[5] RDAT[4] RDAT[3] RDAT[2] RDAT[1] RDAT[0]

Type

Output A20

Ball

No. Function

The receive cell data bus (RDAT[15:0]) carries the C19 D19 D21 C23 D22 E21 D23 E22 F21 G20 E23 F22 G21 H20 G23

ATM cell words that have been read from the S/UNI-

VORTEX internal cell buffers.

The RDAT[15:0] bus is updated on the rising edge of

RCLK and considered valid only when the S/UNI-

VORTEX device was selected after the polling

process and the RENB signal is sampled low. If

RANYPHY is logic low RDAT[15:0] is driven

immediately upon sampling RENB low, but it has an

additional cycle latency when RANYPHY is logic high.

RDAT[15:0] becomes high impedance upon sampling

RENB high or if the S/UNI-VORTEX device is not

selected for transfer.

When RANYPHY is high, autonomous deselection

occurs after the last word of a cell resulting in setting

RDAT[15:0] high-impedance until reselection.

RPRTY Output B19 The Receive Parity (RPRTY) signal completes the

parity (programmable for odd or even parity) of the

RDAT[15:0] bus.

The RPRTY signal is updated on the rising edge of

RCLK and is considered valid only when the S/UNI-

VORTEX device was selected after the polling

process and the RENB signal is sampled low. If

RANYPHY is logic low RPRTY is driven immediately

upon sampling RENB low, but it has an additional

cycle latency when RANYPHY is logic high. RPRTY

becomes high impedance upon sampling RENB high

or if the S/UNI-VORTEX device is not selected for

transfer.

When RANYPHY is high, autonomous deselection

occurs after the last word of a cell resulting in setting

RPRTY high-impedance until reselection.

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PM7351 S/UNI-VORTEX

Ball Name

Type

Ball

No. Function

Downstream (Transmit) Bus

TCLK Input R21 The transmit FIFO clock (TCLK) is used to transfer

cells from a traffic scheduler device to the internal

downstream cell buffers. TCLK must cycle at a 52

MHz or lower instantaneous rate. TSX, TENB,

TADR[11:0], TPRTY and TDAT[15:0] are sampled on

the rising edge of TCLK. TPA is updated on the rising

edge of TCLK.

TPA Output U23 The S/UNI-VORTEX indicates the availability of space

in the FIFO associated with a logical channel when

polled using the TADR[11:0] signals. The S/UNI-

VORTEX will drive the TPA signal to the appropriate

value during the second clock cycle following that in

which a particular logical channel is addressed. When

high, TPA indicates that the corresponding buffer

segment is empty and a complete cell may be written.

The buffer status for the particular logical channel

involved in the transfer is updated immediately upon

sampling the first word of the cell when the

INADDUDF bit of the Downstream Cell Interface

Configuration register is logic 0. When the

INADDUDF bit is logic 1, the buffer status is stale until

nine cycles after the cell transfer is completed;

therefore, the master should refrain from polling that

logical channel in the interim.

TPA becomes high impedance when an address not

matching the address space set by the Control

Channel Base Address, Logical Channel Base

Address and Logical Channel Address Range /

Logical Channel Base Address MSB registers is

sampled from the TADR[11:3] inputs.

TPA is updated on the rising edge of TCLK.

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PMC PM7351-BI Datasheet

REVISION HISTORY

CONTENTS

LIST OF REGISTERS

LIST OF FIGURES

LIST OF TABLES