PMC PM7351 Datasheet

PMC-Sierra,Inc.

Octal Serial Link Multiplexer

PM7351

S/UNI-VORTEX

FEATURES

• Integrated analog/digital device that interfaces a high speed parallel bus to 8 bidirectional data streams.

• Each stream trav els over a high speed Low Voltage Differential Signal (LVDS) serial link.

• Interfaces to 8 S/UNI

devices (via the LVDS links) to create a point-to-multipoint serial backplane architecture.

• In the LVDS receive direction: accepts cell streams f rom the 8 LVDS links, multiplexing them into a single cell stream, which is presented to the system bus as a single UTOPIA L2 compatible PHY.

• In the LVDS transmit direction: receives cell streams from the bus master, and routes the cells to the appropriate serial link.

• Cell read/write to the 8 LVDS links is available via the microprocessor port.

• Provides optional hardware assisted CRC32 calculation across cells, which creates an embedded inter-processor communication channel across the LVDS links.

-DUPLEX

• Optionally routes the embedded control channels from the 8 links to/ from the system bus.

• Under software control, the 8 LVDS links can be individually marked active or standby. This is used by the far end S/UNI-DUPLEX to implement 1:1 protected systems.

• Error monitoring and cell counting on all links.

• Requires no external memories.

• Low power 3.3V CMOS technology.

• Standard 5 pin P1149 JTAG port.

• 304 ball SBGA, 31mm x 31mm.

PARALLEL BUS INTERFACE

• Both directions: 16 bit wide, 52 MHz max clock rate, bus slave.

• Cells transferred to the bus:

• UTOPIA L2 compatible with optional

expanded cell length.

• Appears as a single P HY, with a cel l

prepend identifying the so urce PHY ID of each cell.

• Alternatively, UTOPIA L2

compliance is supported by placing PHY ID inside the UDF/HEC fields of a standard ATM cell.

• Cells received from the bu s:

• UTOPIA L2 with expanded cell

length and addressing capabilities.

• The S/UNI-VORTEX appears to the

bus master as a 264 port multi-PHY device (8 links, each with 32 PHYs & one communication channel).

LVDS INTERFACES

• 8 independent 4-wire LVDS serial transceivers, each operating at up to 200 Mb/s.

• Operates across PCB or backplane traces, or across up to 10 meters of 4-wire twisted pair cabling for inter-shelf communications.

• Fully integrated LVDS clock synthesis and recovery. No external analog components are required.

• Usable bandwidth (excludes system overhead) of 186 Mbit/s.

LVDS RECEIVE DIRECTION

• Weighted round-robin multiplex of cell streams from the 8 LVDS links into a single cell stream, which is transferred to the parallel bus under control of the bus master.

• Back-pressure sent to far end to prevent overflow of receiver FIFO .

DIAGRAM

TENB TADR[11:0] TDAT[15:0]

TPRTY

TSX

TCLK

TPA

VADR[4:0] RANYPHY

RENB

RADR[4:0]

RDAT[15:0]

RPRTY

RSOP

RSX

RCLK

RPA

Any-PHY Transmit

Slave

SCI-PHY/

Any-PHY

Receive

Slave

Clock

Synthesis

REFCLK

TX8K

33 Cell Per-

PHY Buffer

Cell

FIFO

WRB

RDB

Processor

INTB

RSTB

6 Cell FIFO

FIFO

4 Cell

é é é

Microprocessor Interface

ALE

CSB

A[9:0]

D[7:0]

RX8K

JTAG Test Access

Port

TDI

TCK

TMS

TDO

TXD0+ TXD0-

RXD0+ RXD0-

é é é

TXD7+ TXD7-

RXD7+ RXD7-

TRSTB

Octal Serial Link Multiplexer

PM7351 S/UNI-VORTEX

• LVDS link ID and S/UNI-VORTEX ID is added to each cell (alon g with the PHY ID already added by S/UNI-DUPLEX) for use by ATM layer to identify cell source.

LVDS TRANSMIT DIRECTION

• Per PHY and microprocessor port back-pressure used on each of the 8 links to prevent overflow of downstream buffers.

TYPICAL APPLICATIONS

MULTI-SHELF 1024 LINE ATM DSLAM

xDSL PHY

é é é

xDSL PHY

modem

é é é

modem

UTOPIA Line Cards

S/UNI-DUPLEX

processor

Clock/Data Line Cards

S/UNI-DUPLEX

processor

• Device polling: provides UTOPIA-like TCA status for 264 PHYs based on back-pres s ure from LVDS links.

• Cell transfer: Bus master adds a PHY address to each cell via a 12 bit ID. S/UNI-VORTEX decodes and accepts cells for its links based on software configured base address .

S/UNI-VORTEX

é é é

S/UNI-VORTEX

é é é

S/UNI-VORTEX

processor

S/UNI-APEX

RAM RAM

processor

S/UNI-APEX S/UNI-ATLAS S/UNI-PLUS

RAM RAM

APPLICATIONS

• Single shelf or multi-shelf Digital Subscriber Loop Access Multiplexer (DSLAM)

• ATM, frame relay, IP switch

• Multi-service access multiplexer

• UMTS wireless base stations

• UMTS wireless ba se st ati on c ontrollers

• Multi-shelf access concentrators

S/UNI-ATLAS S/UNI-PLUS

Common Card,

working

Common Card,

spare

8 Links per S/UNI-VORTEX

PACKET ACCESS MULTIPLIER

modem

é é é

modem

Freedm-NG

Head Office: PMC-Sierra, Inc. #105 - 8555 Baxter Place Burnaby, B.C. V5A 4V7 Canada Tel: 604.415.6000

Cut-thru AAL5

Line Cards

S/UNI-DUPLEX

processor

S/UNI-

VORTEX

é é é

S/UNI-

VORTEX

S/UNI-

VORTEX

é é é

S/UNI-

VORTEX

8 Links per S/UNI-VORTEX

To order documentation, send email to: document@pmc-sierra.com or contact the head office, Attn: Document Coordinator

Flow

Classifier

Flow

Classifier

processor, flow

co-processor

S/UNI-

APEX

RAM

processor, flow

co-processor

S/UNI-

APEX

RAM

All product documentation is available on our web site at: http://www.pmc-sierra.com For corpo rate information, send email to: info@pmc-sierra.com

Fax: 604.415.6200

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

Cut-thru

AAL5 +

Classifier

Cut-thru

AAL5 +

Classifier

Freedm-NG

Common Card,

Freedm-NG

Common Card,

PMC-990148 (P2)  1999 PMC-Sierra, Inc.

Framer

working

Framer

protection