PMC PM7347-BI Datasheet
PM7347
T
TM
S/UNI
JE
-
S/UNI®-JET Data Sheet
Released
S/UNI®-JET
SATURN® USER NETWORK INTERFACE
for J2/E3/T3
Data Sheet
Released
Issue 3: June 2001
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990267, Issue 3
S/UNI®-JET Data Sheet
Released
Legal Information
Copyright
© 2001 PMC-Sierra, Inc.
The information is proprietary and confidential to PMC-Sierra, Inc., and for its customers’
internal use. In any event, you cannot reproduce any part of this document, in any form, without
the express written consent of PMC-Sierra, Inc.
PMC-1990267 (R3)
Disclaimer
None of the information contained in this document constitutes an express or implied warranty by
PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such
information or the fitness, or suitability for a particular purpose, merchantability, performance,
compatibility with other parts or systems, of any of the products of PMC-Sierra, Inc., or any
portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all
representations and warranties of any kind regarding the contents or use of the information,
including, but not limited to, express and implied warranties of accuracy, completeness,
merchantability, fitness for a particular use, or non-infringement.
In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or
consequential damages, including, but not limited to, lost profits, lost business or lost data
resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has
been advised of the possibility of such damage.
Trademarks
S/UNI and SATURN are registerd trademarks of PMC-Sierra, Inc. SCI-PHY is a trademark of
PMC-Sierra, Inc.
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Tel: (604) 415-6000
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S/UNI®-JET Data Sheet
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Revision History
Issue No. Issue Date Details of Change
3 June 2001 Included Application examples, Description, and Functional Description,
Functional Timing, Microprocessor Timing, and A.C. Timing sections.
Completed Normal Mode Register and Operation sections.
Changed all read-only “Reserved” bits to “Unused”.
Changed IDDOP values.
Changed Thermal “Case” temperature to “Ambient”, Section 11.
Divided Pin Diagram into quadrants for readability.
2 March 2000 Preliminary label removed.
S/UNI-JET errata added.
1 April 1999 Document created.
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Document ID: PMC-1990267, Issue 3
S/UNI®-JET Data Sheet
Table of Contents
1 Features..................................................................................................................... 17
2 Applications ...............................................................................................................21
3 References ................................................................................................................22
4 Definitions ..................................................................................................................24
5 Application Examples ................................................................................................ 26
6 Block Diagram ...........................................................................................................28
7 Description.................................................................................................................29
8 Pin Diagram ...............................................................................................................32
9 Pin Description........................................................................................................... 34
10 Functional Description ...............................................................................................54
10.1 DS3 Framer.......................................................................................................54
10.2 E3 Framer ......................................................................................................... 56
Released
10.3 J2 Framer..........................................................................................................58
10.3.1 J2 Frame Find Algorithms ....................................................................59
10.4 RBOC Bit-Oriented Code Detector ...................................................................62
10.5 RDLC PMDL Receiver ......................................................................................62
10.6 PMON Performance Monitor Accumulator........................................................ 63
10.7 SPLR PLCP Layer Receiver .............................................................................63
10.8 ATMF ATM Cell Delineator................................................................................64
10.9 PRGD Pseudo-Random Sequence Generator/Detector .................................. 65
10.10 RXCP-50 Receive Cell Processor ....................................................................66
10.11 RXFF Receive FIFO..........................................................................................68
10.12 CPPM Cell and PLCP Performance Monitor .................................................... 69
10.13 DS3 Transmitter ................................................................................................69
10.14 E3 Transmitter...................................................................................................70
10.15 J2 Transmitter ...................................................................................................71
10.16 XBOC Bit Oriented Code Generator .................................................................72
10.17 TDPR PMDL Transmitter ..................................................................................72
10.18 SPLT SMDS PLCP Layer Transmitter ..............................................................73
10.19 TXCP-50 Transmit Cell Processor .................................................................... 74
10.20 TXFF Transmit FIFO .........................................................................................74
10.21 TTB Trail Trace Buffer ....................................................................................... 75
10.22 JTAG Test Access Port......................................................................................75
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S/UNI®-JET Data Sheet
10.23 Microprocessor Interface ..................................................................................76
11 Normal Mode Register Description............................................................................81
12 Test Features Description........................................................................................249
12.1 Test Mode 0 Details.........................................................................................251
12.2 JTAG Test Port ................................................................................................255
13 Operation .................................................................................................................259
13.1 Software Initialization Sequence.....................................................................259
13.2 Register Settings for Basic Configurations .....................................................260
13.3 PLCP Frame Formats .....................................................................................261
13.3.1 PLCP Path Overhead Octet Processing ............................................264
13.4 DS3 Frame Format .........................................................................................267
13.5 G.751 E3 Frame Format .................................................................................269
13.6 G.832 E3 Frame Format .................................................................................270
13.7 J2 Frame Format ............................................................................................271
Released
13.8 S/UNI-JET Cell Data Structure........................................................................273
13.9 Resetting the RXFF and TXFF FIFOs ............................................................277
13.10 Servicing Interrupts .........................................................................................277
13.11 Using the Performance Monitoring Features .................................................. 277
13.12 Using the Internal PMDL Transmitter..............................................................278
13.12.1 Interrupt Driven Mode......................................................................... 279
13.12.2 TDPR Interrupt Routine......................................................................280
13.13 Using the Internal Data Link Receiver ............................................................281
13.14 PRGD Pattern Generation ..............................................................................285
13.14.1 Generating and detecting repetitive patterns .....................................286
13.14.2 Common Test Patterns....................................................................... 286
13.15 JTAG Support.................................................................................................. 288
13.15.1 TAP Controller ....................................................................................289
14 Functional Timing.....................................................................................................295
15 Absolute Maximum Ratings ..................................................................................... 319
16 D.C. Characteristics.................................................................................................320
17 Microprocessor Interface Timing Characteristics ....................................................322
18 A.C. Timing Characteristics .....................................................................................325
19 Ordering and Thermal Information ..........................................................................339
20 Mechanical Information ........................................................................................... 340
Notes ...............................................................................................................................341
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 6
Document ID: PMC-1990267, Issue 3
S/UNI®-JET Data Sheet
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Document ID: PMC-1990267, Issue 3
S/UNI®-JET Data Sheet
List of Registers
Register 300H: S/UNI-JET Configuration 1.......................................................................82
Register 301H: S/UNI-JET Configuration 2.......................................................................85
Register 302H: S/UNI-JET Transmit Configuration ...........................................................87
Register 303H: S/UNI-JET Receive Configuration............................................................89
Register 304H: S/UNI-JET Data Link and FERF/RAI Control ...........................................91
Register 305H: S/UNI-JET Interrupt Status.......................................................................95
Register 006H: S/UNI-JET Identification, Master Reset, and Global Monitor
Update ...................................................................................................................... 96
Register 307H: S/UNI-JET Clock Activity Monitor and Interrupt Identification ..................97
Register 308H: SPLR Configuration..................................................................................98
Register 309H: SPLR Interrupt Enable ...........................................................................100
Register 30AH: SPLR Interrupt Status ............................................................................102
Released
Register 30BH: SPLR Status...........................................................................................104
Register 30CH: SPLT Configuration................................................................................ 106
Register 30DH: SPLT Control..........................................................................................109
Register 30EH: SPLT Diagnostics and G1 Octet ............................................................ 111
Register 30FH: SPLT F1 Octet........................................................................................ 113
Register 310H: Change of PMON Performance Meters .................................................114
Register 311H: PMON Interrupt Enable/Status ............................................................... 115
Register 314H: PMON LCV Event Count LSB ................................................................ 116
Register 315H: PMON LCV Event Count MSB ............................................................... 116
Register 316H: PMON Framing Bit Error Event Count LSB ...........................................117
317H: PMON Framing Bit Error Event Count MSB ......................................................... 117
Register 318H: PMON Excessive Zero Count LSB ........................................................ 118
Register 319H: PMON Excessive Zero Count MSB ....................................................... 118
Register 31AH: PMON Parity Error Event Count LSB ....................................................119
Register 31BH: PMON Parity Error Event Count MSB ...................................................119
Register 31CH: PMON Path Parity Error Event Count LSB............................................ 120
Register 31DH: PMON Path Parity Error Event Count MSB........................................... 120
Register 31EH: PMON FEBE/J2-EXZS Event Count LSB..............................................121
Register 31FH: PMON FEBE/J2-EXZS Event Count MSB.............................................121
Register 321H: CPPM Change of CPPM Performance Meters ......................................122
Register 322H: CPPM B1 Error Count LSB ....................................................................123
Register 323H: CPPM B1 Error Count MSB ...................................................................123
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Document ID: PMC-1990267, Issue 3
S/UNI®-JET Data Sheet
Register 324H: CPPM Framing Error Event Count LSB .................................................124
Register 325H: CPPM Framing Error Event Count MSB ................................................124
Register 326H: CPPM FEBE Count LSB ........................................................................125
Register 327H: CPPM FEBE Count MSB .......................................................................125
Register 330H: DS3 FRMR Configuration.......................................................................126
Register 331H: DS3 FRMR Interrupt Enable (ACE=0) ...................................................128
Register 331H: DS3 FRMR Additional Configuration Register .......................................130
Register 332H: DS3 FRMR Interrupt Status....................................................................133
Register 333H: DS3 FRMR Status ..................................................................................135
Register 334H: DS3 TRAN Configuration .......................................................................137
Register 335H: DS3 TRAN Diagnostic............................................................................139
Register 338H: E3 FRMR Framing Options ....................................................................141
Register 339H: E3 FRMR Maintenance Options ............................................................143
Register 33AH: E3 FRMR Framing Interrupt Enable ......................................................145
Released
Register 33BH: E3 FRMR Framing Interrupt Indication and Status................................146
Register 33CH: E3 FRMR Maintenance Event Interrupt Enable .................................... 148
Register 33DH: E3 FRMR Maintenance Event Interrupt Indication ................................ 150
Register 33EH: E3 FRMR Maintenance Event Status ....................................................152
Register 340H: E3 TRAN Framing Options.....................................................................154
Register 341H: E3 TRAN Status and Diagnostic Options...............................................155
Register 342H: E3 TRAN BIP-8 Error Mask....................................................................157
Register 343H: E3 TRAN Maintenance and Adaptation Options ....................................158
Register 344H: J2-FRMR Configuration..........................................................................160
Register 345H: J2-FRMR Status ..................................................................................... 162
Register 346H: J2-FRMR Alarm Interrupt Enable ...........................................................163
Register 347H: J2-FRMR Alarm Interrupt Status ............................................................165
Register 348H: J2-FRMR Error/Xbit Interrupt Enable ..................................................... 167
Register 349H: J2-FRMR Error/Xbit Interrupt Status ...................................................... 169
Register 34CH: J2-TRAN Configuration..........................................................................171
Register 34DH: J2-TRAN Diagnostic ..............................................................................172
Register 34EH: J2-TRAN TS97 Signaling.......................................................................173
Register 34FH: J2-TRAN TS98 Signaling .......................................................................174
Register 350H: RDLC Configuration ...............................................................................175
Register 351H: RDLC Interrupt Control...........................................................................177
Register 352H: RDLC Status........................................................................................... 178
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Document ID: PMC-1990267, Issue 3
S/UNI®-JET Data Sheet
Register 353H: RDLC Data .............................................................................................180
Register 354H: RDLC Primary Address Match ...............................................................181
Register 355H: RDLC Secondary Address Match ..........................................................182
Register 358H: TDPR Configuration ...............................................................................183
Register 359H: TDPR Upper Transmit Threshold...........................................................185
Register 35AH: TDPR Lower Interrupt Threshold...........................................................186
Register 35BH: TDPR Interrupt Enable...........................................................................187
Register 35CH: TDPR Interrupt Status/UDR Clear ......................................................... 188
Register 35DH: TDPR Transmit Data.............................................................................. 190
Register 360H: RXCP-50 Configuration 1.......................................................................191
Register 361H: RXCP-50 Configuration 2.......................................................................193
Register 362H: RXCP-50 FIFO/UTOPIA Control & Configuration ..................................195
Register 363H: RXCP-50 Interrupt Enables and Counter Status.................................... 197
Register 364H: RXCP-50 Status/Interrupt Status............................................................199
Released
Register 365H: RXCP-50 LCD Count Threshold (MSB) .................................................201
Register 366H: RXCP-50 LCD Count Threshold (LSB) ..................................................201
Register 367H: RXCP-50 Idle Cell Header Pattern......................................................... 203
Register 368H: RXCP-50 Idle Cell Header Mask............................................................ 204
Register 369H: RXCP-50 Corrected HCS Error Count ...................................................205
Register 36AH: RXCP-50 Uncorrected HCS Error Count...............................................206
Register 36BH: RXCP-50 Receive Cell Counter (LSB) ..................................................207
Register 36CH: RXCP-50 Receive Cell Counter ............................................................207
Register 36DH: RXCP-50 Receive Cell Counter (MSB) .................................................208
Register 36EH: RXCP-50 Idle Cell Counter (LSB).......................................................... 209
Register 36FH: RXCP-50 Idle Cell Counter ....................................................................209
Register 370H: RXCP-50 Idle Cell Counter (MSB) .........................................................210
Register 380H: TXCP-50 Configuration 1 ....................................................................... 211
Register 381H: TXCP-50 Configuration 2 ....................................................................... 213
Register 382H: TXCP-50 Cell Count Status....................................................................215
Register 383H: TXCP-50 Interrupt Enable/Status...........................................................216
Register 384H: TXCP-50 Idle Cell Header Control .........................................................218
Register 385H: TXCP-50 Idle Cell Payload Control........................................................219
Register 386H: TXCP-50 Transmit Cell Count (LSB)......................................................220
Register 387H: TXCP-50 Transmit Cell Count ................................................................220
Register 388H: TXCP-50 Transmit Cell Count (MSB).....................................................221
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Document ID: PMC-1990267, Issue 3
S/UNI®-JET Data Sheet
Register 390H: TTB Control ............................................................................................222
Register 391H: TTB Trail Trace Identifier Status .............................................................224
Register 392H: TTB Indirect Address..............................................................................225
Register 393H: TTB Indirect Data ...................................................................................226
Register 394H: TTB Expected Payload Type Label........................................................227
Register 395H: TTB Payload Type Label Control/Status ................................................228
Register 398H: RBOC Configuration/Interrupt Enable .................................................... 230
Register 399H: RBOC Interrupt Status............................................................................231
Register 39AH: XBOC Code ...........................................................................................232
Register 39BH: S/UNI-JET Miscellaneous ...................................................................... 233
Register 39CH: S/UNI-JET FRMR LOF Status. ..............................................................235
Register 3A0H: PRGD Control ........................................................................................237
Register 3A1H: PRGD Interrupt Enable/Status............................................................... 239
Register 3A2H: PRGD Length.........................................................................................241
Released
Register 3A3H: PRGD Tap ..............................................................................................242
Register 3A4H: PRGD Error Insertion Register ..............................................................243
Register 3A8H: Pattern Insertion #1................................................................................244
Register 3A9H: Pattern Insertion #2................................................................................244
Register 3AAH: Pattern Insertion #3 ............................................................................... 245
Register 3ABH: Pattern Insertion #4 ............................................................................... 245
Register 3ACH: PRGD Pattern Detector #1.................................................................... 246
Register 3ADH: PRGD Pattern Detector #2.................................................................... 246
Register 3AEH: PRGD Pattern Detector #3 ....................................................................247
Register 3AFH: PRGD Pattern Detector #4 ....................................................................247
Register 40CH: S/UNI-JET Identification Register .......................................................... 248
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 11
Document ID: PMC-1990267, Issue 3
S/UNI®-JET Data Sheet
List of Figures
Figure 1 S/UNI-JET Operating as an ATM PHY in an ATM Switch ................................26
Figure 2 S/UNI-JET Operating as a Framer Device in Frame Relay Equipment............27
Figure 3 Block Diagram ...................................................................................................28
Figure 4 Framing algorithm (CRC_REFR = 0) ................................................................60
Figure 5 Framing Algorithm (CRC_REFR = 1)................................................................61
Figure 6 Cell delineation State Diagram .........................................................................65
Figure 7 HCS Verification State Diagram........................................................................68
Figure 8 DS3 PLCP Frame Format...............................................................................262
Figure 9 DS1 PLCP Frame Format...............................................................................262
Figure 10 G.751 E3 PLCP Frame Format..................................................................... 263
Figure 11 E1 PLCP Frame Format................................................................................264
Figure 12 DS3 Frame Structure ....................................................................................267
Released
Figure 13 G.751 E3 Frame Structure............................................................................269
Figure 14 G.832 E3 Frame Structure............................................................................270
Figure 15 J2 Frame Structure .......................................................................................272
Figure 16 16-bit Wide, 26-byte Word Structure............................................................. 273
Figure 17 16-bit Wide, 27-byte Word Structure............................................................. 274
Figure 18 8-bit Wide, 52-byte Word Structure............................................................... 275
Figure 19 8-bit Wide, 53-byte Word Structure............................................................... 276
Figure 20 Typical Data Frame.......................................................................................284
Figure 21 Example Multi-Packet Operational Sequence ..............................................284
Figure 22 PRGD Pattern Generator ..............................................................................285
Figure 23 Boundary Scan Architecture .........................................................................288
Figure 24 TAP Controller Finite State Machine.............................................................290
Figure 25 Input Observation Cell (IN_CELL) ................................................................293
Figure 26 Output Cell (OUT_CELL) ..............................................................................293
Figure 27 Bi-directional Cell (IO_CELL) ........................................................................ 294
Figure 28 Layout of Output Enable and Bi-directional Cells .........................................294
Figure 29 Receive DS1 Stream.....................................................................................295
Figure 30 Receive E1 Stream .......................................................................................295
Figure 31 Receive Bipolar DS3 Stream ........................................................................296
Figure 32 Receive Unipolar DS3 Stream ......................................................................296
Figure 33 Receive Bipolar E3 Stream ........................................................................... 296
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Document ID: PMC-1990267, Issue 3
S/UNI®-JET Data Sheet
Figure 34 Receive Unipolar E3 Stream.........................................................................297
Figure 35 Receive Bipolar J2 Stream ...........................................................................297
Figure 36 Receive Unipolar J2 Stream .........................................................................298
Figure 37 Generic Receive Stream ...............................................................................298
Figure 38 Receive DS3 Overhead ................................................................................299
Figure 39 Receive G.832 E3 Overhead ........................................................................300
Figure 40 Receive G.751 E3 Overhead ........................................................................300
Figure 41 Receive J2 Overhead....................................................................................301
Figure 42 Receive PLCP Overhead .............................................................................. 301
Figure 43 Transmit DS1 Stream....................................................................................302
Figure 44 Transmit E1 Stream ......................................................................................302
Figure 45 Transmit Bipolar DS3 Stream .......................................................................303
Figure 46 Transmit Unipolar DS3 Stream .....................................................................303
Figure 47 Transmit Bipolar E3 Stream .......................................................................... 304
Released
Figure 48 Transmit Unipolar E3 Stream........................................................................304
Figure 49 Transmit Bipolar J2 Stream ..........................................................................305
Figure 50 Transmit Unipolar J2 Stream ........................................................................305
Figure 51 Generic Transmit Stream ..............................................................................306
Figure 52 Transmit DS3 Overhead ...............................................................................307
Figure 53 Transmit G.832 E3 Overhead .......................................................................308
Figure 54 Transmit G.751 E3 Overhead .......................................................................309
Figure 55 Transmit J2 Overhead...................................................................................309
Figure 56 Transmit PLCP Overhead .............................................................................310
Figure 57 Framer Mode DS3 Transmit Input Stream .................................................... 311
Figure 58 Framer Mode DS3 Transmit Input Stream With TGAPCLK.......................... 311
Figure 59 Framer Mode DS3 Receive Output Stream ..................................................311
Figure 60 Framer Mode DS3 Receive Output Stream with RGAPCLK ........................ 312
Figure 61 Framer Mode G.751 E3 Transmit Input Stream ...........................................312
Figure 62 Framer Mode G.751 E3 Transmit Input Stream With TGAPCLK .................312
Figure 63 Framer Mode G.751 E3 Receive Output Stream.......................................... 313
Figure 64 Framer Mode G.751 E3 Receive Output Stream with RGAPCLK ................313
Figure 65 Framer Mode G.832 E3 Transmit Input Stream ...........................................314
Figure 66 Framer Mode G.832 E3 Transmit Input Stream With TGAPCLK .................314
Figure 67 Framer Mode G.832 E3 Receive Output Stream.......................................... 314
Figure 68 Framer Mode G.832 E3 Receive Output Stream with RGAPCLK ................314
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 13
Document ID: PMC-1990267, Issue 3
S/UNI®-JET Data Sheet
Figure 69 Framer Mode J2 Transmit Input Stream .......................................................315
Figure 70 Framer Mode J2 Transmit Input Stream With TGAPCLK.............................315
Figure 71 Framer Mode J2 Receive Output Stream .....................................................316
Figure 72 Framer Mode J2 Receive Output Stream with RGAPCLK ...........................316
Figure 73 Multi-PHY Polling and Addressing Transmit Cell Interface...........................317
Figure 74 Multi-PHY Polling and Addressing Receive Cell Interface............................ 318
Figure 75 Microprocessor Interface Read Timing .........................................................322
Figure 76 Microprocessor Interface Write Timing .........................................................324
Figure 77 RSTB Timing.................................................................................................325
Figure 78 Transmit ATM Cell Interface Timing .............................................................326
Figure 79 Receive ATM Cell Interface Timing ..............................................................328
Figure 80 Transmit Interface Timing .............................................................................330
Figure 81 Receive Interface Timing ..............................................................................335
Figure 82 JTAG Port Interface Timing...........................................................................337
Released
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Document ID: PMC-1990267, Issue 3
S/UNI®-JET Data Sheet
List of Tables
Table 1 Supported Operating Formats............................................................................17
Table 2 Transmission System Sublayer Processing Acceptance and Output ................29
Table 3 Summary of Receive Detection Features ..........................................................29
Table 4 Multiframe Format .............................................................................................. 58
Table 5 C1 Octet Pattern.................................................................................................74
Table 6 Register Memory Map ........................................................................................ 76
Table 7 STATSEL[2:0] Options .......................................................................................86
Table 8 TFRM[1:0] Transmit Frame Structure Configurations ........................................88
Table 9 LOF[1:0] Integration Period Configuration .........................................................90
Table 10 RFRM[1:0] Receive Frame Structure Configurations ......................................90
Table 11 SPLR FORM[1:0] Configurations .....................................................................99
Table 12 PLCP LOF Declaration/Removal Times.........................................................104
Released
Table 13 SPLT FORM[1:0] Configurations ...................................................................107
Table 14 DS3 FRMR EXZS/LCV Count Configurations................................................131
Table 15 DS3 FRMR AIS Configurations ...................................................................... 132
Table 16 E3 FRMR FORMAT[1:0] Configurations ........................................................141
Table 17 E3 TRAN FORMAT[1:0] Configurations.........................................................154
Table 18 J2 FRMR LOS Threshold Configurations.......................................................161
Table 19 RDLC PBS[2:0] Data Status...........................................................................178
Table 20 RXCP-50 HCS Filtering Configurations .........................................................193
Table 21 RXCP-50 Cell Delineation Algorithm Base ....................................................193
Table 22 RXCP-50 LCD Integration Periods.................................................................201
Table 23 TXCP-50 FIFO Depth Configurations ............................................................213
Table 24 TTB Payload Type Match Configurations ......................................................227
Table 25 PRGD Pattern Detector Register Configuration............................................. 237
Table 26 PRGD Generated Bit Error Rate Configurations............................................243
Table 27 Test Mode Register Memory Map .................................................................. 249
Table 28 Test Mode 0 Input Read Address Locations.................................................251
Table 29 Test Mode 0 Output Write Address Locations ...............................................253
Table 30 Instruction Register ........................................................................................255
Table 31 Identification Register.....................................................................................256
Table 32 Boundary Scan Register ................................................................................256
Table 33 Register Settings for Basic Configurations.....................................................260
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Document ID: PMC-1990267, Issue 3
S/UNI®-JET Data Sheet
Table 34 PLCP Overhead Processing ..........................................................................264
Table 35 PLCP Path Overhead Identifier Codes ..........................................................266
Table 36 DS3 PLCP Trailer Length...............................................................................266
Table 37 E3 PLCP Trailer Length .................................................................................267
Table 38 DS3 Frame Overhead Operation ...................................................................268
Table 39 G.751 E3 Frame Overhead Operation ...........................................................269
Table 40 G.832 E3 Frame Overhead Operation ...........................................................270
Table 41 J2 Frame Overhead Operation.......................................................................272
Table 42 Pseudo Random Pattern Generation (PS bit = 0)..........................................286
Table 43 Repetitive Pattern Generation (PS bit = 1)..................................................... 287
Table 44 DS3 Receive Overhead Bits...........................................................................299
Table 45 DS3 Transmit Overhead Bits.........................................................................307
Table 46 Absolute Maximum Ratings............................................................................319
Table 47 DC Characteristics .........................................................................................320
Released
Table 48 Microprocessor Interface Read Access (Figure 75).......................................322
Table 49 Microprocessor Interface Write Access (Figure 76) .......................................323
Table 50 RSTB Timing (Figure 77) ...............................................................................325
Table 51 Transmit ATM Cell Interface Timing (Figure 78) ............................................325
Table 52 Receive ATM Cell Interface Timing (Figure 79) .............................................327
Table 53 Transmit Interface Timing (Figure 80) ............................................................329
Table 54 Receive Interface Timing (Figure 81) .............................................................334
Table 55 JTAG Port Interface (Refer to Figure 82) .......................................................336
Table 56 Packaging Information....................................................................................339
Table 57 Thermal Information ....................................................................................... 339
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Document ID: PMC-1990267, Issue 3
1 Features
The S/UNI®-JET is a single chip Asynchronous Transfer Mode (ATM) User Network Interface
(UNI) operating at 44.736 Mbit/s, 34.368 Mbit/s, and 6.312 Mbit/s that:
• Conforms to AF-Physical (PHY)-0054.000, AF-PHY-0034.000 and AF-PHY-0029.000.
• Implements ATM Direct Cell Mapping into DS1, DS3, E1, E3, and J2 transmission systems
according to ITU-T Recommendation G.804.
• Provides a UTOPIA Level 2 compatible ATM-PHY Interface.
• Implements the Physical Layer Convergence Protocol (PLCP) for DS1 and DS3 transmission
systems according to the ATM Forum User Network Interface Specification and ANSI TATSY-000773, TA-TSY-000772, and E1 and E3 transmission systems according to the ETSI
300-269 and ETSI 300-270.
• Supports Switched Multi-megabit Data Service (SMDS) and ATM mappings into various rate
transmission systems as shown in Table 1:
S/UNI®-JET Data Sheet
Released
Table 1 Supported Operating Formats
Rate Format Framer Only SMDS PLCP
Mapping
T3
(44.736 Mbit/s)
E3
(34.368 Mbit/s)
J2
(6.312 Mbit/s)
E1
(2.048 Mbit/s)
T1
(1.544 Mbit/s)
Arbitrary Cell Rate
(up to 52 Mbit/s)
C-bit Parity YES YES YES
M23 YES YES YES
G.751 YES YES YES
G.832 YES n/a YES
G.704 & NTT YES n/a YES
CRC-4 external YES YES
PCM30 external YES YES
ESF external YES YES
SF external YES YES
bypass n/a YES
• Implements the ATM physical layer for Broadband ISDN according to ITU-T
Recommendation I.432.
• Provides on-chip DS3, E3 (G.751 and G.832), and J2 framers.
• Is configurable for sole DS3, E3, or J2 Framer use.
ATM Direct
Mapping
Note: When configured to operate as a DS3, E3, or J2 Framer, gapped transmit and receive clocks
can be optionally generated for interface to devices which only need access to payload data bits.
• Provides support for an arbitrary rate external transmission system interface up to a maximum
rate of 52 Mbit/s, which enables the S/UNI-JET to be used as an ATM cell delineator.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 17
Document ID: PMC-1990267, Issue 3
S/UNI®-JET Data Sheet
Released
• Uses the PMC-Sierra™ PM4351 COMET, PM4341 T1XC and PM6341 E1XC T1 and E1
framer/line interface chips for DS1 and E1 applications.
• Provides programmable pseudo-random test pattern generation, detection, and analysis
features.
• Provides integral transmit and receive HDLC controller with 128-byte FIFO depth.
• Provides performance monitoring counters suitable for accumulation periods of up to 1
second.
• Provides an 8-bit microprocessor interface for configuration, control and status monitoring.
• Provides a standard 5 signal P1149.1 JTAG test port for boundary scan board test purposes.
• Uses low power 3.3V CMOS technology with 5V tolerant inputs.
• Is available in a 256-pin SBGA package (27mm x 27mm).
The receiver section of the S/UNI-JET:
• Provides frame synchronization for the M23 or C-bit parity DS3 applications and alarm
detection. Also:
° Accumulates line code violations, framing errors, parity errors, path parity errors and
FEBE events.
° Detects far end alarm channel codes.
° Provides an integral HDLC receiver to terminate the path maintenance data link.
• Provides frame synchronization for the G.751 or G.832 E3 applications and alarm detection.
Also:
° Accumulates line code violations, framing errors, parity errors, and FEBE events.
° Detects the Trail Trace in G.832, the Trail Trace is detected.
° Provides an integral HDLC receiver is provided to terminate either the Network
Requirement or the General Purpose data link.
• Provides frame synchronization for G.704 and NTT 6.312 Mbit/s J2 applications and alarm
detection. Also:
° Accumulates line code violations, framing errors, and CRC parity errors.
° Provides an integral HDLC receiver to terminate the data link.
• Provides frame synchronization, cell delineation and extraction for DS3, G.751 E3, G.832 E3,
and G.704 and NTT J2 ATM direct-mapped formats.
• Provides PLCP frame synchronization, path overhead extraction, and cell extraction for DS1
PLCP, DS3 PLCP, E1 PLCP, and G.751 E3 PLCP formatted streams.
• Provides a 50 MHz 8-bit wide or 16-bit wide Utopia FIFO buffer in the receive path with
parity support, and multi-PHY (Level 2) control signals.
• Provides ATM framing using cell delineation. Note: ATM cell delineation may optionally be
disabled to allow passing of all cell bytes regardless of cell delineation status.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 18
Document ID: PMC-1990267, Issue 3
S/UNI®-JET Data Sheet
Released
• Provides cell descrambling, header check sequence (HCS) error detection, idle cell filtering,
header descrambling (for use with PPP packets), and accumulates the number of received idle
cells, the number of received cells written to the FIFO, and the number of HCS errors.
• Provides a four cell FIFO for rate decoupling between the line, and a higher layer processing
entity. FIFO latency may be reduced by changing the number of operational cell FIFOs.
• Provides a receive HDLC controller with a 128-byte FIFO to accumulate data link
information.
• Provides detection of yellow alarm and loss of frame (LOF), and accumulates BIP-8 errors,
framing errors and FEBE events.
32
• Provides programmable pseudo-random test-sequence detection (up to 2
-1 bit length
patterns conforming to ITU-T O.151 standards) and analysis features.
The transmitter section of the S/UNI-JET:
• Provides frame insertion for the M23 or C-bit parity DS3 applications, alarm insertion, and
diagnostic features. Also:
° Optionally inserts far end alarm channel codes.
° Provides an integral HDLC transmitter is provided to insert the path maintenance data
link.
• Provides frame insertion for the G.751 or G.832 E3 applications, alarm insertion, and
diagnostic features. Also:
° Inserts the Trail Trace for G.832
° Provides an integral HDLC transmitter to insert either the Network Requirement or the
General Purpose data link.
• Provides frame insertion for G.704 6.312 Mbit/s J2 applications, alarm insertion, and
diagnostic features, and also an integral HDLC transmitter to insert the path maintenance data
link.
• Provides frame insertion and path overhead insertion for DS1, DS3, E1 or E3 based PLCP
formats, and also alarm insertion and diagnostic features.
• Provides a 50 MHz 8-bit wide or 16-bit wide Utopia FIFO buffer in the transmit path with
parity support and multi-PHY (Level 2) control signals.
• Provides optional ATM cell scrambling, header scrambling (for use with PPP packets), HCS
generation/insertion, programmable idle cell insertion, diagnostics features and accumulates
transmitted cells read from the FIFO.
• Provides a four cell FIFO for rate decoupling between the line and a higher layer processing
entity. FIFO latency may be reduced by changing the number of operational cells in the FIFO.
• Provides a transmit HDLC controller with a 128-byte FIFO.
• Provides an 8 kHz reference input for locking the transmit PLCP frame rate to an externally
applied frame reference.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 19
Document ID: PMC-1990267, Issue 3
S/UNI®-JET Data Sheet
Released
• Provides programmable pseudo-random test sequence generation (up to 232-1 bit length
sequences conforming to ITU-T O.151 standards). Diagnostic abilities include single bit error
insertion or error insertion at bit error rates ranging from 10-1 to 10-7.
The bypass and loopback features of the S/UNI-JET:
• Allow bypassing of the DS3, E3, and J2 framers to enable transmission system sublayer
processing by an external device.
• Allow bypassing of the PLCP and ATM functions to enable use of the S/UNI-JET as a DS3,
E3, or J2 framer.
• Provide diagnostic loopbacks, line loopbacks, and payload loopbacks.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 20
Document ID: PMC-1990267, Issue 3
2 Applications
• ATM or SMDS Switches, Multiplexers, and Routers
• SONET/SDH Mux E3/DS3 Tributary Interfaces
• PDH Mux J2/E3/DS3 Line Interfaces
• DS3/E3/J2 Digital Cross Connect Interfaces
• DS3/E3/J2 PPP Internet Access Interfaces
• DS3/E3/J2 Frame Relay Interfaces
• DSLAM Uplinks
S/UNI®-JET Data Sheet
Released
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 21
Document ID: PMC-1990267, Issue 3
3 References
• ANSI T1.627 - 1993, "Broadband ISDN - ATM Layer Functionality and Specification".
• ANSI T1.107a - 1990, "Digital Hierarchy - Supplement to Formats Specifications (DS3
Format Applications)".
• ANSI T1.107 - 1995, "Digital Hierarchy - Formats Specifications".
• ANSI T1.646 - 1995, "Broadband ISDN - Physical Layer Specification for User-Network
Interfaces Including DS1/ATM".
• ATM Forum - ATM User-Network Interface Specification, V3.1, October, 1995.
• ATM Forum - “UTOPIA, An ATM PHY Interface Specification, Level 2, Version 1”, June,
1995.
• ATM Forum, af-PHY-0034.000, "E3 (34,368 kbps) Physical Layer Interface", August, 1995.
• ATM Forum, af-PHY-0054.000, "DS3 Physical Layer Interface Specification", January, 1996.
• ATM Forum, af-PHY-0029.000, "6,312 Kbps UNI Specification, Version 1.0", June 1995.
S/UNI®-JET Data Sheet
Released
• Bell Communications Research, TA-TSY-000773 - “Local Access System Generic
Requirements, Objectives, and Interface in Support of Switched Multi-megabit Data Service”
Issue 2, March 1990 and Supplement 1, December 1990.
• ETS 300 269 Draft Standard T/NA(91)17 - “Metropolitan Area Network Physical Layer
Convergence Procedure for 2.048 Mbit/s”, April 1994.
• ETS 300 270 Draft Standard T/NA(91)18 - “Metropolitan Area Network Physical Layer
Convergence Procedure for 34.368 Mbit/s”, April 1994.
• ITU-T Recommendation O.151 - "Error Performance Measuring Equipment Operating at the
Primary Rate and Above", October, 1992.
• ITU-T Recommendation I.432 - "B-ISDN User-Network Interface - Physical Layer
Specification", 1993
• ITU-T Recommendation G.703 - "Physical/Electrical Characteristics of Hierarchical Digital
Interfaces", 1991.
• ITU-T Recommendation G.704 - "General Aspects of Digital Transmission Systems;
Terminal Equipment - Synchronous Frame Structures Used At 1544, 6312, 2048, 8488 and 44
736 kbit/s Hierarchical Levels", July, 1995.
• ITU-T Recommendation G.751 - CCITT Blue Book Fasc. III.4, "Digital Multiplex Equipment
Operating at the Third Order Bit Rate of 34,368 kbit/s and the Fourth Order Bit Rate of
139,264 kbit/s and Using Positive Justification", 1988.
• ITU-T Draft Recommendation G.775 - "Loss of Signal (LOS) and Alarm Indication Signal
(AIS) Defect Detection and Clearance Criteria", October 1993.
• ITU-T Recommendation G.804 - "ATM Cell Mapping into Plesiochronous Digital Hierarchy
(PDH)", 1993.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 22
Document ID: PMC-1990267, Issue 3
S/UNI®-JET Data Sheet
Released
• ITU-T Recommendation G.832 - "Transport of SDH Elements on PDH Networks: Frame and
Multiplexing Structures", 1993.
• ITU-T Recommendation Q.921 - "ISDN User-Network Interface - Data Link Layer
Specification", March, 1993.
• NTT Technical Reference, "NTT Technical Reference for High-Speed Digital Leased Circuit
Services", 1991.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 23
Document ID: PMC-1990267, Issue 3
4 Definitions
The following table defines the abbreviations for the S/UNI-JET.
AIC Application Identification Channel
AIS Alarm Indication Signal
ATM Asynchronous Transfer Mode
BIP Bit Interleaved Parity
CMOS Complementary Metal Oxide Semiconductor
COFA Change of Frame Alignment
CPERR Path Parity Error
CRC Cyclic Redundancy Check
DSLAM DSL Access Multiplexer
DS1 Digital Signal Level 1
DS3 Digital Signal Level 3
EXZS Excess Zeros
F-bit Framing Bit
FAS Framing Alignment Signal
FEAC Far-End Alarm Control
FEBE Far-End Block Error
FERF Far End Receive Failure
FERR Framing Bit Error
FIFO First-In First-Out
HCS Header Check Sequence
HDLC High-level Data Link Control
ISDN Integrated Services Digital network
ITU International Telecommunications Union
JTAG Joint Test Action Group
LCD Loss of Cell Delineation
LCV Line Code Violation
LOF Loss of Frame
LOS Loss of Signal
NRZ Non Return to Zero
OOF Out of Frame
PERR Parity Error
PHY Physical Layer
PLCP Physical Layer Convergence Procedure
PMDL Path Maintenance Data Link
PMON Performance Monitor
POS Packet Over SONET
PPP Point-to-Point Protocol
S/UNI®-JET Data Sheet
Released
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 24
Document ID: PMC-1990267, Issue 3
RAI Receive Alarm Indication
RBOC Bit Oriented Code Detector
RDLC Data Link Receiver
RED Receive Error Detection
SBGA Super Ball Grid Array
SCI-PHY
TM
SATURN® Compatible Interface Specification for PHY and ATM
layer devices
SMDS Switched Multi-Megabit Data Service
SONET Synchronous Optical Network
TAP Test Access Port
TSB Telecom System Block
TTB Trail Trace Buffer
S/UNI®-JET Data Sheet
Released
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 25
Document ID: PMC-1990267, Issue 3
5 Application Examples
The S/UNI-JET is configurable as:
• An ATM device
• A J2/E3/T3 framer
• A cell processor
As an ATM-PHY layer device, the S/UNI-JET connects on the line side to one J2/E3/T3 line
interface unit and on the system side, it interfaces with an ATM layer device, such as the PM7322
RCMP-800, over an 8- or 16-bit wide UTOPIA Level 2 interface. Refer to Figure 1.
Figure 1 S/UNI-JET Operating as an ATM PHY in an ATM Switch
T1/E1 Line Card
PM4314
QDSX
J2/E3/T3 Line Card
J2/E3/T3
LIU
PM7344
S/UNI-MPH
PM7347
S/UNI-JET
S/UNI®-JET Data Sheet
Released
OC-12 Line Card
UTOPIA Bus
ATM Switch Core
Switch
Fabric
PM7322
RCMP-800
UTOPIA Bus
Egress
Device
PM5355
S/UNI-622
OC-3 Line Cards
PM5346
S/UNI-LITE
PM7348
S/UNI-
DUAL
PM5347
S/UNI-PLUS
PMD
As a J2/E3/T3 framer, the S/UNI-JET can be used in router, frame relay switch, and multiplexer
applications. Refer to Figure 2.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 26
Document ID: PMC-1990267, Issue 3
S/UNI®-JET Data Sheet
Figure 2 S/UNI-JET Operating as a Framer Device in Frame Relay Equipment
Released
Access Side
Unchannelized J2/E3/T3 Card
8 Port Channelized T1 Card
PM4314
QDSX
PM4314
QDSX
28 Port Unchannelized T1 Card (M13)
DS-3
LIU
PM4388
TOCTL
4 Port Channelized E1 Card
PM6344
EQUAD
PM4388
TOCTL
PM8313
D3MX
FREEDM-8
FREEDM-8
PM7366
PM7366
PM7364
FREEDM-
IP Switch/Router Core
Switch
Fabric
Processor
Packet
Memory
PCI Bus
32
PCI Bus
PM7366
FREEDM-8
PM7347
S/UNI-
JET
In an unchannelized J2/E3/T3 line card, the S/UNI-JET directly connects to one PM7366
FREEDM-8 HDLC controller. Each FREEDM-8 can process two high-speed links such as T3 and
E3, or can process up to eight lower speed links such as J2. The S/UNI-JET gaps all the overhead
bits so that only the payload data is passed to and from FREEDM-8. On the line side, the S/UNIJET is connected to one J2/E3/T3 line interface unit. On the system side, the S/UNI-JET
interfaces with a data link device over a serial bit interface.
Uplink Side
J2/E3/T3
LIU
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Document ID: PMC-1990267, Issue 3
6 Block Diagram
Figure 3 Block Diagram
S/UNI®-JET Data Sheet
Released
TPOHFP/TFPO/TMFPO/TGAPCLK/TCELL
TIOHM/TFPI/TMFPI
TPOS/TDATO
TNEG/TOHM
TCLK
RCLK
RPOS/RDATI
RNEG/RLCV/ROHM
RBOC
Rx
FEAC
XBOC
Tx
FEAC
Line
Encode
Line
Decode
RDLC
HDLC
TDPR
Tx
HDLC
J2, E3, or DS3
Transmit Framer
J2, E3, or DS3
Receive Framer
Rx
Monitor
TRAN
FRMR
PMON
Perfor.
TOHINS
Tx O/H
Access
TOH
TOHCLK
TOHFP
Rx O/H
Access
ROH
1/2 TTB
Tx Trail
Buffer
ROHCLK
1/2 TTB
Rx Trail
Buffer
ROHFP
TPOH/TDATI
TPOHINS
TICLK
SPLT
Transmit ATM and
PLCP Framer
ATMF/ SPLR
Receive ATM
and PLCP Framer
TPOHCLK
LCD/RDATO
RPOH/ROVRHD
REF8KI
PLCP/cell
Performance
Monitor
FRMSTAT
PRGD BER Tester
CPPM
TDO
TXCP_50
Tx Cell
Processor
RXCP_50
Rx Cell
Processor
TCK
TDI
IEEE P1149.1
JTAG Test
Access Port
Tx 4 Cell
Rx 4 Cell
Microprocessor
D[7.0]
A[10.0]
TRSTB
TMS
TXFF
FIFO
RXFF
FIFO
Interface
ALE
CSB
DTCA
TDAT[15.0]
TPRTY
TSOC
TCA
TADR[2.0]
TENB
TFCLK
System
I/F
RDB
INTB
WRB
RSTB
PHY_ADR[2.0]
ATM8
RFCLK
RENB
RADR[2.0]
RCA
RSOC
RPRTY
RDAT[15.0]
DRCA
RPOHCLK/RSCLK/RGAPCLK
REF8KO/RPOHFP/RFPO/RMFPO
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 28
Document ID: PMC-1990267, Issue 3
7 Description
The PM7346 S/UNI-JET is an ATM physical layer processor with integrated DS3, E3, and J2
framers. It supports PLCP sublayer DS1, DS3, E1, and E3 processing and ATM cell delineation.
The S/UNI-JET contains:
• An Integral DS3 framer that provides DS3 framing and error accumulation in accordance
with ANSI T1.107, and T1.107a.
• An Integral E3 framer that provide E3 framing in accordance with ITU-T Recommendations
G.832 and G.751.
• An Integral J2 framer that provide J2 framing in accordance with ITU-T Recommendation
G.704 and I.432.
When configured for various transmission system sublayer processing, the S/UNI-JET accepts
and outputs the appropriate type of bipolar and unipolar signals as described in Table 2:
S/UNI®-JET Data Sheet
Released
Table 2 Transmission System Sublayer Processing Acceptance and Output
Transmission System
Sublayer Processing
DS3 Accepts and outputs both digital B3ZS-encoded bipolar and unipolar
E3 Accepts and outputs both HDB3-encoded bipolar and unipolar signals
J2 Accepts and outputs both B8ZS-encoded bipolar and unipolar signals
DS1, or E1 Accepts and outputs outputs unipolar signals with appropriate clock and
Other transmission systems Provides a generic interface for physical sublayer processing.
Acceptance and Output
signals compatible with M23 and C-bit parity applications.
compatible with G.751 and G.832 applications.
compliant with G.704 and NTT 6.312 Mbit/s applications.
frame pulse signals for physical sublayer processing.
In the DS3 receive direction, the S/UNI-JET frames to DS3 signals with a maximum average
reframe time of 1.5 ms and detects line code violations (LCV), loss of signal (LOS), framing bit
errors, parity errors, path parity errors, alarm indication signals (AIS), far end receive failure
(FERF), and idle code. The DS3 overhead bits are extracted and presented on serial outputs.
When in C-bit parity mode, the Path Maintenance Data Link (PMDL) and the Far End Alarm and
Control (FEAC) channels are extracted. HDLC receivers are provided for PMDL support. Valid
bit-oriented codes in the FEAC channels are also detected and are available through the
microprocessor port.
Table 3 Summary of Receive Detection Features
Transmission System
Sublayer Processing
DS3 Receive
E3 Receive LCV, LOS, framing bit errors, AIS, and RAI
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 29
Document ID: PMC-1990267, Issue 3
Transmit or
Receive
Detected Features
LCV, LOS, framing bit errors, parity errors, path parity
errors, AIS, FERF, and idle code
S/UNI®-JET Data Sheet
Released
Transmission System
Sublayer Processing
J2 Receive
Transmit or
Receive
Detected Features
LCV, LOS, LOF, framing bit errors, physical layer AIS,
payload AIS, CRC-5 errors, Remote End Alarm, and RAI
In the E3 receive direction, the S/UNI-JET frames to G.751 and G.832 E3 signals with a
maximum average reframe times of 135 µs for G.751 frames and 250 µs for G.832 frames. LCVs,
LOS, framing bit errors, AIS, and remote alarm indication (RAI) are detected. Further, when
processing G.832 formatted data, parity errors, far end receive failure, and far end block errors are
also detected; and the Trail Trace message can be extracted and made available through the
microprocessor port. HDLC receivers are provided for either the G.832 Network Requirement or
the G.832 General Purpose Data Link support.
In the J2 receive direction, the S/UNI-JET frames to G.704 6.312 MHz signals with a maximum
average reframe time of 5.07 ms. An alternate framing algorithm that uses the CRC-5 bits to rule
out 99.9% of all static mimic framing patterns is available with a maximum average reframe time
of 10.22 ms when operating with a 10
4
-
bit error rate. The alternate framing algorithm can be
selected by the CRC_REFR bit in the J2-FRMR Configuration Register. LCV, LOS, loss of frame
(LOF), framing bit errors, physical layer AIS, payload AIS, CRC-5 errors, Remote End Alarm,
and RAI are detected. HDLC receivers are provided for Data Link support.
Error event accumulation is also provided by the S/UNI-JET. Framing bit errors, LCV, parity
errors, path parity errors, and far end block errors (FEBE) are accumulated, when appropriate, in
saturating counters for DS3, E3, and J2 frames. LOF detection for DS3, E3, and J2 is provided as
recommended by ITU-T G.783 with integration times of 1ms, 2ms, and 3ms.
In the DS3 transmit direction, the S/UNI-JET inserts DS3 framing, X and P bits. When enabled
for C-bit parity operation, bit-oriented code transmitters and HDLC transmitters are provided for
the insertion of FEAC channels and the PMDL in the appropriate overhead bits. AIS can be
inserted by using internal register bits and other status signals such as the idle signal can be
inserted when enabled by internal register bits. When M23 operation is selected, the C-bit Parity
ID bit (the first C-bit of the first M sub-frame) is forced to toggle so that downstream equipment
will not confuse an M23-formatted stream with stuck-at 1 C-bits for C-bit parity application.
In the E3 transmit direction, the S/UNI-JET inserts E3 framing in either G.832 or G.751 format.
When enabled for G.832 operation, an HDLC transmitter is provided so that the Network
Requirement or General Purpose Data Link is inserted into the appropriate overhead bits. The
AIS and other status signals can be inserted by internal register bits.
In the J2 transmit direction, the S/UNI-JET inserts J2 6.312 Mbit/s G.704 framing. HDLC
transmitters are provided the Data Links are inserted. CRC-5 check bits are calculated and
inserted into the J2 multiframe. External pins are provided so that any of the overhead bits within
the J2 frame can be overwritten.
The S/UNI-JET also supports diagnostic options that allow it to insert, when appropriate, the
transmit framing format, parity or path parity errors, F-bit framing errors, M-bit framing errors,
invalid X or P-bits, LCV, all-zeros, AIS, RAIs, and Remote End Alarms.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 30
Document ID: PMC-1990267, Issue 3
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