PMC PM7340-PI Datasheet

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PMC-2001723 ISSUE 3 INVERSE MULTIPLEXING OVER ATM

PM7340 S/UNI-IMA-8

PM7340

S/UNI-IMA-8

S/UNI INVERSE MULTIPLEXING FOR

ATM, 8 LINKS

DATA SHEET

PROPRIETARY AND CONFIDENTIAL

PRELIMINARY

ISSUE 3: FEBUARY, 2001

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LIST OF FIGURES

FIGURE 1 - MULTI-SERVICE ACCESS – IADS AND ACCESS

CONCENTRATORS. ......................................................................... 10

FIGURE 2 -S/UNI-IMA-8 IN A REMOTE DSLAM WAN UPLINK APPLICATION.11

FIGURE 3 - S/UNI-IMA-8 BLOCK DIAGRAM.................................................. 12

FIGURE 4 - S/UNI-IMA PRELIMINARY PINOUT (BOTTOM VIEW) ............... 15

FIGURE 5 - 16-BIT TRANSMIT CELL TRANSFER FORMAT ......................... 43

FIGURE 6 - 8-BIT TRANSMIT CELL TRANSFER FORMAT ........................... 44

FIGURE 7 - 16-BIT RECEIVE CELL TRANSFER FORMAT ........................... 47

FIGURE 8 - 8-BIT RECEIVE CELL TRANSFER FORMAT ............................. 48

FIGURE 9 - INVERSE MULTIPLEXING.......................................................... 51

FIGURE 10- IFSM STATE MACHINE .............................................................. 58

FIGURE 11 - STUFF EVENT WITH ERRORED ICP (ADVANCED INDICATION)

60

FIGURE 12- INVALID STUFF SEQUENCE (ADVANCED INDICATION) ......... 60

FIGURE 13- ERRORED/INVALID ICP CELLS IN PROXIMITY TO A STUFF

EVENT............................................................................................... 61

FIGURE 14- SNAPSHOT OF DCB BUFFERS................................................. 62

FIGURE 15- SNAPSHOT OF DCB BUFFERS AFTER ADDITION OF LINK WITH

SMALLER TRANSPORT DELAY....................................................... 63

FIGURE 16- SNAPSHOT OF DCB BUFFERS WHEN TRYING TO ADD LINK

WITH LARGER TRANSPORT DELAY............................................... 64

FIGURE 17- SNAPSHOT OF DCB BUFFERS AFTER DELAY ADJUSTMENT 65

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FIGURE 18- SNAPSHOT OF DCB BUFFERS AFTER DELETION OF LINKS

FROM GROUP .................................................................................. 66

FIGURE 19- IMA ERROR/MAINTENANCE STATE DIAGRAM........................ 67

FIGURE 20- CELL STORAGE MAP................................................................. 82

FIGURE 21- 2 MBYTE ..................................................................................... 83

FIGURE 22- 8 MBYTE ..................................................................................... 83

FIGURE 23- CELL DELINEATION STATE DIAGRAM...................................... 86

FIGURE 24-BURST RAM FORMAT............................................................... 121

FIGURE 25- UNCHANNELIZED RECEIVE LINK TIMING ............................. 286

FIGURE 26- CHANNELIZED T1 RECEIVE LINK TIMING ............................. 287

FIGURE 27- CHANNELIZED E1 RECEIVE LINK TIMING ............................. 287

FIGURE 28- UNCHANNELIZED TRANSMIT LINK TIMING........................... 288

FIGURE 29- CHANNELIZED T1 TRANSMIT LINK TIMING W/ CLOCK GAPPED

LOW ................................................................................................ 288

FIGURE 30- CHANNELIZED T1 TRANSMIT LINK TIMING W/ CLOCK GAPPED

HIGH................................................................................................ 289

FIGURE 31- CHANNELIZED E1 TRANSMIT LINK TIMING W/ CLOCK GAPPED

LOW ................................................................................................ 289

FIGURE 32- CHANNELIZED E1 TRANSMIT LINK TIMING W/ CLOCK GAPPED

HOW................................................................................................ 289

FIGURE 33- UTOPIA L2 TRANSMIT SLAVE ................................................. 291

FIGURE 34- ANY-PHY TRANSMIT SLAVE.................................................... 292

FIGURE 35- UTOPIA L2 MULTI-PHY RECEIVE SLAVE................................ 293

FIGURE 36- UTOPIA L2 SINGLE-PHY RECEIVE SLAVE ............................. 293

FIGURE 37- ANY-PHY RECEIVE SLAVE ...................................................... 294

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FIGURE 38- SDRAM READ TIMING ............................................................. 295

FIGURE 39- SDRAM WRITE TIMING............................................................ 296

FIGURE 40- SDRAM REFRESH.................................................................... 297

FIGURE 41- POWER UP AND INITIALIZATION SEQUENCE....................... 298

FIGURE 42- MICROPROCESSOR INTERFACE READ TIMING .................. 304

FIGURE 43- MICROPROCESSOR INTERFACE WRITE TIMING................. 306

FIGURE 44- RSTB TIMING............................................................................ 307

FIGURE 45- SYNCHRONOUS I/O TIMING ................................................... 307

FIGURE 46- JTAG PORT INTERFACE TIMING ............................................ 312

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LIST OF TABLES

TABLE 1 REVISION HISTORY......................................................................... 2

TABLE 2 TERMINOLOGY ............................................................................... 1

TABLE 3 UTOPIA L2 AND ANY-PHY COMPARISON.................................... 45

TABLE 4 PM COMMAND DESCRIPTION.................................................... 70

TABLE 5 REGISTER MEMORY MAP............................................................ 91

TABLE 6 CONFIGURATION MEMORY ADDRESS SPACE ........................ 150

TABLE 7 CONTEXT MEMORY ADDRESS SPACE..................................... 151

TABLE 8 RIPP GROUP CONFIGURATION RECORD STRUCTURE ........ 152

TABLE 9 RX PHYSICAL LINK TABLE ....................................................... 159

TABLE 10 RIPP TX LINK CONFIGURATION RECORD STRUCTURE....... 160

TABLE 11 RIPP RX LINK CONFIGURATION RECORD STRUCTURE ....... 162

TABLE 12 RIPP GROUP CONTEXT RECORD STRUCTURE ..................... 163

TABLE 13 RIPP TX LINK CONTEXT RECORD STRUCTURE..................... 175

TABLE 14 RIPP RX LINK CONTEXT RECORD STRUCTURE .................... 178

TABLE 15 COMMAND REGISTER ENCODING .......................................... 195

TABLE 16 COMMAND DATA REGISTER ARRAY FORMAT ........................ 203

TABLE 17 GROUP ERROR/STATUS BIT MAPPING ................................... 204

TABLE 18 LINK EVENT INTERRUPT BIT MAPPING................................... 207

TABLE 19 LINK STATUS BIT MAPPING ...................................................... 209

TABLE 20 RECEIVE ICP CELL BUFFER STRUCTURE .............................. 213

TABLE 21 RDAT LINK STATISTICS RECORD (IMA) ................................... 219

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TABLE 22 RDAT LINK STATISTICS RECORD (TC)..................................... 220

TABLE 23 RDAT IMA GROUP STATISTICS RECORD................................. 221

TABLE 24 RDAT TC GROUP STATISTICS RECORD.................................. 222

TABLE 25 RDAT VALIDATION RECORD ..................................................... 222

TABLE 26 RDAT LINK CONTEXT RECORD ................................................ 225

TABLE 27 RECEIVE ICP CELL BUFFER STRUCTURE .............................. 230

TABLE 28 RDAT IMA GROUP CONTEXT RECORD.................................... 232

TABLE 29 RDAT TC CONTEXT RECORD ................................................... 233

TABLE 30 RECEIVE ATM CONGESTION COUNT REGISTER ................... 233

TABLE 31 TRANSMIT IMA GROUP CONTEXT RECORD........................... 244

TABLE 32 TRANSMIT GROUP CONFIGURATION TABLE RECORD ........... 247

TABLE 33 TRANSMIT LID TO PHYSICAL LINK MAPPING TABLE ............. 248

TABLE 34 TIMA PHYSICAL LINK CONTEXT RECORD............................... 248

TABLE 35 260

TABLE 36 IMA PERFORMANCE PARAMETER SUPPORT......................... 282

TABLE 37 IMA FAILURE ALARM SUPPORT ............................................... 284

TABLE 38 ABSOLUTE MAXIMUM RATINGS ............................................... 299

TABLE 39 D.C. CHARACTERISTICS........................................................... 300

TABLE 40 MICROPROCESSOR INTERFACE READ ACCESS................... 303

TABLE 41 MICROPROCESSOR INTERFACE WRITE ACCESS ................. 305

TABLE 42 RTSB TIMING.............................................................................. 306

TABLE 43 SYSCLK AND REFCLK TIMING.................................................. 307

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TABLE 44 CELL BUFFER SDRAM INTERFACE.......................................... 307

TABLE 45 ANY-PHY/UTOPIA TRANSMIT INTERFACE ............................... 308

TABLE 46 ANY-PHY/UTOPIA RECEIVE INTERFACE ................................. 308

TABLE 47 SERIAL LINK INPUT.................................................................... 309

TABLE 48 SERIAL LINK OUTPUT................................................................ 310

TABLE 49 JTAG PORT INTERFACE .............................................................311

TABLE 50 ORDERING AND THERMAL INFORMATION.............................. 313

TABLE 51 THERMAL INFORMATION - THETA JA VS. AIRFLOW............... 313

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LIST OF REGISTERS

REGISTER 0X000: GLOBAL RESET............................................................... 98

REGISTER 0X002: GLOBAL CONFIGURATION ............................................. 99

REGISTER 0X004: JTAG ID (MSB)................................................................ 101

REGISTER 0X006: JTAG ID (LSB)................................................................. 101

REGISTER 0X008: MASTER INTERRUPT REGISTER................................. 102

REGISTER 0X00A: MISCELLANEOUS INTERRUPT REGISTER................. 104

REGISTER 0X00C: TC INTERRUPT FIFO .................................................... 106

REGISTER 0X010: MASTER INTERRUPT ENABLE REGISTER ................. 108

REGISTER 0X012: MISCELLANEOUS INTERRUPT ENABLE REGISTER .. 109

REGISTER 0X014: TC INTERRUPT ENABLE REGISTER.............................110

REGISTER 0X020: TRANSMIT ANY-PHY/UTOPIA CELL AVAILABLE ENABLE

111

REGISTER 0X022: RECEIVE UTOPIA CELL AVAILABLE ENABLE...............112

REGISTER 0X024: RECEIVE ANY-PHY/UTOPIA CONFIG REG (RXAPS_CFG)

113

REGISTER 0X026: TRANSMIT ANY-PHY/UTOPIA CONFIG REG (TXAPS_CFG)115

REGISTER 0X028: TRANSMIT ANY-PHY ADDRESS CONFIG REGISTER

(TXAPS_ADD_CFG) ........................................................................117

REGISTER 0X040: SDRAM CONFIGURATION .............................................118

REGISTER 0X042 SDRAM DIAGNOSTICS....................................................119

REGISTER 0X044: SDRAM DIAG BURST RAM INDIRECT ACCESS .......... 120

REGISTER 0X046: SDRAM DIAG INDIRECT BURST RAM DATA LSB ........ 121

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REGISTER 0X048: SDRAM DIAG INDIRECT BURST RAM DATA MSB ....... 121

REGISTER 0X04A: SDRAM DIAG WRITE CMD 1 ........................................ 123

REGISTER 0X04C: SDRAM DIAG WRITE CMD 2 ........................................ 123

REGISTER 0X04E: SDRAM DIAG READ CMD 1.......................................... 124

REGISTER 0X050: SDRAM DIAG READ CMD 2 .......................................... 124

REGISTER 0X060: TTTC INDIRECT STATUS............................................... 125

REGISTER 0X062: TTTC INDIRECT LINK DATA REGISTER #1 .................. 126

REGISTER 0X070: RTTC INDIRECT LINK STATUS ..................................... 127

REGISTER 0X072: RTTC INDIRECT LINK DATA REGISTER #1.................. 129

REGISTER 0X074: RTTC INDIRECT LINK DATA REGISTER #2.................. 132

REGISTER 0X076: RTTC INDIRECT LINK DATA REGISTER #3.................. 134

REGISTER 0X078: LCD COUNT THRESHOLD ............................................ 135

REGISTER 0X100: RCAS INDIRECT LINK AND TIME-SLOT SELECT ........ 135

REGISTER 0X102: RCAS INDIRECT LINK DATA ......................................... 137

REGISTER 0X104: RCAS FRAMING BIT THRESHOLD ............................... 139

REGISTER 0X106: RCAS LINK DISABLE ..................................................... 140

REGISTER 0X140- 0X14E: RCAS LINK #0 TO LINK #7 CONFIGURATION. 141

REGISTER 0X180: TCAS INDIRECT LINK AND TIME-SLOT SELECT......... 142

REGISTER 0X182: TCAS INDIRECT CHANNEL DATA................................. 144

REGISTER 0X184: FRAMING BIT THRESHOLD .......................................... 145

REGISTER 0X186: TCAS IDLE TIME-SLOT FILL DATA................................ 146

REGISTER 0X188: TCAS CHANNEL DISABLE REGISTER ......................... 147

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REGISTER 0X1C0 – 0X1CE: TCAS LINK #0 TO LINK #7 CONFIGURATION148

REGISTER 0X200:RIPP CONTROL .............................................................. 149

REGISTER 0X202:RIPP INDIRECT MEMORY ACCESS CONTROL ............ 150

REGISTER 0X204 – 0X206:RIPP INDIRECT MEMORY DATA REGISTER

ARRAY............................................................................................. 152

REGISTER 0X20C: RIPP TIMER TICK CONFIGURATION REGISTER ........ 185

REGISTER 0X20E: GROUP TIMEOUT REGISTER # 1 ................................ 186

REGISTER 0X210: GROUP TIMEOUT REGISTER # 2................................. 187

REGISTER 0X212: TX LINK TIMEOUT REGISTER ...................................... 188

REGISTER 0X214: RX LINK TIMEOUT REGISTER...................................... 189

REGISTER 0X216: RIPP INTERRUPT STATUS REGISTER......................... 190

REGISTER 0X218:RIPP GROUP INTERRUPT ENABLE REGISTER........... 191

REGISTER 0X21A:RIPP TX LINK INTERRUPT ENABLE REGISTER .......... 192

REGISTER 0X21C:RIPP RX LINK INTERRUPT ENABLE REGISTER.......... 193

REGISTER 0X220-22C: RIPP COMMAND REGISTER ................................. 194

REGISTER 0X22E: COMMAND READ DATA CONTROL REGISTER........... 198

REGISTER 0X230: ICP CELL FORWARDING STATUS REGISTER............. 199

REGISTER 0X232: ICP CELL FORWARDING CONTROL REGISTER ......... 200

REGISTER 0X240- 0X29E:RIPP COMMAND DATA REGISTER ARRAY ...... 201

REGISTER 0X2C0- 0X2FE: FORWARDING ICP CELL BUFFER.................. 212

REGISTER 0X300: RDAT INDIRECT MEMORY COMMAND ........................ 215

REGISTER 0X302: RDAT INDIRECT MEMORY ADDRESS.......................... 217

REGISTER 0X304: RDAT INDIRECT MEMORY DATA LSB .......................... 218

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REGISTER 0X306: RDAT INDIRECT MEMORY DATA MSB ......................... 219

REGISTER 0X308: RDAT CONFIGURATION ................................................ 234

REGISTER 0X30A: RECEIVE ATM CONGESTION STATUS ........................ 236

REGISTER 0X30E: RECEIVE TC OVERRUN STATUS................................. 237

REGISTER 0X310: RDAT MASTER INTERRUPT STATUS........................... 238

REGISTER 0X312: RECEIVE ATM CONGESTION INTERRUPT ENABLE... 239

REGISTER 0X316: RDAT MASTER INTERRUPT ENABLE .......................... 240

REGISTER 0X320: TIMA INDIRECT MEMORY COMMAND ......................... 241

REGISTER 0X322: TIMA INDIRECT MEMORY ADDRESS........................... 242

REGISTER 0X324: TIMA INDIRECT MEMORY DATA LSB............................ 243

REGISTER 0X326: TIMA INDIRECT MEMORY DATA MSB........................... 244

REGISTER 0X328 TX LINK FIFO OVERFLOW STATUS .............................. 251

REGISTER 0X336 INTERRUPT ENABLE...................................................... 252

REGISTER 0X340: TXIDCC INDIRECT LINK ACCESS................................. 252

REGISTER 0X342: TXIDCC INDIRECT LINK DATA REGISTER 1 ................ 254

REGISTER 0X350: RXIDCC INDIRECT LINK ACCESS ................................ 254

REGISTER 0X352: RXIDCC INDIRECT LINK DATA REGISTER 1................ 256

REGISTER 0X366: DLL CONTROL STATUS................................................. 257

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1 DEFINITIONS

Table 2 Terminology

Term Definition

Any-PHY Interoperable version of UTOPIA and UTOPIA L2, with

inband addressing.

ATM Asynchronous Transfer Mode

CDV Cell Delay Variation

CTC Common Transmit Clock

DLL Delay Locked Loop

ECBI Enhanced Common Bus Interface (asynchronous

register bus and interface)

FIFO First-In-First-Out

Framed Framing information available – may be channelized or

unchannelized.

HEC Header Error Check

HCS Header Check Sequence

ICP IMA Control Protocol Cell

IDCC IMA Data Cell Clock

IDCR IMA Data Cell Rate

IFSN IMA Frame Sequence Number

IMA Inverse Multiplexing for ATM

ITC Independent Transmit Clock

LCD Loss of Cell Delineation

LID Link ID

LSI Link Stuff Indication

MIB Management Information Base

MCFD Multi-Channel Cell Based FIFO

OAM Operation, Administration and Maintenance

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OCD Out of Cell Delineation

PISO Parallel in Serial Out

PM Plane Management

RCAS Receive Channel Assigner

RDAT RX IMA Data Processor

RIPP RX IMA Protocol Processor

RMTS RX Master TX Slave

SIPO Serial in Parallel Out

SPE Synchronous Payload Envelope

TC Transmission Convergence

TCAS Transmit Channel Assigner

TDM Time Division Multiplexing

TRL Timing Reference Link

TRLCR TRL Cell Rate

TSB Telecom Systems Block

TC Transmission Convergence

TIMA TX IMA Processor

Unframed No framing information available

UTOPIA Universal Test & Operations PHY Interface for ATM

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2 FEATURES

The PM7340 S/UNI-IMA-8 is a monolithic integrated circuit that implements the Inverse Multiplexing for ATM (IMA 1.1) protocol with backward compatibility to IMA 1.0 and the Transmission Convergence (TC) layer function. The S/UNIIMA-8 supports 8 T1, E1 or unchannelized links where each link is dynamically configurable to support either IMA 1.1, backward compatible IMA 1.0, ATM over T1/E1, ATM over fractional T1/E1 or ATM HEC cell delination for unchannelized links Unchannelized links may be used to support applications such as ADSL.

Standards Supported

• ATM Forum Inverse Multiplexing for ATM Specification Version 1.1, March

1999

• ATM Forum Inverse Multiplexing for ATM Specification Version 1.0 – supports

the method of reporting Rx cell information as in Appendix C.8 of the ATM Forum Inverse Multiplexing for ATM Specification Version 1.1 for symmetrical configurations with M=128.

• I.432-1 B-ISDN user network interface – Physical Layer specification: General

characteristics

• I.432-3 B-ISDN user network interface – Physical Layer specification: 1544

kbps and 2048 kbps operation

• ATM on Fractional E1/T1, af-phy-0130.00 October, 1999

IMA Features

• IMA 1.1 protocol including group and link state machines implemented by on-

chip hardware.

• Supports up to 4 simultaneous IMA groups.

• Each IMA group can support any number of supported links.

• Each link can be programmed for either IMA processing or cell delineation.

• Supports all IMA Group Symmetry modes:

• Symmetrical configuration with symmetrical operation

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• Symmetrical configuration with asymmetrical operation.

• Asymmetrical configuration with asymmetrical operation.

• Performs IMA differential delay calculation and synchronization.

• Provides programmable limit on allowable differential delay and minimum

number of links per group.

• Supports up to 279 ms (for T1 links) and 226 ms (for E1 links) link-differential

delay between links in an IMA group.

• Performs ICP and stuff-cell insertion and removal.

• Supports both Common Transmit Clock (CTC) and Independent Transmit

Clock (ITC) transmit ICP stuffing modes.

• Supports IMA frame length (M) equal to 32, 64, 128, or 256.

• Optionally supports the IMA 1.0 method of reporting Rx cell information as

defined in appendix C.8 of the ATM Forum Inverse Multiplexing for ATM Specification Version 1.1 for symmetrical configurations with M=128.

• Provides IMA layer statistic counts and alarms for support of IMA

Performance and Failure Alarm Monitoring and MIB support.

• Provides per link counters for statistics and performance monitoring:

• ICP Violations

• OIF anomalies

• Rx Link stuff events

• Tx Link stuff events

• User cells

• Filler cells

• Provides per group counters for statistics and performance monitoring:

• User cells received

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• Filler cells received

• User cells transmitted

• Filler cells transmitted

TC Features

• Performs cell delineation on all links.

• Performs receive cell Header Error Check (HEC) checking and transmit cell

HEC generation.

• Optionally supports receive cell payload unscrambling and transmit cell

payload scrambling.

• Provides TC layer statistics counts and alarms for MIB support.

Interface Support

• Supports 8 individual serial T1, E1 or unchannelized links via a 2-pin clock

and data interface.

• Supports ATM over fractional T1/E1 by providing the capability to select any

DS0 timeslots that are active in a link.

• Serial link interface supports both independent transmit clock (ITC) and

common transmit clock (CTC) options.

• Interfaces to a 1M x 16 SDRAM for 279 msec of T1, 226 msec of E1

differential delay tolerance through a 16-bit SDRAM interface.

• Provides a 16-bit microprocessor bus interface for configuration and Link and

Unit Management.

• ATM receive interface supports 8- and 16-bit UTOPIA L2 or Any-PHY cell

interfaces at clock rates up to 52 MHz.

• Any-PHY receive slave appears as a single device. The PHY-ID of each cell is

identified in the in-band address.

• UTOPIA L2 receive slave appears as a 31 port multi-PHY.

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• UTOPIA L2 receive slave can also appear as a single port with the logical port

provided as a prepend or in the HEC/UDF field.

• ATM transmit interface supports 8- and 16-bit UTOPIA L2 and Any-PHY cell

interfaces at clock rates up to 52 MHz.

• Each link configured for cell delineation or each IMA group appears as a PHY

port on the Any-PHY and UTOPIA L2 bus.

• Any-PHY transmit slave appears as an 8-port multi-PHY. The PHY-ID of each

cell is identified in the in-band address.

• UTOPIA L2 transmit slave appears as an 8-port multi-PHY.

• Seamlessly interconnects to PMC-Sierra’s PM7326 S/UNI-APEX ATM/Packet

Traffic Manager and Switch and PM7324 S/UNI-ATLAS ATM layer device.

Loopback and Diagnostic Features

• Supports UTOPIA L2/Any-PHY Loopback (global loopback– where all cells

received on the UTOPIA L2 / Any-PHY interface are looped back out)

• Supports Line Side Loopback (global loopback– where all data received on

the line side is looped back out)

• Supports the capability to trace ICP cells for any group

Software

• The S/UNI-IMA device driver, written in ANSI C, provides a well-defined

Application Programming Interface (API) for use by application software. Low level utility functions are also provided for diagnostics and debugging purposes. Software wrappers are used for RTOS-related functions making the S/UNI-IMA device driver portable to any Real Time Operating System (RTOS) and hardware environment. The S/UNI-IMA device driver is compatible across the S/UNI-IMA family of devices.

Packaging

• Implemented in low power, 0.18 micron, 1.8V CMOS technology with TTL

compatible inputs and outputs.

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• Provides a standard 5-pin P1149 JTAG port.

• 324 ball PBGA, 23mm x 23mm

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3 APPLICATIONS

• Digital Subscriber Line Access Multiplexers (DSLAMs)

• Access Concentrators

• Integrated Access Devices (IAD)

• Wireless Base Transceiver Stations

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4 REFERENCES

• AF-PHY-0086.001 “Inverse Multiplexing for ATM (IMA) Specification Version

1.1”, March 1999

• I.432-1 B-ISDN User Network Interface – Physical Layer specification:

General characteristics

• I.432-3 B-ISDN User Network Interface – Physical Layer specification: 1544

kbps and 2048 kbps operation

• G.804 “ATM Cell Mapping into Plesiochronous Digital Hierarchy (PDH)”

• AF-PHY-0016.000 “ATM Forum DS1 Physical Layer Specification”

• AF-PHY-0064.000 “ATM Forum E1 Physical Interface”

• ATM Forum, UTOPIA, an ATM-PHY Layer Specification, Level 2, V. 1.0,

Foster City, CA USA, June 1995.

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5 APPLICATION EXAMPLES

5.1 Multi-Service Access – IADs, Access Concentrators

Multi-Service access equipment such as Integrated Access Devices (IADs) and Access Concentrators consolidate voice, data, Internet, and video wide-area network services over ATM unifying the functions of many different types of equipment including CSUs, DSUs, multiplexers and FRADs. Figure 1 illustrates an example of a multi-service access box using IMA over multiple T1/E1 lines for WAN access.

Figure 1 - Multi-Service Access – IADs and Access Concentrators.

AAL1

PM73124

AAL1gator-4

AAL2

PM73140

MECA-4A

Frame Relay over AAL5

PM7366

FREEDM-8

IWF/AAL5

SAR

UTOPIA L2 /

Any-PHY

On the lineside, the S/UNI-IMA-8 interfaces seamlessly to standard devices such as the PM4354 COMET-QUAD T1/E1 Framer plus LIU.

5.2 Remote DSLAM WAN Uplink

IMA is ideally suited for remote DSLAM applications for several reasons. Firstly, remote DSLAMs are physically located at remote sites of which many are served by T1 or E1 lines. Secondly, the benefits of ATM have resulted in its almost exclusive use in DSLAMs. Coupled with ATM, DSLAMs enable service providers to utilize the bandwidth of the T1/E1 infrastructure for delivering integrated services such as high-speed Internet access and real-time voice and video. ATM over T1/E1 is a suitable DSLAM WAN uplink technology and IMA, due to its

PM7326

S/UNI-APEX

PM7324

S/UNI-ATLAS

UTOPIA L2

PM7340

S/UNI-IMA-8

Clock/Data

PM4354

COMET-

QUAD x 2

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 10

PRELIMINARY

INVERSE MULTIPLEXING OVER ATM

DATA SHEET

PMC-2001723 ISSUE 3 INVERSE MULTIPLEXING OVER ATM

PM7340 S/UNI-IMA-8

benefits of higher bandwidth, statistical gain and fault tolerance, is even more suitable.

Figure 2 illustrates an example of the S/UNI-IMA-8 in a remote DSLAM WAN uplink application.

Figure 2 -S/UNI-IMA-8 in a Remote DSLAM WAN Uplink Application.

UTOPIA L2 /

Any-PHY

PM7326

S/UNI-APEX

UTOPIA L2

Clock/Data

PM7351

S/UNI-VORTEX

PM7324

S/UNI-ATLAS

PM7340

S/UNI-IMA-8

PM4354

COMET-

QUAD x 2

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 11

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INVERSE MULTIPLEXING OVER ATM

DATA SHEET

PMC-2001723 ISSUE 3 INVERSE MULTIPLEXING OVER ATM

PM7340 S/UNI-IMA-8

6 BLOCK DIAGRAM

IMA-8 Block Diagram

Figure 3 - S/UNI-IMA-8 Block Diagram

TSCLK[7:0]

TSDATA[7:0]

CTSCLK

RSCLK[7:0]

RSDATA[7:0]

TCAS

RCAS

RSTB

OE

TC Layer (TTTC-8)

TC Layer (RTTC-8)

REFCLK

8-chan x 7 cell

FIFO

(MCFD)

8-chan

FIFO

x 2 cell

DLL

SYSCLK

Tx IMA Processor

IDCC

Internal Bus

IDCC

Rx IMA Data Processor

Cell Writer Ce ll Reader

Memory Interface

D[15:0]

A[10:1]

ALE

WRB

RDB

CSB

INTB

MicroProcess I/F JTAG

8-chan

(TIMA)

Rx IMA

Protocol

Processor

(RIPP)

(RDAT)

(MEMI)

x 3 cell

FIFO

chan 4 cell FIFO

TCK

8

TMS

TDI

TRSTB

TDO

Any-

PHY/ UTOPIA Tx Slave (TXAPS)

Any-

PHY/ UTOPIA Rx Slave (RXAPS)

Tx Slave ATM I/F

TCLK TPA TENB TADR[6:0] TCSB TSOP TSX TDAT[15:0] TPRTY

Rx Slave ATM I/F

RCLK RPA RENB RADR[4:0] RCSB RSOP RSX RDAT[15:0] RPRTY

CBCSB

CBRASB

CBCASB

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 12

CBWEB

CBA[11:0]

CBBS[1:0]

CBDQM

CBDQ[15:0]

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INVERSE MULTIPLEXING OVER ATM

DATA SHEET

PMC-2001723 ISSUE 3 INVERSE MULTIPLEXING OVER ATM

PM7340 S/UNI-IMA-8

7 DESCRIPTION

The PM7340 S/UNI-IMA-8 is a monolithic integrated circuit that implements the Inverse Multiplexing for ATM (IMA 1.1) protocol with backward compatibility to IMA 1.0 and the Transmission Convergence (TC) layer function.

IMA is a protocol designed to combine the transport bandwidth of multiple links into a single logical link. The logical link is called a group. The S/UNI-IMA-8 can support up to 4 independent groups with each group capable of supporting from 1 to 8 links. All links within an IMA group must be at the same nominal rate, however the link rates within a group can be different across groups. The S/UNIIMA-8 can be programmed on a per link basis for cell delination or IMA.

The S/UNI-IMA-8 supports 8 T1, E1 or unchannelized links where each link is dynamically configurable to support either IMA 1.1, backward compatible IMA

1.0, ATM over T1/E1, ATM over fractional T1/E1 or ATM HEC cell delination for unchannelized links. Unchannelized links may be used to support applications such as ADSL.

The S/UNI-IMA-8 supports a clock and data interface where eight 2-pin serial clock and data interfaces are provided. Each clock and data interface can be configured to simultaneously support combinations of either T1, E1, or unchannelized links. Unchannelized links may be used to support applications such as ADSL. Additionally, for cell delineation only, ATM over fractional T1/E1 is supported by allowing individual DS0 timeslots to be configured as active or inactive.

In the transmit direction, the S/UNI-IMA-8 accepts cells from the AnyPHY/UTOPIA interface. As per the IMA specification, the cells, destined for a group, are distributed in a round-robin fashion to the links within the group, adding IMA Control Protocol (ICP) cells, filler cells, and stuff cells as needed. The ICP cells convey state information to the far end and are used to format an IMA Frame. The IMA Frame is used as a mechanism to synchronize the links at the far end. Cell rate decoupling is performed at the IMA sub-layer via filler cells. Filler cells are used instead of physical layer cells for cell rate decoupling, thus a continuous stream of cells is sent to the TC layer. The stuff cells are used to maintain synchronization between links in a group by absorbing the rate differential that exists when links are running at slightly different rates.

The data from the IMA sub-layer is passed on to the TC layer. In the TC layer, the HEC is calculated and inserted into the cell headers; optional scrambling of the

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 13

PMC PM7340-PI Datasheet

CONTENTS

LIST OF FIGURES

LIST OF TABLES