PMC PM7329-BI Datasheet

PM7329 S/UNI-APEX-1K800

DATASHEET

PMC-2010141 ISSUE 2 ATM TRAFFIC MANAGER AND SWITCH

PM7329

/UNI

PEX-1k80

S/UNI-APEX-1K800

ATM/PACKET TRAFFIC MANAGER AND SWITCH

DATASHEET

ISSUE 2: JUNE, 2001

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

PM7329 S/UNI-APEX-1K800

DATASHEET

PMC-2010141 ISSUE 2 ATM TRAFFIC MANAGER AND SWITCH

REVISION HISTORY

Issue No. Issue Date Details of Change

Issue 1 February, 2001 Document created.

Issue 2 June, 2001 Document revision

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PM7329 S/UNI-APEX-1K800

DATASHEET

PMC-2010141 ISSUE 2 ATM TRAFFIC MANAGER AND SWITCH

1 DEFINITIONS .......................................................................................... 1

2 FEATURES .............................................................................................. 3

3 APPLICATIONS ....................................................................................... 7

4 REFERENCES......................................................................................... 8

5 APPLICATION EXAMPLES ..................................................................... 9

6 BLOCK DIAGRAM ................................................................................. 10

7 DESCRIPTION ...................................................................................... 12

8 PIN DIAGRAM ....................................................................................... 16

9 PIN DESCRIPTION................................................................................ 17

9.1 LOOP ANY-PHY RECEIVE MASTER/TRANSMIT SLAVE

INTERFACE (28 SIGNALS) ........................................................ 17

9.2 LOOP ANY-PHY TRANSMIT MASTER/RECEIVE SLAVE

INTERFACE (34 SIGNALS) ........................................................ 22

9.3 WAN ANY-PHY RECEIVE MASTER/TRANSMIT SLAVE

INTERFACE (25 SIGNALS) ........................................................ 26

9.4 WAN ANY-PHY TRANSMIT MASTER/RECEIVE SLAVE

INTERFACE (25 SIGNALS) ........................................................ 31

9.5 CONTEXT MEMORY SYNCHRONOUS SSRAM INTERFACE (59

SIGNALS).................................................................................... 36

9.6 CELL BUFFER SDRAM INTERFACE (52 SIGNALS) ................. 38

9.7 MICROPROCESSOR INTERFACE (44 SIGNALS)..................... 40

9.8 GENERAL (10 SIGNALS) ........................................................... 44

9.9 JTAG & SCAN INTERFACE (7 SIGNALS).................................. 45

9.10 POWER....................................................................................... 47

10 FUNCTIONAL DESCRIPTION................................................................. 49

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PMC-2010141 ISSUE 2 ATM TRAFFIC MANAGER AND SWITCH

10.1 ANY-PHY INTERFACES ............................................................. 49

10.1.1 RECEIVE INTERFACE..................................................... 49

10.1.2 TRANSMIT INTERFACE .................................................. 51

10.2 LOOP PORT SCHEDULER ........................................................ 54

10.3 WAN PORT SCHEDULER .......................................................... 55

10.4 WAN PORT ALIASING................................................................ 57

10.5 WAN AND LOOP ICI SELECTION .............................................. 58

10.6 MICROPROCESSOR INTERFACE ............................................ 58

10.7 MEMORY PORT ......................................................................... 62

10.8 SAR ASSIST ............................................................................... 63

10.8.1 TRANSMIT ....................................................................... 63

10.8.2 RECEIVE.......................................................................... 64

10.9 QUEUE ENGINE......................................................................... 65

10.9.1 SERVICE ARBITRATION ................................................. 66

10.9.2 CELL QUEUING ............................................................... 67

10.9.3 CLASS SCHEDULING ..................................................... 74

10.9.4 CONGESTION CONTROL ............................................... 76

10.9.5 STATISTICS ..................................................................... 83

10.9.6 MICROPROCESSOR QUEUE BUFFER RE-

ALLOCATION/TEAR DOWN ............................................ 85

10.10 CONTEXT MEMORY SSRAM INTERFACE................................ 85

10.11 CELL BUFFER SDRAM INTERFACE ......................................... 90

10.12 JTAG TEST ACCESS PORT....................................................... 93

11 PERFORMANCE ................................................................................... 94

11.1 THROUGHPUT ........................................................................... 94

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PMC-2010141 ISSUE 2 ATM TRAFFIC MANAGER AND SWITCH

11.2 LATENCY.................................................................................... 96

11.3 CDV............................................................................................. 96

12 REGISTER............................................................................................. 97

12.1 GENERAL CONFIGURATION AND STATUS.............................. 98

12.2 LOOP CELL INTERFACE ......................................................... 107

12.3 WAN CELL INTERFACE ............................................................113

12.4 MEMORY PORT ........................................................................119

12.5 SAR........................................................................................... 125

12.5.1 RECEIVE........................................................................ 125

12.5.2 TRANSMIT ..................................................................... 127

12.5.3 CELL BUFFER DIAGNOSTIC ACCESS......................... 128

12.6 QUEUE ENGINE....................................................................... 129

12.7 MEMORY INTERFACE ............................................................. 144

12.8 CBI INTERFACE ....................................................................... 145

13 CBI REGISTER PORT MAPPING ....................................................... 147

14 MEMORY PORT MAPPING................................................................. 153

14.1 CONTEXT SIZE AND LOCATION............................................. 153

14.2 QUEUE CONTEXT DEFINITION .............................................. 156

14.2.1 VC CONTEXT RECORDS.............................................. 157

14.2.2 PORT CONTEXT RECORDS......................................... 165

14.2.3 CLASS CONTEXT RECORDS....................................... 169

14.2.4 SHAPING CONTEXT RECORDS................................... 174

14.2.5 CELL CONTEXT RECORD ............................................ 176

14.2.6 MISC CONTEXT ............................................................ 176

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PMC-2010141 ISSUE 2 ATM TRAFFIC MANAGER AND SWITCH

14.3 WAN PORT SCHEDULER CONTEXT ...................................... 180

14.3.1 WAN TRANSMIT PORT POLLING WEIGHT RECORD. 180

14.3.2 WAN TRANSMIT CLASS STATUS RECORD ................ 181

14.4 LOOP PORT SCHEDULER CONTEXT .................................... 182

14.4.1 LOOP TRANSMIT PORT POLLING SEQUENCE RECORD

182

14.4.2 LOOP TRANSMIT PORT POLLING WEIGHT RECORD183

14.4.3 LOOP TRANSMIT CLASS STATUS RECORD............... 184

15 TEST FEATURES DESCRIPTION ...................................................... 186

15.1 JTAG TEST PORT .................................................................... 186

16 OPERATION ......................................................................................... 190

17 FUNCTIONAL TIMING......................................................................... 191

17.1 MICROPROCESSOR INTERFACE .......................................... 191

17.2 SDRAM INTERFACE ................................................................ 193

17.3 ZBT SSRAM INTERFACE......................................................... 195

17.4 LATE WRITE SSRAM INTERFACE .......................................... 196

17.5 ANY-PHY/UTOPIA INTERFACES ............................................. 197

17.5.1 RECEIVE MASTER/TRANSMIT SLAVE INTERFACES . 197

17.5.2 TRANSMIT MASTER/RECEIVE SLAVE INTERFACES . 200

18 ABSOLUTE MAXIMUM RATINGS ....................................................... 205

19 D.C. CHARACTERISTICS ................................................................... 206

20 A.C. TIMING CHARACTERISTICS...................................................... 208

20.1 JTAG INTERFACE .................................................................... 213

21 ORDERING AND THERMAL INFORMATION...................................... 215

22 MECHANICAL INFORMATION ............................................................ 216

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PMC-2010141 ISSUE 2 ATM TRAFFIC MANAGER AND SWITCH

LIST OF REGISTERS

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DATASHEET

PMC-2010141 ISSUE 2 ATM TRAFFIC MANAGER AND SWITCH

CBI REGISTER 0X00: CONFIGURATION ..................................................... 147

CBI REGISTER 0X01: VERNIER CONTROL................................................. 149

CBI REGISTER 0X02: DELAY TAP STATUS ................................................. 150

CBI REGISTER 0X03: CONTROL STATUS ................................................... 151

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PM7329 S/UNI-APEX-1K800

DATASHEET

PMC-2010141 ISSUE 2 ATM TRAFFIC MANAGER AND SWITCH

LIST OF FIGURES

FIGURE 1 - S/UNI-APEX-1K800 IN OC3 MINI-DSLAM APPLICATION............ 7

FIGURE 2 - S/UNI-APEX-1K800 BLOCK DIAGRAM WITH DATAPATH..........11

FIGURE 3 - S/UNI-APEX-1K800 BOTTOM VIEW PIN OUT........................... 16

FIGURE 4 - 16BIT RECEIVE CELL TRANSFER FORMAT............................. 49

FIGURE 5 - 8-BIT RECEIVE CELL TRANSFER FORMAT ............................. 50

FIGURE 6 - 16-BIT TRANSMIT CELL TRANSFER FORMAT ......................... 52

FIGURE 7 - 8-BIT TRANSMIT CELL TRANSFER FORMAT ........................... 53

FIGURE 8 - I960 (80960CF) INTERFACE....................................................... 61

FIGURE 9 - POWERPC (MPC860) INTERFACE............................................ 61

FIGURE 10- SAR ASSIST TRANSMIT CELL TRANSFER FORMAT ............... 64

FIGURE 11 - SAR ASSIST RECEIVE CELL TRANSFER FORMAT ................. 65

FIGURE 12- SERVICE ARBITRATION HIERARCHY ...................................... 67

FIGURE 13- QUEUE LINKED LIST STRUCTURE .......................................... 68

FIGURE 14- TRAFFIC SHAPING ON THE WAN PORT .................................. 72

FIGURE 15- NON-INTEGER SHPINCR........................................................... 73

FIGURE 16- THRESHOLDS AND COUNT DEFINITIONS............................... 77

FIGURE 17- EPD/PPD CONGESTION DISCARD RULES .............................. 80

FIGURE 18 - CELL CONGESTION DISCARD RULES.................................... 81

FIGURE 19 - FCQ DISCARD RULES .............................................................. 82

FIGURE 20- 1 BANK CONFIGURATION FOR 1MB OF ZBT SSRAM............. 86

FIGURE 21- 1 BANK OF 1MB OF LATE WRITE SSRAM (2 X 256K*18) ........ 87

FIGURE 22- 1 BANK OF 1MB OF LATE WRITE SSRAM (1 X 256K*36) ........ 87

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PMC-2010141 ISSUE 2 ATM TRAFFIC MANAGER AND SWITCH

FIGURE 23- 2 BANK CONFIGURATION FOR 2MB OF ZBT SSRAM............. 88

FIGURE 24- 2 BANK CONFIGURATION FOR 2MB OF LATE WRITE SSRAM89

FIGURE 25- CELL STORAGE MAP................................................................. 90

FIGURE 26- 4 MB – 64K CELLS...................................................................... 91

FIGURE 27- 8 MB – 128K CELLS.................................................................... 91

FIGURE 28- 16 MB – 256K CELLS.................................................................. 92

FIGURE 29- CONTEXT LOCATION............................................................... 153

FIGURE 30- INPUT OBSERVATION CELL (IN_CELL).................................. 187

FIGURE 31- OUTPUT CELL (OUT_CELL) .................................................... 188

FIGURE 32- BI-DIRECTIONAL CELL (IO_CELL) .......................................... 188

FIGURE 33- LAYOUT OF OUTPUT ENABLE AND BIDIRECTIONAL CELLS189

FIGURE 34- SINGLE WORD READ AND WRITE ......................................... 191

FIGURE 35- BURST READ AND WRITE....................................................... 192

FIGURE 36- CONSECUTIVE WRITE ACCESSES USING WRDONEB........ 193

FIGURE 37- READ TIMING ........................................................................... 194

FIGURE 38- WRITE TIMING.......................................................................... 194

FIGURE 39- REFRESH.................................................................................. 195

FIGURE 40- POWER UP AND INITIALIZATION SEQUENCE....................... 195

FIGURE 41- READ FOLLOWED BY WRITE TIMING.................................... 196

FIGURE 42- READ FOLLOWED BY WRITE TIMING.................................... 197

FIGURE 43- UTOPIA L2 TRANSMIT SLAVE (LOOP & WAN) ....................... 198

FIGURE 44- UTOPIA L1 RECEIVE MASTER (LOOP & WAN) ...................... 198

FIGURE 45- UTOPIA L2 RECEIVE MASTER (LOOP & WAN) ...................... 199

FIGURE 46- ANY-PHY RECEIVE MASTER (LOOP & WAN)......................... 200

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PMC-2010141 ISSUE 2 ATM TRAFFIC MANAGER AND SWITCH

FIGURE 47- UTOPIA L2 RECEIVE SLAVE (LOOP & WAN).......................... 201

FIGURE 48- WAN UTOPIA L1 TRANSMIT MASTER .................................... 201

FIGURE 49- LOOP UTOPIA L1 TRANSMIT MASTER................................... 202

FIGURE 50- WAN UTOPIA L2 TRANSMIT MASTER .................................... 202

FIGURE 51- LOOP UTOPIA L2 TRANSMIT MASTER................................... 203

FIGURE 52- WAN ANY-PHY TRANSMIT MASTER....................................... 203

FIGURE 53- LOOP ANY-PHY TRANSMIT MASTER...................................... 204

FIGURE 54- RSTB TIMING............................................................................ 208

FIGURE 55- SYNCHRONOUS I/O TIMING ................................................... 209

FIGURE 56- JTAG PORT INTERFACE TIMING ............................................ 213

FIGURE 57- MECHANICAL DRAWING 352 PIN BALL GRID ARRAY (SBGA)216

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DATASHEET

PMC-2010141 ISSUE 2 ATM TRAFFIC MANAGER AND SWITCH

LIST OF TABLES

TABLE 1 - TERMINOLOGY ............................................................................ 1

TABLE 2 - SAMPLE FEATURE SET AS A FUNCTION OF MEMORY

CAPACITY ..................................................................................... 15

TABLE 3 - PIN TYPE DEFINITION ............................................................... 17

TABLE 4 - NUMBER OF PORTS SUPPORTED, RECEIVE INTERFACE .... 51

TABLE 5 - NUMBER OF PORTS SUPPORTED, TRANSMIT INTERFACE.. 54

TABLE 6 - EXAMPLE WIRR TRANSMISSION SEQUENCE........................ 57

TABLE 7 - AVAILABLE QUEUING PROCEDURES ...................................... 69

TABLE 8 - OAM & RRM CELL IDENTIFICATION ......................................... 74

TABLE 9 - CONGESTION ERROR FLAGS .................................................. 78

TABLE 10 - CONGESTION DISCARD RULES SELECTION ......................... 79

TABLE 11 - STATISTICAL COUNTS .............................................................. 83

TABLE 12 - IN/OUT BOUND CLP STATE FOR STATISTICAL COUNTS....... 84

TABLE 13 - CONGESTION RULE & COUNT SUMMARY.............................. 84

TABLE 14 - RECEIVE INTERFACE THROUGHPUT, MCELLS/SEC ............. 94

TABLE 15 - QUEUE ENGINE THROUGHPUT, MCELLS/SEC....................... 95

TABLE 16 - TRANSMIT INTERFACE THROUGHPUT, MCELLS/SEC ........... 95

TABLE 17 - EXTERNAL QUEUE CONTEXT MEMORY MAP....................... 154

TABLE 18 - INTERNAL QUEUE CONTEXT MEMORY MAP........................ 154

TABLE 19 - INTERNAL WAN PORT SCHEDULER CONTEXT MEMORY MAP

155

TABLE 20 - INTERNAL LOOP PORT SCHEDULER CONTEXT MEMORY MAP

155

TABLE 21 - 2 BIT LOGARITHMIC, 2 BIT FRACTIONAL .............................. 156

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PMC-2010141 ISSUE 2 ATM TRAFFIC MANAGER AND SWITCH

TABLE 22 - 4 BIT LOGARITHMIC, 2 BIT FRACTIONAL .............................. 156

TABLE 23 - 4 BIT LOGARITHMIC, 4 BIT FRACTIONAL .............................. 156

TABLE 24 - VC CONTEXT RECORD STRUCTURE .................................... 157

TABLE 25 - VC STATISTICS RECORD STRUCTURE................................. 163

TABLE 26 - VC ADDRESS MAP RECORD STRUCTURE ........................... 164

TABLE 27 - PORT THRESHOLD CONTEXT RECORD STRUCTURE ........ 166

TABLE 28 - PORT COUNT CONTEXT RECORD STRUCTURE.................. 167

TABLE 29 - CLASS SCHEDULER RECORD STRUCTURE ........................ 169

TABLE 30 - CLASS CONTEXT RECORD STRUCTURE ............................. 172

TABLE 31 - SHAPE TXSLOT CONTEXT RECORD STRUCTURE .............. 174

TABLE 32 - SHAPE RATE CONTEXT RECORD STRUCTURE................... 175

TABLE 33 - CELL CONTEXT RECORD STRUCTURE ................................ 176

TABLE 34 - FREE COUNT CONTEXT STRUCTURE .................................. 177

TABLE 35 - OVERALL COUNT CONTEXT STRUCTURE............................ 177

TABLE 36 - CONGESTION DISCARD CONTEXT STRUCTURE ................ 178

TABLE 37 - MAXIMUM CONGESTION ID CONTEXT STRUCTURE........... 179

TABLE 38 - MISC ERROR CONTEXT STRUCTURE................................... 179

TABLE 39 - WAN TRANSMIT PORT POLLING WEIGHT ............................ 180

TABLE 40 - WAN POLL WEIGHT FORMAT ................................................. 181

TABLE 41 - WAN CLASS STATUS............................................................... 181

TABLE 42 - LOOP TRANSMIT PORT POLLING SEQUENCE ..................... 182

TABLE 43 - LOOP TRANSMIT PORT POLLING WEIGHT........................... 183

TABLE 44 - LOOP CLASS STATUS ............................................................. 184

TABLE 45 - INSTRUCTION REGISTER ....................................................... 186

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PMC-2010141 ISSUE 2 ATM TRAFFIC MANAGER AND SWITCH

TABLE 46 - IDENTIFICATION REGISTER ................................................... 186

TABLE 47 - BOUNDARY SCAN REGISTER ................................................ 186

TABLE 48 - ABSOLUTE MAXIMUM RATINGS ............................................. 205

TABLE 49 - D.C. CHARACTERISTICS......................................................... 206

TABLE 50 - RTSB TIMING............................................................................ 208

TABLE 51 - SYSCLK TIMING ....................................................................... 209

TABLE 52 - CELL BUFFER SDRAM INTERFACE........................................ 209

TABLE 53 - CONTEXT MEMORY ZBT & LATE WRITE SSRAM INTERFACE

209

TABLE 54 - MICROPROCESSOR INTERFACE ........................................... 210

TABLE 55 - LOOP ANY-PHY TRANSMIT INTERFACE ................................ 210

TABLE 56 - WAN ANY-PHY TRANSMIT INTERFACE...................................211

TABLE 57 - LOOP ANY-PHY RECEIVE INTERFACE....................................211

TABLE 58 - WAN ANY-PHY RECEIVE INTERFACE .................................... 212

TABLE 59 - JTAG PORT INTERFACE.......................................................... 213

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PMC-2010141 ISSUE 2 ATM TRAFFIC MANAGER AND SWITCH

1 DEFINITIONS

Table 1 - Terminology

Term Definition

AAL5 ATM Adaptation Layer

ABR Available Bit Rate

Any-PHY Interoperable version of UTOPIA and SCI-PHY, with

inband addressing.

ATM Asynchronous Transfer Mode

BOM Beginning of Message

CBI Common Bus Interface

CBR Constant Bit Rate

CDV Cell Delay Variation

CDVT Cell Delay Variation Tolerance

CES Circuit Emulation Service

CLP Cell Loss Priority

COM Continuation of Message

COS Class of Service

CTD Cell Transfer Delay

DLL Delay Locked Loop

DSL Digital Subscriber Loop

DSLAM DSL access Multiplexer

DUPLEX PMC UTOPIA deserializer

ECI Egress Connection Identifier

EFCI Early forward congestion indicator

EOM End of Message

EPD Early Packet Discard

FIFO First-In-First-Out

GCRA Generic Cell Rate Algorithm

GFR Guaranteed Frame Rate

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PMC-2010141 ISSUE 2 ATM TRAFFIC MANAGER AND SWITCH

IBT Intrinsic Burst Tolerance

ICI Ingress Connection Identifier

MBS Maximum Burst Size

MCR Minimum Cell Rate

OAM Operation, Administration and Maintenance

PCR Peak Cell Rate

PDU Packet Data Unit

PHY Physical Layer Device

PPD Partial Packet Discard

PTI Payload Type Indicator

QOS Quality of Service

QRT PMC’s traffic management device

QSE PMC’s switch fabric device

RRM Reserved or Resource Management

SAR Segmentation and Re-assembly

SCI-PHY PMC-Sierra enhanced UTOPIA bus

SCR Sustained Cell Rate

S/UNI-ATLAS PMC’s OAM and Address Resolution device

UBR Unspecified Bit Rate

UTOPIA Universal Test & Operations PHY Interface for ATM

VBR Variable Bit Rate

VCC Virtual Channel Connection

VORTEX PMC UTOPIA/Any-PHY slave serializer

VPC Virtual Path Connection

WAN Wide Area Network

WIRR Weighted Interleaved Round Robin

WRR Weighted Round Robin

ZBT Zero Bus Turnaround

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PMC-2010141 ISSUE 2 ATM TRAFFIC MANAGER AND SWITCH

2 FEATURES

• Monolithic single chip ATM traffic manager providing VC queuing/shaping and VC, Class Of Service(COS), and Port scheduling, congestion management, and switching across 128 ports.

• Targeted at systems where many low speed ATM data ports are multiplexed onto few high speed ports.

• 869 Kcells/s non shaped throughput in full duplex.

• 1.73 Mcells/s non shaped throughput in half duplex.

• 1.42 Mcells/s shaped throughput (aggregate of the four shapers).

• Supports four WAN uplink ports, with port aliasing.

• Supports 128 loop ports. Loop port can support an uncongested rate up to

230Kcells/sec.

• Provides 4 Classes of Service per port with configurable traffic parameters enabling support for a mix of CBR, VBR, GFR, and UBR classes.

• Provides 1024 per-VC queues individually assignable to any COS in any port.

• Provides support of up to 256k cells of shared buffer.

• Provides 2 independent cell emission schedulers, 1 for the WAN ports, and 1

for the Loop ports. The schedulers have the following features: Three level hierarchical cell emission scheduling at the port, class, and VC levels.

• WAN Port Scheduling:

• Weighted Interleaved Round Robin WAN port scheduling.

• Per port Priority Fair Queued class scheduling with port

independence.

• Per Class:

• Weighted Fair Queued VC scheduling with class independence

or,

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• Shaped Fair Queued VC scheduling applying rate based per VC shaping or,

• Frame Continuous Queued VC scheduling for VC Merge and packet re-assembly.

• Loop Port Scheduling:

• Weighted Interleaved Round Robin Loop port scheduling.

• Per port Priority Fair Queued class scheduling with port

independence.

• Per Class:

• Weighted Fair Queued VC scheduling with class independence

or,

• Frame Continuous Queued scheduling for VC Merge and packet re-assembly.

• Congestion Control applied per-VC, per-class, per-port and per-direction.

• Flexible, progressive hierarchical throttling of buffer consumption.

Provides sharing of resources during low congestion, memory reservation during high congestion.

• Applies EPD and PPD on a per-VC, per-class, per-port, and per-direction basis with CLP differentiation, following emerging GFR standards.

• Provides EFCI marking on a per VC basis.

• Provides interrupts and indication of most recent VC/Class/Port that

exceeded maximum thresholds.

• Provides flexible VPC or VCC switching selectable on a per VC basis as follows:

• Any WAN port to any WAN port.

• Any WAN port to any Loop port.

• Any Loop port to any WAN port.

• Any Loop port to any Loop port.

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PMC-2010141 ISSUE 2 ATM TRAFFIC MANAGER AND SWITCH

• Microprocessor port to any loop or WAN port.

• Any loop or WAN port to microprocessor port.

• VP Termination (in conjunction with the S/UNI-ATLAS).

• VPI or VPI/VCI header mapping.

• VC merge.

• Provides flexible signaling and control capabilities:

• Provides 4 independent uP transmit queues.

• Provides simultaneous AAL5 SAR assistance for traffic to/from the uP on

up to 1024 VCs.

• Supports uP cell injection into any queue.

• Provides per VC selectable OAM cell pass through or switching to

microprocessor port.

• Supports CRC10 calculation for OAM cells destined for/originating from

the microprocessor.

• Diagnostic access provided to context memory and cell buffer memory via the microprocessor.

• Provides per VC CLP0/1 transmit counts.

• Provide global per CLP0/1 discard counts.

• Provides various error statistics accumulation.

• Determines the ingress connection identifier from one of several locations:

the cell prepend, the VPI/VCI field, or the HEC/UDF field.

• Interface support:

• Provides a 8/16-bit Any-PHY compliant master/slave Loop side interface

supporting up to 128 ports (logical PHYs).

• Provides an 8/16-bit Any-PHY compliant master/slave WAN side interface

supporting up to 4 ports (PHYs).

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PMC-2010141 ISSUE 2 ATM TRAFFIC MANAGER AND SWITCH

• Provides a 32-bit multiplexed microprocessor bus interface for signaling,

control, and cell message extraction and insertion, context memory access, control and status monitoring, and configuration of the IC.

• Provides a 32-bit SDRAM interface for cell buffering.

• Provides a 36-bit pipelined ZBT or register to register late write SSRAM

interface for context storage.

• Packaging:

• Provides a standard 5 signal P1149.1 JTAG test port for boundary scan

board test purposes.

• Implemented in low power, 0.25 micron, +2.5/3.3V CMOS technology with

CMOS compatible inputs and outputs.

• 352-pin high-performance ball grid array (SBGA) package.

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PMC-2010141 ISSUE 2 ATM TRAFFIC MANAGER AND SWITCH

3 APPLICATIONS

• Mini-DSL Access Multiplexers (Mini-DSLAMs).

• Subscriber Access terminal devices.

• APON Customer Located Subscriber Access Equipment

• LMDS Customer Located Subscriber Access Equipment.

• Integrated Access Devices.

Figure 1 shows the S/UNI-APEX-1K800 in a mini-DSLAM application. The S/UNI-APEX-1K800 acts as a cell buffer and traffic manager. The S/UNI-ATLAS1K800 provides address resolution and policing.

The mini-DSLAM application supports eight LIU devices per Line Card. Each xDSL modem is connected by its Utopia port to a FPGA which provides an interface to the AnyPhy bus. If Hot Swap capability is needed the bus signals need to be passed through switching or tristate drivers to isolate the card when being plugged in.

The FPGA performs the task of interfacing several 31 logical port Utopia bus signals to the single 128 logical port Any-PHY bus supported by the S/UNIAPEX-1K800.

Figure 1 - S/UNI-APEX-1K800 in OC3 Mini-DSLAM Application

line cards

up to 31

Utopia L2

ports

up to 31

Utopia L2

ports

DSL Phy

line cards

DSL Phy

S/UNI-

DUPLEX

S/UNI-

DUPLEX

200Mbps

LVDS

S/UNI-

VORTEX

Up to 8 LVDS links to S/UNI-Duplex devices per S/UNI-VORTEX

AnyPhy/

SciPhy

Context SSRAM

S/UNIAPEX1K800

Packet/Cell

SDRAM

S/UNI-

ATLAS-

1K800

Ingress

SSRAM

Egress

SSRAM

Phy

Host CPU

core card

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PMC-2010141 ISSUE 2 ATM TRAFFIC MANAGER AND SWITCH

4 REFERENCES

1. PMC-Sierra; “Saturn Compatible Interface For ATM PHY Layer And ATM Layer Devices, Level 2”; PMC-940212; Dec. 8, 1995.

2. PMC-Sierra; DSLAM engineering document.

3. “Traffic Management And Switching With The Vortex Chip Set: S/UNI-APEX Technical Overview”, PMC-981024.

4. ATM Forum, “Universal Test & Operations PHY Interface for ATM (UTOPIA), Level 2”, Version 1.0, af-phy-0039.000, June 1995.

5. ITU-T Recommendation I.432.1, “B-ISDN user-network interface – Physical layer specification: General characteristics”, 08/96.

6. ITU-T Recommendation I.363, “B-ISDN ATM Adaptation Layer (AAL) Specification”, March 1993.

7. AF Traffic Management Specification Version 4.1 AF-TM-0121.000, March 1999.

8. AF Traffic Management Baseline Text Document BTD-TM-01.01, April 1998.

9. I.610 OAM.

10. PMC Sierra, “Saturn Interface Specification and Interoperability Framework for Packet and Cell Transfer Between Physical Layer and Link Layer Devices”, PMC980902.

11. PMC Sierra, “S/UNI APEX H/W Programmer’s Guide”, PMC-991454.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 8

PM7329 S/UNI-APEX-1K800

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PMC-2010141 ISSUE 2 ATM TRAFFIC MANAGER AND SWITCH

5 APPLICATION EXAMPLES

Please refer to the document “Traffic Management And Switching With The Vortex Chip Set: S/UNI-APEX Technical Overview”, PMC-981024.

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6 BLOCK DIAGRAM

Figure 2 shows the function block diagram of the S/UNI-APEX-1K800 ATM traffic manager. The functional diagram is arranged such that cell traffic flows through the S/UNI-APEX-1K800 from left to right.

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Figure 2 - S/UNI-APEX-1K800 Block Diagram With Datapath

CMD[33:0]

CMP[1:0]

CMA[18:0]

CMRWB

CMCEB

CMAB[18:17]

SSRAM I/F

Queue Engine

BCLK

CSB

AD[31:0]

ADSB

BURSTB

BLAST

READYB

WRDONEB

INTHIB

INTLOB

BUSPOL

uProc I/F

FIFO

4 chan

2 cell

FIFO 2 cell

SAR

Assist

FIFO 4 cell

Loop Port Scheduler

Loop Tx

Any-PHY

LTADR[7:0] LTPA LTENB LTSX LTSOP LTDAT[15:0] LTPRTY LTCLK

LRCLK

LRPA LRSX

LRSOP

LRDAT[15:0]

LRPRTY

LRENB

LRADR[5:0]

WRCLK

WRPA WRSX

WRSOP

WRDAT[15:0]

WRPRTY

WRENB

WRADDR[2:0]

Loop Rx

Any-PHY

WAN Rx

Any-PHY

Cell Data Path

Context Data Path

FIFO 4 cell

ICI

Select

ICI

Select

SDRAM I/F

C B

WTADR[2:0]

FIFO

4 chan

4 cell

Wan Port

Scheduler

]

B E

W R B C

]

[

WAN Tx

Any-PHY

JTAG

WTPA WTENB WTSX WTSOP WTDAT[15:0] WTPRTY WTCLK

TDO TDI TCK TMS TRSTB

SYSCLK

RSTB OE

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 11

PM7329 S/UNI-APEX-1K800

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7 DESCRIPTION

The PM7329 S/UNI-APEX-1K800 is a full duplex ATM traffic management device, providing cell switching, per VC queuing, traffic shaping, congestion management, and hierarchical scheduling to up to 128 loop ports and up to 4 WAN ports.

The S/UNI-APEX-1K800 provides per-VC queuing for 1024 VCs. A per-VC queue may be allocated to any Class of Service (COS), within any port, in either direction (ingress or egress path). Per-VC queuing enables PCR or SCR per-VC shaping on WAN ports and greater fairness of bandwidth allocation between VCs within a COS.

The S/UNI-APEX-1K800 provides three level hierarchical scheduling for port, COS, and VC level scheduling. There are two, three level schedulers; one for the loop ports and one for the WAN ports. The three level scheduler for the WAN ports provides:

• Weighted Interleaved Round Robin (WIRR) scheduling across the 4 WAN ports enabling selectability of bandwidth allocation between the ports.

• Priority Fair scheduling across the 4 COS’s within each port. This class scheduler is a modified priority scheduler allowing minimum bandwidth allocations to lower priority classes within the port. Class scheduling within a port is independent of activity on all other ports.

• There are three types of VC schedulers. VC scheduling within a class is independent of activity on all other classes

• Shaped fair queuing is available for 4 classes. If the COS is shaped,

each VC within the class is scheduled for emission based on its VCs shaping rate. During class congestion, the VC scheduler may lower a VCs rate in proportion to a normalization factor calculated as a function of the VCs rate and the aggregate rate of all active VCs within the class.

• Weighted Fair Queuing in which weights are used to provide fairness

between the VCs within a class.

• Frame continuous scheduling where an entire packet is accumulated

prior to transferring to a class queue.

The three-level scheduler for the loop ports provides:

• Weighted Interleaved Round Robin (WIRR) scheduling across the 128 loop ports enabling selectability of bandwidth allocation between the ports

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and ensuring minimal PHY layer FIFOing is required to support a wide range of port bandwidths.

• Priority scheduling across the 4 COS’s within each port. Class scheduling within a port is independent of activity on all other ports.

• VCs within a class are scheduled with a Weighted Fair Queue (WFQ) scheduler or Frame Continuous scheduling. VC scheduling within a class is independent of activity on all other classes. Shaping is not supported on loop ports.

The S/UNI-APEX-1K800 forwards cells via tail of queue enqueuing and head of queue dequeuing (emission) where tail of queue enqueuing is controlled by the VC context record and subject to congestion control, and head of queue dequeuing is controlled by the three-level hierarchical schedulers. The VC context record allows for enqueuing to any queue associated with any port, thus full switching is supported, any port to any port.

The S/UNI-APEX-1K800 supports up to 256k cells of shared buffering in a 32-bit wide SDRAM. Memory protection is provided via an inband CRC on a cell-by-cell basis. Buffering is shared across direction, port, class, and VC levels. The congestion control mechanism provides guaranteed resources to all active VCs, allows sharing of available resources to VCs with excess bandwidth, and restricts buffer allocation on a per-VC, per-class, per-port, and per-direction basis. The congestion control mechanism supports PPD and EPD on a CLP0 and CLP1 basis across per-VC, per-class, per-port, and per-direction structures. EFCI marking is supported on a per-VC basis. Congestion thresholds and packet awareness is selectable on a per connection basis.

The S/UNI-APEX-1K800 provides flexible capabilities for signaling, management, and control traffic. There are 4 independent uP receive queues to which both cell and AAL5 frame traffic may be en-queued for termination by the uP. A staging buffer is also provided enabling the uP to en-queue both cell and AAL5 frame traffic to any outgoing queue. AAL5 SAR assistance is provided for AAL5 frame traffic to and from the uP. AAL5 SAR assistance includes the generation and checking of the 32-bit CRC field and the ability to reassemble all the cells from a frame in the VC queue prior to placement on the uP queues. Any or all of the 1024 VCs may be configured to be routed to/from the uP port. Any or all of the VCs configured to be routed to/from the uP port may also be configured for AAL5 SAR assistance simultaneously. OAM cells may optionally (per-VC selectable) be routed to a uP receive queue or switched with the user traffic. CRC10 generation and checking is optionally provided on OAM cells to/from the uP.

The S/UNI-APEX-1K800 maintains cell counts of CLP0 and CLP1 cell transmits on a per-VC basis. Global CLP0 and CLP1 congestion discards are also

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 13

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maintained. Various error monitoring conditions and statistics are accumulated or flagged. The uP has access to both internal S/UNI-APEX-1K800 registers and the context memory as well as diagnostic access to the cell buffer memory.

The S/UNI-APEX-1K800 provides a 8/16-bit Any-PHY compliant loop side master/slave interface supporting up to 128 ports. Egress cell transfers across the interface are identified via an inband port identifier prepended to the cell. The slave devices must match the inband port identifier with their own port ID or port ID range in order to accept the cell. Per port egress flow control is effected via a 8-bit address polling bus to which the appropriate slave device responds with out of band per port flow control status. Ingress cell transfers across the interface are effected via a combination of UTOPIA L2 flow control polling and device selection for up to 32 slave devices. The Any-PHY loop side interface may be reconfigured as a standard single port UTOPIA L2 compliant slave interface. 16bit prepends are optionally supported on both ingress and egress for cell flow identification enabling use with external address resolution devices, switch fabric interfaces, or other layer devices.

The S/UNI-APEX-1K800 provides an 8/16-bit Any-PHY or UTOPIA L2 compliant WAN side master/slave interface supporting up to 4 ports. 16-bit prepends are optionally supported on both ingress and egress for cell flow identification enabling use with external address resolution devices, switch fabric interfaces, or other layer devices. The WAN port has port aliasing on the egress, providing in service re-direction without requiring re-programming the context of active VCs.

The S/UNI-APEX-1K800 provides a 32-bit microprocessor bus interface for signaling, control, cell and frame message extraction and insertion, VC. Class and port context access, control and status monitoring, and configuration of the IC. Microprocessor burst access for registers, cell and frame traffic is supported.

The S/UNI-APEX-1K800 provides a 36-bit ZBT or late write SSRAM interface for context storage supporting up to 4MB of context for up to 1024 VCs and up to 256k cell buffer pointer storage. Context Memory protection is provided via 2 bits of parity over each 34-bit word.

The total number of cells, the total number of VCs, support for address mapping and shaped fair queuing is limited to the amount of context and cell buffer memory available. Below is a table illustrating the most common combinations of memory/features.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 14

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Table 2 - Sample feature set as a function of memory capacity

Context Memory Size

Cell Buffer Memory Size

# VC # Cell

Buffers

Address Mapping

Shaping Support

Support

SSRAM

SDRAM

1 MB 4MB 1024 64 K Yes No

2 MB 4MB 1024 64 K Yes Yes

2 MB 16MB 1024 256 K Yes Yes

The S/UNI-APEX-1K800 provides facilities to enable sparing capability with another S/UNI-APEX-1K800 device. The facilities enable a 'warm standby' capability in which connection setup between the two devices can be maintained identically but some cell loss will occur at the point of device swapping. The facilities do not include a cell by cell lock step between the two S/UNI-APEX1K800 devices. To avoid any cell replication, queues in the 'spare' S/UNI-APEX1K800 will be kept empty, thus causing all queued traffic in the 'active' S/UNIAPEX-1K800 to be lost at the point of switch over. However, since connection setup is maintained identically between the two S/UNI-APEX-1K800 devices, switch over can happen instantaneously, thus avoiding any connection timeout or tear down issues.

The S/UNI-APEX-1K800 facilities provided are the disable and filter control bits in the Receive and Transmit Control register. These control bits are asserted in the spare S/UNI-APEX-1K800 to ensure the queues remain empty until swapping is initiated. Alternatively, asserting only the filter enable bits allow signaling and control traffic continuity to be maintained to the spare S/UNI-APEX1K800 to enable datapath integrity testing on the spare plane and to ensure control communications paths to the spare plane are usable.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 15

PM7329 S/UNI-APEX-1K800

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PMC-2010141 ISSUE 2 ATM TRAFFIC MANAGER AND SWITCH

8 PIN DIAGRAM

The S/UNI-APEX-1K800 is packaged in a 352-pin ball grid array (SBGA) package having a body size of 35 mm by 35 mm.

Figure 3 - S/UNI-APEX-1K800 Bottom View Pin out

2625242322212019181716151413121110987654321

vss5 vss4 CMD [0] CMD [4] CMD [7] C MD [11] C MD [14] CMD [18] CMD [21] PCH CMD [27] CM D [30] vss3 vss2 AD [2] AD [4] PC H AD [10] AD [13] AD [17] AD [20] AD [24] AD [27] AD [31] vss1 vss0

vss9 vdd10 vss8 CMD [1] CMD [5] CMD [8] CMD [12] CMD [15] CMD [19] CMD [23] C MD [25] CMD [29] CMD [32] CMD [33] SYSCLK AD [6] AD [8] AD [12] AD [16] AD [19] AD [23] AD [26] AD [30] vss7 vdd9 vss6

CMRWB vss11 vdd 12 CMP [1] CMD [2] CM D [6] CMD [9] CMD [13] CM D [16] C MD [20] CMD [24] CMD [28] CMD [31] AD [0] AD [3] AD [7] AD [11] AD [15] AD [18] AD [22] AD [25] A D [29] INTHIB vdd11 vss10 BCLK

CMAB [1] CMCEB CMP [0] vdd17 nc CM D [3] PCH CMD [10] vdd16 CMD [17] CMD [22] CMD [26] vdd15 AD [1] AD [5] AD [9] AD [14] vdd14 AD [21] PCH AD [28] nc vd d13 INTLOB WRDONEB BLAST

CMA [16] CMA [ 17] CMA [19] nc BUSPOL BTERMB BURSTB C SB

CMA [12] CMA [ 15] CMAB [0] CMA [18] READYB WR ADSB LRADR [2]

CMA [9] CMA [11] CMA [14] PCH PCH LRADR [ 0] LRADR [3] LRADR [5]

CMA [5] CMA [8] CMA [10] CMA [13] LRADR [1] LRADR [4] LRENB LRPRTY

CMA [2] CMA [4] CMA [7] vdd18 vd d 1 9 LRPA LRSO P LRDA T [0 ]

PCH CMA [0] CMA [3] C MA [6] LRC LK LRSX LRDA T [ 1] LRD A T [3 ]

LTDAT [12] LTDAT [14] LTDAT [15] CMA [1] PCH LRDAT [2] LRDAT [4] LRDAT [6]

LTD A T [ 9] LTD A T [ 1 0] LTD A T [ 1 1] LTD A T [ 1 3] LRDAT [5] LRDAT [7] LRDAT [8] LRDAT [9]

v ss1 3 LTD A T [ 6] LTD A T [ 7 ] LTD A T [ 8 ] vd d20 LRDAT [10] LRDAT [11] vss12

v ss1 5 LTD A T [ 5] LTD A T [ 4 ] v d d 2 1 LRDAT [14] LRDAT [13] LRDAT [12] vss14

WRDAT

[13]

RSTB

WRADR

[1]

WRDAT

[10]

WRDAT

[14]

WRDAT [8]WRDAT [6]

LTD A T [ 3] LTD A T [ 2 ] LTD A T [ 1 ] LTPA PCH

LTDAT [ 0] LTCLK LTENB LTSOP WRSO P WRC LK WRENB

PCH LTSX LTADR [11] LTADR [8] WRDAT [3] WRDAT [0] WRPRTY WRPA

LTPRTY LTADR [ 10] LTADR [ 7] vd d 23 vdd22 WRDAT [4] WRDAT [1] WRSX

LTADR [9] LTADR [6] LTADR [4] LTADR [1] PCH WRDAT [7] WRDAT [5] WRDA T [2]

LTADR [5] LTADR [3] LTADR [0]

WTDAT

LTADR [ 2]

[15]

WTDAT

PCH

[12]

WTDAT

WTDAT [8] WTDAT [6] vdd4 SCANMB WTDAT [2] WTENB WTSOP vd d3 CBA [9] CBA [4] CBA [0] CBCASB vdd2

[11]

WTDA T [7] v ss17 vd d 6 SC ANEN WTDA T [3] WTPA WTCLK WTADR [ 1] CBA [1 0] C BA [6] C BA [2 ] CBBS [0] C BWEB

vss21 vd d8 vss19 WTDAT [4] WTDAT [0] WTSX WTA DR [0] CBA [11] CBA [7] CBA [3] CBA [1] CBCSB

vss27 v ss26 WTDA T [5] WTDA T [1 ] PC H WTPRTY W TADR [ 2] C BA [ 8] C BA [5] PC H C BBS [1] CBRA SB vss25 v ss24

2625242322212019181716151413121110987654321

WTDAT

[14]

WTDAT

[13]

[10]

WTDAT [9] nc nc TDI

vdd1

CBDQ

[16]

CBDQ

[19]

CBDQ

[21]

CBDQ

CBDQ [7] C BDQ [3] nc vdd0 TRSTB TMS OE

[10]

CBDQ

CBDQ [9] C BDQ [6] CBDQ [2] TDO vdd5 vss16 TCK

[13]

CBDQ

CBDQ [8] C BDQ [5] CBDQ [1] vss20 vdd7 vss18

[15]

[12]

CBDQ

[18]

[14]

PCH C BDQ [4 ] C BDQ [ 0] vss23 v ss22

[11]

CBDQ M

[1]

CBDQ

[31]

CBDQM

[0]

CBDQ

[26]

CBDQ

[28]

CBDQ

[29]

CBDQ

[30]

CBDQ

[22]

CBDQ

[24]

CBDQ

[25]

CBDQ

[27]

CBDQ

[17]

CBDQ

[20]

CBDQ

[23]

PCH

WRADR

[0]

WRDAT

[11]

WRDAT

[15]

LRDA T [ 15 ]

WRADR

[2]

WRDAT [9]

WRDAT

[12]

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 16

+ 202 hidden pages

PMC PM7329-BI Datasheet

REVISION HISTORY

CONTENTS

LIST OF REGISTERS

LIST OF FIGURES

LIST OF TABLES