PMC PM7328-BI Datasheet

STANDARD PRODUCT

DATASHEET

PMC-2010142 ISSUE 2 ATM LAYER SOLUTION

PM7328 S/UNI-ATLAS-1K800

PM7328

S/UNI-ATLAS-1K800

ATM LAYER SOLUTION

DATASHEET

PROPRIETARY AND CONFIDENTIAL

RELEASED

ISSUE 2: JUNE 2001

PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000

STANDARD PRODUCT

DATASHEET

PMC-2010142 ISSUE 2 ATM LAYER SOLUTION

PM7328 S/UNI-ATLAS-1K800

CONTENTS

1 FEATURES.............................................................................................. 1

1.1 POLICING ..................................................................................... 5

1.2 CELL COUNTING ......................................................................... 5

2 APPLICATIONS....................................................................................... 7

3 REFERENCES......................................................................................... 9

4 APPLICATION EXAMPLES................................................................... 10

5 DESCRIPTION ...................................................................................... 11

6 PIN DIAGRAM ....................................................................................... 12

7 PIN DESCRIPTION................................................................................ 13

8 FUNCTIONAL DESCRIPTION............................................................... 49

8.1 INGRESS VC TABLE.................................................................. 52

8.2 CONNECTION IDENTIFICATION............................................... 54

8.2.1 INGRESS CONNECTION IDENTIFICATION ................... 54

8.3 SEARCH TABLE DATA STRUCTURE ....................................... 58

8.3.1 PRIMARY SEARCH TABLE ............................................. 59

8.3.2 SECONDARY SEARCH KEY TABLE .............................. 59

8.4 INGRESS CELL PROCESSING ................................................. 61

8.5 EGRESS VC TABLE ................................................................... 71

8.5.1 EGRESS CONNECTION IDENTIFICATION .................... 73

8.6 EGRESS CELL PROCESSING .................................................. 75

8.7 PERFORMANCE MONITORING ................................................ 84

8.7.1 PERFORMANCE MONITORING FLOWS........................ 96

8.8 CHANGE OF CONNECTION STATE ......................................... 99

8.9 HEADER TRANSLATION ......................................................... 100

8.10 CELL ROUTING........................................................................ 102

8.11 CELL RATE POLICING............................................................. 102

8.11.1 PER-PHY POLICING...................................................... 109

8.11.2 GUARANTEED FRAME RATE....................................... 113

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8.11.3 CONTINUOUSLY VIOLATING MODE ........................... 116

8.11.4 S/UNI-ATLAS-1K800 POLICING CONFIGURATION..... 117

8.12 CELL COUNTING ..................................................................... 117

8.13 OPERATIONS, ADMINISTRATION AND MAINTENANCE (OAM)

CELL SERVICING..................................................................... 121

8.14 FAULT MANAGEMENT CELLS................................................ 124

8.15 LOOPBACK CELLS .................................................................. 126

8.16 ACTIVATION/DEACTIVATION CELLS ..................................... 126

8.17 SYSTEM MANAGEMENT CELLS............................................. 126

8.18 F4 TO F5 OAM PROCESSING................................................. 127

8.19 F5 TO F4 OAM PROCESSING................................................. 137

8.20 RESOURCE MANAGEMENT CELLS ....................................... 144

8.21 S/UNI-ATLAS-1K800 BACKGROUND PROCESSES............... 144

8.22 INGRESS BACKWARD OAM CELL INTERFACE .................... 146

8.23 EGRESS BACKWARD OAM CELL INTERFACE ..................... 147

8.24 JTAG TEST ACCESS PORT .................................................... 147

8.25 MICROPROCESSOR INTERFACE .......................................... 147

8.26 EXTERNAL SRAM ACCESS .................................................... 148

8.27 WRITING CELLS ...................................................................... 148

8.28 READING CELLS...................................................................... 152

8.29 S/UNI-ATLAS-1K800 DLL CLOCK OPERATION...................... 155

9 NORMAL MODE REGISTER MEMORY MAP..................................... 156

9.1 NORMAL MODE REGISTER DESCRIPTION .......................... 167

10 TEST FEATURES DESCRIPTION ...................................................... 436

10.1 TEST MODE 0 DETAILS .......................................................... 439

10.2 JTAG TEST PORT .................................................................... 439

11 OPERATION........................................................................................ 446

11.1 SCI-PHY EXTENDED CELL FORMAT ..................................... 446

11.2 SYNCHRONOUS STATIC RAMS ............................................. 448

11.2.1 INGRESS VC-TABLE SRAM.......................................... 448

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11.2.2 EGRESS VC-TABLE SRAM........................................... 449

11.3 ATM CELL PROCESSING........................................................ 450

11.3.1 OAM CELL FORMAT ..................................................... 450

11.4 INGRESS VC IDENTIFICATION SEARCH ALGORITHM......... 453

11.4.1 OVERVIEW .................................................................... 453

11.4.2 INGRESS PERFORMANCE MONITORING ACTIVATION /

DEACTIVATION ............................................................. 459

11.5 EGRESS VC TABLE OPERATION........................................... 460

11.5.1 INITIALIZATION PROCEDURE ..................................... 460

11.5.2 CONNECTION SETUP................................................... 460

11.5.3 EGRESS PERFORMANCE MONITORING ACTIVATION /

DEACTIVATION ............................................................. 461

11.6 JTAG SUPPORT....................................................................... 462

11.6.1 TAP CONTROLLER ....................................................... 463

12 FUNCTIONAL TIMING......................................................................... 468

12.1 INGRESS INPUT CELL INTERFACE ....................................... 468

12.2 INGRESS OUTPUT CELL INTERFACE ................................... 471

12.3 EGRESS INPUT CELL INTERFACE ........................................ 473

12.4 EGRESS OUTPUT CELL INTERFACE .................................... 476

13 ABSOLUTE MAXIMUM RATINGS....................................................... 479

14 D.C. CHARACTERISTICS ................................................................... 480

15 A.C. TIMING CHARACTERISTICS...................................................... 482

16 MECHANICAL INFORMATION ........................................................... 497

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LIST OF FIGURES

FIGURE 1 ........ S/UNI-ATLAS-1K800 IN OC3 MINI-DSLAM APPLICATION................................ 7

FIGURE 2 ........ S/UNI-ATLAS-1K800 BLOCK DIAGRAM........................................................... 10

FIGURE 3 ........ VC SEARCH KEY COMPOSITION.................................................................... 54

FIGURE 4 ........ PARAMETERS OF THE PRIMARY KEY AND SECONDARY KEY................... 56

FIGURE 5 ........ SEARCH KEY LOCATIONS WITHIN THE ROUTING WORD..........................57

FIGURE 6 ........ ATLAS SEARCH TABLE STRUCTURE ............................................................59

FIGURE 7 ........ EGRESS ROUTING WORD AND EGRESS LOOKUP ADDRESS ...................73

FIGURE 8 ........ S/UNI-ATLAS-1K800 PM FLOWS ..................................................................... 97

FIGURE 9 ........ F4 TO F5 OAM FLOWS...................................................................................128

FIGURE 10 ...... INGRESS TERMINATION OF F4 SEGMENT AND END-TO-END-POINT

CONNECTIONS. ..........................................................................129

FIGURE 11 ...... INGRESS TERMINATION OF F4 SEGMENT AND END-TO-END POINT

CONNECTION..............................................................................130

FIGURE 12 ...... INGRESS TERMINATION OF F4 SEGMENT END-POINT CONNECTION. .. 132

FIGURE 13 ...... INGRESS TERMINATION OF F4 END-TO-END POINT CONNECTION. ......133

FIGURE 14 ...... F5 TO F4 OAM FLOWS...................................................................................138

FIGURE 15 ...... EGRESS TERMINATION OF A VPC SEGMENT END-POINT ....................... 139

FIGURE 16 ...... VPC INTERMEDIATE POINT .......................................................................... 140

FIGURE 17 ...... VCC INTERMEDIATE POINT .......................................................................... 141

FIGURE 18 ...... VPC SEGMENT END-POINT .......................................................................... 141

FIGURE 19 ...... VCC SEGMENT END POINT .......................................................................... 142

FIGURE 20 ...... VPC SEGMENT END-POINT AND END-TO-END POINT .............................. 142

FIGURE 21 ...... INGRESS VPC END-TO-END POINT AND SEGMENT END-POINT, VC

SEGMENT END-POINT AND SEGMENT SOURCE POINT.

EGRESS VPC END-TO-END AND SEGMENT SOURCE

POINT WITH VCC SEGMENT END-POINT AND VCC

SEGMENT SOURCE POINT........................................................ 143

FIGURE 22 ...... INGRESS VPC END-TO-END AND SEGMENT END POINT WITH VC

INTERMEDIATE POINT. EGRESS VPC END-TO-END AND

SEGMENT SOURCE POINT WITH VC INTERMEDIATE

POINT AND VC SEGMENT SOURCE POINT.............................143

FIGURE 23 ...... INPUT OBSERVATION CELL (IN_CELL)........................................................ 442

FIGURE 24 ...... OUTPUT CELL (OUT_CELL)...........................................................................443

FIGURE 25 ...... BI-DIRECTIONAL CELL (IO_CELL) ................................................................ 444

FIGURE 26 ...... LAYOUT OF OUTPUT ENABLE AND BI-DIRECTIONAL CELLS ................... 445

FIGURE 27 ...... EIGHT BIT WIDE CELL FORMAT ................................................................... 447

FIGURE 28 ...... SIXTEEN BIT WIDE CELL FORMAT............................................................... 448

FIGURE 29 ...... COMMON OAM CELL FORMAT .....................................................................451

FIGURE 30 ...... SPECIFIC FIELDS FOR AIS/RDI FAULT MANAGEMENT CELL ...................451

FIGURE 31 ...... SPECIFIC FIELDS FOR THE FPM CELL ........................................................ 452

FIGURE 32 ...... SPECIFIC FIELDS FOR THE BR CELL........................................................... 452

FIGURE 33 ...... CONNECTION INSERTION W HEN BINARY TREE IS EMPTY...................... 456

FIGURE 34 ...... CONNECTION INSERTION W HEN BINARY TREE CONTAINS ONLY

SINGLE VC RECORD. ................................................................. 456

FIGURE 35 ...... CONNECTION INSERTION AT THE ROOT OF THE TREE. .........................457

FIGURE 36 ...... CONNECTION INSERTION IN THE MIDDLE OF THE BINARY TREE..........458

FIGURE 37 ...... NEW SECONDARY SEARCH TABLE ENTRY INSERTED AT A LEAF. ........458

FIGURE 38 ...... BOUNDARY SCAN ARCHITECTURE ............................................................. 462

FIGURE 39 ...... TAP CONTROLLER FINITE STATE MACHINE .............................................. 464

FIGURE 40 ...... INGRESS INPUT CELL INTERFACE (RPOLL=0)........................................... 468

FIGURE 41 ...... INGRESS INPUT CELL INTERFACE (RPOLL=1) EXAMPLE 1...................... 469

FIGURE 42 ...... INGRESS INPUT CELL INTERFACE (RPOLL=1) EXAMPLE 2...................... 470

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FIGURE 43 ...... INGRESS OUTPUT CELL INTERFACE (OTSEN=0) ...................................... 471

FIGURE 44 ...... INGRESS OUTPUT CELL INTERFACE (OTSEN=1) ...................................... 472

FIGURE 45 ...... EGRESS INPUT CELL INTERFACE (IPOLL=0)..............................................473

FIGURE 46 ...... EGRESS INPUT CELL INTERFACE POLLED MODE (IPOLL=1)...................475

FIGURE 47 ...... EGRESS OUTPUT CELL INTERFACE DIRECT MODE (TPOLL=0) .............. 476

FIGURE 48 ...... EGRESS OUTPUT CELL INTERFACE POLLED MODE (TPOLL=1) ............. 477

FIGURE 49 ...... MICROPROCESSOR INTERFACE READ TIMING ........................................ 483

FIGURE 50 ...... MICROPROCESSOR INTERFACE WRITE TIMING....................................... 485

FIGURE 51 ...... EGRESS INPUT CELL INTERFACE TIMING.................................................. 487

FIGURE 52 ...... INGRESS OUTPUT CELL INTERFACE TIMING ............................................ 488

FIGURE 53 ...... INGRESS INPUT CELL INTERFACE TIMING ................................................ 489

FIGURE 54 ...... EGRESS OUTPUT CELL INTERFACE TIMING.............................................. 490

FIGURE 55 ...... INGRESS SRAM INTERFACE TIMING ........................................................... 492

FIGURE 56 ...... EGRESS SRAM INTERFACE TIMING ............................................................493

FIGURE 57 ...... JTAG PORT INTERFACE TIMING .................................................................. 494

FIGURE 58 ...... ATLAS-1K800 THETA JA VS. AIR FLOW GRAPH .........................................496

FIGURE 59 ...... 432 PIN SBGA – 40 X 40 MM BODY -(B SUFFIX) .......................................... 497

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LIST OF TABLES

TABLE 1 .......... INGRESS VC TABLE ......................................................................................... 53

TABLE 2 .......... INGRESS VC TABLE CELL FIELDS .................................................................55

TABLE 3 .......... INGRESS VC TABLE STATUS FIELD .............................................................. 62

TABLE 4 .......... INGRESS VC TABLE CONFIGURATION FIELD .............................................. 63

TABLE 5 .......... INGRESS VC TABLE OAM CONFIGURATION FIELD ..................................... 65

TABLE 6 .......... INGRESS INTERNAL STATUS FIELD .............................................................. 67

TABLE 7 .......... INGRESS VC TABLE MISCELLANEOUS FIELDS............................................ 68

TABLE 8 .......... INGRESS VC TABLE ACTIVATION FIELDS.....................................................70

TABLE 9 .......... EGRESS VC TABLE .......................................................................................... 71

TABLE 10 ........ EGRESS VC TABLE CONNECTION IDENTIFIER FIELDS .............................. 72

TABLE 11 ........ EGRESS VC TABLE ACTIVATION FIELD ........................................................ 76

TABLE 12 ........ EGRESS VC TABLE STATUS FIELD................................................................ 76

TABLE 13 ........ EGRESS VC TABLE CONFIGURATION FIELD................................................78

TABLE 14 ........ EGRESS OAM CONFIGURATION FIELD ......................................................... 79

TABLE 15 ........ EGRESS INTERNAL STATUS FIELD ...............................................................81

TABLE 16 ........ EGRESS VC TABLE MISCELLANEOUS FIELDS ............................................. 82

TABLE 17 ........ INTERNAL PM TABLE ....................................................................................... 84

TABLE 18 ........ PM TABLE CONFIGURATION FIELD ...............................................................85

TABLE 19 ........ QOS PARAMETERS FOR PERFORMANCE MONITORING............................ 88

TABLE 20 ........ INGRESS AND EGRESS CHANGE OF STATE FIFO .................................... 100

TABLE 21 ........ S/UNI-ATLAS-1K800 ACTIONS ON POLICING WITH COCUP=0 ................ 107

TABLE 22 ........ S/UNI-ATLAS-1K800 ACTIONS ON POLICING WITH COCUP=1 ................ 108

TABLE 23 ........ S/UNI-ATLAS-1K800 ACTIONS WITH PER-PHY POLICING ......................... 110

TABLE 24 ........ INTERNAL PER-PHY POLICING RAM............................................................ 111

TABLE 25 ........ PER-PHY AND PER-VC NON-COMPLIANT CELL COUNTING

PHYVCCOUNT=0......................................................................... 112

TABLE 26 ........ PER-PHY AND PER-VC NON-COMPLIANT CELL COUNTING

PHYVCCOUNT=1......................................................................... 113

TABLE 27 ...... INGRESS/EGRESS OAM CONFIGURATION FIELD......................................122

TABLE 28 ........ F4 TO F5 FAULT MANAGEMENT PROCESSING.......................................... 135

TABLE 29 ........ REGISTER MEMORY MAP ............................................................................. 156

TABLE 30 ........ INSTRUCTION REGISTER ............................................................................. 439

TABLE 31 ........ IDENTIFICATION REGISTER ......................................................................... 440

TABLE 32 ........ BOUNDARY SCAN REGISTER.......................................................................440

TABLE 33 ........ S/UNI-ATLAS-1K800 VC-TABLE AVAILABLE SRAM TYPES.........................449

TABLE 34 ........ OAM TYPE AND FUNCTION TYPE IDENTIFIERS......................................... 450

TABLE 35 ........ VC TABLE CONNECTION SETUP .................................................................. 460

TABLE 36 ........ ABSOLUTE MAXIMUM RATINGS ................................................................... 479

TABLE 37 ........ D.C. CHARACTERISTICS ...............................................................................480

TABLE 38 ........ MICROPROCESSOR INTERFACE READ ACCESS ......................................482

TABLE 39 ........ MICROPROCESSOR INTERFACE WRITE ACCESS ....................................484

TABLE 40 ........ JTAG PORT INTERFACE ................................................................................ 493

TABLE 41 ........ ORDERING INFORMATION............................................................................ 495

TABLE 42 ........ THERMAL INFORMATION ..............................................................................495

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1 FEATURES

• Monolithic single chip device which handles bi-directional ATM Layer

functions including VPI/VCI address translation, cell appending (ingress only),
cell rate policing (ingress only), per-connection counting and I.610 compliant
OAM requirements for 1024 VCs (virtual connections).

• Instantaneous bi-directional transfer rate of 800 Mbit/s supports a bi-

directional cell transfer rate of 1.42x106 cells/s (one STS-12c or four STS-3c).

• The Ingress input interface supports an 8 or 16 bit SCI-PHY interface using

direct addressing for up to 4 PHY devices (compatible with Utopia Level 1
cell-level handshaking) and Multi-PHY addressing for up to 32 PHY devices
(Utopia Level 2 compatible).

• The Ingress output interface supports an 8 or 16 bit SCI-PHY (52 – 64 byte

extended ATM cell with prepend/postpend) interface (compatible with Utopia
Level 1 cell-level handshaking) to a switch fabric.

• The Egress input interface supports an 8 or 16 bit extended cell format SCI-

PHY interface using direct addressing for up to 4 PHY devices (compatible
with Utopia Level 1 cell-level handshaking) and Multi-PHY addressing for up
to 32 PHY devices (Utopia Level 2 compatible).

• The Egress output interface supports an 8 or 16 bit extended cell format SCI-

PHY interface using direct addressing for up to 4 PHY devices (compatible
with Utopia Level 1 cell-level handshaking) and Multi-PHY addressing for up
to 32 PHY devices (Utopia Level 2 compatible).

• Compatible with a wide range of switching fabrics and traffic management

architectures including per-VC or per-PHY queuing.

• Highly flexible OAM-type cell and connection identification which can use

arbitrary PHYID/VPI/VCI values and/or cell appended bytes for connection
identification (N.B. this is an ingress function only). A direct lookup function is
provided in the egress direction. The direct lookup can use an arbitrary
header or prepend/postpend location.

• Ingress functionality includes a highly flexible search engine that covers the

entire PHYID/VPI/VCI address range, programmable dual leaky bucket
UPC/NPC, per-connection CLP0 and CLP1 cell counts (programmable),
OAM-PM termination, generation and monitoring, and OAM-FM termination,
generation and alarm generation (monitoring).

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• Egress functionality includes programmable direct lookup function, OAM-PM

termination, generation and monitoring, per-connection CLP0 and CLP1 cell
counts (programmable) and OAM-FM termination, generation and alarm
generation (monitoring). An egress per-PHY output buffering scheme
resolves the head-of-line blocking issue.

• UPC/NPC function is a programmable dual leaky bucket policing device with

a programmable action (tag, discard, or count only) for each bucket. A total of
3 programmable 16 bit non-compliant cell counts are provided. The non­compliant cell counts may be programmed to count, for example, dropped
CLP0 cells, dropped CLP1 cells, and tagged CLP0 cells. The UPC/NPC
function also has a continuously violating mode, where a programmable
action is taken on all cells regardless of their compliance. AAL5 partial packet
discard is also provided so that the remainder of an AAL5 packet can be
tagged or discarded if a single cell in the packet is tagged or discarded as a
result of violating policing.

• In addition to the per-connection dual leaky bucket, a single leaky bucket

UPC/NPC function is provided on a per-PHY basis. A programmable action
(tag, discard or count only) may be configured for each PHY policing device.
Three programmable non-compliant cell counts are provided for each PHY.
The non-compliant cell counts may be programmed to count, for example,
dropped CLP0 cells, dropped CLP1 cells and tagged CLP0 cells. The per­PHY policing parameters and non-compliant cell counts are maintained in an
on-chip RAM that can be programmed and read via the 16-bit general
purpose microprocessor interface.

• Guaranteed Frame Rate frame-based policing selectable on a per-connection

basis.

• OAM-Performance monitoring is provided in the ingress and egress direction

for bi-directional PM sessions. A maximum of 512 (256 bi-directional
sessions) PM sessions may be simultaneously active. PM is supported on the
F4 and F5 levels. The S/UNI-ATLAS-1K800 provides for the generation of
Forward Monitoring and Backward Reporting PM cells (both segment and
end-to-end), the termination of Forward Monitoring and Backward Reporting
cells, and for non-intrusive monitoring of Forward Monitoring and Backward
Reporting cells. The following statistics are collected when terminating or
monitoring PM flows:

1. Forward Impaired Block.

2. Forward Lost/Misinserted Impaired Block

3. Forward Severely Errored Cell Block (Lost).

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4. Forward Severely Errored Cell Block (Misinserted).

5. Forward Severely Errored Cell Block (BIP-16 violations).

6. Forward Severely Errored Cell Block Combined (non-saturating)

7. Forward Lost CLP0+1 cell count.

8. Forward Lost CLP0 cell count.

9. Forward Tagged CLP0 cell count

10. Forward Misinserted CLP0+1 cell count.

11. Forward Errored cell count.

12. Forward Total Lost CLP0+1 cell count.

13. Forward Total Lost CLP0 cell count.

14. Forward Lost Forward Monitoring cell count.

15. Backward Impaired Block.

16. Backward Lost/Misinserted Impaired Block.

17. Backward Severely Errored Cell Block (Lost).

18. Backward Severely Errored Cell Block (Misinserted).

19. Backward Severely Errored Cell Block (BIP-16 violations).

20. Backward Severely Errored Cell Block Combined (non-saturating)

21. Backward Severely Errored Cell Block Combined (saturating)

22. Backward Lost CLP0+1 cell count.

23. Backward Lost CLP0 cell count.

24. Backward Tagged CLP0 cell count.

25. Backward Misinserted CLP0+1 cell count.

26. Backward Errored cell count.

27. Backward Total Lost CLP0+1 cell count.

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28. Backward Total Lost CLP0 cell count.

29. Backward Lost Fwd Monitoring PM cell count.

30. Backward Lost Backward Reporting PM cell count.

31. Total Transmitted CLP0+1 cell count.

32. Total Transmitted CLP0 cell count.

Statistics for PM sessions are held in on-chip RAM that can be read at any
time through the 16-bit general-purpose microprocessor port.
Paced insertion of PM cells is provided.
PM block size generation and termination is per-session programmable
ranging from 128 – 32768 cells.
Each of the 512 PM sessions can be configured to be a source, sink or
non-intrusive monitoring point of PM cells.

• OAM-Fault Management is provided on a per-connection basis in the ingress

and egress directions. Simultaneous segment and end-to-end F4 and F5 AIS,
RDI and CC cell generation, termination and monitoring is supported. Alarm
bits and interrupt masks are provided on a per-connection basis. F4 to F5 AIS
alarm splitting is provided in the Ingress direction. Paced insertion of FM cells
is provided.

• OAM-Loopback extraction (to a Microprocessor Cell Interface) is per-

connection configurable in both the ingress and egress directions.Includes a
FIFO buffered microprocessor bus interface for cell insertion and extraction
(in both the ingress and egress directions), Ingress and Egress VC Table
access, control and status monitoring and configuration of the device.

• Supports DMA access for cell extraction.

• Uses common external Synchronous Flow-Through SRAM (with or without

parity) for maintaining per-connection information. Separate SRAM’s are used
for the Ingress and Egress context tables.

• Provides a standard 5 signal P1149.1 JTAG test port for boundary scan board

test purposes.

• Provides a generic 16 bit microprocessor bus interface for configuration,

control and status monitoring.

• Low power 0.35 micron, 3.3 V CMOS technology with a 3.3 V UTOPIA (SCI-

PHY), 3.3/5 V Microprocessor I/O interfaces and 3.3 V external synchronous
SRAM interfaces.

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• The UTOPIA (SCI-PHY) and external Synchronous SRAM interfaces are 52

MHz max.

• 432 Super BGA package.

1.1 Policing

• Policing is performed in the ingress direction for adherence to peak cell rate

(PCR), cell delay variation tolerance (CDVT), sustained cell rate (SCR) and
burst tolerance (BT). Violating cells can be noted, dropped or tagged.

• Policing is performed using the virtual scheduling Generic Cell Rate Algorithm

(GCRA) described in ITU-T I.371.

• Two policing instantiations available per VC. The policed cell streams can be

any combination of user cells, OAM cells, Resource Management, high
priority cells or low priority cells.

• Per-PHY policing may also be enabled. Each of 32 PHY devices may have a

single leaky bucket enabled, in addition to the dual leaky bucket of the
connection. Violating cells can be noted (counted only), dropped or tagged.

1.2 Cell Counting

• Counts maintained on a per-VC basis include total low priority cells, total high

priority cells and cells violating the traffic contract. Per-VC counts are
maintained for both the ingress and egress directions.

• Counts maintained on a per-PHY basis (in both the Ingress and Egress

directions) include:

• number of CLP0 cells received.

• number of CLP1 cells received.

• number of OAM cells received.

• number of RM cells received.

• number of errored OAM cells.

• number of errored RM cells.

• number of cells with unassigned/invalid VPI/VCI/PTI.

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• number of cells received with a non-zero GFC (ingress UNI only).

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2 APPLICATIONS

• Mini DSL Access Multiplexers (Mini-DSLAMs).

• Multiservice Access Multiplexers.

• 3rd generation wireless base stations and base station controllers.

• Subscriber Access terminal devices.

• APON Subscriber Access CLE.

• LMDS Subscriber Access CLE.

• Integrated Access Devices.

Figure 1 S/UNI-ATLAS-1K800 in OC3 mini-DSLAM Application

line cards

up to 31

Utopia L2

ports

up to 31

Utopia L2

ports

DSL Phy

DSL Phy

line cards

DSL Phy

DSL Phy

S/UNI-

DUPLEX

S/UNI-

DUPLEX

200Mbps

LVDS

S/UNI-

VORTEX

Up to 8 LVDS links to
S/UNI-Duplex devices
per S/UNI-VORTEX

AnyPhy/

SciPhy

Context
SSRAM

S/UNI­APEX­1K800

Packet/Cell

SDRAM

S/UNI-

ATLAS-

1K800

Ingress

SSRAM

Egress

SSRAM

Figure 1 shows the S/UNI-ATLAS-1K800 in a mini DSLAM application. The
S/UNI-APEX-1K800 acts as a cell buffer and traffic manager. The S/UNI-ATLAS­1K800 provides address resolution and policing.

Phy

Host
CPU

core card

The mini-DSLAM application supports eight LIU devices per Line Card. Each
xDSL modem is connected by its Utopia port to a FPGA which provides an
interface to the AnyPhy bus. If Hot Swap capability is needed the bus signals
need to be passed through switching or tristate drivers to isolate the card when
being plugged in.

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The FPGA performs the task of converting the Utopia to signals compatible with
the APEX-1K800 and ATLAS-1K800.

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3 REFERENCES

• ATM Forum – ATM User-Network Interface Specification, V3.1 September,

1994.

• ITU-T Recommendation I.361 – “B-ISDN ATM Layer Specification”,

November 1995.

• ITU-T Recommendation I.371 – “Traffic Control and Congestion Control in B-

ISDN”, May, 1996.

• ITU-T Recommendation I.610 – “B-ISDN Operation and Maintenance

Principles and Functions”, June, 1997 (Rapporteur’s edition)

• Bell Communications Research – Broadband Switching System (BSS)

Generic Requirements, GR-1110-CORE, Issue 1, September 1994.

• Bell Communications Research – Asynchronous Transfer Mode (ATM) and

ATM Adaptation Layer (AAL) Protocols, GR-1113-CORE, Issue 1, July 1994.

• Bell Communications Research – Generic Requirements for Operations of

Broadband Switching Systems, GR-1248-CORE, Issue 3, August, 1996.

• IEEE 1149.1 – Standard Test Access Port and Boundary Scan Architecture,

May 21, 1990.

• PMC-940212, ATM SCI-PHY, “SATURN Compliant Interface for ATM

Devices”, July 1994, Issue 2.

• ATMF TM4.0 – ATM Forum Traffic Management Specification Version 4.0, af-

tm-0056.000, April, 1996.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC 9

STANDARD PRODUCT

PM7328 S/UNI-ATLAS-1K800

DATASHEET

PMC-2010142 ISSUE 2 ATM LAYER SOLUTION

4 APPLICATION EXAMPLES

Figure 2 S/UNI-ATLAS-1K800 Block Diagram

(Slave)
SCI-PHY Level1 I nterfac e

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SCI-PHY Level1 /Level2 I nterf ace

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC 10

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(Master)
SCI-PHY Level1/Level2 Interface

STANDARD PRODUCT

DATASHEET

PMC-2010142 ISSUE 2 ATM LAYER SOLUTION

PM7328 S/UNI-ATLAS-1K800

5 DESCRIPTION

The S/UNI-ATLAS-1K800 is a bi-directional ATM Layer device that implements
the ATM layer functions including header translation, policing, fault management,
performance monitoring, per-connection and per-PHY counting. The S/UNI­ATLAS-1K800 is intended to be situated between a switch core and a physical
layer device. The S/UNI-ATLAS-1K800 supports a sustained throughput of

1.42x10

6

cells/s in both the ingress (from the PHY into the switch core) and the
egress (from the switch core to the PHY device) directions. The S/UNI-ATLAS­1K800 uses external synchronous flow-through SRAM to store the per­connection data structures. The device is capable of supporting up to 1024
connections.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC 11

STANDARD PRODUCT

PM7328 S/UNI-ATLAS-1K800

DATASHEET

PMC-2010142 ISSUE 2 ATM LAYER SOLUTION

6 PIN DIAGRAM

The S/UNI-ATLAS-1K800 is packaged in a 432 thermally enhanced BGA -SBGA
package having a body size of 40 mm x 40 mm x 1.54 mm and a ball pitch of

1.27 mm. This pin diagram can be downloaded from the PMC-Sierra website
(http://www.pmc-sierra.com).

NC

NC

NC

NC

NC

NC

NC

NC

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC 12

STANDARD PRODUCT

DATASHEET

PMC-2010142 ISSUE 2 ATM LAYER SOLUTION

PM7328 S/UNI-ATLAS-1K800

7 PIN DESCRIPTION

Pin Name Type Pin No. Function

Ingress Input Cell Interface: 28 pins

RFCLK Input

RPOLL Input

U3 The Ingress Input Cell Interface clock (RFCLK) is

used to read words from the PHY receive side into
the S/UNI-ATLAS-1K800 Ingress Input Cell Interface.
RFCLK must cycle at a 52 MHz or lower
instantaneous rate. RSOC, RCA[4:1], RPRTY and
RDAT[15:0] are sampled on the rising edge of
RFCLK. RRDENB[4:1], RADDR[4:0] and RAVALID
are updated on the rising edge of RFCLK.

U4 The Ingress Input Cell Interface Poll pin (RPOLL) is

used to control whether the Ingress Input Cell
Interface operates in SCI-PHY Level 1 mode or SCI­PHY Level 2 mode. If RPOLL is low, the Ingress Input
Cell Interface operates in SCI-PHY Level 1 mode
(compatible with UTOPIA Level 1 cell-level
handshaking). This is a direct addressing mode using
the RCA[4:1] inputs and the RRDENB[4:1] outputs. If
RPOLL is high, the Ingress Input Cell Interface
operates in a SCI-PHY Level 2 mode (compatible
with UTOPIA Level 2). This is a polled addressing
mode using the RADDR[4:0], RAVALID and
RRDENB[1] outputs, and the RCA[1] input. If fewer
than 32 PHY devices are used, the RAVALID pin
need not be connected.

Note: In direct addressing mode, the 4-PHY
configuration is not recommended. Instead the 4­PHY address-polling mode should be used. This
does not apply to the Single or Dual-PHY
configurations.

RPOLL is assumed to be a static input.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC 13

STANDARD PRODUCT

DATASHEET

PMC-2010142 ISSUE 2 ATM LAYER SOLUTION

PM7328 S/UNI-ATLAS-1K800

Pin Name Type Pin No. Function

RSOC Input

RCA[1]

I/O

RCA[2]

RCA[3]

RCA[4]

V2 The Ingress Input Cell Interface Start of Cell (RSOC)

marks the start of the cell on the RDAT[15:0] bus.
When RSOC is high, the first word of the cell
structure is present on the RDAT[15:0] stream. It is
not necessary for RSOC to be asserted for each cell.
An interrupt may be generated if RSOC is high during
any word other than the first word of the cell
structure.

RSOC is sampled on the rising edge of RFCLK and
considered valid only when one of the RRDENB[4:1]
signals so indicates.

U2

T1

R3

R4

The active polarity of these signals is programmable
and defaults to active high.

If the RPOLL pin is low, the ATLAS-1K800 asserts the
appropriate RRDENB[4:1] signal in response to a
round robin polling of the RCA[4:1] signals. Once
committed, the ATLAS-1K800 will transfer an entire
cell from a single PHY before servicing the next. The
ATLAS-1K800 will complete the read of an entire cell
even if the associated RCA[4:1] input is deasserted
during the cell transfer. Sampling of the RCA[4:1]
inputs resumes the cycle after the last octet of a cell
has been transferred.

Note, RCA[1] is an input only.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC 14

STANDARD PRODUCT

DATASHEET

PMC-2010142 ISSUE 2 ATM LAYER SOLUTION

PM7328 S/UNI-ATLAS-1K800

Pin Name Type Pin No. Function

RCA[4:1]
(continued)

RRDENB[1]

RRDENB[2]

RRDENB[3]

RRDENB[4]

Output

U1

T4

T3

T2

If the RPOLL pin is high, the RCA[3:2] pins are
redefined as RADDR[4:3] and the RCA[4] pin is
redefined as RAVALID.

If the RPOLL pin is high, the ATLAS-1K800 polls up
to 32 PHYs using the PHY address signals
RADDR[4:0]. A PHY device being addressed by
RADDR[4:0] is expected to indicate whether or not it
has a complete cell available for transfer by driving
RCA[1] during the clock cycle following that in which
it is addressed. When a cell transfer is in progress,
the ATLAS-1K800 will not poll the PHY device which
is sending the cell and so PHY devices need not
support the cell availability indication during cell
transfer. The selection of a particular PHY device
from which to transfer a cell is indicated by the state
of RADDR[4:0] and when RRDENB[1] is asserted.

Note, RCA[1] is an input only. The RCA[4:1] signals
are sampled on the rising edge of RFCLK.

The active low read enable (RRDENB[4:1]) outputs
are used to initiate the reading of cells from a PHY
device into the Ingress Input Cell Interface.

If the RPOLL pin is low, the ATLAS-1K800 asserts
one of the RRDENB[4:1] outputs to transfer a cell
from one of up to 4 PHY devices. A valid word is
expected on the RDAT[15:0] bus at the second rising
edge of RFCLK after one of the enables is asserted.
When all of the enables are deasserted, no valid data
is expected.

The RRDENB[4:1] outputs are updated on the rising
edge of RFCLK.

If the RPOLL pin is high, the RRDENB[4:2] pins are
redefined as RADDR[2:0]. The RRDENB[1] pin is
used to transfer all cells. The source PHY is selected
by the RADDR[4:0] signals.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC 15

STANDARD PRODUCT

DATASHEET

PMC-2010142 ISSUE 2 ATM LAYER SOLUTION

PM7328 S/UNI-ATLAS-1K800

Pin Name Type Pin No. Function

RADDR[4]

Output

RADDR[3]

RADDR[2]

RADDR[1]

RADDR[0]

RAVALID I/O

R3

T1

T2

T3

T4

If the RPOLL pin is high, the RADDR[4:0] pins are
used for PHY addressing. If the RPOLL pin is low, the
RADDR[4:0] pins are redefined as RCA[3:2] and
RRDENB[4:2].

If the RPOLL pin is high, the RADDR[4:0] signals are
used to address up to 32 PHY devices for the
purposes of polling and selection for cell transfer.
When conducting polling, in order to avoid bus
contention, the ATLAS-1K800 inserts gap cycles
during which RADDR[4:0] is set to 0x1F and
RAVALID is logic 0. When this occurs, no PHY device
should drive RCA[1] during the following clock cycle.
Polling is performed in incrementing sequential order.
The PHY device selected for transfer is based on the
RADDR[4:0] value present when RRDENB[1] is falls.
The RADDR[4:0] bus is updated on the rising edge of
RFCLK.

R4 If the RPOLL pin is high, the PHY Address Valid

(RAVALID) pin is active. If the RPOLL pin is low, the
RAVALID pin is redefined as RCA[4].

If the RPOLL pin is high, the RAVALID pin indicates
that the RADDR[4:0] bus is asserting a valid PHY
address for polling purposes. When this signal is
deasserted, the RADDR[4:0] bus is set to 0x1F.

RAVALID is not necessary when less than 32 PHY
devices are being polled. RAVALID is updated on the
rising edge of RFCLK.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC 16

STANDARD PRODUCT

DATASHEET

PMC-2010142 ISSUE 2 ATM LAYER SOLUTION

PM7328 S/UNI-ATLAS-1K800

Pin Name Type Pin No. Function

RDAT[15]

RDAT[14]

RDAT[13]

RDAT[12]

RDAT[11]

RDAT[10]

RDAT[9]

RDAT[8]

RDAT[7]

RDAT[6]

RDAT[5]

RDAT[4]

RDAT[3]

RDAT[2]

RDAT[1]

RDAT[0]

Input

W1

W2

W3

Y1

Y2

W4

Y3

AA1

AA2

Y4

AA3

AB1

AB2

AA4

AB3

The Ingress Input Cell Interface cell data bus
(RDAT[15:0]) carries the ATM cell octets that are
written to the Ingress Input Cell Interface. The
RDAT[15:0] bus is sampled on the rising edge of
RFCLK and considered valid only when one of the
RRDENB[4:1] signals so indicates. RDAT[15:8] is
only valid if the RBUS8 register bit is low.

AC1

RPRTY Input

V3 The Ingress Input Cell Interface parity (RPRTY)

Ingress SRAM Interface: 96 pins

signal indicates the parity (programmable for odd or
even parity) of the RDAT[15:0] bus. If the RBUS8
register bit is low, the RPRTY signal indicates parity
over the RDAT[15:0] data bus. If RBUS8 is high, the
RPRTY signal indicates parity over the RDAT[7:0]
data bus. A maskable interrupt status is generated
upon a parity error; no other actions are taken. The
RPRTY signal is sampled on the rising edge of
RFCLK and is considered valid only when one of the
RRDENB[4:1] signals so indicates.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC 17

STANDARD PRODUCT

DATASHEET

PMC-2010142 ISSUE 2 ATM LAYER SOLUTION

PM7328 S/UNI-ATLAS-1K800

Pin Name Type Pin No. Function

ISYSCLK Input

ISD[63]

I/O AG1

ISD[62]

ISD[61]

ISD[60]

ISD[59]

ISD[58]

ISD[57]

ISD[56]

ISD[55]

ISD[54]

ISD[53]

ISD[52]

ISD[51]

AH21 The Ingress System clock (ISYSCLK) is used for the

Ingress portion of the ATLAS-1K800. ISYSCLK must
cycle at a 52 MHz or lower instantaneous rate, but a
high enough rate to maintain an 800Mbit/s
throughput. ISADSB, ISOEB, ISRWB are updated on
the rising edge of ISYSCLK. When ISD[63:0] and
ISP[7:0] are outputs, they are updated on the rising
edge of ISYSCLK. When ISD[63:0] and ISP[7:0] are
inputs, they are sampled on the rising edge of
ISYSCLK.

The bi-directional Ingress VC Table SRAM data bus

AG2

AF4

AG3

AH1

(ISD[63:0]) pins interface directly with the
synchronous SRAM data ports.

A SRAM read is performed when the ATLAS-1K800
drives the address strobe (ISADSB) low and the
ISRWB output high. The ATLAS-1K800 tristates the
ISD[63:0] pins and samples the value driven by the

AJ5

AH6

AK5

SRAM on the second rising edge of the ISYSCLK
input after ISADSB is asserted.

A SRAM write is performed when the ATLAS-1K800
drives the address strobe low (ISADSB) and the

AL5

AJ6

AK6

AL6

AJ7

ISRWB output low. The ATLAS-1K800 presents valid
data on the ISD[63:0] pins upon the rising edge of
ISYSCLK which is written into the SRAM on the next
ISYSCLK rising edge. ISD[63:0] is tristated on the
rising edge of ISYSCLK. Contention is avoided by not
performing a write during the cycle after a read burst.

ISD[50]

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC 18

AH8

STANDARD PRODUCT

DATASHEET

PMC-2010142 ISSUE 2 ATM LAYER SOLUTION

PM7328 S/UNI-ATLAS-1K800

Pin Name Type Pin No. Function

ISD[49]

ISD[48]

ISD[47]

ISD[46]

ISD[45]

ISD[44]

ISD[43]

ISD[42]

ISD[41]

ISD[40]

ISD[39]

ISD[38]

ISD[37]

ISD[36]

ISD[35]

I/O AK7

AL7

AJ8

AH9

AK8

AL8

AJ9

AK9

AL9

AJ10

AH11

AK10

AL10

AJ11

AH12

Continued

ISD[34]

ISD[33]

ISD[32]

AK11

AL11

AJ12

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC 19

STANDARD PRODUCT

DATASHEET

PMC-2010142 ISSUE 2 ATM LAYER SOLUTION

PM7328 S/UNI-ATLAS-1K800

Pin Name Type Pin No. Function

ISD[31]

ISD[30]

ISD[29]

ISD[28]

ISD[27]

ISD[26]

ISD[25]

ISD[24]

ISD[23]

ISD[22]

ISD[21]

ISD[20]

ISD[19]

ISD[18]

ISD[17]

ISD[16]

I/O

AH13

AK12

AL12

AJ13

AK13

AL13

AJ14

AK14

AH15

AJ15

AL16

AK16

AJ16

AH16

AL17

Continued

AK17

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC 20

STANDARD PRODUCT

DATASHEET

PMC-2010142 ISSUE 2 ATM LAYER SOLUTION

PM7328 S/UNI-ATLAS-1K800

Pin Name Type Pin No. Function

ISD[15]

ISD[14]

ISD[13]

ISD[12]

ISD[11]

ISD[10]

ISD[9]

ISD[8]

ISD[7]

ISD[6]

ISD[5]

ISD[4]

ISD[3]

ISD[2]

ISD[1]

ISD[0]

I/O

AJ17

AK18

AH17

AJ18

AL19

AK19

AJ19

AL20

AK20

AH19

AJ20

AL21

AK21

AH20

AJ21

Continued

AL22

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC 21

STANDARD PRODUCT

DATASHEET

PMC-2010142 ISSUE 2 ATM LAYER SOLUTION

PM7328 S/UNI-ATLAS-1K800

Pin Name Type Pin No. Function

ISP[7]

ISP[6]

ISP[5]

ISP[4]

ISP[3]

ISP[2]

ISP[1]

ISP[0]

I/O

AD3

AE1

AE2

AD4

AE3

AF1

AF2

AF3

The Ingress VC Table SRAM parity (ISP[7:0]) pins
provide parity protection over the ISD[63:0] data bus.

ISP[0] completes odd parity for ISD[7:0]

ISP[1] completes odd parity for ISD[15:8]

ISP[2] completes odd parity for ISD[23:16]

ISP[3] completes odd parity for ISD[31:24]

ISP[4] completes odd parity for ISD[39:32]

ISP[5] completes odd parity for ISD[47:40]

ISP[6] completes odd parity for ISD[55:48]

ISP[7] completes odd parity for ISD[63:56]

ISP[7:0] has the same timing as ISD[63:0]. When
data are being written into the SRAM, the ATLAS­1K800 generates correct parity. When data are being
read from the SRAM, the ATLAS-1K800 asserts a
maskable interrupt indication upon parity error
detection. No other action is taken, therefore, the
ISP[7:0] may be unconnected if parity protection is
not required.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC 22

STANDARD PRODUCT

DATASHEET

PMC-2010142 ISSUE 2 ATM LAYER SOLUTION

PM7328 S/UNI-ATLAS-1K800

Pin Name Type Pin No. Function

ISA[19]

ISA[18]

ISA[17]

ISA[16]

ISA[9]

ISA[8]

ISA[7]

ISA[6]

ISA[5]

ISA[4]

ISA[3]

ISA[2]

ISA[1]

ISA[0]

Output

AJ23

AL24

AK24

AH23

AK26

AJ26

AL27

AK27

AH26

AJ27

AH31

AG29

AF28

AG30

The Ingress VC Table SRAM (ISA[19:0]) outputs
identify the SRAM locations accessed.

The least significant bits (ISA[9:0]) locate 1 of 1024
possible Ingress VC Table entries.

The four most significant bits (ISA[19:16]) identify the
fields within an Ingress VC Table record. In most
applications, the ISA[19:16] pins are decoded to
SRAM chip selects. Physical memory need not be
allocated for unused fields.

The ISA[9:0] outputs are also used to access the
Ingress VC Table Search Table.

The ISA[19:0] bus is updated on the rising edge of
ISYSCLK.

ISRWB Output

ISADSB Output

AJ22 The Ingress VC Table SRAM Read Write Bar

(ISRWB) qualifies the data and parity busses. If the
ISRWB output is asserted high, a read operation is
performed and the ATLAS-1K800 tristates the data
and parity busses so they may be driven by the
SRAM. If the ISRWB output is asserted low, a write
operation is performed and the ATLAS-1K800 drives
the data and parity busses.

ISRWB is updated on the rising edge of ISYSCLK.

AK23 The Ingress VC Table SRAM Address Strobe

(ISADSB) qualifies the address bus. If the ISADSB
output is asserted low, an SRAM access is initiated.

ISADSB is updated on the rising edge of ISYSCLK.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC 23