PMC PM73123-PI Datasheet

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DATASHEET PMC-2000097 ISSUE 2 8 LINK CES/DBCES AAL1 SAR

PM73123 AAL1GATOR-8

PM73123

AAL1GATOR-8

8 LINK CES/DBCES ATM ADAPTATION LAYER 1 (AAL1) SEGMENTATION AND

REASSEMBLY PROCESSOR

DATASHEET

PROPRIET A R Y A ND CONFIDENTIAL

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ISSUE 2: AUGUST 2001

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DATASHEET PMC-2000097 ISSUE 2 8 LINK CES/DBCES AAL1 SAR

PM73123 AAL1GATOR-8

REVISION HISTORY

Issue No.

1 January

Issue Date

Details of Change

Document created.

2000

2 August

Updated with additional detail and clarification.

2001

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PM73123 AAL1GATOR-8

CONTENTS

1 FEATURES ............................................................................................20

2 APPLICATIONS .....................................................................................26

3 REFERENCES.......................................................................................27

4 APPLICATION EXAMPLES ...................................................................29

4.1 INTEGRA TED ACCESS DEVICE................................................29

4.2 ATM PASSIVE OPTICAL NETWORKS (APON)..........................30

5 BLOCK DIAGRAM .................................................................................31

6 DESCRIPTION.......................................................................................32

7 PIN DIAGRAM........................................................................................33

8 PIN DESCRIPTION................................................................................35

9 FUNCTIONAL DESCRIPTION............................................................... 64

9.1 UTOPIA INTERFACE BLOCK (UI)..............................................64

9.1.1 UTOPIA SOURCE INTERFACE (SRC_INTF)...................66

9.1.2 UTOPIA SINK INTERFACE (SNK_INTF)..........................69

9.1.3 UTOPIA MUX BLOCK (UMUX).........................................72

9.2 AAL1 SAR PROCESSING BLOCK (A1SP).................................73

9.2.1 AAL1 SAR TRANSMIT SIDE (TXA1SP)...........................75

9.2.2 AAL1 SAR RECEIVE SIDE (RXA1SP)...........................102

9.3 AAL1 CLOCK GENERATION CONTROL ................................. 137

9.3.1 DESCRIPTION ............................................................... 137

9.3.2 CGC BLOCK DIAGRAM.................................................139

9.3.3 FUNCTIONAL DESCRIPTION........................................139

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9.4 PROCESSOR INTERFACE BLOCK (PROCI)...........................151

9.4.1 INTERRUPT DRIVEN ERROR/STATUS REPORTING.. 156

9.4.2 ADD QUEUE FIFO .........................................................159

9.5 RAM INTERFACE BLOCK (RAMI)............................................161

9.6 LINE INTERFACE BLOCK (AAL1_LI) ....................................... 162

9.6.1 CONVENTIONS..............................................................162

9.6.2 FUNCTIONAL DESCRIPTION........................................162

9.6.3 TRANSMIT DIRECTION.................................................167

9.7 JT AG TEST ACCESS PORT.....................................................171

10 MEMORY MAPPED REGISTER DESCRIPTION ................................172

10.1 INITIALIZATION ........................................................................173

10.2 A1SP AND LINE CONFIGURATION STRUCTURES................173

10.2.1 HS_LIN_REG..................................................................174

10.3 TRANSMIT STRUCTURES SUMMARY....................................179

10.3.1 P_FILL_CHAR................................................................ 181

10.3.2 T_SEQNUM_TBL...........................................................181

10.3.3 T_COND_SIG.................................................................182

10.3.4 T_COND_DATA.............................................................. 184

10.3.5 RESERVED (TRANSMIT SIGNALING BUFFER)...........185

10.3.6 T_OAM_QUEUE.............................................................186

10.3.7 T_QUEUE_TBL..............................................................187

10.3.8 RESERVED (TRANSMIT DATA BUFFER) .....................200

10.4 RECEIVE DATA STRUCTURES SUMMARY............................201

10.4.1 R_OAM_QUEUE_TBL....................................................203

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10.4.2 R_OAM_CELL_CNT.......................................................204

10.4.3 R_DROP_OAM_CELL.................................................... 204

10.4.4 R_SRTS_CONFIG.......................................................... 205

10.4.5 R_CRC_SYNDROME.....................................................206

10.4.6 R_CH_TO_QUEUE_TBL................................................ 209

10.4.7 R_COND_SIG.................................................................212

10.4.8 R_COND_DATA..............................................................213

10.4.9 RESERVED (RECEIVE SRTS QUEUE).........................214

10.4.10 RESERVED (RECEIVE SIGNALING BUFFER)..........215

10.4.11 R_QUEUE_TBL...........................................................217

10.4.12 R_OAM_QUEUE.........................................................234

10.4.13 RESERVED (RECEIVE DATA BUFFER).....................235

11 NORMAL MODE REGISTER DESCRIPTION......................................237

11.1 COMMAND REGISTERS..........................................................238

11.2 RAM INTERFACE REGISTERS................................................ 244

11.3 UTOPIA INTERFACE REGISTERS...........................................246

11.4 LINE INTERFACE REGISTERS................................................255

11.5 DIRECT MODE REGISTERS....................................................255

11.6 INTERRUPT AND STATUS REGISTERS .................................258

11.7 IDLE CHANNEL DETECTION CONFIGURATION AND STATUS

REGISTERS..............................................................................274

11.8 DLL CONTROL AND STATUS REGISTERS.............................288

12 OPERATION ........................................................................................293

12.1 HARDWARE CONFIGURATION...............................................293

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12.2 START-UP................................................................................. 293

12.2.1 LINE CONFIGURATION.................................................294

12.2.2 QUEUE CONFIGURATION ............................................294

12.2.3 ADDING QUEUES.......................................................... 294

12.2.4 LINE CONFIGURATION DETAILS ................................. 294

12.3 UTOPIA INTERFACE CONFIGURATION..................................297

12.4 SPECIAL QUEUE CONFIGURATION MODES.........................297

12.4.1 AAL0...............................................................................297

12.5 JTAG SUPPORT .......................................................................298

12.5.1 TAP CONTROLLER........................................................299

13 FUNCTIONAL TIMING.........................................................................306

13.1 SOURCE UTOPIA.....................................................................307

13.2 SINK UTOPIA............................................................................312

13.3 PROCESSOR I/F ......................................................................318

13.4 EXTERNAL CLOCK GENERATION CONTROL I/F (CGC)....... 320

13.4.1 SRTS DATA OUTPUT ..................................................... 320

13.4.2 CHANNEL UNDERRUN STATUS OUTPUT...................321

13.4.3 ADAPTIVE STATUS OUTPUT........................................ 322

13.5 EXT FREQ SELECT INTERFACE.............................................323

13.6 LINE INTERFACE TIMING........................................................324

13.6.1 16 LINE MODE............................................................... 324

13.6.2 H-MVIP TIMING..............................................................327

13.6.3 DS3/E3 TIMING..............................................................331

14 ABSOLUTE MAXIMUM RATINGS.......................................................333

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15 D.C. CHARACTERISTICS ................................................................... 334

16 A.C. TIMING CHARACTERISTICS......................................................336

16.1 RESET TIMING.........................................................................336

16.2 SYS_CLK TIMING..................................................................... 337

16.3 NCLK TIMING............................................................................338

16.4 MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS

...................................................................................................339

16.5 EXTERNAL CLOCK GENERATION CONTROL INTERFACE... 343

16.6 RAM INTERFACE......................................................................344

16.7 UTOPIA INTERFACE................................................................345

16.8 LINE I/F TIMING........................................................................348

16.8.1 DIRECT LOW SPEED TIMING.......................................348

16.8.2 H-MVIP TIMING..............................................................350

16.8.3 HIGH SPEED TIMING ....................................................352

16.9 JT AG TIMING............................................................................ 354

17 ORDERING AND THERMAL INFORMATION......................................356

18 MECHANICAL INFORMATION ............................................................ 357

19 DEFINITIONS.......................................................................................359

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LIST OF REGISTERS

.............................................................................................................242

(A_CLK_CFG)...................................................................................... 243

.............................................................................................................245

(UI_COMN_CFG).................................................................................247

(UI_SRC_ADD_CFG)........................................................................... 253

(UI_SNK_ADD_CFG)...........................................................................254

REGISTERS(LS_LN_CFG_REG)........................................................ 256

.............................................................................................................259

(A1SP_TIDLE_FIFO) ...........................................................................265

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(MSTR_INTR_EN_REG)...................................................................... 270

(A1SP_EN_REG)................................................................................. 271

.............................................................................................................273

(RX_CHG_PTR)...................................................................................279

CONFIGURATION (PAT_MTCH_CFG )...............................................283

CONFIGURA TION TABLE ...................................................................285

.............................................................................................................289

REGISTER 0X84002H: DLL SW RESET REGISTER (DLL_SW_RST_REG)290 REGISTER 0X84003H: DLL CONTROL STATUS REGISTER (DLL_STAT_REG)291

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LIST OF FIGURES

FIGURE 1. AAL1GATOR-8 IN AN INTEGRATED ACCESS DEVICE (IAD)

APPLICATION. .................................................................................................29

FIGURE 3. AAL1GA TOR-8 IN AN APON ONU APPLICA TION.........................30

FIGURE 5 - AAL1GATOR-8 INTERNAL BLOCK DIAGRAM ...........................31

FIGURE 6 DATA FLOW AND BUFFERING IN THE UI AND THE A1SP BLOCKS 65

FIGURE 8 UI BLOCK DIAGRAM...................................................................66

FIGURE 10 A1SP BLOCK DIAGRAM.............................................................74

FIGURE 12 CAPTURE OF T1 SIGNALING BITS (SHIFT_CAS=0)................76

FIGURE 14 CAPTURE OF E1 SIGNALING BITS (SHIFT_CAS=0) ...............76

FIGURE 16 TRANSMIT FRAME TRANSFER CONTROLLER.......................76

FIGURE 18 T1 ESF SDF-MF FORMAT OF THE T_DATA_BUFFER..............78

FIGURE 20 T1 SF-SDF-MF FORMAT OF THE T_DATA_BUFFER................78

FIGURE 22 T1 SDF-FR FORMAT OF THE T_DATA_BUFFER......................79

FIGURE 24 E1 SDF-MF FORMAT OF THE T_DATA_BUFFER.....................80

FIGURE 26 E1 SDF-MF WITH T1 SIGNALING FORMAT OF THE

T_DATA_BUFFER............................................................................................80

FIGURE 28 E1 SDF-FR FORMAT OF THE T_DATA_BUFFER......................81

FIGURE 30 UNSTRUCTURED FORMAT OF THE T_DATA_BUFFER..........81

FIGURE 32 SDF-MF T1 ESF FORMAT OF THE T_SIGNALING_BUFFER....82

FIGURE 34 SDF-MF T1 SF FORMAT OF THE T_SIGNALING BUFFER ...... 82

FIGURE 36 SDF-MF E1 FORMAT OF THE T_SIGNALING_BUFFER...........82

FIGURE 38 SDF-MF E1 WITH T1 SIGNALING FORMAT OF THE

T_SIGNALING_BUFFER.................................................................................. 83

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FIGURE 40 TRANSMIT SIDE SRTS FUNCTION...........................................84

FIGURE 42 CAS IDLE DETECTION CONFIGURATION REGISTER

STRUCTURE.................................................................................................... 85

FIGURE 44 CAS IDLE DETECTION INTERRUPT WORD.............................86

FIGURE 46 PROCESSOR CONTROLLED IDLE DETECTION INTERRUPT WORD 86

FIGURE 48 PROCESSOR CONTROLLED CONFIGURATION REGISTER

STRUCTURE.................................................................................................... 87

FIGURE 50 TX CHANNEL ACTIVE/IDLE BIT TABLE STRUCT URE..............87

FIGURE 52 PAT_MTCH_CFG REGISTER STRUCTURE.............................. 88

FIGURE 53 PATTERN MATCH IDLE DETECTION REGISTER STRUCTURE89

FIGURE 55 PATTERN MATCH IDLE DETECTION INTERRUPT WORD......89

FIGURE 57 FRAME ADVANCE FIFO OPERATION.......................................91

FIGURE 59 PAYLOAD GENERATION............................................................99

FIGURE 61 LOCAL LOOPBACK.................................................................. 102

FIGURE 63 CELL HEADER INTERPRETATION..........................................104

FIGURE 65 FAST SN ALGORITHM.............................................................. 110

FIGURE 67 RECEIVE CELL PROCESSING FOR FAST SN.........................111

FIGURE 69 ROBUST SN ALGORITHM........................................................ 114

FIGURE 71 CELL RECEPTION.................................................................... 116

FIGURE 73 T1 ESF SDF-MF FORMAT OF THE R_DATA_BUFFER........... 117

FIGURE 75 T1 SF SDF-MF FORMAT OF THE R_DATA_BUFFER ............. 117

FIGURE 77 T1 SDF-FR FORMAT OF THE R_DATA_BUFFER ................... 118

FIGURE 79 E1 SDF-MF FORMAT OF THE R_DATA_BUFFER................... 118

FIGURE 81 E1 SDF-MF WITH T1 SIGNALING FORMAT OF THE

R_DATA_BUFFER.......................................................................................... 119

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FIGURE 83 E1 SDF-FR FORMAT OF THE R_DATA_BUFFER...................119

FIGURE 85 UNSTRUCTURED FORMAT OF THE R_DATA_BUFFER........120

FIGURE 87 T1 ESF SDF-MF FORMAT OF THE R_SIG_BUFFER..............120

FIGURE 89 T1 SF SDF-MF FORMAT OF THE R_SIG_BUFFER ................ 121

FIGURE 91 E1 SDF-MF FORMAT OF THE R_SIG_BUFFER......................121

FIGURE 93 E1 SDF-MF WITH T1 SIGNALING FORMAT OF THE

R_SIG_BUFFER.............................................................................................122

FIGURE 49 POINTER/STRUCTURE STATE MACHINE..............................127

FIGURE 96 OVERRUN DETECTION...........................................................129

FIGURE 52 DBCES RECEIVE SIDE BUFFERING ......................................132

FIGURE 54 OUTPUT OF T1 SIGNALING BITS (SHIFT_CAS=0)................ 134

FIGURE 56 OUTPUT OF E1 SIGNALING BITS (SHIFT_CAS=0)................134

FIGURE 58 CHANNEL-TO-QUEUE TABLE OPERATION ...........................136

FIGURE 60 RECEIVE SIDE SRTS SUPPORT.............................................137

FIGURE 62 SRTS DATA............................................................................... 141

FIGURE 64 CHANNEL STATUS FUNCTIONAL TIMING..............................141

FIGURE 66 ADAPTIVE DATA FUNCTIONAL TIMING..................................143

FIGURE 67 EXT FREQ SELECT FUNCTIONAL TIMING.............................144

FIGURE 69 RECEIVE SIDE SRTS SUPPORT.............................................145

FIGURE 71 DIRECT ADAPTIVE CLOCK OPERATION ............................... 147

FIGURE 73 MEMORY MAP..........................................................................152

FIGURE 75 A1SP SRAM MEMORY MAP.....................................................152

FIGURE 77 CONTROL REGISTERS MEMORY MAP..................................153

FIGURE 79 TRANSMIT DATA STRUCTURES MEMORY MAP ...................154

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FIGURE 81 RECEIVE DATA STRUCTURES ...............................................155

FIGURE 83 NORMAL MODE REGISTERS MEMORY MAP ........................ 156

FIGURE 85 INTERRUPT HIERARCHY........................................................ 157

FIGURE 87 ADDQ_FIFO WORD STRUCTURE........................................... 159

FIGURE 89 LINE INTERFACE BLOCK ARCHITECT URE ........................... 164

FIGURE 91 CAPTURE OF T1 SIGNALING BITS.........................................167

FIGURE 93 CAPTURE OF E1 SIGNALING BITS ........................................167

FIGURE 95 OUTPUT OF T1 SIGNALING BITS...........................................168

FIGURE 97 OUTPUT OF E1 SIGNALING BITS........................................... 169

FIGURE 99 SDF-MF FORMAT OF THE T_SIGNALING BUFFER ............... 186

FIGURE 100 R_CRC_SYNDROME MASK BIT TABLE LEGEND................207

FIGURE 101 BOUNDARY SCAN ARCHITECT URE.....................................298

FIGURE 102 TAP CONTROLLER FINITE STATE MACHINE ......................300

FIGURE 103 INPUT OBSERVATION CELL (IN_CELL)................................303

FIGURE 104 OUTPUT CELL (OUT_CELL)..................................................304

FIGURE 105 BIDIRECTIONAL CELL (IO_CELL).........................................304

FIGURE 106 LAYOUT OF OUTPUT ENABLE AND BIDIRECTIONAL CELLS 305

FIGURE 107 PIPELINED SINGLE-CYCLE DESELECT SSRAM.................306

FIGURE 108 PIPELINED ZBT SSRAM........................................................306

FIGURE 109 SRC_INTF START OF TRANSFER TIMING (UTOPIA 1 ATM MODE) 307

FIGURE 111 SRC_INTF END-OF-TRANSFER TIMING (UTOPIA 1 ATM MODE)308 FIGURE 113 UI_SRC_INTF START-OF-TRANSFER TIMING (UTOPIA 1 PHY

MODE) 308

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FIGURE 114 UI_SRC_INTF END-OF-TRANSFER (UTOPIA 1 PHY MODE)309 FIGURE 116 UI_SRC_INTF START-OF-TRANSFER TIMING (UTOPIA 2 PHY

MODE) 310 FIGURE 118 UI_SRC_INTF END-OF-TRANSFER TIMING (UTOPIA 2 PHY

MODE) 310 FIGURE 120 UI_SRC_INTF START-OF-TRANSFER TIMING (ANY-PHY PHY

MODE) 311 FIGURE 122 UI_SRC_INTF END-OF-TRANSFER TIMING (ANY-PHY PHY

MODE) 311 FIGURE 124 SNK_INTF START-OF-TRANSFER TIMING (UTOPIA 1 ATM

MODE) 312 FIGURE 126 SNK_INTF END-OF-TRANSFER TIMING (UTOPIA 1 ATM

MODE) 313 FIGURE 128 SNK_INTF START-OF-TRANSFER TIMING (UTOPIA 1 PHY

MODE) 314 FIGURE 130 SNK_INTF START-OF-TRANSFER UTOPIA 2 PHY MODE...314

FIGURE 132 SNK_INTF CLAV DISABLE UTOPIA 2 ( PHY MODE) ............315

FIGURE 134 SNK_INTF END-OF-TRANSFER UTOPIA 2 ( PHY MODE)....315

FIGURE 136 SNK_INTF START-OF-TRANSFER (ANY-PHY PHY MODE)..316

FIGURE 138 SNK_INTF END-OF-TRANSFER (ANY-PHY PHY MODE) ..... 317

FIGURE 140 MICROPROCESSOR WRITE ACCESS .................................318

FIGURE 142 MICROPROCESSOR READ ACCESS ................................... 319

FIGURE 144 MICROPROCESSOR WRITE ACCESS WITH ALE................319

FIGURE 146 MICROPROCESSOR READ ACCESS WITH ALE .................319

FIGURE 148 SRTS DATA............................................................................. 320

FIGURE 150 CHANNEL STATUS FUNCTIONAL TIMING............................321

FIGURE 152 ADAPTIVE DATA FUNCTIONAL TIMING................................323

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FIGURE 154 EXT FREQ SELECT FUNCTIONAL TIMING...........................324

FIGURE 156 RECEIVE LINE SIDE T1 TIMING(RL_CLK = 1.544 MHZ)......324

FIGURE 158 RECEIVE LINE SIDE E1 TIMING(RL_CLK = 2.048 MHZ)...... 325

FIGURE 160 MVIP-90 RECEIVE FUNCTIONAL TIMING.............................325

FIGURE 161 TRANSMIT LINE SIDE T1 TIMING(TL_CLK = 1.544 MHZ)....326

FIGURE 163 TRANSMIT LINE SIDE E1 TIMING(TL_CLK = 2.048 MHZ)....326

FIGURE 165 MVIP-90 TRANSMIT FUNCTIONAL TIMING..........................327

FIGURE 166 RECEIVE H-MVIP TIMING, CLOSE-UP VIEW........................328

FIGURE 168 RECEIVE H-MVIP TIMING, EXPANDED VIEW.......................329

FIGURE 169 TRANSMIT H-MVIP TIMING, CLOSE-UP VIEW ..................... 330

FIGURE 171 TRANSMIT H-MVIP TIMING, EXPANDED VIEW....................331

FIGURE 172 RECEIVE HIGH-SPEED FUNCTIONAL TIMING ....................331

FIGURE 174 TRANSMIT HIGH-SPEED FUNCTIONAL TIMING..................332

FIGURE 176 RSTB TIMING .........................................................................337

FIGURE 177 SYS_CLK TIMING...................................................................338

FIGURE 178 NCLK TIMING .........................................................................338

FIGURE 179 MICROPROCESSOR INTERFACE READ TIMING ................ 340

FIGURE 180 MICROPROCESSOR INTERFACE WRITE TIMING ..............342

FIGURE 181 EXTERNAL CLOCK GENERATION CONTROL INTERFACE TIMING 343

FIGURE 182 RAM INTERFACE TIMING......................................................344

FIGURE 183 SINK UTOPIA INTERFACE TIMING ....................................... 346

FIGURE 184 SOURCE UTOPIA INTERFACE TIMING.................................347

FIGURE 185 TRANSMIT LOW SPEED INTERFACE TIMING .....................348

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FIGURE 186 RECEIVE LOW SPEED INTERFACE TIMING........................ 349

FIGURE 187 H-MVIP SINK DATA & FRAME PULSE TIMING......................351

FIGURE 188 H-MVIP INGRESS DATA TIMING............................................351

FIGURE 189 TRANSMIT HIGH SPEED TIMING..........................................352

FIGURE 190 RECEIVE HIGH SPEED INTERFACE TIMING.......................353

FIGURE 191 JTAG PORT INTERFACE TIMING..........................................355

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LIST OF TABLES

TABLE 1 - LINE INTERFACE SIGNAL TABLE SELECTION......................... 50

TABLE 3 - LINE INTERFACE SUMMARY.....................................................56

TABLE 5 CFG_ADDR AND PHY_ADDR BIT USAGE IN SRC DIRECTION...69 TABLE 7 CFG_ADDR AND PHY_ADDR BIT USAGE IN SNK DIRECTION... 72 TABLE 9 MINIMUM PARTIAL CELL SIZE PERMITTED IF ALL CONNECTIONS

ARE ACTIVE...................................................................................................100

TABLE 10 CHANNEL STATUS.....................................................................142

TABLE 12 BUFFER DEPTH .........................................................................143

TABLE 14 FREQUENCY SELECT – T1 MODE............................................ 149

TABLE 16 FREQUENCY SELECT – E1 MODE ...........................................151

TABLE 18 LINE_MODE ENCODING............................................................ 163

TABLE 19 AAL1GATOR-8 MEMORY MAP................................................... 172

TABLE 20 A1SP AND LINE CONFIGURATION STRUCT URES SUMMARY1 73

TABLE 21 TRANSMIT STRUCTURES SUMMARY...................................... 179

TABLE 22 R_CRC_SYNDROME MASK BIT TABLE....................................207

TABLE 23R_QUEUE_TBL FORMAT .............................................................. 217

TABLE 24 REGISTER MEMORY MAP.........................................................238

TABLE 25 COMMAND REGISTER MEMORY MAP..................................... 238

TABLE 26 RAM INTERFACE REGISTERS MEMORY MAP ........................244

TABLE 27 UTOPIA INTERFACE REGISTERS MEMORY MAP...................246

TABLE 20 CFG_ADDR AND PHY_ADDR BIT USAGE IN SRC DIRECTION253 TABLE 29 CFG_ADDR AND PHY_ADDR BIT USAGE IN SNK DIRECTION254

TABLE 22 LINE INTERFACE REGISTER MEMORY MAP SUMMARY........ 255

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TABLE 23 DIRECT LOW SPEED MODE REGISTER MEMORY MAP ........255

TABLE 24 INTERRUPT AND STATUS REGISTERS MEMORY MAP.......... 258

TABLE 25 IDLE CHANNEL DETECTION CONFIGURATION AND STATUS

REGISTERS MEMORY MAP..........................................................................274

TABLE 26 DLL CONTROL AND STATUS REGISTERS MEMORY MAP......288

TABLE 27 CHANNEL STATUS.....................................................................321

TABLE 29 FRAME DIFFERENCE ................................................................322

TABLE 31 ABSOLUTE MAXIMUM RATINGS...............................................333

TABLE 32 AAL1GATOR-8 D.C. CHARACTERIST ICS..................................334

TABLE 33 RTSB TIMING..............................................................................336

TABLE 34 SYS_CLK TIMING.......................................................................337

TABLE 35 NCLK TIMING..............................................................................338

TABLE 36 MICROPROCESSOR INTERFACE READ ACCESS...................339

TABLE 37 MICROPROCESSOR INTERFACE WRITE ACCESS.................341

TABLE 38 EXTERNAL CLOCK GENERATION CONTROL INTERFACE..... 343

TABLE 39 RAM INTERFACE ........................................................................ 344

TABLE 40 UTOPIA SOURCE AND SINK INTERFACE................................345

TABLE 41 TRANSMIT LOW SPEED INTERFACE TIMING..........................348

TABLE 42 RECEIVE LOW SPEED INTERFACE TIMING............................349

TABLE 43 H-MVIP SINK TIMING..................................................................350

TABLE 44 H-MVIP SOURCE TIMING...........................................................351

TABLE 45 TRANSMIT HIGH SPEED INTERFACE TIMING.........................352

TABLE 46 RECEIVE HIGH SPEED INTERFACE TIMING ........................... 353

TABLE 47 JTAG PORT INTERFACE............................................................354

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TABLE 48 - AAL1GATOR-8 (PM73123) ORDERING INFORMATION..........356

TABLE 49 – AAL1GATOR-8 (PM73123) THERMAL INFORMATION .............356

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1 FEATURES

The AAL1gator-8 AAL1 Segmentation And Reassembly (SAR) Processor is a monolithic single chip device that provides DS1, E1, E3, or DS3 line interface access to an ATM Adaptation Layer One (AAL1) Constant Bit Rate (CBR) ATM network. It arbitrates access to an external SRAM for storage of the configuration, the user data, and the statistics. The device provides a microprocessor interface for configuration, management, and statistics gathering. PMC-Sierra also provides a software device driver for the AAL1gator-8 device.

• Compliant with the ATM Forum’s Circuit Emulation Services (CES) specification (AF-VTOA-0078), and the ITU-T I.363.1

• Supports Dynamic Bandwidth Circuit Emulation Services (DBCES). Compliant with the ATM Forum’s DBCES specification (AF-VTOA-

0085). Supports idle channel detection via processor intervention, CAS signaling, or data pattern detection. Provides idle channel indication on a per channel basis.

• Supports non-DBCES idle channel detection by activating a queue when any of its constituent time slots are active, and deactivating a queue when all of its constituent time slots are inactive.

• Provides AAL1 segmentation and reassembly of 8 individual E1 or T1 lines, 2 H-MVIP lines at 8 MHz, or 1 E3 or DS3 or STS-1 unstructured line.

•

• Provides a standard UTOPIA level 2 Interface which optionally

supports parity and runs up to 52 MHz. Only Cell Level Handshaking is supported. The following modes are supported:

• 8/16-bit Level 2, Multi-Phy Mode (MPHY)

• 8/16-bit Level 1, SPHY

• 8-bit Level 1, ATM Master

• Provides an optional 8/16-bit Any-PHY slave interface.

• Supports up to 256 Virtual Channels (VC).

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• Supports n x 64 (consecutive channels) and m x 64 (non-consecutive channels) structured data format.

• Provides transparent transmission of Common Channel Signaling (CCS) and Channel Associated Signaling (CAS). Provides for termination of CAS signaling.

• Allows the CAS nibble to be coincident with either the first or second nibble of the data.

• Provides per-VC data and signaling conditioning in the transmit cell direction and per DS0 data and signaling conditioning in the transmit line direction. Data and signaling conditioning can be individually enabled. Includes DS3 AIS conditioning support in both directions. Transmit line conditioning options include programmable byte pattern, pseudo-random pattern or old data. Conditioning automatically occurs on underruns.

• In Cell Transmit direction, provides per-VC configuration of time slots allocated, CAS signaling support, partial cell size, data and signaling conditioning, ATM Cell header definition. Generates AAL1 sequence numbers, pointers and SRTS values in accordance with ITU-T I.363.1. Multicast connections are supported.

• In Cell Transmit direction provides counters for:

• Conditioned cells transmitted for each queue

• Cells which were suppressed for each queue

• Total number of cells transmitted for each queue

• In Cell Receive direction, provides per-VC configuration of time slots

allocated, CAS signaling support, partial cell size, sequence number processing options, cell delay variation tolerance buffer depth, maximum buffer depth. Processes AAL1 headers in accordance with ITU-T I.363.1.

• In Cell Receive direction, supports the Fast Sequence Number processing algorithm on all types of connections and Robust Sequence Number processing on Unstructured Data Format (UDF) connections. Cells are inserted/dropped to maintain bit integrity on lost or misinserted cells. Bit integrity is maintained through any single errored cell or up to six lost cells. Bit integrity can also optionally be maintained even if an underrun occurs. Pointer bytes, signaling bytes,

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and bitmask bytes are taken into account. Cell insertion options include a programmable single byte pattern, pseudo-random data, or old data .

• In Cell Receive direction provides counters for the following events which include all counters required by the ATM Forum’s CES-IS 2.0 MIB:

• Incorrect sequence numbers per queue

• Incorrect sequence number protection fields per queue

• Total number of received cells per queue

• Total number of dropped cells per queue

• Total number of underruns per queue

• Total number of lost cells per queue

• Total number of overruns per queue

• Total number of reframes per queue

• Total number of pointer parity errors per queue

• Total number of misinserted cells per queue

• Total number of OAM or non-data cells received

• Total number of OAM or non-data cells dropped.

• For each receive queue the following sticky bits are maintained:

• Cell received

• Structured pointer rule error detected

• DBCES bitmask parity error

• Cell dropped due to blank allocation table

• Cells dropped due to pointer search

• Cell dropped due to forced underrun

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• Cell dropped due to sequence number processing algorithm

• Valid pointer was received

• Pointer parity error detecte d

• SRTS resume from an underrun condition

• SRTS underrun occurred

• Resume occurred from an underrun condition

• Pointer reframe occurred

• Overrun condition detected

• Cell received while in an underrun

• Supports AAL0 mode, selectable on a per VC basis.

• Provides system side loopback support. When enabled and the

incoming VCI matches the programmable loopback VCI, the cell received on the Receive UTOPIA interface is looped back to the Transmit UTOPIA interface. Alternatively the UTOPIA interface can be put into remote loopback mode where all incoming cells are looped back out. Provides line side loopback, enabled on a per queue basis, which can loop a single channel or any group of channels which can be mapped to a single queue.

• Provides a patented frame based calendar queue service algorithm with anti-clumping add-queue mechanism that produces minimal Cell Delay Variation (CDV). In UDF mode uses non-frame based scheduling to optimize CDV.

• Queues are added by making entries into an add-queue FIFO to minimize queue activation overhead. An offset can be configured when queue is added to distribute cell build times to minimize CDV due to clumping.

• Provides single maskable, open-collector interrupt with master interrupt register to facilitate in terrupt processing. The master interrupt register indicates the following conditions each of which can be masked:

• Error/status condition with the AAL1 block

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• Ram parity error

• UTOPIA parity error

• Transmit UTOPIA FIFO is full

• Transmit UTOPIA transfer error

• UTOPIA loopback FIFO is full

• UTOPIA runt cell is detected

• For the AAL1 block the following conditions can cause an interrupt,

each of which can be masked. A 64 entry FIFO is used to track receive and transmit status.

• A receive queue sticky bit was just set (individual mask per sticky bit)

• Receive queue entered underrun state

• Receive queue exited underrun state

• DBCES bitmask changed

• Receive Status FIFO overflow

• Transmit Frame Advance FIFO full

• Reception of OAM cells

• Change in idle state of a channel enabled for idle channel

detection

• Transmit Channel Idle State change FIFO overflow

• Line frame resync event

• Transmit ATM Layer Processor (TALP) FIFO full

• Provides a 16-bit microprocessor interface to internal registers, and

one external 128K x 16(18) (10 ns) Pipelined Single-Cycle Deselect Synchronous SRAMs, or Synchronous ZBT SRAMs.

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• Provides a transmit buffer which can be used for Operations, Administration and Maintenance (OAM) cells as well as any other user-generated cells such as AAL5 cells for ATM signaling. A corresponding receive buffer exists for the reception of OAM cells or non-AAL1 data cells.

• Includes an internal E1/T1 clock synthesizer for each line which can generate a nominal E1/T1 clock or be controlled via Synchronous Residual Time Stamp (SRTS) clock recovery method in Unstructured Data Format (UDF) mode or a programmable weighted moving average adaptive clocking algorithm. DS3 and E3 SRTS or adaptive clocking is supported using an external clock synthesizer and the clock control port.

• The clock synthesizers can also be controlled externally to provide customization of SRTS or adaptive algorithms. SRTS can also be disabled via a hardware input. Adaptive and SRTS information is output to a port for external processing for both low speed and high speed mode, if needed. Buffer depth is provided in units of bytes. The synthesizer can be set to 256 discrete frequencies between either +/100 ppm for E1 or +/-200 ppm for T1.

• Low-power 2.5 Volt CMOS technology with 3.3 Volt, 5 Volt tolerant I/O.

• 324-pin fine pitch plastic ball grid array (PBGA) package.

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2 APPLICATIONS

• Multi-service A TM Switch

• A TM Access Concentrator

• Digital Cross Connect

• Computer Telephony Chassis with ATM infrastructure

• Wireless Local Loop Back Haul

• ATM Passive Optical Network Equipment

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3 REFERENCES

Applicable Recommendations and Standards.

1. ANSI T1 Recommendation T1.403, Network-to-Customer Installation – DS1 Metallic Interface, NY, NY, 1995.

2. ANSI T1 Recommendation T1.630, Broadband ISDN-ATM Adaptation Layer for Constant Bit Rate Services, Functionality and Specification, NY, NY, 1993.

3. ATM Forum, ATM User Network Interface (UNI) Specification, V 3.1, Foster City, CA USA, September 1994.

4. ATM Forum, Circuit Emulation Service – Interoperability Specification (CES-IS), V. 2.0, Foster City, CA USA, August 1996.

5. ATM Forum, Specifications of (DBCES) Dynamic Bandwidth Utilization – in 64Kbps Time Slot Trunking Over ATM – Using CES, Foster City, CA USA, (AF-VTOA-0085) July 1997.

6. ATM Forum, UTOPIA, an ATM-PHY Layer Specification, Level 1, V.

2.01, Foster City, CA USA, March 1994.

7. ATM Forum, UTOPIA, an ATM-PHY Layer Specification, Level 2, V.

1.0, Foster City, CA USA, June 1995.

8. ITU-T Recommendation G.703, Physical/Electrical Characteristics of Hierarchical Digital Interfaces, April 1991.

9. ITU-T Recommendation I.363.1, B-ISDN ATM Adaptation Layer (AAL) Specification, July 1995.

10. ITU-T Recommendation G.823, The Control of Jitter and Wander within Digital Networks Which Are Based on the 2048 kbit/s Hierarchy, March 1993.

11. ITU-T Recommendation G.824 The Control of Jitter and Wander within Digital Networks Which Are Based on the 1544 kbit/s Hierarchy, March

1993.

12. PMC-971268, “High density T1/E1 framer with integrated VT/TU mapper AND M13 multiplexer” (TEMUX), 2000, Issue 5.

13. GO-MVIP, “MVIP-90 Standard” Release 1.1, October 1994.

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14. GO-MVIP, “H-MVIP Standard” Release 1.1a, January 1997.

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4 APPLICATION EXAMPLES

An essential function for ATM networks is to emulate existing Time Division Multiplexing (TDM) circuits. Since most voice and data services are currently provided by TDM circuits, seamless interworking between TDM and ATM has become a system requirement. The ATM Forum has standardized an internetworking function that satisfies this requirement in the Circuit Emulation Service (CES) Specification. The AAL1gator-8 is a direct implementation of that service specification in silicon, including the Nx64 channelized service and support of CAS.

4.1 Integrated Access Device

An Integrated Access Device (IAD) consolidates voice, data, Internet, and video wide-area network services using ATM over shared T1/E1 lines. IADs can also unify the functions of many different types of equipment including CSUs, DSUs and multiplexers. Figure 1 shows the AAL1gator-8 connected to PM4354 COMET-QUADs, a PM7329 S/UNI-APEX-1K800 Traffic Manager, a PM7328 S/UNI-ATLAS-1K800 ATM Layer device and the PM7347 S/UNI-JET.

T1/E1 x 8

PM4354

COMET-

PM4354

QUAD

COMET-

QUAD

Ethernet

Video

PM73123

AAL1gator-8

ATM

Interworking

Function,

AAL5 SAR

Any-PHY

PM7329

S/UNI-APEX-

PM7328

S/UNI-ATLAS-

1K800

UTOPIA L2

PM7347

S/UNI-JET

DS3 LIU

Figure 1. AAL1gator-8 in an Integrated Access Device (IAD)

Application.

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4.2 ATM Passive Optical Networks (APON)

The general architecture of a Passive Optical Network (PON) access network consists of two key elements: the Optical Line Termination (OLT) and the Optical Network Unit (ONU). The OLT is connected to the ONU through a point-to-multipoint Passive Optical Network that consists of fiber, splitters and other passive components. Typically, up to 32 ONUs are connected to a single OLT, depending on the splitting factor. OLTs are typically located in local exchanges and ONUs on street locations, in buildings or even in homes. Figure 2 shows the use of the AAL1gator-8 in an ONU application supporting CES functions.

Any-PHY

UTOPIA L2

T1/E1 x 8

PM4354

COMET-

PM4354

QUAD

COMET-

QUAD

PM73123

AAL1gator-8

PM7329

S/UNI-APEX-

1K800

Optical

Module

Ethernet

Video

ATM

Interworking

Function,

AAL5 SAR

PM7328

S/UNI-ATLAS-

1K800

Figure 2. AAL1gator-8 in an APON ONU Application.

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+ 334 hidden pages

PMC PM73123-PI Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual