PMC PM73123 Technical data

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PM73123 AAL1GATOR-8

PM4354 COMET-QUAD

PM73123

AAL1GATOR-8

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ISSUE 2: JUNE 2001

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PM73123 AAL1GATOR-8

PM4354 COMET-QUAD

PUBIC REVISION HISTORY

Issue

Issue Date Details of Change

No.

1 December

Document created.

1999

2 June 2001 Updated COMET-QUAD decoupling (C4, C6, C14,

C21, C42, C49, C56, C65) in the schematics and corrected power sequencing description.

Updated power calculations.

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PM4354 COMET-QUAD

CONTENTS

1 INTRODUCTION...................................................................................... 1

1.1 PURPOSE..................................................................................... 1

1.2 SCOPE.......................................................................................... 1

1.3 APPLICATIONS ............................................................................ 1

2 GENERAL DESCRIPTION....................................................................... 3

2.1 AAL1GATOR-8 ARCHITECTURE ................................................. 3

3 FEATURES .............................................................................................. 6

4 HIGH LEVEL DESIGN ............................................................................. 7

5 BLOCK DESCRIPTION ......................................................................... 13

5.1 AAL1GATOR-8............................................................................ 13

5.2 COMET ....................................................................................... 15

5.3 COMET-QUAD ............................................................................ 17

5.4 THE MICROPROCESSOR INTERFACE BLOCK....................... 18

5.5 AAL1GATOR-8 TO COMET/COMET-QUADS

INTERCONNECTIONS ............................................................... 19

5.6 THE FPGA BLOCK ..................................................................... 20

5.7 AAL1GATOR-8’S SRAM ............................................................. 21

5.8 REGULATORS BLOCK............................................................... 21

5.9 LED BLOCKS.............................................................................. 21

5.10 RESET BLOCK ........................................................................... 22

5.11 JTAG PORT ................................................................................ 22

5.12 TIMING BLOCK........................................................................... 22

5.13 UTOPIA INTERFACE .................................................................. 23

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6 DESIGN ISSUES ................................................................................... 24

6.1 AAL1GATOR-8 DESIGN CONSIDERATIONS ............................ 24

6.1.1 POWER SUPPLY............................................................. 24

6.1.2 DECOUPLING.................................................................. 24

6.1.3 LINE MODE SELECTION................................................. 24

6.2 LINE TERMINATION ................................................................... 24

6.3 COMET DESIGN CONSIDERATIONS........................................ 24

6.3.1 POWER SUPPLY............................................................. 24

6.3.2 DECOUPLING.................................................................. 25

6.3.3 VOLTAGE REFERENCES................................................ 25

6.4 COMET-QUAD DESIGN CONSIDERATIONS ............................ 25

6.4.1 POWER SUPPLY SEQUENCING.................................... 25

6.4.2 DECOUPLING.................................................................. 26

6.4.3 VOLTAGE REFERENCES................................................ 26

6.5 MICROPROCESSOR INTERFACE ............................................ 26

6.6 POWER REQUIREMENTS......................................................... 31

7 IMPLEMENTATION DESCRIPTION ...................................................... 33

7.1 AAL1GATOR-8 WITH COMET SCHEMATICS ........................... 33

7.2 AAL1GATOR-8 WITH COMET-QUAD SCHEMATICS ................ 35

8 GLOSSARY ........................................................................................... 37

9 DEFINITIONS ........................................................................................ 38

10 REFERENCES....................................................................................... 39

11 DISCLAIMER ......................................................................................... 40

12 APPENDIX A: BILL OF MATERIALS (COMET VERSION) .................... 41

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13 APPENDIX B: BILL OF MATERIALS (COMET-QUAD VERSION)......... 43

14 APPENDIX C: AAL1GATOR-8 W/COMETS SCHEMATICS.................. 45

15 APPENDIX D: AAL1GATOR-8 W/COMET-QUADS SCHEMATICS ....... 46

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PM4354 COMET-QUAD

LIST OF FIGURES

FIGURE 1 AAL1GATOR-8 CONFIGURATIONS ............................................... 3

FIGURE 2 AAL1GATOR-8 AND COMETS ........................................................ 4

FIGURE 3 AAL1GATOR-8 AND COMET-QUADS............................................. 5

FIGURE 4 AAL1GATOR-8 REF DESIGN BLOCK DIAGRAM WITH COMETS 8

FIGURE 5 AAL1GATOR-8 REF DESIGN DIAGRAM WITH COMET-QUADS .. 9

FIGURE 6 GLUELESS AAL1GATOR-8 TO COMETS CONNECTION.............11

FIGURE 7 GLUELESS AAL1GATOR-8 TO COMET-QUADS CONNECTION .11

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PM4354 COMET-QUAD

LIST OF TABLES

TABLE 1 AAL1GATOR-8 TO COMET/COMET-QUAD CONNECTIONS ...... 19

TABLE 2 OSCILLATORS .............................................................................. 22

TABLE 3 AAL1GATOR-8’S UTOPIA OPERATING MODES ......................... 23

TABLE 4 INTERFACE PINOUT FOR AAL1GATOR-8 W/COMETS.............. 26

TABLE 5 INTERFACE PINOUT FOR AAL1GATOR-8 W/COMET-QUADS... 28

TABLE 6 ADDRESS SPACE FOR AAL1GATOR-8 W/COMETS .................. 30

TABLE 7 ADDRESS SPACE FOR AAL1GATOR-8 W/COMET-QUADS....... 30

TABLE 8 POWER CONSUMPTION FOR AAL1GATOR-8 W/COMETS .......... 31

TABLE 9 POWER FOR AAL1GATOR-8 W/COMET-QUADS........................... 31

TABLE 10 MAJOR COMPONENTS LIST 1 .................................................... 41

TABLE 11 MAJOR COMPONENTS LIST 2 .................................................... 43

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PM4354 COMET-QUAD

1 INTRODUCTION

The AAL1gator-8 Reference Design assists customers in designing a Circuit Emulation Service (CES) and/or a Dynamic Bandwidth Circuit Emulation Service (DBCES) card. The CES/DBCES card is used to emulate circuit oriented transmission characteristics to support Constant Bit Rate (CBR) traffic.

1.1 PURPOSE

This reference design will assist engineers in designing their products using PMC-Sierra's AAL1gator-8, COMET and COMET-QUAD devices thereby bringing customers’ designs to market earlier.

1.2 SCOPE

This document is a paper reference design and describes the scope and deliverables required for the AAL1gator-8 Reference Design. Note that the design was not actually built and tested, but has only been designed on paper.

This reference design is a modularized card with two design options:

1. AAL1gator-8, two COMET-QUADs, a microprocessor interface, and line interfaces.

2. AAL1gator-8, eight COMETs, a microprocessor interface, and line interfaces.

A block diagram is shown for the two designs. Descriptions are provided for each of the functional blocks and detailed implementation descriptions then follow.

1.3 APPLICATIONS

Emulating existing TDM circuits is an essential function for ATM switches. Currently TDM circuits provide most voice and data services and therefore seamless interaction between TDM and ATM has become a system requirement. The ATM Forum has standardized an internetworking function that satisfies this requirement called the Circuit Emulation Services (CES) Specification.

The following are some application examples of the AAL1gator-8 Reference Design:

• An 8-Link T1/E1 CES Cards in a PBX

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PM4354 COMET-QUAD

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• TDM to ATM Access Service Concentrator

• Part of a TDM to ATM Multiservice ATM Switch

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2 GENERAL DESCRIPTION

2.1 AAL1gator-8 Architecture

The purpose of the AAL1gator-8 is to provide high density T1/E1, or DS3/E3/J2 line interfaces access to an AAL1 CBR ATM network. The AAL1gator-8 can support 8 T1/E1 lines, 1 DS3/E3/STS-1 link or 2 8Mbps H-MVIP links. The AAL1gator-8 is capable of supporting 256 VCs. On the system side, the AAL1gator-8 supports a standard UTOPIA Level 2 interface that optionally supports parity and runs up to 52 MHz. An optional 8/16-bit Any-PHY slave interface and UTOPIA Level 1 master/slave interface are also supported on the system side. Figure 1 indicates the ways in which an AAL1gator-8 can be used to connect to T1/E1 or DS3/E3 line interfaces.

Figure 1 AAL1gator-8 Configurations

T1/E1

Framer+LIU

(COMET)

(COMET-Q)

Any-PHY / UTOPIA

AAL1gator-8

Structured or unstructured T1/E1 with CAS support Unstructured DS3/E3

MVIP

TDM Switch

T1/E1 Framer

(TQUAD/EQUAD)

T1/E1

LIU

(QDSX)

M13 Mux

(D3MX)

DS3

LIU

DS3/E3

Framer

(S/UNI-QJET)

DS3/E3

LIU

Figures 2 and 3 show the system context in which the AAL1gator-8 devices reside within the reference designs. In these designs each AAL1gator-8 can interface with eight COMETs or two COMET-QUADs to support 8 structured/unstructured T1s or E1s.

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PM4354 COMET-QUAD

The PM4351 COMET is a single channel combined E1/T1 transceiver and framer, and the PM4354 COMET-QUAD is a four channel combined E1/T1 transceiver and framer – both devices are capable for use in long and short haul T1, J1 and E1 systems with a minimum of external circuitry. When used with the COMETs or COMET-QUADs, AAL1gator-8 can be part of a multiservice switch application which can provide circuit emulation services on E1 or T1 pipes.

Figure 2 AAL1gator-8 and COMETs

Data and Clock Lines

Line Interface

PM4351 COMET

PM73123

AAL1gator-8

UTOPIA / Any-

PHY

Line Interface

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PM4351 COMET

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Figure 3 AAL1gator-8 and COMET-QUADs

Data and Clock Lines

PM4354

COMET-QUAD

PM73123

AAL1gator-8

UTOPIA / Any-

PHY

PM4354

COMET-QUAD

The COMETs or COMET-QUADs receive data through the T1/E1 line interfaces. The formatted data is then passed through the T1/E1 framers to the AAL1gator-8 for CBR servicing. The cells are then routed through a UTOPIA L2 connector for routing, switching, traffic policing and shaping.

In the transmit path, the AAL1gator-8 receives the ATM cells from the UTOPIA bus. The AAL1gator-8 retrieves the data and signaling information, and places the data to be transmitted over the T1 or E1 lines via the COMETs or COMETQUADs in the appropriate port and time slot.

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3 FEATURES

• Implementation strategy for the AAL1gator-8 in a Multi Service Access Concentrator environment using the PM4351 COMET and PM4354 COMETQUAD.

• Supports 8 T1/E1 rates and channelized mode.

• Supports a CES.

• Supports independently clocked links.

• Has a microprocessor interface for configuration and monitoring.

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4 HIGH LEVEL DESIGN

The block diagrams of the AAL1gator-8 reference design are shown in Figure 4 and Figure 5. Figure 4 illustrates the high level design of the reference design with 8 COMET devices while Figure 5 shows the high level design with two COMET-QUAD devices.

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PM4354 COMET-QUAD

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Figure 4 AAL1gator-8 Ref Design Block Diagram with COMETs

Line

Interface

RXRING1 & RXTIP1

TXRING1 &TXTIP1

RXRING2 & RXTIP2

TXRING2 &TXTIP2

RXRING3 & RXTIP3

TXRING3 &TXTIP3

RXRING4 & RXTIP4

TXRING4 &TXTIP4

RXRING5 & RXTIP5

TXRING5 &TXTIP5

Microprocessor Interface

Data Bus

(Buffers/XCVRs, Decode Logic)

Address, Data and Control Bus

PM4351 COMET

Address Bus

Memory system

Data and clock

FPGA

Lines

Reset

Switch

Control Bus

2.5 V and 3.3 V Regulators

Power LEDs

Oscillators

128Kx16

RAM

PM73123

AAL1gator-8

UTOPIA L2

UTIOPA

Connect

RXRING6 & RXTIP6

PM4351

TXRING6 &TXTIP6

RXRING7 & RXTIP7

TXRING7 &TXTIP7

RXRING8 & RXTIP8

TXRING8 &TXTIP8

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COMET

PM4351 COMET

AAL1gator-8

ALARM LEDs

COMET ALARMS

LEDs

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Figure 5 AAL1gator-8 Ref Design Diagram with COMET-QUADs

RXRING[4:1]

RXTIP[4:1]

TXTIP[4:1]

TXRING[4:1]

Microprocessor Interface

Data Bus

Memory system

(Buffers/XCVRs, Decode Logic)

Address, Data and Control Bus

PM4354

COMET-QUAD

Address Bus

FPGA

Reset

Switch

Control Bus

2.5 V and 3.3 V Regulators

Power LEDs

Oscillators

128Kx16

RAM

Line

Interface

Data and clock Lines

PM73123

AAL1gator-8

TXRING[8:5]

TXTIP[8:5]

PM4354

RXTIP[8:5]

COMET-QUAD

RXRING[8:5]

COMET-QUAD ALARMS LEDs

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AAL1gator-8

ALARM LEDs

UTOPIA L2

UTIOPA

Connect

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As illustrated, the designs contain the following functional blocks:

1. PM73123 AAL1gator-8

2. PM4351 COMET/PM4354 COMET-QUAD

3. Microprocessor and Memory System Interface

4. Field Programmable Gate Array (FPGA)

5. Line Interface

6. UTOPIA Interface

7. Power and Clock Sources

The hardware allows full access to the AAL1gator-8 and COMET/COMET-QUAD devices via the microprocessor interface. Each COMET device acts as a single line interface unit with the integrated long haul LIU, and a T1/E1 framer/deframer while each COMET-QUAD device acts as four line interface units with the integrated long haul LIUs, and T1/E1 framers/de-framers.

In the receive path (from a T1 or E1 line), a COMET or COMET-QUAD converts the incoming line data (in the form of channels) to a serial bit stream. The AAL1gator-8 then receives this data and clocking information and builds AAL1 cells to be sent to the UTOPIA bus.

In the transmit path (to a T1 or E1 line), the AAL1gator-8 receives the ATM cells from the UTOPIA bus. The AAL1gator-8 retrieves the data and signaling information, and places the data to be transmitted over the T1 or E1 lines via the COMETs/COMET-QUADs in the appropriate port and time slot.

As illustrated in both Figure 4 and Figure 5, the connections from the FPGA to the PMC’s devices are dotted lines. This is because it is possible to connect the AAL1gator-8 to the COMETs or COMET-QUADs directly (i.e. without using a FPGA). Figure 6 shows the direct connection between the AAL1gator-8 and COMETs while Figure 7 illustrates this glueless interconnection between AAL1gator-8 and COMET-QUADs.

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Figure 6 Glueless AAL1gator-8 to COMETs Connection

Optional

External Clock

Source

BTCLK[7..0] TL_CLK[7..0]

BTSIG[7..0] TL_SIG[7..0]

8 COMET Blocks

BTFP[7..0] TL_SYNC[7..0]

PM73123

AAL1gator-8

Figure 7 Glueless AAL1gator-8 to COMET-QUADs Connection

Optional

External Clock

Source

BTCLK[4..1]

BTSIG[4..1]

PM4354

COMET-QUAD

BTFP[4..1]

TL_CLK[7..0]

TL_SIG[7..0]

PM73123

AAL1gator-8

BTFP[4..1]

TL_SYNC[7..0]

PM4354

COMET-QUAD

BTSIG[4..1]

BTCLK[4..1]

The AAL1gator-8 also supports 8Mbit/s H-MVIP on the line interface, and the COMET-QUAD also supports 8Mbit/s H-MVIP on the system interface.

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Therefore, an H-MVIP interface is optionally provided for the AAL1gator-8 with COMET-QUAD Reference design.

The main purpose of the FPGA is to provide maximum clock distribution flexibility by allowing for independently clocked links. The AAL1gator-8 is capable of implementing SRTS and the Adaptive Clock Recovery algorithm on its own; however, using an FPGA it is possible to implement an external Adaptive Clock Recovery scheme or SRTS clock scheme. The FPGA is also used for the generation of TL_CLK (AAL1gator-8) and BTCLK (COMET and COMET-QUAD). In addition, the FPGA generates an appropriate signal for the AAL1gator-8 network clock pin, N_CLK, (at 2.43 MHz), and also distributes XCLK signals to the 8 COMET or two COMET-QUAD devices from only two clock oscillators:

1.544 MHz and 2.048 MHz.

In H-MVIP mode, the FPGA is used to distribute the 16.384 MHz clock to the AAL1gator-8’s C16B and to the COMET-QUADs’ CMV8MCLK input pins. The FPGA is also used to distribute the 4.096 MHz Frame Pulse Clock to the AAL1gator-8’s C4B and to the COMET-QUADs’ CMVPFC inputs, and to generate the 8 kHz Common H-MVIP Frame Pulse from the Frame Pulse Clock.

In addition, in both Figures 6 and 7, the TL_SYNC pins of the AAL1gator-8 are connected to the COMET BTFP pin or the COMET-QUAD BTFP pins (configured as outputs). Depending on the value of MF_SYNC_MODE in the LI_CFG_REG register of the AAL1gator-8 for the line, this allows for alignment of signaling bits on multiframe boundaries or a frame boundary.

Power requirements of the boards are +5.0V, +3.3V and +2.5V. The AAL1gator8 and COMET-QUADs require +3.3V and +2.5V while COMETs require only +3.3V. +5.0V is used as input to the COMETs’ BIAS pins and to generate the +3.3V and +2.5V using voltage regulators.

In this reference design, the AAL1gator-8, COMET and COMET-QUAD devices are configured with de-multiplexed microprocessor address and data bus. The microprocessor interface has been provided through a 96-pin connector. This interface provides configuration and monitoring for PMC-Sierra’s devices.

The memory sub-unit of the AAL1gator-8’s block contains a 128k x 16 SRAM module connected to the AAL1gator-8 device’s RAM interface.

Two 80-pin female UTOPIA connectors carry the receive and transmit UTOPIA signals between the AAL1gator-8 and an external PHY board or a Parallel Cell Traffic Generator and Analyzer.

The designs also include several LED circuits for the device alarms and power indications.

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5 BLOCK DESCRIPTION

5.1 AAL1gator-8

The AAL1 Segmentation and Reassembly (SAR) Processor (AAL1gator-8) is a monolithic single chip device that provides DS1, E1, E3, or DS3 line interface access to an ATM Adaptation Layer One (AAL1) Constant Bit Rate (CBR) ATM network. It arbitrates access to an external (128K x 16/18 bits) 10ns SRAM for storage of the configuration, the user data, and the statistics. Some of the device’s important functionality is as follows:

• Compliant with the ATM Forum’s Circuit Emulation Services (CES) specification (AF-VTOA-0078), and the ITU-T I.363.1

• Supports Dynamic Bandwidth Circuit Emulation Services (DBCES). Compliant with the ATM Forum’s DBCES specification (AF-VTOA-0085).

• Supports idle channel detection via processor intervention, CAS signaling, or data pattern detection.

• Provides idle channel indication on a per channel basis.

• Provides AAL1 segmentation and reassembly of 8 individual E1 or T1 lines, 2

H-MVIP lines at 8Mbit/s, or 1 E3 or DS3 line.

• Provides a standard 16/8 bits UTOPIA level 2 Interface which optionally supports parity and runs up to 50 MHz. The following modes are supported:

• 16-bit Level 2, Multi-Phy Mode (MPHY)

• 8-bit Level 2, MPHY

• 8-bit Level 1, SPHY

• 8-bit Level 1, ATM Master

• Supports up to 256 Virtual Channels (VC).

The AAL1gator-8 is configured, controlled and monitored via a generic 8-bit microprocessor bus through which all internal registers are accessed. All sources of interrupts can be masked and acknowledged through the microprocessor interface.

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In this reference design, the AAL1gator-8 is configured with the direct mode at the line interface to connect to 8 COMETs or 2 COMET-QUADs. The line mode of operation needs to be setup from hardware reset and cannot be changed once the chip is powered up. The line mode is controlled by the AAL1gator-8’s LINE_MODE pin. When the LINE_MODE pin is set to low using the provided jumpers the AAL1gator-8 will support 8 low speed lines, or one high speed line, to interface with the COMET or COMET-QUAD devices. When the LINE_MODE pin is set to high, the AAL1gator-8 will be in H-MVIP mode when interfacing to the COMET-QUADs. This mode is provided as an extra and optional interface and can be ignored.

The UTOPIA interface of the AAL1gator-8 will power up with all outputs tri-stated and will remain tri-stated until the UI_EN bit in the UI_COMN_CFG register is set.

Also, during the hardware configuration of the AAL1gator-8, the TL_CLK_OE signal is tied high to use the clock provided on its RL_CLK pin as its TL_CLK and will drive this clock externally.

When the chip is taken out of hardware reset, the internal DLL on SYSCLK, which used to maintain low skew on the RAM interface, will go into hunt mode and will adjust the internal SYSCLK until it aligns with the external SYSCLK. The microprocessor should poll the RUN bit in the DLL_STAT_REG register until this bit is set. At this point, the entire chip with the exception of the microprocessor interface and the DLL are in reset. Before any configuration can be done, including accessing the RAM, the chip must be taken out of software reset by clearing the SW_RESET bit in the DEV_ID_REG register. Then, the RAM should be cleared to all zeros. At this point, the A1SP block is still in reset because its SW_RESET bit in the CMD_REG register is still set. The line interface is configured in the direct low speed mode indicated by the LINE_MODE pins but all internal registers are in the reset state. The line interface is out of reset at this point but will only be driving data as if all lines and/or queues are disabled. The UTOPIA interface, as mentioned above, is disabled and all UTOPIA outputs are tri-stated.

The software configuration of the AAL1gator-8 is done in three steps:

1. Line Configuration: while the A1SP is in reset, the memory mapped registers which contain the line configuration (the LIN_STR_MODE and HS_LIN_REG registers) can be initialized. Then, the CMD_ATTN bit in the CMD_REG register can be set so that the A1SP can read its configuration. The SW_RESET bit of the CMD_REG register should remain set.

2. Queue Configuration: the SW_RESET bit in the CMD_REG register is cleared which takes A1SP out of reset. The R_CHAN_2_QUE_TBL will then

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PM4354 COMET-QUAD

begin a 640 SYSCLK cycle initialization, which reset each timeslot to playing out conditioned data. At this point, the queues can be initialized as needed.

3. Adding Queues: By setting the corresponding bits in the ADDQ_FIFO register, the queues are added.

For a more detailed description of the AAL1gator-8, please refer to [1].

5.2 COMET

The PM4351 Combined E1/T1 Transceiver (COMET) is a feature-rich monolithic integrated circuit suitable for use in long haul and short haul T1 and E1 systems with a minimum of external circuitry. The COMET is software configurable, allowing feature selection without changes to external wiring.

Analog circuitry is provided to allow direct reception of long haul E1 and T1 compatible signals with up to 36 dB cable loss (at 1.024MHz in E1 mode) or up to 36 dB cable loss (at 772 kHz in T1 mode) using a minimum of external components. Typically, only line protection, a transformer and a line termination resistor are required. Digital line inputs are provided for applications not requiring a physical T1 or E1 interface.

The COMET recovers clock and data from the line and frames to incoming data. In T1 mode, it can frame to several DS-1 signal formats: SF, ESF, T1DM (DDS) and SLC®96. In E1 mode, the COMET frames to basic G.704 E1 signals and CRC-4 multiframe alignment signals, and automatically performs the G.706 interworking procedure. AMI, HDB3 and B8ZS line codes are supported.

In T1 mode, the COMET generates framing for SF, ESF and T1DM (DDS) formats. In E1 mode, the COMET generates framing for a basic G.704 E1 signal. The signaling multiframe alignment structure and the CRC multiframe structure may be optionally inserted. Framing can be optionally disabled.

Internal analog circuitry allows direct transmission of long haul and short haul T1 and E1 compatible signals using a minimum of external components. Typically, only line protection, a transformer and a line termination resistor are required. Digitally programmable pulse shaping allows transmission of DSX-1 compatible signals up to 655 feet from the cross-connect, E1 short haul pulses into 120 ohm twisted pair or 75 ohm coaxial cable, E1 long haul pulses into 120 ohm twisted pair as well as long haul DS-1 pulses into 100 ohm twisted pair with integrated support for LBO filtering as required by the FCC rules. In addition, the programmable pulse shape extending over 5-bit periods allows customization of short haul and long haul line interface circuits to application requirements. Digital line inputs and outputs are provided for applications not requiring a physical T1 or E1 interface.

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REFERENCE DESIGN

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PM4354 COMET-QUAD

The COMET provides both a parallel microprocessor interface for controlling the operation of the device and serial PCM interfaces that allow backplane rates from 1.544 Mbit/s to 8.192 Mbit/s to be directly supported.

In this reference design, each COMET interfaces with the AAL1gator-8 can be configured independently in T1 or E1 mode. After the power up or a hardware/software reset, the following steps are performed to configure the COMET:

1. Initialize the XLPG (Transmit Pulse Template) registers to clear the pulse template.

2. Setup the XLPG to program the pulse template to generate short-haul or long-haul pulses as specified in [2]. Also, set the amplitude of the pulse template and enable the XLPG.

3. Program the COMET for T1 or E1 mode by writing to the E1/T1B bit of the Global Configuration register.

4. Configure the Clock Synthesis Unit (CSU) by selecting 1.544MHz or

2.048MHz for the line rate (XCLK and TCLKO).

5. Configure the Clock and Data Recovery Unit (CDRC) to receive the appropriate line decoding (AMI or B8ZS in T1 mode, HDB3 in E1 mode).

6. Configure the Receive and Transmit Elastic Stores units (RX-ELST and TXELST).

7. Set the framing format and line encoding for the transmitter (XBAS in T1 mode, E1-TRAN in E1 mode).

8. Program the framing format for the receiver.

9. Configure the framing format and the data rate for the facility data link.

10. Configure the Signaling Extraction Block register (SIGX).

11. Configure the Receive Line Interface (RLPS).

12. Configure the Transmit/Receive Jitter Attenuator and the Receive Option registers to disable or enable the jitter attenuation on transmit or receive line side.

13. Configure the Backplane Receive System Interface (BRIF) block (registers 0x30 and 0x31):

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• Full Frame mode

• BRCLK as an output

• BRPCM, BRSIG, and BRFP updated on the rising edge of

BRCLK

• BRCLK backplane rate (1.544MHz or 2.048MHz)

• BRFP (Backplane Frame Pulse) as an output

14. Configure the Backplane Transmit System Interface (BTIF) block (registers 0x40 and 0x41):

• Full Frame mode

• BRCLK as an input

• BTPCM, BTSIG, and BTFP updated on the rising edge of

• BTCLK backplane rate (1.544MHz or 2.048MHz)

• BRFP (Backplane Frame Pulse) as an output

15. Program the Receive Line Equalization table as stated in [2].

For more information about the COMET please refer to [2].

5.3 COMET-QUAD

The PM4354 Four Channel Combined E1/T1/J1 Transceiver and Framer (COMET-QUAD) is a feature-rich monolithic integrated circuit suitable for use in long haul and short haul T1, J1 and E1 systems with a minimum of external circuitry. The COMET-QUAD is software configurable, allowing feature selection without changes to external wiring.

Analog circuitry is provided to allow direct reception of long haul E1 and T1/J1 compatible signals typically with up to 43 dB cable loss at 1024 kHz (E1) and up to 44 dB cable loss at 772 kHz (T1/J1) using a minimum of external components. Typically, only line protection, a transformer and a line termination resistor are required.

BTCLK

The COMET-QUAD recovers clock and data from the line and frames to incoming data. In T1 mode, it can frame to SF and ESF signal formats. In E1

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mode, the COMET-QUAD frames to basic G.704 E1 signals and CRC-4 multiframe alignment signals, and automatically performs the G.706 interworking procedure. AMI, HDB3 and B8ZS line codes are supported.

In T1 mode, the COMET-QUAD generates framing for SF and ESF formats. In E1 mode, the COMET-QUAD generates framing for a basic G.704 E1 signal. The signaling multiframe alignment structure and the CRC multiframe structure may be optionally inserted. Framing can be optionally disabled.

Serial PCM interfaces to each T1 framer allow 1.544 Mbit/s backplane receive/backplane transmit system interfaces to be directly supported. Tolerance of gapped clocks allows other backplane rates to be supported with a minimum of external logic.

In synchronous backplane systems 8Mbit/s H-MVIP interfaces are provided for access channel associated signaling (CAS) and common channel signaling (CCS) for each T1 or E1. The DS0 data channel H-MVIP and CAS H-MVIP access is multiplexed with the serial PCM interface pins. The CCS signaling HMVIP interface is independent of the DS0 channel and CAS H-MVIP access. The use of any of the H-MVIP interfaces requires that common clocks and frame pulse be used along with T1/E1 slip buffers.

The COMET-QUAD is configured, controlled and monitored via a generic 8-bit microprocessor bus through which all internal registers are accessed. All sources of interrupts can be masked and acknowledged through the microprocessor interface.

Please refer to [3] for more information about the COMET-QUAD.

5.4 The Microprocessor Interface Block

The microprocessor interface contains de-multiplexed address and data buses and a control bus to perform the following functions on the AAL1gator-8 Reference Design:

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• Configuration of the AAL1gator-8 and COMET or COMET-QUAD devices

• Monitoring of alarms and interrupts in the AAL1gator-8 and COMET or

COMET-QUAD devices

In order to provide maximum system implementation flexibility, a particular microprocessor has not been specified. However, the system microprocessor must have the following minimum capabilities:

1. 23 bit address bus

2. 6 bit data bus

3. 3 programmable chip selects

4. 2 independent interrupt request lines

An example of a microprocessor that meets these minimum requirements is the Motorola MC68340. Another option would be to implement the design in a PCI or compact PCI system.

5.5 AAL1gator-8 to COMET/COMET-QUADs Interconnections

The AAL1gator-8 communicates with the COMET/COMET-QUAD devices via framer bus signals listed in Table 1. Four bits of each signal group connects to one COMET-QUAD device. For instance, TL_SYNC[3..0] are connected to the COMET-QUAD 1, while TL_SYNC[7..4] are connected to COMET-QUAD 2.

Table 1 AAL1gator-8 to COMET/COMET-QUAD Connections

SIGNAL DESCRIPTION

TL_SYNC[7..0] The FPGA generates this signal for both the AAL1gator-8 and

COMET/COMET-QUADs. In T1 mode, this signal consists of a pulse once every 193 bit periods.

TL_CLK[7..0] This is a clock signal at the transmit line rate. Its source is

determined by the configuration of the FPGA.

RL_CLK[7..0] Receive line clock at either 1.544 MHz or 2.048 MHz, derived from

the recovered line rate timing.

RL_SYNC[7..0] Carries receive frame synchronization from the COMET/COMET-

QUAD devices.

RL_SIG[7..0] Carries the CAS signaling information from the COMET/COMET-

QUAD devices. RL_DATA[7..0] Carries the receive data from the COMET/COMET-QUAD devices. TL_SIG[7..0] Carries the CAS signaling outputs to the COMET/COMET-QUAD

devices. TL_DATA[7..0] Carries the serial data to the COMET/COMET-QUAD devices.

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5.6 The FPGA Block

If the direct connections between the AAL1gator-8 and the COMETs or the COMET-QUADs are not used, depending upon the configuration, the Field Programmable Gate Array (FPGA) performs the following optional functions:

1. Implements an external Adaptive Clock Recovery scheme if a designer would like to perform an external algorithm instead of the AAL1gator-8’s own internal algorithm.

2. Distributes XCLK source among the COMET or COMET-QUAD devices.

3. Generates the 8 kHz framing pulses.

4. Generates a software selected N_CLK signal (2.43 MHz) from the Network clock.

Note that the AAL1gator-8 is capable of implementing SRTS or Adaptive Clock Recovery scheme on its own; therefore, the FPGA is not required to perform these methods, but it is required to perform the other functions as mentioned in items 2-4 above.

In the adaptive Clock recovery mode, the AAL1gator-8 provides a queue depth difference for controlling of an external clock. The FPGA latches the channel status and frame difference and uses them to adjust the synthesized clock frequency. If the queue depth is low, the clock frequency is reduced; however, if the queue depth is high, the clock frequency is increased.

The FPGA also distributes XCLK signals to the 8 COMET or two COMET-QUAD devices from only two clock oscillators: 1.544 MHz and 2.048 MHz.

Another function of the FPGA is to generate the 8 kHz framing pulse from the transmit line clock (BTCLK in the COMET or in the COMET-QUAD) to the framers. This 8 kHz signal connects to the AAL1gator-8 TL_SYNC input and the COMET’s or COMET-QUAD’s BTFP input. In the T1 mode, the frame pulse (BTFP) is one clock (BTCLK) period wide, generated every 193 bits. But, in the E1 mode, the frame pulse is generated every 256 bits.

For implementation of the synchronous residual time stamp (SRTS), the AAL1gator-8’s network clock (N_CLK) must be a 2.43 MHz signal. This signal is generated by dividing a 155.52 MHz ATM network clock by 64 in the FPGA.

In the AAL1gator-8 with COMET-QUADs Reference Design, if the H-MVIP mode is used, the FPGA is used to distribute the 16.384 MHz clock to the AAL1gator8’s C16B and to the COMET-QUADs’ CMV8MCLK input pins. The FPGA is also used to distribute the 4.096 MHz Frame Pulse Clock to the AAL1gator-8’s C4B

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