PMC PM73122-BI Datasheet

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PMC-1981419 ISSUE 7 32 LINK CES/DBCES AAL1 SAR PROCESSOR

PM73122 AAL1GATOR-32

PM73122

AAL1GATOR-32

ATM ADAPTATION LAYER 1

SEGMENTATION AND REASSEMBLY

PROCESSOR-32

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PM73122 AAL1GATOR-32

REVISION HISTORY

Issue

Issue Date Details of Change

No.

1 Dec 1998 Document created.

2 Sept 1999 Significant design details added.

3 Nov 1999 Further design details and pinout added.

4 Jan 2000 Updated to reflect functional details based on latest design. Clarified and added further

descriptive text. Finalized pinout.

5 May 2000 Added description of the floating CAS nibble capability. (SHIFT_CAS). Added more functional

detail.

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Issue

Issue Date Details of Change

No.

6 May 2001 Added section: Changes from Rev B to Rev C.

Added “BUSMASTER” bit in SBI_BUS_CFG_REG, along with description.

Clarified NODROP_IN_START and DROPPED_CELL counter functionality is that

NODROP_IN_START has no effect for ROBUST SN Processing and UDF-HS mode.

In LIN_STR_MODE added cross reference to HS Operations section for Dual DS3 mode.

Corrected “Out of Band Signaling Idle Detection” section with respect to RX and TX CAS.

Fixed Robust SN processing Figure.

Added note in SN PROCESSING register to clarify that only ROBUST_SN_EN or DISABLE_SN

can be set, not both.

Only SBI mapping ram has 2 pages not SBI control RAM.

Sometimes An_SW_RESET needs to be used with high speed queue. Updated Operations

section and An_SW_RESET description.

Added times when OFFSET needs to be set to FRAMES_PER_CELL in OFFSET bit description.

Clarified MVIP-90 configuration in the Operations section

Changed DC_INT from link to tributary.

Flipped HIZDATA and HIZIO.

In DC Characteristics, made operating current for I/O typical, added .5 ns margin to C1FP hold

and SBI Tz. Also applied C1FP timing to C1FP_ADD also.

Default value corrected for MIN_DEPTH for DS3 Register.

Clarified and/or corrected “INSBI/EXSBI Programming Steps” section, “SBI Operation” section,

tributary mapping sequences in “Programming Sequence for SBI” section and lack of depth check

support in SBI Synchronous Mode.

Added statements describing that UDF_HS Loopback Mode requires that the High Speed Queue

be reset, that SPE Activation Must Occur After Tributaries are Enabled, that SPE Activation must

occur after tributaries are enabled.

Updated applications section with new PMC devices: PM8316 TEMUX-84, PM7341 S/UNI-IMA-

84.

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Issue

Issue Date Details of Change

No.

7 June 2001

Changed DC_INT_EN to SYNC_INT_EN in operations section.

In DC Characteristics, corrected IDDOP(2.7) for HS mode.

In Operations section, clarified function of SBI Parity Error Detection and recommended setting

the BUSMASTER bit in the PHY SBI device.

Added note at beginning of AC Characteristics recommending that transition times on clock inputs

is less than 15 ns.

Corrected Ram Interface Timing

In Memory Mapped Register Section added CSD_BYTES_LEFT register definition in

T_QUEUE_TABLE. Added hidden bits in QUE_CREDITS word and added

R_DBCES_BM_IN_NEXT to R_TOT_LEFT memory register and changed

R_DBCES_BM_IN_NEXT bit to R_DBCES_BM_INACT in R_STATE_0 memory register.

Clarified C1FP signal definition in SBI Signal Definition section.

Changed “Out of Band” idle detection mode to “Processor Controlled” idle detection mode in Idle

Detection section of Functional Description.

Updated PCR section in Functional Description

Added SRTS patent legal note to footer of last page

Corrected T1/E1 Link Rate Table (reversed polarity of C1FP)

Corrected cross reference in ADD QUEUE FIFO section

Removed equations from partial cell PCR section and replaced with summary table.

Added reference by RL_CLK that clock can not be gapped and must have jitter less than .3 UI if

using SRTS.

Added minor clarifications, including: R_LINE_STATE location not used in UDF-HS mode,

explanation of PCR for UDF-ML, removed references to E3 over SBI, added recommendation to

tie unused TL_CLK pins high in UDF-HS modes, renamed RPHY_ADD_RSX pin to

RPHY_ADD[4]/RSX to match Tx side, removed ‘sampled on rising edge’ from ADETECT pin

description, added that PAGE bit is a don’t care when accessing SBI Control RAM’s, clarified max

RSTB timing and max 400 SYSCLK rd/wr timing, clarified T1/E1 granularity in SBI mode(at

DA1SP level), E1_w_T1_sig mode not supported over SBI, clarified that SN state machines

freeze during underruns.

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LIST OF REGISTERS

REGISTER 0X80000: RESET AND DEVICE ID REGISTER (DEV_ID_REG)253

REGISTER 0X80010, … 13: A1SPN COMMAND REGISTER (AN_CMD_REG)

............................................................................................................. 254

REGISTER 0X80020, … 23 : A1SPN ADD QUEUE FIFO REGISTER

(AN_ADDQ_FIFO) ............................................................................... 256

REGISTER 0X80030, … 33 : A1SPN CLOCK CONFIGURATION REGISTER

(AN_CLK_CFG) ................................................................................... 257

REGISTER 0X80100: RAM CONFIGURATION REGISTER (RAM_CFG_REG)

............................................................................................................. 259

REGISTER 0X80120: UI COMMON CONFIGURATION REGISTER

(UI_COMN_CFG)................................................................................. 261

REGISTER 0X80121: UI SOURCE CONFIG REG (UI_SRC_CFG) ............ 263

REGISTER 0X80122: UI SINK CONFIG REG (UI_SNK_CFG).................... 265

REGISTER 0X80123: SLAVE SOURCE ADDRESS CONFIG REGISTER

(UI_SRC_ADD_CFG) .......................................................................... 267

REGISTER 0X80124: SLAVE SINK ADDRESS CONFIG REGISTER

(UI_SNK_ADD_CFG)........................................................................... 268

REGISTER 0X80125: UI TO UI LOOPBACK VCI (U2U_LOOP_VCI)........... 269

REGISTER 0X80126: UI SOURCE POLLING PRIORITY LIST REGISTER

(UI_SRC_POLL_LIST)......................................................................... 270

REGISTER 0X80200H, 01H … 0FH: LOW SPEED LINE N CONFIGURATION

REGISTERS(LS_LN_CFG_REG)........................................................ 272

REGISTER 0X80210H: LINE MODE REGISTER(LINE_MODE_REG).......... 273

REGISTER 0X80300H: SBI BUS CONFIGURATION

REGISTER(SBI_BUS_CFG_REG)...................................................... 275

REGISTER 0X80301H: SBI LINK CONFIGURATION

REGISTER(SBI_LNK_CFG_REG) ...................................................... 278

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REGISTER 0X80302H: SBI LINK DISABLE REGISTER

LOW(SBI_LINK_DIS_REGL)............................................................... 280

REGISTER 0X80304H: SBI SYNC LINK REGISTER

LOW(SBI_SYNC_LINK_REGL) ........................................................... 282

REGISTER 0X80305H: SBI SYNC LINK HIGH REGISTER(SBI_SYNC

LINKH_REG) ....................................................................................... 283

REGISTER 0X80309H: SBI EXTRACT BUS ALARM INTERRUPT REGISTER

HIGH (EXT_ALRM_INTH) ................................................................... 285

REGISTER 0X8030AH: SBI EXTRACT BUS ALARM STATUS REGISTER LOW

(EXT_ALRM_STAT_REGL) ................................................................. 286

REGISTER 0X8030CH: SBI INSERT BUS ALARM INSERT REGISTER LOW

(INS_ALRM_REGL)............................................................................. 288

REGISTER 0X8030DH: SBI INSERT BUS ALARM INSERT REGISTER HIGH

(INS_ALRM_REGH) ............................................................................ 289

REGISTER 0X80400H: EXTRACT CONTROL REGISTER (EXT_CTL)........ 291

REGISTER 0X80401H: EXTRACT FIFO UNDER RUN INTERRUPT STATUS

REGISTER (EXT_FI_URI) ................................................................... 294

REGISTER 0X80403H: EXTRACT TRIBUTARY RAM INDIRECT ACCESS

ADDRESS REGISTER (EXT_TRIAD) ................................................. 297

REGISTER 0X80404H: EXTRACT TRIBUTARY RAM INDIRECT ACCESS

CONTROL REGISTER (EXT_TRIAC) ................................................. 299

REGISTER 0X80405H: EXTRACT TRIBUTARY MAPPING RAM INDIRECT

ACCESS DATA REGISTER (EXT_TRIB_MAP)................................... 301

REGISTER 0X80406H: EXTRACT TRIBUTARY CONTROL RAM INDIRECT

ACCESS DATA REGISTER (EXT_TRIB_CTL).................................... 303

REGISTER 0X80407H: SBI PARITY ERROR INTERRUPT STATUS REGISTER

(SBI_PERR)......................................................................................... 306

REGISTER 0X80409H: MIN_DEPTH FOR DS3 REGISTER......................... 308

REGISTER 0X8040AH: T1 THRESHOLD REGISTER................................... 309

REGISTER 0X8040CH: DS3 THRESHOLD REGISTER.................................311

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REGISTER 0X8040EH: EXTRACT DEPTH CHECK INTERRUPT STATUS

REGISTER (EXT_DCR_INT)............................................................... 312

REGISTER 0X80500H: INSERT CONTROL REGISTER (INS_CTL)............. 316

REGISTER 0X80501H: INSERT FIFO UNDERRUN INTERRUPT STATUS

REGISTER (INS_FI_URI) .................................................................... 319

REGISTER 0X80503H: INSERT TRIBUTARY REGISTER INDIRECT ACCESS

ADDRESS REGISTER(INS_TRIAD) ................................................... 323

REGISTER 0X80504H: INSERT TRIBUTARY REGISTER INDIRECT ACCESS

CONTROL REGISTER (INS_TRIAC) .................................................. 325

REGISTER 0X80505H: INSERT TRIBUTARY MAPPING INDIRECT ACCESS

DATA REGISTER (INS_TRIB_MAP..................................................... 327

REGISTER 0X80506H: INSERT TRIBUTARY CONTROL INDIRECT ACCESS

DATA REGISTER (INS_TRIB_CTL) .................................................... 329

REGISTER 0X80507H: MIN_DEPTH FOR T1 AND E1 REGISTER .............. 331

REGISTER 0X80509H: MIN_THR AND MAX_THR FOR T1 REGISTER ...... 333

REGISTER 0X8050BH: MIN_THR AND MAX_THR FOR DS3 REGISTER... 335

REGISTER 0X80511H: INSERT DEPTH CHECK INTERRUPT STATUS

REGISTER (INS_DVR_INT) ................................................................ 336

REGISTER 0X81000: MASTER INTERRUPT REGISTER (MSTR_INTR_REG)

............................................................................................................. 341

REGISTER 0X81010, … 13: A1SPN INTERRUPT REGISTER

(A1SPN_INTR_REG)........................................................................... 345

REGISTER 0X81020, … 23: A1SPN STATUS REGISTER (A1SPN_STAT_REG)347

REGISTER 0X81030, …, 33: A1SPN TRANSMIT IDLE STATE FIFO

(A1SPN_TIDLE_FIFO)......................................................................... 349

REGISTER 0X81040, …, 43: A1SPN RECEIVE STATUS FIFO

(A1SPN_RSTAT_FIFO) ....................................................................... 352

REGISTER 0X81100: MASTER INTERRUPT ENABLE REGISTER

(MSTR_INTR_EN_REG) ..................................................................... 354

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REGISTER 0X81110, … 13: A1SPN INTERRUPT ENABLE REGISTER

(A1SPN_EN_REG) .............................................................................. 355

REGISTER 0X81150, …, 53: RECEIVE(N) QUEUE ERROR ENABLE

(RCV_Q_ERR_EN).............................................................................. 357

REGISTER 0X82000-0X8200F + 0X400*N (N=0-3): A1SP N RX CHANNEL

ACTIVE TABLE .................................................................................... 360

REGISTER 0X82010-0X8201F + 0X400*N (N=0-3): A1SP N RX PENDING

TABLE.................................................................................................. 362

REGISTER 0X82100-0X821FF + 0X400*N (N=0-3): A1SP N RX CHANGE

POINTER TABLE (RX_CHG_PTR)...................................................... 364

REGISTER 0X82200-0X8220F + 0X400*N (N=0-3): A1SP N TX CHANNEL

ACTIVE TABLE .................................................................................... 366

REGISTER 0X82210-0X82217 + 0X400*N (N=0-3): A1SP N PATTERN

MATCHING LINE CONFIGURATION (PAT_MTCH_CFG0 )................ 368

REGISTER 0X82220 + 0X400*N (N=0-3): A1SP N IDLE DETECTION

CONFIGURATION TABLE ................................................................... 369

REGISTER 0X82300-0X823FF + 0X400*N (N=0-3): A1SP N CAS/PATTERN

MATCHING CONFIGURATION TABLE ............................................... 370

REGISTER 0X84000H: DLL CONFIGURATION REGISTER (DLL_CFG_REG)

............................................................................................................. 374

REGISTER 0X84002H: DLL SW RESET REGISTER (DLL_SW_RST_REG) 375

REGISTER 0X84003H: DLL CONTROL STATUS REGISTER (DLL_STAT_REG)376

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LIST OF FIGURES

FIGURE 1 MULTI-SERVICE SWITCH APPLICATION ................................... 12

FIGURE 2 USING THE AAL1GATOR-32 IN AN ATM PASSIVE OPTICAL

NETWORK. ...................................................................................................... 13

FIGURE 3 USING THE AAL1GATOR-32 IN A DACS APPLICATION............. 13

FIGURE 4 AAL1GATOR-32 INTERNAL BLOCK DIAGRAM........................... 14

FIGURE 5 DATA FLOW AND BUFFERING IN THE UI AND DUAL A1SP BLOCKS 60

FIGURE 6 UI BLOCK DIAGRAM................................................................... 61

FIGURE 7 SOURCE PRIORITY SERVICING EXAMPLE............................... 68

FIGURE 8 CELL HEADER INTERPRETATION.............................................. 69

FIGURE 9 A1SP BLOCK DIAGRAM .............................................................. 71

FIGURE 10 CAPTURE OF T1 SIGNALING BITS (SHIFT_CAS=0) ............... 73

FIGURE 11 CAPTURE OF E1 SIGNALING BITS (SHIFT_CAS=0) ............... 73

FIGURE 12 TRANSMIT FRAME TRANSFER CONTROLLER ....................... 74

FIGURE 13 T1 ESF SDF-MF FORMAT OF THE T_DATA_BUFFER ............. 75

FIGURE 14 T1 SF-SDF-MF FORMAT OF THE T_DATA_BUFFER ............... 75

FIGURE 15 T1 SDF-FR FORMAT OF THE T_DATA_BUFFER...................... 76

FIGURE 16 E1 SDF-MF FORMAT OF THE T_DATA_BUFFER..................... 77

FIGURE 17 E1 SDF-MF WITH T1 SIGNALING FORMAT OF THE

T_DATA_BUFFER ............................................................................................ 77

FIGURE 18 E1 SDF-FR FORMAT OF THE T_DATA_BUFFER ..................... 78

FIGURE 19 UNSTRUCTURED FORMAT OF THE T_DATA_BUFFER.......... 78

FIGURE 20 SDF-MF T1 ESF FORMAT OF THE T_SIGNALING_BUFFER.... 79

FIGURE 21 SDF-MF T1 SF FORMAT OF THE T_SIGNALING BUFFER ...... 79

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FIGURE 22 SDF-MF E1 FORMAT OF THE T_SIGNALING_BUFFER........... 79

FIGURE 23 SDF-MF E1 WITH T1 SIGNALING FORMAT OF THE

T_SIGNALING_BUFFER.................................................................................. 80

FIGURE 24 TRANSMIT SIDE SRTS FUNCTION........................................... 81

FIGURE 25 CAS IDLE DETECTION CONFIGURATION REGISTER

STRUCTURE.................................................................................................... 82

FIGURE 26 CAS IDLE DETECTION INTERRUPT WORD ............................ 83

FIGURE 27 PROCESSOR CONTROLLED IDLE DETECTION INTERRUPT WORD 83

FIGURE 28 PROCESSOR CONTROLLED CONFIGURATION REGISTER

STRUCTURE.................................................................................................... 84

FIGURE 29 TX CHANNEL ACTIVE/IDLE BIT TABLE STRUCTURE ............. 84

FIGURE 30 PAT_MTCH_CFG REGISTER STRUCTURE ............................. 85

FIGURE 31 PATTERN MATCH IDLE DETECTION REGISTER STRUCTURE86

FIGURE 32 PATTERN MATCH IDLE DETECTION INTERRUPT WORD...... 86

FIGURE 33 FRAME ADVANCE FIFO OPERATION ....................................... 88

FIGURE 34 PAYLOAD GENERATION ........................................................... 96

FIGURE 35 LOCAL LOOPBACK.................................................................... 99

FIGURE 36 CELL HEADER INTERPRETATION.......................................... 101

FIGURE 37 FAST SN ALGORITHM ............................................................. 107

FIGURE 38 RECEIVE CELL PROCESSING FOR FAST SN ....................... 108

FIGURE 39 ROBUST SN ALGORITHM ........................................................111

FIGURE 40 CELL RECEPTION ....................................................................113

FIGURE 41 T1 ESF SDF-MF FORMAT OF THE R_DATA_BUFFER............114

FIGURE 42 T1 SF SDF-MF FORMAT OF THE R_DATA_BUFFER ..............114

FIGURE 43 T1 SDF-FR FORMAT OF THE R_DATA_BUFFER ....................115

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FIGURE 44 E1 SDF-MF FORMAT OF THE R_DATA_BUFFER....................115

FIGURE 45 E1 SDF-MF WITH T1 SIGNALING FORMAT OF THE

R_DATA_BUFFER...........................................................................................116

FIGURE 46 E1 SDF-FR FORMAT OF THE R_DATA_BUFFER....................116

FIGURE 47 UNSTRUCTURED FORMAT OF THE R_DATA_BUFFER.........117

FIGURE 48 T1 ESF SDF-MF FORMAT OF THE R_SIG_BUFFER...............117

FIGURE 49 T1 SF SDF-MF FORMAT OF THE R_SIG_BUFFER .................118

FIGURE 50 E1 SDF-MF FORMAT OF THE R_SIG_BUFFER ......................118

FIGURE 51 E1 SDF-MF WITH T1 SIGNALING FORMAT OF THE

R_SIG_BUFFER..............................................................................................119

FIGURE 52 POINTER/STRUCTURE STATE MACHINE.............................. 124

FIGURE 53 OVERRUN DETECTION........................................................... 126

FIGURE 54 DBCES RECEIVE SIDE BUFFERING ...................................... 129

FIGURE 55 OUTPUT OF T1 SIGNALING BITS (SHIFT_CAS=0)................ 131

FIGURE 56 OUTPUT OF E1 SIGNALING BITS (SHIFT_CAS=0) ............... 131

FIGURE 57 CHANNEL-TO-QUEUE TABLE OPERATION ........................... 133

FIGURE 58 RECEIVE SIDE SRTS SUPPORT ............................................ 134

FIGURE 59 SRTS DATA............................................................................... 138

FIGURE 60 CHANNEL STATUS FUNCTIONAL TIMING ............................. 138

FIGURE 61 ADAPTIVE DATA FUNCTIONAL TIMING.................................. 140

FIGURE 62 EXT FREQ SELECT FUNCTIONAL TIMING ............................ 141

FIGURE 63 RECEIVE SIDE SRTS SUPPORT ............................................ 142

FIGURE 64 DIRECT ADAPTIVE CLOCK OPERATION ............................... 144

FIGURE 65 MEMORY MAP.......................................................................... 149

FIGURE 66 A1SP SRAM MEMORY MAP .................................................... 149

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FIGURE 67 CONTROL REGISTERS MEMORY MAP ................................. 150

FIGURE 68 TRANSMIT DATA STRUCTURES MEMORY MAP ................... 151

FIGURE 69 RECEIVE DATA STRUCTURES ............................................... 152

FIGURE 70 NORMAL MODE REGISTERS MEMORY MAP........................ 153

FIGURE 71 INTERRUPT HIERARCHY........................................................ 154

FIGURE 72 ADDQ_FIFO WORD STRUCTURE .......................................... 157

FIGURE 73 LINE INTERFACE BLOCK ARCHITECTURE ........................... 162

FIGURE 74 LINE INTERFACE AND 2ND RAM INTERFACE ........................ 163

FIGURE 75 CAPTURE OF T1 SIGNALING BITS ........................................ 166

FIGURE 76 CAPTURE OF E1 SIGNALING BITS ........................................ 166

FIGURE 77 OUTPUT OF T1 SIGNALING BITS........................................... 167

FIGURE 78 OUTPUT OF E1 SIGNALING BITS........................................... 168

FIGURE 79 T1/E1 LINK RATE INFORMATION............................................ 170

FIGURE 80 MULTI-PHY TO MULTI-LINK LAYER DEVICE INTERFACE..... 172

FIGURE 81 SBI BLOCK ARCHITECTURE .................................................. 177

FIGURE 82 SDF-MF FORMAT OF THE T_SIGNALING BUFFER............... 200

FIGURE 83 R_CRC_SYNDROME MASK BIT TABLE LEGEND .................. 221

FIGURE 84 UTOPIA-2 MULTI-ADDRESS MODE WITH VCI BASED

LOOPBACK .................................................................................................... 391

FIGURE 85 BOUNDARY SCAN ARCHITECTURE ...................................... 393

FIGURE 86 TAP CONTROLLER FINITE STATE MACHINE ........................ 395

FIGURE 87 INPUT OBSERVATION CELL (IN_CELL) ................................. 398

FIGURE 88 OUTPUT CELL (OUT_CELL).................................................... 399

FIGURE 89 BIDIRECTIONAL CELL (IO_CELL) ........................................... 399

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FIGURE 90 LAYOUT OF OUTPUT ENABLE AND BIDIRECTIONAL CELLS400

FIGURE 91 PIPELINED SINGLE-CYCLE DESELECT SSRAM................... 401

FIGURE 92 PIPELINED ZBT SSRAM .......................................................... 401

FIGURE 93 SRC_INTF START OF TRANSFER TIMING (UTOPIA 1 ATM MODE) 402

FIGURE 94 SRC_INTF END-OF-TRANSFER TIMING (UTOPIA 1 ATM MODE)

403

FIGURE 95 UI_SRC_INTF START-OF-TRANSFER TIMING (UTOPIA 1 PHY MODE) 403

FIGURE 96 UI_SRC_INTF END-OF-TRANSFER (UTOPIA 1 PHY MODE). 404

FIGURE 97 UI_SRC_INTF START-OF-TRANSFER TIMING (UTOPIA 2 PHY MODE) 405

FIGURE 98 UI_SRC_INTF END-OF-TRANSFER TIMING (UTOPIA 2 PHY MODE) 405

FIGURE 99 UI_SRC_INTF START-OF-TRANSFER TIMING (ANY-PHY PHY MODE) 406

FIGURE 100 UI_SRC_INTF END-OF-TRANSFER TIMING (ANY-PHY PHY MODE) 406

FIGURE 101 SNK_INTF START-OF-TRANSFER TIMING (UTOPIA 1 ATM MODE) 407

FIGURE 102 SNK_INTF END-OF-TRANSFER TIMING (UTOPIA 1 ATM MODE) 408

FIGURE 103 SNK_INTF START-OF-TRANSFER TIMING (UTOPIA 1 PHY MODE) 409

FIGURE 104 SNK_INTF START-OF-TRANSFER UTOPIA 2 (SINGLE

ADDRESS PHY MODE) ................................................................................. 409

FIGURE 105 SNK_INTF CLAV DISABLE UTOPIA 2 (SINGLE-ADDRESS PHY MODE) 410

FIGURE 106 SNK_INTF END-OF-TRANSFER UTOPIA 2 (SINGLE ADDRESS

PHY MODE).................................................................................................... 410

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FIGURE 107 SNK_INTF START-OF-TRANSFER UTOPIA 2 (MULTI-ADDRESS

PHY MODE).....................................................................................................411

FIGURE 108 SNK_INTF END-OF-TRANSFER UTOPIA 2 (MULTI-ADDRESS

PHY MODE).....................................................................................................411

FIGURE 109 SNK_INTF START-OF-TRANSFER (ANY-PHY PHY MODE) . 412

FIGURE 110 SNK_INTF END-OF-TRANSFER (ANY-PHY PHY MODE) ..... 413

FIGURE 111 MICROPROCESSOR WRITE ACCESS.................................. 414

FIGURE 112 MICROPROCESSOR READ ACCESS ................................... 415

FIGURE 113 MICROPROCESSOR WRITE ACCESS WITH ALE................ 415

FIGURE 114 MICROPROCESSOR READ ACCESS WITH ALE ................. 415

FIGURE 115 SRTS DATA............................................................................. 416

FIGURE 116 CHANNEL STATUS FUNCTIONAL TIMING............................ 417

FIGURE 117 ADAPTIVE DATA FUNCTIONAL TIMING................................ 419

FIGURE 118 EXT FREQ SELECT FUNCTIONAL TIMING........................... 420

FIGURE 119 RECEIVE LINE SIDE T1 TIMING(RL_CLK = 1.544 MHZ) ...... 420

FIGURE 120 RECEIVE LINE SIDE E1 TIMING(RL_CLK = 2.048 MHZ)...... 421

FIGURE 121 MVIP-90 RECEIVE FUNCTIONAL TIMING ............................ 421

FIGURE 122 TRANSMIT LINE SIDE T1 TIMING(TL_CLK = 1.544 MHZ).... 422

FIGURE 123 TRANSMIT LINE SIDE E1 TIMING(TL_CLK = 2.048 MHZ) ... 422

FIGURE 124 MVIP-90 TRANSMIT FUNCTIONAL TIMING .......................... 423

FIGURE 125 RECEIVE H-MVIP TIMING, CLOSE-UP VIEW ....................... 424

FIGURE 126 RECEIVE H-MVIP TIMING, EXPANDED VIEW ...................... 425

FIGURE 127 TRANSMIT H-MVIP TIMING, CLOSE-UP VIEW ..................... 426

FIGURE 128 TRANSMIT H-MVIP TIMING, EXPANDED VIEW .................... 427

FIGURE 129 SBI DROP BUS T1/E1 FUNCTIONAL TIMING ....................... 428

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FIGURE 130 SBI DROP BUS DS3 FUNCTIONAL TIMING.......................... 428

FIGURE 131 SBI ADD BUS ADJUSTMENT REQUEST FUNCTIONAL TIMING

429

FIGURE 132 RECEIVE HIGH-SPEED FUNCTIONAL TIMING.................... 429

FIGURE 133 TRANSMIT HIGH-SPEED FUNCTIONAL TIMING.................. 430

FIGURE 134 RSTB TIMING ......................................................................... 435

FIGURE 135 SYS_CLK TIMING................................................................... 436

FIGURE 136 NCLK TIMING ......................................................................... 436

FIGURE 137 MICROPROCESSOR INTERFACE READ TIMING ................ 438

FIGURE 138 MICROPROCESSOR INTERFACE WRITE TIMING .............. 440

FIGURE 139 EXTERNAL CLOCK GENERATION CONTROL INTERFACE TIMING 441

FIGURE 140 RAM INTERFACE TIMING...................................................... 442

FIGURE 141 SINK UTOPIA INTERFACE TIMING ....................................... 444

FIGURE 142 SOURCE UTOPIA INTERFACE TIMING ................................ 445

FIGURE 143 TRANSMIT LOW SPEED INTERFACE TIMING..................... 446

FIGURE 144 RECEIVE LOW SPEED INTERFACE TIMING ....................... 447

FIGURE 145 SBI FRAME PULSE TIMING................................................... 448

FIGURE 146 SBI DROP BUS TIMING ......................................................... 449

FIGURE 147 SBI ADD BUS TIMING ............................................................ 450

FIGURE 148 SBI ADD BUS COLLISION AVOIDANCE TIMING................... 450

FIGURE 149 H-MVIP SINK DATA & FRAME PULSE TIMING ..................... 452

FIGURE 150 H-MVIP INGRESS DATA TIMING ........................................... 452

FIGURE 151 TRANSMIT HIGH SPEED TIMING ......................................... 453

FIGURE 152 RECEIVE HIGH SPEED INTERFACE TIMING....................... 454

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FIGURE 153 JTAG PORT INTERFACE TIMING.......................................... 456

FIGURE 154 352 PIN ENHANCED BALL GRID ARRAY (SBGA)................. 458

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LIST OF TABLES

TABLE 1 LINE INTERFACE SIGNAL TABLE SELECTION............................ 30

TABLE 2 LINE INTERFACE SUMMARY ........................................................ 48

TABLE 3 CFG_ADDR AND PHY_ADDR BIT USAGE IN SRC DIRECTION .. 64

TABLE 4 CFG_ADDR AND PHY_ADDR BIT USAGE IN SNK DIRECTION .. 67

TABLE 5 MINIMUM PARTIAL CELL SIZE PERMITTED IF ALL CONNECTIONS

ARE ACTIVE..................................................................................................... 97

TABLE 6 CHANNEL STATUS....................................................................... 139

TABLE 7 BUFFER DEPTH ........................................................................... 140

TABLE 8 FREQUENCY SELECT – T1 MODE ............................................. 146

TABLE 9 FREQUENCY SELECT – E1 MODE ............................................. 148

TABLE 10 LINE_MODE ENCODING............................................................ 161

TABLE 11 T1/E1 CLOCK RATE ENCODING ............................................... 171

TABLE 12 SUPPORTED LINKS ................................................................... 173

TABLE 13 STRUCTURE FOR CARRYING MULTIPLEXED LINKS ............. 174

TABLE 14 T1 TRIBUTARY COLUMN NUMBERING .................................... 174

TABLE 15 E1 TRIBUTARY COLUMN NUMBERING .................................... 175

TABLE 16 DESYNCHRONIZER E1/T1 CLOCK GENERATION ALGORITHM

179

TABLE 17 AAL1GATOR-32 MEMORY MAP................................................. 186

TABLE 18 A1SP AND LINE CONFIGURATION STRUCTURES SUMMARY 187

TABLE 19 TRANSMIT STRUCTURES SUMMARY...................................... 193

TABLE 20 R_CRC_SYNDROME MASK BIT TABLE .................................... 221

TABLE 21R_QUEUE_TBL FORMAT .............................................................. 231

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TABLE 22 REGISTER MEMORY MAP......................................................... 252

TABLE 23 COMMAND REGISTER MEMORY MAP..................................... 252

TABLE 24 RAM INTERFACE REGISTERS MEMORY MAP ........................ 258

TABLE 25 UTOPIA INTERFACE REGISTERS MEMORY MAP ................... 260

TABLE 26 CFG_ADDR AND PHY_ADDR BIT USAGE IN SRC DIRECTION267

TABLE 27 CFG_ADDR AND PHY_ADDR BIT USAGE IN SNK DIRECTION268

TABLE 28 LINE INTERFACE REGISTER MEMORY MAP SUMMARY ....... 271

TABLE 29 DIRECT LOW SPEED MODE REGISTER MEMORY MAP ........ 271

TABLE 30 GENERAL SBI REGISTER MEMORY MAP................................ 274

TABLE 31 EXSBI BLOCK REGISTER MEMORY MAP................................ 290

TABLE 32 TRIB_TYP ENCODING ............................................................... 304

TABLE 33 INSBI BLOCK REGISTER MEMORY MAP ................................. 315

TABLE 34 TRIB_TYP ENCODING ............................................................... 330

TABLE 35 INTERRUPT AND STATUS REGISTERS MEMORY MAP.......... 339

TABLE 36 IDLE CHANNEL DETECTION CONFIGURATION AND STATUS

REGISTERS MEMORY MAP ......................................................................... 358

TABLE 37 DLL CONTROL AND STATUS REGISTERS MEMORY MAP ..... 373

TABLE 38 CHANNEL STATUS..................................................................... 417

TABLE 39 FRAME DIFFERENCE ................................................................ 418

TABLE 40 ABSOLUTE MAXIMUM RATINGS............................................... 431

TABLE 41 AAL1GATOR-32 D.C. CHARACTERISTICS ............................... 432

TABLE 42 RTSB TIMING.............................................................................. 434

TABLE 43 SYS_CLK TIMING ....................................................................... 435

TABLE 44 NCLK TIMING.............................................................................. 436

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TABLE 45 MICROPROCESSOR INTERFACE READ ACCESS .................. 437

TABLE 46 MICROPROCESSOR INTERFACE WRITE ACCESS ................ 439

TABLE 47 EXTERNAL CLOCK GENERATION CONTROL INTERFACE..... 441

TABLE 48 RAM INTERFACE........................................................................ 442

TABLE 49 UTOPIA SOURCE AND SINK INTERFACE ............................... 443

TABLE 50 TRANSMIT LOW SPEED INTERFACE TIMING ......................... 446

TABLE 51 RECEIVE LOW SPEED INTERFACE TIMING............................ 447

TABLE 52 CLOCKS AND SBI FRAME PULSE (FIGURE 145)..................... 448

TABLE 53 SBI DROP BUS (FIGURE 146) ................................................... 448

TABLE 54 SBI ADD BUS (FIGURE 147 TO FIGURE 148)........................... 449

TABLE 55 H-MVIP SINK TIMING ................................................................. 451

TABLE 56 H-MVIP SOURCE TIMING .......................................................... 452

TABLE 57 TRANSMIT HIGH SPEED INTERFACE TIMING......................... 453

TABLE 58 RECEIVE HIGH SPEED INTERFACE TIMING ........................... 454

TABLE 59 JTAG PORT INTERFACE............................................................ 455

TABLE 60 AAL1GATOR-32 (PM73122) ORDERING INFORMATION.......... 457

TABLE 61 AAL1GATOR-32 (PM73122) THERMAL INFORMATION............ 457

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1 CHANGES FROM REV. A TO REV. B

There are four main changes when transitioning from Rev. A to Rev. B:

1. The DEV_ID has changed from 0000 to 0001.

2. The JTAG version number has changed from 0 to 1.

3. The SHIFT_CAS feature which allows the signaling to be aligned with the first nibble of data has been added. This feature is enabled by setting SHIFT_CAS in the LIN_STR_MODE register.

4. The capability to have a separate C1FP for the ADD and DROP side of the SBI bus has been added. In Rev. A there is only one C1FP pin, but Rev. B has the option to support two separate C1FP pins. The original C1FP pin becomes the C1FP for the drop side of the SBI bus and the new pin, C1FP_ADD, is the C1FP for the add side of the SBI bus. Rev. B defaults to using one C1FP pin which makes it backwards compatible with Rev. A, but two C1FP capability can be enabled by setting TWO_C1FP_EN in the SBI_BUS_CFG_REG register.

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2 CHANGES FROM REV B TO REV C

There are three main changes when transitioning from Rev. B to Rev. C:

1. The DEV_ID has changed from 0001 to 0010.

2. The JTAG version number has changed from 1 to 2.

3. A BUSMASTER bit has been added (bit 15 of SBI_BUS_CFG_REG). When set, the AAL1gator32 will drive all SBI bytes that are not driven by other devices. The will prevent parity errors from being detected due to floating bytes.

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3 FEATURES

The AAL1 Segmentation And Reassembly (SAR) Processor (AAL1gator-32) is a monolithic single chip device that provides DS1, E1, E3, or DS3 line interface access to an ATM Adaptation Layer One (AAL1) Constant Bit Rate (CBR) ATM network. It arbitrates access to an external SRAM for storage of the configuration, the user data, and the statistics. The device provides a microprocessor interface for configuration, management, and statistics gathering. PMC-Sierra also offers a software device control package for the AAL1gator-32 device.

• Compliant with the ATM Forum’s Circuit Emulation Services (CES) specification (AF-VTOA-0078), and the ITU-T I.363.1

• Supports Dynamic Bandwidth Circuit Emulation Services (DBCES). Compliant with the ATM Forum’s DBCES specification (AF-VTOA-0085). Supports idle channel detection via processor intervention, CAS signaling, or data pattern detection. Provides idle channel indication on a per channel basis.

• Supports non-DBCES idle channel detection by activating a queue when any of its constituent time slots are active, and deactivating a queue when all of its constituent time slots are inactive.

• Provides AAL1 segmentation and reassembly of 16 individual E1 or T1 lines, 8 H-MVIP lines at 8 MHz, or 2 E3 or DS3 or STS-1 unstructured lines.

• Using the optional Scalable Bandwidth Interconnect (SBI) Interface, provides AAL1 segmentation and reassembly of up to 32 T1, E1, or 2 DS3 links. In SBI mode can map any SBI tributary to any of the 32 AAL1 links. Supports floating and locked tributaries as well as unframed, framed without CAS and framed with CAS tributaries. CAS is only supported on Synchronous tributaries.

• Provides a standard UTOPIA level 2 Interface which optionally supports parity and runs up to 52 MHz. Only Cell Level Handshaking is supported. In MPHY mode, can act like a single port or 4 port device. The following modes are supported:

• 8/16-bit Level 2, Multi-Phy Mode (MPHY)

• 8/16-bit Level 1, SPHY

• 8-bit Level 1, ATM Master

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• Provides an optional 8/16-bit Any-PHY slave interface.

• Supports up to 1024 Virtual Channels (VC).

• Supports n x 64 (consecutive channels) and m x 64 (non-consecutive

channels) structured data format.

• Provides transparent transmission of Common Channel Signaling (CCS) and Channel Associated Signaling (CAS). Provides for termination of CAS signaling.

• Allows the CAS nibble to be coincident with either the first or second nibble of the data.

• Provides per-VC data and signaling conditioning in the transmit cell direction and per DS0 data and signaling conditioning in the transmit line direction. Data and signaling conditioning can be individually enabled. Includes DS3 AIS conditioning support in both directions. Transmit line conditioning options include programmable byte pattern, pseudo-random pattern or old data. Conditioning automatically occurs on underruns.

• In Cell Transmit direction, provides per-VC configuration of time slots allocated, CAS signaling support, partial cell size, data and signaling conditioning, ATM Cell header definition. Generates AAL1 sequence numbers, pointers and SRTS values in accordance with ITU-T I.363.1. Multicast connections are supported.

• In Cell Transmit direction provides counters for:

• Conditioned cells transmitted for each queue

• Cells which were suppressed for each queue

• Total number of cells transmitted for each queue

• In Cell Receive direction, provides per-VC configuration of time slots

allocated, CAS signaling support, partial cell size, sequence number processing options, cell delay variation tolerance buffer depth, maximum buffer depth. Processes AAL1 headers in accordance with ITU-T I.363.1.

• In Cell Receive direction, supports the Fast Sequence Number processing algorithm on all types of connections and Robust Sequence Number processing on Unstructured Data Format (UDF) connections. Cells are inserted/dropped to maintain bit integrity on lost or misinserted cells. Bit integrity is maintained through any single errored cell or up to six lost cells. Bit

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integrity can also optionally be maintained even if an underrun occurs. Pointer bytes, signaling bytes, and bitmask bytes are taken into account. Cell insertion options include a programmable single byte pattern, pseudo-random data, or old data .

• In Cell Receive direction provides counters for the following events which include all counters required by the ATM Forum’s CES-IS 2.0 MIB:

• Incorrect sequence numbers per queue

• Incorrect sequence number protection fields per queue

• Total number of received cells per queue

• Total number of dropped cells per queue

• Total number of underruns per queue

• Total number of lost cells per queue

• Total number of overruns per queue

• Total number of reframes per queue

• Total number of pointer parity errors per queue

• Total number of misinserted cells per queue

• Total number of OAM or non-data cells received

• Total number of OAM or non-data cells dropped.

• For each receive queue the following sticky bits are maintained:

• Cell received

• Structured pointer rule error detected

• DBCES bitmask parity error

• Cell dropped due to blank allocation table

• Cells dropped due to pointer search

• Cell dropped due to forced underrun

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PMC PM73122-BI Datasheet

REVISION HISTORY

CONTENTS

LIST OF REGISTERS

LIST OF FIGURES

LIST OF TABLES

1 CHANGES FROM REV. A TO REV. B

2 CHANGES FROM REV B TO REV C