PMC PM73122-BI Datasheet

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PMC-1981419 ISSUE 7 32 LINK CES/DBCES AAL1 SAR PROCESSOR

PM73122 AAL1GATOR-32

PM73122

AAL1GATOR-32

ATM ADAPTATION LAYER 1

SEGMENTATION AND REASSEMBLY

PROCESSOR-32

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ISSUE 7: JUNE 2001

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REVISION HISTORY

Issue

Issue Date Details of Change

No.

1 Dec 1998 Document created.

2 Sept 1999 Significant design details added.

3 Nov 1999 Further design details and pinout added.

4 Jan 2000 Updated to reflect functional details based on latest design. Clarified and added further

descriptive text. Finalized pinout.

5 May 2000 Added description of the floating CAS nibble capability. (SHIFT_CAS). Added more functional

detail.

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Issue

Issue Date Details of Change

No.

6 May 2001 Added section: Changes from Rev B to Rev C.

Added “BUSMASTER” bit in SBI_BUS_CFG_REG, along with description.

Clarified NODROP_IN_START and DROPPED_CELL counter functionality is that

NODROP_IN_START has no effect for ROBUST SN Processing and UDF-HS mode.

In LIN_STR_MODE added cross reference to HS Operations section for Dual DS3 mode.

Corrected “Out of Band Signaling Idle Detection” section with respect to RX and TX CAS.

Fixed Robust SN processing Figure.

Added note in SN PROCESSING register to clarify that only ROBUST_SN_EN or DISABLE_SN

can be set, not both.

Only SBI mapping ram has 2 pages not SBI control RAM.

Sometimes An_SW_RESET needs to be used with high speed queue. Updated Operations

section and An_SW_RESET description.

Added times when OFFSET needs to be set to FRAMES_PER_CELL in OFFSET bit description.

Clarified MVIP-90 configuration in the Operations section

Changed DC_INT from link to tributary.

Flipped HIZDATA and HIZIO.

In DC Characteristics, made operating current for I/O typical, added .5 ns margin to C1FP hold

and SBI Tz. Also applied C1FP timing to C1FP_ADD also.

Default value corrected for MIN_DEPTH for DS3 Register.

Clarified and/or corrected “INSBI/EXSBI Programming Steps” section, “SBI Operation” section,

tributary mapping sequences in “Programming Sequence for SBI” section and lack of depth check

support in SBI Synchronous Mode.

Added statements describing that UDF_HS Loopback Mode requires that the High Speed Queue

be reset, that SPE Activation Must Occur After Tributaries are Enabled, that SPE Activation must

occur after tributaries are enabled.

Updated applications section with new PMC devices: PM8316 TEMUX-84, PM7341 S/UNI-IMA-

84.

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Issue

Issue Date Details of Change

No.

7 June 2001

Changed DC_INT_EN to SYNC_INT_EN in operations section.

In DC Characteristics, corrected IDDOP(2.7) for HS mode.

In Operations section, clarified function of SBI Parity Error Detection and recommended setting

the BUSMASTER bit in the PHY SBI device.

Added note at beginning of AC Characteristics recommending that transition times on clock inputs

is less than 15 ns.

Corrected Ram Interface Timing

In Memory Mapped Register Section added CSD_BYTES_LEFT register definition in

T_QUEUE_TABLE. Added hidden bits in QUE_CREDITS word and added

R_DBCES_BM_IN_NEXT to R_TOT_LEFT memory register and changed

R_DBCES_BM_IN_NEXT bit to R_DBCES_BM_INACT in R_STATE_0 memory register.

Clarified C1FP signal definition in SBI Signal Definition section.

Changed “Out of Band” idle detection mode to “Processor Controlled” idle detection mode in Idle

Detection section of Functional Description.

Updated PCR section in Functional Description

Added SRTS patent legal note to footer of last page

Corrected T1/E1 Link Rate Table (reversed polarity of C1FP)

Corrected cross reference in ADD QUEUE FIFO section

Removed equations from partial cell PCR section and replaced with summary table.

Added reference by RL_CLK that clock can not be gapped and must have jitter less than .3 UI if

using SRTS.

Added minor clarifications, including: R_LINE_STATE location not used in UDF-HS mode,

explanation of PCR for UDF-ML, removed references to E3 over SBI, added recommendation to

tie unused TL_CLK pins high in UDF-HS modes, renamed RPHY_ADD_RSX pin to

RPHY_ADD[4]/RSX to match Tx side, removed ‘sampled on rising edge’ from ADETECT pin

description, added that PAGE bit is a don’t care when accessing SBI Control RAM’s, clarified max

RSTB timing and max 400 SYSCLK rd/wr timing, clarified T1/E1 granularity in SBI mode(at

DA1SP level), E1_w_T1_sig mode not supported over SBI, clarified that SN state machines

freeze during underruns.

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1 CHANGES FROM REV. A TO REV. B ..................................................... 1

2 CHANGES FROM REV B TO REV C ...................................................... 2

3 FEATURES .............................................................................................. 3

4 APPLICATIONS ....................................................................................... 9

5 REFERENCES....................................................................................... 10

6 APPLICATION EXAMPLES ....................................................................11

6.1 ATM MULTI-SERVICE SWITCH ..................................................11

6.2 PASSIVE OPTICAL NETWORK (PON) SYSTEM....................... 12

6.3 DIGITAL ACCESS CROSS-CONNECT SYSTEM (DACS) WITH AN

ATM INTERFACE........................................................................ 13

7 BLOCK DIAGRAM ................................................................................. 14

8 DESCRIPTION ...................................................................................... 15

9 PIN DIAGRAM ....................................................................................... 16

10 PIN DESCRIPTION................................................................................ 17

10.1 UTOPIA INTERFACE SIGNALS (52) .......................................... 17

10.2 MICROPROCESSOR INTERFACE SIGNALS (43)..................... 26

10.3 RAM 1 INTERFACE SIGNALS(41) ............................................. 28

10.4 LINE INTERFACE SIGNALS(DIRECT LOW SPEED)(132) ........ 31

10.5 LINE INTERFACE SIGNALS(H-MVIP)(37) ................................. 36

10.6 SBI INTERFACE SIGNALS (ONLY USED IN SBI MODE)(64).... 38

10.7 LINE INTERFACE SIGNALS(HIGH SPEED)(10) ........................ 45

10.8 RAM 2 INTERFACE SIGNALS (ONLY USED IN H-MVIP, HS, AND

SBI MODES)(41)......................................................................... 46

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10.9 SUMMARY OF LINE INTERFACE SIGNALS.............................. 48

10.10 CLOCK GENERATION CONTROL INTERFACE(18).................. 53

10.11 JTAG/TEST SIGNALS(5) ............................................................ 54

10.12 GENERAL SIGNALS(3+POWER/GND)...................................... 55

11 FUNCTIONAL DESCRIPTION............................................................... 59

11.1 UTOPIA INTERFACE BLOCK (UI).............................................. 59

11.1.1 UTOPIA SOURCE INTERFACE (SRC_INTF) .................. 61

11.1.2 UTOPIA SINK INTERFACE (SNK_INTF) ......................... 64

11.1.3 UTOPIA MUX BLOCK (UMUX)......................................... 67

11.2 AAL1 SAR PROCESSING BLOCK (A1SP)................................. 70

11.2.1 AAL1 SAR TRANSMIT SIDE (TXA1SP)........................... 72

11.2.2 AAL1 SAR RECEIVE SIDE (RXA1SP)............................. 99

11.3 AAL1 CLOCK GENERATION CONTROL ................................. 134

11.3.1 DESCRIPTION ............................................................... 134

11.3.2 CGC BLOCK DIAGRAM................................................. 136

11.3.3 FUNCTIONAL DESCRIPTION ....................................... 136

11.4 PROCESSOR INTERFACE BLOCK (PROCI) .......................... 148

11.4.1 INTERRUPT DRIVEN ERROR/STATUS REPORTING.. 153

11.4.2 ADD QUEUE FIFO ......................................................... 156

11.5 RAM INTERFACE BLOCK (RAMI)............................................ 159

11.6 LINE INTERFACE BLOCK (AAL1_LI)....................................... 159

11.6.1 CONVENTIONS ............................................................. 159

11.6.2 FUNCTIONAL DESCRIPTION ....................................... 160

11.6.3 TRANSMIT DIRECTION................................................. 166

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11.7 JTAG TEST ACCESS PORT..................................................... 184

12 MEMORY MAPPED REGISTER DESCRIPTION ................................ 185

12.1 INITIALIZATION ........................................................................ 186

12.2 A1SP AND LINE CONFIGURATION STRUCTURES................ 187

12.2.1 HS_LIN_REG ................................................................. 187

12.3 TRANSMIT STRUCTURES SUMMARY ................................... 193

12.3.1 P_FILL_CHAR ................................................................ 195

12.3.2 T_SEQNUM_TBL ........................................................... 195

12.3.3 T_COND_SIG................................................................. 196

12.3.4 T_COND_DATA.............................................................. 198

12.3.5 RESERVED (TRANSMIT SIGNALING BUFFER)........... 199

12.3.6 T_OAM_QUEUE ............................................................ 200

12.3.7 T_QUEUE_TBL.............................................................. 201

12.3.8 RESERVED (TRANSMIT DATA BUFFER) ..................... 214

12.4 RECEIVE DATA STRUCTURES SUMMARY............................ 215

12.4.1 R_OAM_QUEUE_TBL ................................................... 216

12.4.2 R_OAM_CELL_CNT ...................................................... 218

12.4.3 R_DROP_OAM_CELL.................................................... 218

12.4.4 R_SRTS_CONFIG.......................................................... 219

12.4.5 R_CRC_SYNDROME..................................................... 220

12.4.6 R_CH_TO_QUEUE_TBL................................................ 223

12.4.7 R_COND_SIG ................................................................ 226

12.4.8 R_COND_DATA ............................................................. 227

12.4.9 RESERVED (RECEIVE SRTS QUEUE)......................... 228

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12.4.10 RESERVED (RECEIVE SIGNALING BUFFER).......... 229

12.4.11 R_QUEUE_TBL .......................................................... 231

12.4.12 R_OAM_QUEUE......................................................... 248

12.4.13 RESERVED (RECEIVE DATA BUFFER) .................... 249

13 NORMAL MODE REGISTER DESCRIPTION ..................................... 251

13.1 COMMAND REGISTERS.......................................................... 252

13.2 RAM INTERFACE REGISTERS................................................ 258

13.3 UTOPIA INTERFACE REGISTERS .......................................... 260

13.4 LINE INTERFACE REGISTERS ............................................... 271

13.5 DIRECT LOW SPEED MODE REGISTERS ............................. 271

13.6 SBI MODE REGISTERS ........................................................... 274

13.6.1 GENERAL SBI REGISTERS .......................................... 274

13.6.2 EXSBI REGISTERS ....................................................... 290

13.6.3 INSBI REGISTERS ........................................................ 315

13.7 INTERRUPT AND STATUS REGISTERS ................................. 339

13.8 IDLE CHANNEL DETECTION CONFIGURATION AND STATUS

REGISTERS.............................................................................. 358

13.9 DLL CONTROL AND STATUS REGISTERS............................. 373

14 OPERATION ........................................................................................ 378

14.1 HARDWARE CONFIGURATION............................................... 378

14.2 START-UP................................................................................. 378

14.2.1 LINE CONFIGURATION................................................. 379

14.2.2 QUEUE CONFIGURATION ............................................ 379

14.2.3 ADDING QUEUES.......................................................... 379

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14.2.4 LINE CONFIGURATION DETAILS ................................. 380

14.3 UTOPIA INTERFACE CONFIGURATION ................................. 389

14.3.1 VCI LOOPBACK SETUP EXAMPLE IN MULTI-ADDRESS

MODE............................................................................. 390

14.4 SPECIAL QUEUE CONFIGURATION MODES......................... 391

14.4.1 AAL0............................................................................... 391

14.5 JTAG SUPPORT ....................................................................... 392

14.5.1 TAP CONTROLLER ....................................................... 394

15 FUNCTIONAL TIMING......................................................................... 401

15.1 SOURCE UTOPIA..................................................................... 402

15.2 SINK UTOPIA............................................................................ 407

15.3 PROCESSOR I/F ...................................................................... 414

15.4 EXTERNAL CLOCK GENERATION CONTROL I/F (CGC)....... 416

15.4.1 SRTS DATA OUTPUT .................................................... 416

15.4.2 CHANNEL UNDERRUN STATUS OUTPUT ................... 417

15.4.3 ADAPTIVE STATUS OUTPUT ....................................... 418

15.5 EXT FREQ SELECT INTERFACE ............................................ 419

15.6 LINE INTERFACE TIMING........................................................ 420

15.6.1 16 LINE MODE ............................................................... 420

15.6.2 H-MVIP TIMING.............................................................. 423

15.6.3 SBI INTERFACE............................................................. 427

15.6.4 DS3/E3 TIMING.............................................................. 429

16 ABSOLUTE MAXIMUM RATINGS ....................................................... 431

17 D.C. CHARACTERISTICS ................................................................... 432

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18 A.C. TIMING CHARACTERISTICS...................................................... 434

18.1 RESET TIMING......................................................................... 434

18.2 SYS_CLK TIMING..................................................................... 435

18.3 NCLK TIMING ........................................................................... 436

18.4 MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS

.................................................................................................. 437

18.5 EXTERNAL CLOCK GENERATION CONTROL INTERFACE .. 441

18.6 RAM INTERFACE ..................................................................... 442

18.7 UTOPIA INTERFACE ................................................................ 443

18.8 LINE I/F TIMING........................................................................ 446

18.8.1 DIRECT LOW SPEED TIMING ...................................... 446

18.8.2 SBI TIMING .................................................................... 448

18.8.3 H-MVIP TIMING.............................................................. 451

18.8.4 HIGH SPEED TIMING .................................................... 453

18.9 JTAG TIMING ............................................................................ 455

19 ORDERING AND THERMAL INFORMATION...................................... 457

20 MECHANICAL INFORMATION ............................................................ 458

21 DEFINITIONS ...................................................................................... 459

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LIST OF REGISTERS

............................................................................................................. 254

(AN_ADDQ_FIFO) ............................................................................... 256

(AN_CLK_CFG) ................................................................................... 257

............................................................................................................. 259

(UI_COMN_CFG)................................................................................. 261

(UI_SRC_ADD_CFG) .......................................................................... 267

(UI_SNK_ADD_CFG)........................................................................... 268

(UI_SRC_POLL_LIST)......................................................................... 270

REGISTERS(LS_LN_CFG_REG)........................................................ 272

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LOW(SBI_LINK_DIS_REGL)............................................................... 280

LOW(SBI_SYNC_LINK_REGL) ........................................................... 282

LINKH_REG) ....................................................................................... 283

HIGH (EXT_ALRM_INTH) ................................................................... 285

(EXT_ALRM_STAT_REGL) ................................................................. 286

(INS_ALRM_REGL)............................................................................. 288

(INS_ALRM_REGH) ............................................................................ 289

ADDRESS REGISTER (EXT_TRIAD) ................................................. 297

CONTROL REGISTER (EXT_TRIAC) ................................................. 299

ACCESS DATA REGISTER (EXT_TRIB_MAP)................................... 301

ACCESS DATA REGISTER (EXT_TRIB_CTL).................................... 303

(SBI_PERR)......................................................................................... 306

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ADDRESS REGISTER(INS_TRIAD) ................................................... 323

CONTROL REGISTER (INS_TRIAC) .................................................. 325

DATA REGISTER (INS_TRIB_MAP..................................................... 327

DATA REGISTER (INS_TRIB_CTL) .................................................... 329

............................................................................................................. 341

(A1SPN_INTR_REG)........................................................................... 345

(A1SPN_TIDLE_FIFO)......................................................................... 349

(A1SPN_RSTAT_FIFO) ....................................................................... 352

(MSTR_INTR_EN_REG) ..................................................................... 354

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(A1SPN_EN_REG) .............................................................................. 355

(RCV_Q_ERR_EN).............................................................................. 357

ACTIVE TABLE .................................................................................... 360

TABLE.................................................................................................. 362

POINTER TABLE (RX_CHG_PTR)...................................................... 364

ACTIVE TABLE .................................................................................... 366

MATCHING LINE CONFIGURATION (PAT_MTCH_CFG0 )................ 368

CONFIGURATION TABLE ................................................................... 369

MATCHING CONFIGURATION TABLE ............................................... 370

............................................................................................................. 374

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LIST OF FIGURES

FIGURE 1 MULTI-SERVICE SWITCH APPLICATION ................................... 12

FIGURE 2 USING THE AAL1GATOR-32 IN AN ATM PASSIVE OPTICAL

NETWORK. ...................................................................................................... 13

FIGURE 3 USING THE AAL1GATOR-32 IN A DACS APPLICATION............. 13

FIGURE 4 AAL1GATOR-32 INTERNAL BLOCK DIAGRAM........................... 14

FIGURE 5 DATA FLOW AND BUFFERING IN THE UI AND DUAL A1SP BLOCKS 60

FIGURE 6 UI BLOCK DIAGRAM................................................................... 61

FIGURE 7 SOURCE PRIORITY SERVICING EXAMPLE............................... 68

FIGURE 8 CELL HEADER INTERPRETATION.............................................. 69

FIGURE 9 A1SP BLOCK DIAGRAM .............................................................. 71

FIGURE 10 CAPTURE OF T1 SIGNALING BITS (SHIFT_CAS=0) ............... 73

FIGURE 11 CAPTURE OF E1 SIGNALING BITS (SHIFT_CAS=0) ............... 73

FIGURE 12 TRANSMIT FRAME TRANSFER CONTROLLER ....................... 74

FIGURE 13 T1 ESF SDF-MF FORMAT OF THE T_DATA_BUFFER ............. 75

FIGURE 14 T1 SF-SDF-MF FORMAT OF THE T_DATA_BUFFER ............... 75

FIGURE 15 T1 SDF-FR FORMAT OF THE T_DATA_BUFFER...................... 76

FIGURE 16 E1 SDF-MF FORMAT OF THE T_DATA_BUFFER..................... 77

FIGURE 17 E1 SDF-MF WITH T1 SIGNALING FORMAT OF THE

T_DATA_BUFFER ............................................................................................ 77

FIGURE 18 E1 SDF-FR FORMAT OF THE T_DATA_BUFFER ..................... 78

FIGURE 19 UNSTRUCTURED FORMAT OF THE T_DATA_BUFFER.......... 78

FIGURE 20 SDF-MF T1 ESF FORMAT OF THE T_SIGNALING_BUFFER.... 79

FIGURE 21 SDF-MF T1 SF FORMAT OF THE T_SIGNALING BUFFER ...... 79

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FIGURE 22 SDF-MF E1 FORMAT OF THE T_SIGNALING_BUFFER........... 79

FIGURE 23 SDF-MF E1 WITH T1 SIGNALING FORMAT OF THE

T_SIGNALING_BUFFER.................................................................................. 80

FIGURE 24 TRANSMIT SIDE SRTS FUNCTION........................................... 81

FIGURE 25 CAS IDLE DETECTION CONFIGURATION REGISTER

STRUCTURE.................................................................................................... 82

FIGURE 26 CAS IDLE DETECTION INTERRUPT WORD ............................ 83

FIGURE 27 PROCESSOR CONTROLLED IDLE DETECTION INTERRUPT WORD 83

FIGURE 28 PROCESSOR CONTROLLED CONFIGURATION REGISTER

STRUCTURE.................................................................................................... 84

FIGURE 29 TX CHANNEL ACTIVE/IDLE BIT TABLE STRUCTURE ............. 84

FIGURE 30 PAT_MTCH_CFG REGISTER STRUCTURE ............................. 85

FIGURE 31 PATTERN MATCH IDLE DETECTION REGISTER STRUCTURE86

FIGURE 32 PATTERN MATCH IDLE DETECTION INTERRUPT WORD...... 86

FIGURE 33 FRAME ADVANCE FIFO OPERATION ....................................... 88

FIGURE 34 PAYLOAD GENERATION ........................................................... 96

FIGURE 35 LOCAL LOOPBACK.................................................................... 99

FIGURE 36 CELL HEADER INTERPRETATION.......................................... 101

FIGURE 37 FAST SN ALGORITHM ............................................................. 107

FIGURE 38 RECEIVE CELL PROCESSING FOR FAST SN ....................... 108

FIGURE 39 ROBUST SN ALGORITHM ........................................................111

FIGURE 40 CELL RECEPTION ....................................................................113

FIGURE 41 T1 ESF SDF-MF FORMAT OF THE R_DATA_BUFFER............114

FIGURE 42 T1 SF SDF-MF FORMAT OF THE R_DATA_BUFFER ..............114

FIGURE 43 T1 SDF-FR FORMAT OF THE R_DATA_BUFFER ....................115

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FIGURE 44 E1 SDF-MF FORMAT OF THE R_DATA_BUFFER....................115

FIGURE 45 E1 SDF-MF WITH T1 SIGNALING FORMAT OF THE

R_DATA_BUFFER...........................................................................................116

FIGURE 46 E1 SDF-FR FORMAT OF THE R_DATA_BUFFER....................116

FIGURE 47 UNSTRUCTURED FORMAT OF THE R_DATA_BUFFER.........117

FIGURE 48 T1 ESF SDF-MF FORMAT OF THE R_SIG_BUFFER...............117

FIGURE 49 T1 SF SDF-MF FORMAT OF THE R_SIG_BUFFER .................118

FIGURE 50 E1 SDF-MF FORMAT OF THE R_SIG_BUFFER ......................118

FIGURE 51 E1 SDF-MF WITH T1 SIGNALING FORMAT OF THE

R_SIG_BUFFER..............................................................................................119

FIGURE 52 POINTER/STRUCTURE STATE MACHINE.............................. 124

FIGURE 53 OVERRUN DETECTION........................................................... 126

FIGURE 54 DBCES RECEIVE SIDE BUFFERING ...................................... 129

FIGURE 55 OUTPUT OF T1 SIGNALING BITS (SHIFT_CAS=0)................ 131

FIGURE 56 OUTPUT OF E1 SIGNALING BITS (SHIFT_CAS=0) ............... 131

FIGURE 57 CHANNEL-TO-QUEUE TABLE OPERATION ........................... 133

FIGURE 58 RECEIVE SIDE SRTS SUPPORT ............................................ 134

FIGURE 59 SRTS DATA............................................................................... 138

FIGURE 60 CHANNEL STATUS FUNCTIONAL TIMING ............................. 138

FIGURE 61 ADAPTIVE DATA FUNCTIONAL TIMING.................................. 140

FIGURE 62 EXT FREQ SELECT FUNCTIONAL TIMING ............................ 141

FIGURE 63 RECEIVE SIDE SRTS SUPPORT ............................................ 142

FIGURE 64 DIRECT ADAPTIVE CLOCK OPERATION ............................... 144

FIGURE 65 MEMORY MAP.......................................................................... 149

FIGURE 66 A1SP SRAM MEMORY MAP .................................................... 149

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FIGURE 67 CONTROL REGISTERS MEMORY MAP ................................. 150

FIGURE 68 TRANSMIT DATA STRUCTURES MEMORY MAP ................... 151

FIGURE 69 RECEIVE DATA STRUCTURES ............................................... 152

FIGURE 70 NORMAL MODE REGISTERS MEMORY MAP........................ 153

FIGURE 71 INTERRUPT HIERARCHY........................................................ 154

FIGURE 72 ADDQ_FIFO WORD STRUCTURE .......................................... 157

FIGURE 73 LINE INTERFACE BLOCK ARCHITECTURE ........................... 162

FIGURE 74 LINE INTERFACE AND 2ND RAM INTERFACE ........................ 163

FIGURE 75 CAPTURE OF T1 SIGNALING BITS ........................................ 166

FIGURE 76 CAPTURE OF E1 SIGNALING BITS ........................................ 166

FIGURE 77 OUTPUT OF T1 SIGNALING BITS........................................... 167

FIGURE 78 OUTPUT OF E1 SIGNALING BITS........................................... 168

FIGURE 79 T1/E1 LINK RATE INFORMATION............................................ 170

FIGURE 80 MULTI-PHY TO MULTI-LINK LAYER DEVICE INTERFACE..... 172

FIGURE 81 SBI BLOCK ARCHITECTURE .................................................. 177

FIGURE 82 SDF-MF FORMAT OF THE T_SIGNALING BUFFER............... 200

FIGURE 83 R_CRC_SYNDROME MASK BIT TABLE LEGEND .................. 221

FIGURE 84 UTOPIA-2 MULTI-ADDRESS MODE WITH VCI BASED

LOOPBACK .................................................................................................... 391

FIGURE 85 BOUNDARY SCAN ARCHITECTURE ...................................... 393

FIGURE 86 TAP CONTROLLER FINITE STATE MACHINE ........................ 395

FIGURE 87 INPUT OBSERVATION CELL (IN_CELL) ................................. 398

FIGURE 88 OUTPUT CELL (OUT_CELL).................................................... 399

FIGURE 89 BIDIRECTIONAL CELL (IO_CELL) ........................................... 399

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FIGURE 90 LAYOUT OF OUTPUT ENABLE AND BIDIRECTIONAL CELLS400

FIGURE 91 PIPELINED SINGLE-CYCLE DESELECT SSRAM................... 401

FIGURE 92 PIPELINED ZBT SSRAM .......................................................... 401

FIGURE 93 SRC_INTF START OF TRANSFER TIMING (UTOPIA 1 ATM MODE) 402

FIGURE 94 SRC_INTF END-OF-TRANSFER TIMING (UTOPIA 1 ATM MODE)

403

FIGURE 95 UI_SRC_INTF START-OF-TRANSFER TIMING (UTOPIA 1 PHY MODE) 403

FIGURE 96 UI_SRC_INTF END-OF-TRANSFER (UTOPIA 1 PHY MODE). 404

FIGURE 97 UI_SRC_INTF START-OF-TRANSFER TIMING (UTOPIA 2 PHY MODE) 405

FIGURE 98 UI_SRC_INTF END-OF-TRANSFER TIMING (UTOPIA 2 PHY MODE) 405

FIGURE 99 UI_SRC_INTF START-OF-TRANSFER TIMING (ANY-PHY PHY MODE) 406

FIGURE 100 UI_SRC_INTF END-OF-TRANSFER TIMING (ANY-PHY PHY MODE) 406

FIGURE 101 SNK_INTF START-OF-TRANSFER TIMING (UTOPIA 1 ATM MODE) 407

FIGURE 102 SNK_INTF END-OF-TRANSFER TIMING (UTOPIA 1 ATM MODE) 408

FIGURE 103 SNK_INTF START-OF-TRANSFER TIMING (UTOPIA 1 PHY MODE) 409

FIGURE 104 SNK_INTF START-OF-TRANSFER UTOPIA 2 (SINGLE

ADDRESS PHY MODE) ................................................................................. 409

FIGURE 105 SNK_INTF CLAV DISABLE UTOPIA 2 (SINGLE-ADDRESS PHY MODE) 410

FIGURE 106 SNK_INTF END-OF-TRANSFER UTOPIA 2 (SINGLE ADDRESS

PHY MODE).................................................................................................... 410

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FIGURE 107 SNK_INTF START-OF-TRANSFER UTOPIA 2 (MULTI-ADDRESS

PHY MODE).....................................................................................................411

FIGURE 108 SNK_INTF END-OF-TRANSFER UTOPIA 2 (MULTI-ADDRESS

PHY MODE).....................................................................................................411

FIGURE 109 SNK_INTF START-OF-TRANSFER (ANY-PHY PHY MODE) . 412

FIGURE 110 SNK_INTF END-OF-TRANSFER (ANY-PHY PHY MODE) ..... 413

FIGURE 111 MICROPROCESSOR WRITE ACCESS.................................. 414

FIGURE 112 MICROPROCESSOR READ ACCESS ................................... 415

FIGURE 113 MICROPROCESSOR WRITE ACCESS WITH ALE................ 415

FIGURE 114 MICROPROCESSOR READ ACCESS WITH ALE ................. 415

FIGURE 115 SRTS DATA............................................................................. 416

FIGURE 116 CHANNEL STATUS FUNCTIONAL TIMING............................ 417

FIGURE 117 ADAPTIVE DATA FUNCTIONAL TIMING................................ 419

FIGURE 118 EXT FREQ SELECT FUNCTIONAL TIMING........................... 420

FIGURE 119 RECEIVE LINE SIDE T1 TIMING(RL_CLK = 1.544 MHZ) ...... 420

FIGURE 120 RECEIVE LINE SIDE E1 TIMING(RL_CLK = 2.048 MHZ)...... 421

FIGURE 121 MVIP-90 RECEIVE FUNCTIONAL TIMING ............................ 421

FIGURE 122 TRANSMIT LINE SIDE T1 TIMING(TL_CLK = 1.544 MHZ).... 422

FIGURE 123 TRANSMIT LINE SIDE E1 TIMING(TL_CLK = 2.048 MHZ) ... 422

FIGURE 124 MVIP-90 TRANSMIT FUNCTIONAL TIMING .......................... 423

FIGURE 125 RECEIVE H-MVIP TIMING, CLOSE-UP VIEW ....................... 424

FIGURE 126 RECEIVE H-MVIP TIMING, EXPANDED VIEW ...................... 425

FIGURE 127 TRANSMIT H-MVIP TIMING, CLOSE-UP VIEW ..................... 426

FIGURE 128 TRANSMIT H-MVIP TIMING, EXPANDED VIEW .................... 427

FIGURE 129 SBI DROP BUS T1/E1 FUNCTIONAL TIMING ....................... 428

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FIGURE 130 SBI DROP BUS DS3 FUNCTIONAL TIMING.......................... 428

FIGURE 131 SBI ADD BUS ADJUSTMENT REQUEST FUNCTIONAL TIMING

429

FIGURE 132 RECEIVE HIGH-SPEED FUNCTIONAL TIMING.................... 429

FIGURE 133 TRANSMIT HIGH-SPEED FUNCTIONAL TIMING.................. 430

FIGURE 134 RSTB TIMING ......................................................................... 435

FIGURE 135 SYS_CLK TIMING................................................................... 436

FIGURE 136 NCLK TIMING ......................................................................... 436

FIGURE 137 MICROPROCESSOR INTERFACE READ TIMING ................ 438

FIGURE 138 MICROPROCESSOR INTERFACE WRITE TIMING .............. 440

FIGURE 139 EXTERNAL CLOCK GENERATION CONTROL INTERFACE TIMING 441

FIGURE 140 RAM INTERFACE TIMING...................................................... 442

FIGURE 141 SINK UTOPIA INTERFACE TIMING ....................................... 444

FIGURE 142 SOURCE UTOPIA INTERFACE TIMING ................................ 445

FIGURE 143 TRANSMIT LOW SPEED INTERFACE TIMING..................... 446

FIGURE 144 RECEIVE LOW SPEED INTERFACE TIMING ....................... 447

FIGURE 145 SBI FRAME PULSE TIMING................................................... 448

FIGURE 146 SBI DROP BUS TIMING ......................................................... 449

FIGURE 147 SBI ADD BUS TIMING ............................................................ 450

FIGURE 148 SBI ADD BUS COLLISION AVOIDANCE TIMING................... 450

FIGURE 149 H-MVIP SINK DATA & FRAME PULSE TIMING ..................... 452

FIGURE 150 H-MVIP INGRESS DATA TIMING ........................................... 452

FIGURE 151 TRANSMIT HIGH SPEED TIMING ......................................... 453

FIGURE 152 RECEIVE HIGH SPEED INTERFACE TIMING....................... 454

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FIGURE 153 JTAG PORT INTERFACE TIMING.......................................... 456

FIGURE 154 352 PIN ENHANCED BALL GRID ARRAY (SBGA)................. 458

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LIST OF TABLES

TABLE 1 LINE INTERFACE SIGNAL TABLE SELECTION............................ 30

TABLE 2 LINE INTERFACE SUMMARY ........................................................ 48

TABLE 3 CFG_ADDR AND PHY_ADDR BIT USAGE IN SRC DIRECTION .. 64

TABLE 4 CFG_ADDR AND PHY_ADDR BIT USAGE IN SNK DIRECTION .. 67

TABLE 5 MINIMUM PARTIAL CELL SIZE PERMITTED IF ALL CONNECTIONS

ARE ACTIVE..................................................................................................... 97

TABLE 6 CHANNEL STATUS....................................................................... 139

TABLE 7 BUFFER DEPTH ........................................................................... 140

TABLE 8 FREQUENCY SELECT – T1 MODE ............................................. 146

TABLE 9 FREQUENCY SELECT – E1 MODE ............................................. 148

TABLE 10 LINE_MODE ENCODING............................................................ 161

TABLE 11 T1/E1 CLOCK RATE ENCODING ............................................... 171

TABLE 12 SUPPORTED LINKS ................................................................... 173

TABLE 13 STRUCTURE FOR CARRYING MULTIPLEXED LINKS ............. 174

TABLE 14 T1 TRIBUTARY COLUMN NUMBERING .................................... 174

TABLE 15 E1 TRIBUTARY COLUMN NUMBERING .................................... 175

TABLE 16 DESYNCHRONIZER E1/T1 CLOCK GENERATION ALGORITHM

179

TABLE 17 AAL1GATOR-32 MEMORY MAP................................................. 186

TABLE 18 A1SP AND LINE CONFIGURATION STRUCTURES SUMMARY 187

TABLE 19 TRANSMIT STRUCTURES SUMMARY...................................... 193

TABLE 20 R_CRC_SYNDROME MASK BIT TABLE .................................... 221

TABLE 21R_QUEUE_TBL FORMAT .............................................................. 231

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TABLE 22 REGISTER MEMORY MAP......................................................... 252

TABLE 23 COMMAND REGISTER MEMORY MAP..................................... 252

TABLE 24 RAM INTERFACE REGISTERS MEMORY MAP ........................ 258

TABLE 25 UTOPIA INTERFACE REGISTERS MEMORY MAP ................... 260

TABLE 26 CFG_ADDR AND PHY_ADDR BIT USAGE IN SRC DIRECTION267

TABLE 27 CFG_ADDR AND PHY_ADDR BIT USAGE IN SNK DIRECTION268

TABLE 28 LINE INTERFACE REGISTER MEMORY MAP SUMMARY ....... 271

TABLE 29 DIRECT LOW SPEED MODE REGISTER MEMORY MAP ........ 271

TABLE 30 GENERAL SBI REGISTER MEMORY MAP................................ 274

TABLE 31 EXSBI BLOCK REGISTER MEMORY MAP................................ 290

TABLE 32 TRIB_TYP ENCODING ............................................................... 304

TABLE 33 INSBI BLOCK REGISTER MEMORY MAP ................................. 315

TABLE 34 TRIB_TYP ENCODING ............................................................... 330

TABLE 35 INTERRUPT AND STATUS REGISTERS MEMORY MAP.......... 339

TABLE 36 IDLE CHANNEL DETECTION CONFIGURATION AND STATUS

REGISTERS MEMORY MAP ......................................................................... 358

TABLE 37 DLL CONTROL AND STATUS REGISTERS MEMORY MAP ..... 373

TABLE 38 CHANNEL STATUS..................................................................... 417

TABLE 39 FRAME DIFFERENCE ................................................................ 418

TABLE 40 ABSOLUTE MAXIMUM RATINGS............................................... 431

TABLE 41 AAL1GATOR-32 D.C. CHARACTERISTICS ............................... 432

TABLE 42 RTSB TIMING.............................................................................. 434

TABLE 43 SYS_CLK TIMING ....................................................................... 435

TABLE 44 NCLK TIMING.............................................................................. 436

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TABLE 45 MICROPROCESSOR INTERFACE READ ACCESS .................. 437

TABLE 46 MICROPROCESSOR INTERFACE WRITE ACCESS ................ 439

TABLE 47 EXTERNAL CLOCK GENERATION CONTROL INTERFACE..... 441

TABLE 48 RAM INTERFACE........................................................................ 442

TABLE 49 UTOPIA SOURCE AND SINK INTERFACE ............................... 443

TABLE 50 TRANSMIT LOW SPEED INTERFACE TIMING ......................... 446

TABLE 51 RECEIVE LOW SPEED INTERFACE TIMING............................ 447

TABLE 52 CLOCKS AND SBI FRAME PULSE (FIGURE 145)..................... 448

TABLE 53 SBI DROP BUS (FIGURE 146) ................................................... 448

TABLE 54 SBI ADD BUS (FIGURE 147 TO FIGURE 148)........................... 449

TABLE 55 H-MVIP SINK TIMING ................................................................. 451

TABLE 56 H-MVIP SOURCE TIMING .......................................................... 452

TABLE 57 TRANSMIT HIGH SPEED INTERFACE TIMING......................... 453

TABLE 58 RECEIVE HIGH SPEED INTERFACE TIMING ........................... 454

TABLE 59 JTAG PORT INTERFACE............................................................ 455

TABLE 60 AAL1GATOR-32 (PM73122) ORDERING INFORMATION.......... 457

TABLE 61 AAL1GATOR-32 (PM73122) THERMAL INFORMATION............ 457

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1 CHANGES FROM REV. A TO REV. B

There are four main changes when transitioning from Rev. A to Rev. B:

1. The DEV_ID has changed from 0000 to 0001.

2. The JTAG version number has changed from 0 to 1.

3. The SHIFT_CAS feature which allows the signaling to be aligned with the first nibble of data has been added. This feature is enabled by setting SHIFT_CAS in the LIN_STR_MODE register.

4. The capability to have a separate C1FP for the ADD and DROP side of the SBI bus has been added. In Rev. A there is only one C1FP pin, but Rev. B has the option to support two separate C1FP pins. The original C1FP pin becomes the C1FP for the drop side of the SBI bus and the new pin, C1FP_ADD, is the C1FP for the add side of the SBI bus. Rev. B defaults to using one C1FP pin which makes it backwards compatible with Rev. A, but two C1FP capability can be enabled by setting TWO_C1FP_EN in the SBI_BUS_CFG_REG register.

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2 CHANGES FROM REV B TO REV C

There are three main changes when transitioning from Rev. B to Rev. C:

1. The DEV_ID has changed from 0001 to 0010.

2. The JTAG version number has changed from 1 to 2.

3. A BUSMASTER bit has been added (bit 15 of SBI_BUS_CFG_REG). When set, the AAL1gator32 will drive all SBI bytes that are not driven by other devices. The will prevent parity errors from being detected due to floating bytes.

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3 FEATURES

The AAL1 Segmentation And Reassembly (SAR) Processor (AAL1gator-32) is a monolithic single chip device that provides DS1, E1, E3, or DS3 line interface access to an ATM Adaptation Layer One (AAL1) Constant Bit Rate (CBR) ATM network. It arbitrates access to an external SRAM for storage of the configuration, the user data, and the statistics. The device provides a microprocessor interface for configuration, management, and statistics gathering. PMC-Sierra also offers a software device control package for the AAL1gator-32 device.

• Compliant with the ATM Forum’s Circuit Emulation Services (CES) specification (AF-VTOA-0078), and the ITU-T I.363.1

• Supports Dynamic Bandwidth Circuit Emulation Services (DBCES). Compliant with the ATM Forum’s DBCES specification (AF-VTOA-0085). Supports idle channel detection via processor intervention, CAS signaling, or data pattern detection. Provides idle channel indication on a per channel basis.

• Supports non-DBCES idle channel detection by activating a queue when any of its constituent time slots are active, and deactivating a queue when all of its constituent time slots are inactive.

• Provides AAL1 segmentation and reassembly of 16 individual E1 or T1 lines, 8 H-MVIP lines at 8 MHz, or 2 E3 or DS3 or STS-1 unstructured lines.

• Using the optional Scalable Bandwidth Interconnect (SBI) Interface, provides AAL1 segmentation and reassembly of up to 32 T1, E1, or 2 DS3 links. In SBI mode can map any SBI tributary to any of the 32 AAL1 links. Supports floating and locked tributaries as well as unframed, framed without CAS and framed with CAS tributaries. CAS is only supported on Synchronous tributaries.

• Provides a standard UTOPIA level 2 Interface which optionally supports parity and runs up to 52 MHz. Only Cell Level Handshaking is supported. In MPHY mode, can act like a single port or 4 port device. The following modes are supported:

• 8/16-bit Level 2, Multi-Phy Mode (MPHY)

• 8/16-bit Level 1, SPHY

• 8-bit Level 1, ATM Master

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• Provides an optional 8/16-bit Any-PHY slave interface.

• Supports up to 1024 Virtual Channels (VC).

• Supports n x 64 (consecutive channels) and m x 64 (non-consecutive

channels) structured data format.

• Provides transparent transmission of Common Channel Signaling (CCS) and Channel Associated Signaling (CAS). Provides for termination of CAS signaling.

• Allows the CAS nibble to be coincident with either the first or second nibble of the data.

• Provides per-VC data and signaling conditioning in the transmit cell direction and per DS0 data and signaling conditioning in the transmit line direction. Data and signaling conditioning can be individually enabled. Includes DS3 AIS conditioning support in both directions. Transmit line conditioning options include programmable byte pattern, pseudo-random pattern or old data. Conditioning automatically occurs on underruns.

• In Cell Transmit direction, provides per-VC configuration of time slots allocated, CAS signaling support, partial cell size, data and signaling conditioning, ATM Cell header definition. Generates AAL1 sequence numbers, pointers and SRTS values in accordance with ITU-T I.363.1. Multicast connections are supported.

• In Cell Transmit direction provides counters for:

• Conditioned cells transmitted for each queue

• Cells which were suppressed for each queue

• Total number of cells transmitted for each queue

• In Cell Receive direction, provides per-VC configuration of time slots

allocated, CAS signaling support, partial cell size, sequence number processing options, cell delay variation tolerance buffer depth, maximum buffer depth. Processes AAL1 headers in accordance with ITU-T I.363.1.

• In Cell Receive direction, supports the Fast Sequence Number processing algorithm on all types of connections and Robust Sequence Number processing on Unstructured Data Format (UDF) connections. Cells are inserted/dropped to maintain bit integrity on lost or misinserted cells. Bit integrity is maintained through any single errored cell or up to six lost cells. Bit

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integrity can also optionally be maintained even if an underrun occurs. Pointer bytes, signaling bytes, and bitmask bytes are taken into account. Cell insertion options include a programmable single byte pattern, pseudo-random data, or old data .

• In Cell Receive direction provides counters for the following events which include all counters required by the ATM Forum’s CES-IS 2.0 MIB:

• Incorrect sequence numbers per queue

• Incorrect sequence number protection fields per queue

• Total number of received cells per queue

• Total number of dropped cells per queue

• Total number of underruns per queue

• Total number of lost cells per queue

• Total number of overruns per queue

• Total number of reframes per queue

• Total number of pointer parity errors per queue

• Total number of misinserted cells per queue

• Total number of OAM or non-data cells received

• Total number of OAM or non-data cells dropped.

• For each receive queue the following sticky bits are maintained:

• Cell received

• Structured pointer rule error detected

• DBCES bitmask parity error

• Cell dropped due to blank allocation table

• Cells dropped due to pointer search

• Cell dropped due to forced underrun

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• Cell dropped due to sequence number processing algorithm

• Valid pointer was received

• Pointer parity error detected

• SRTS resume from an underrun condition

• SRTS underrun occurred

• Resume occurred from an underrun condition

• Pointer reframe occurred

• Overrun condition detected

• Cell received while in an underrun

• Supports AAL0 mode, selectable on a per VC basis.

• Provides system side loopback support. When enabled and the incoming VCI

matches the programmable loopback VCI, the cell received on the Receive UTOPIA interface is looped back to the Transmit UTOPIA interface. Alternatively the UTOPIA interface can be put into remote loopback mode where all incoming cells are looped back out. Provides line side loopback, enabled on a per queue basis, which can loop a single channel or any group of channels which can be mapped to a single queue.

• Provides a patented frame based calendar queue service algorithm with anticlumping add-queue mechanism that produces minimal Cell Delay Variation (CDV). In UDF mode uses non-frame based scheduling to optimize CDV. In addition, four internal cell generation engines work in parallel to further insure low CDV.

• Queues are added by making entries into an add-queue FIFO to minimize queue activation overhead. An offset can be configured when queue is added to distribute cell build times to minimize CDV due to clumping.

• Provides single maskable, open-collector interrupt with master interrupt register to facilitate interrupt processing. The master interrupt register indicates the following conditions each of which can be masked:

• Error/status condition with one of four AAL1 blocks

• Ram parity error

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• UTOPIA parity error

• Transmit UTOPIA FIFO is full

• Transmit UTOPIA transfer error

• UTOPIA loopback FIFO is full

• UTOPIA runt cell is detected

• SBI error detected

• For each AAL1 block the following conditions can cause an interrupt, each of

which can be masked. Separate 64 entry FIFOs per AAL1 block are used to track receive and transmit status.

• A receive queue sticky bit was just set (individual mask per sticky bit)

• Receive queue entered underrun state

• Receive queue exited underrun state

• DBCES bitmask changed.

• Receive Status FIFO overflow

• Transmit Frame Advance FIFO full

• Reception of OAM cells

• Change in idle state of a channel enabled for idle channel detection

• Transmit Channel Idle State change FIFO overflow

• Line frame resync event

• Transmit ATM Layer Processor (TALP) FIFO full

• For SBI logic the following conditions can cause an interrupt, each of which

can be masked:

• SBI Add bus FIFO overflow or underrun

• SBI Add bus C1FP resync

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• SBI Add bus depth check error

• SBI Drop bus FIFO overflow or underrun

• SBI Drop bus parity error

• SBI Drop bus depth check error

• SBI Drop bus C1FP resync

• SBI Alarm detected

• Provides a 16-bit microprocessor interface to internal registers, and two

external 256K x 16(18) (10 ns) Pipelined Single-Cycle Deselect Synchronous SRAMs, or Synchronous ZBT SRAMs.

• Provides a transmit buffer which can be used for Operations, Administration and Maintenance (OAM) cells as well as any other user-generated cells such as AAL5 cells for ATM signaling. A corresponding receive buffer exists for the reception of OAM cells or non-AAL1 data cells.

• Includes an internal E1/T1 clock synthesizer for each line which can generate a nominal E1/T1 clock or be controlled via Synchronous Residual Time Stamp (SRTS) clock recovery method in Unstructured Data Format (UDF) mode or a programmable weighted moving average adaptive clocking algorithm. DS3 and E3 SRTS or adaptive clocking is supported using an external clock synthesizer and the clock control port.

• The clock synthesizers can also be controlled externally to provide customization of SRTS or adaptive algorithms. SRTS can also be disabled via a hardware input. Adaptive and SRTS information is output to a port for external processing for both low speed and high speed mode, if needed. Buffer depth is provided in units of bytes. The synthesizer can be set to 256 discrete frequencies between either +/-100 ppm for E1 or +/-200 ppm for T1.

• Low-power 2.5 Volt CMOS technology with 3.3 Volt, 5 Volt tolerant I/O.

• 352-pin super ball grid array (SBGA) package.

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4 APPLICATIONS

• Multi-service ATM Switch

• ATM Access Concentrator

• Digital Cross Connect

• Computer Telephony Chassis with ATM infrastructure

• Wireless Local Loop Back Haul

• ATM Passive Optical Network Equipment

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5 REFERENCES

Applicable Recommendations and Standards.

1. ANSI T1 Recommendation T1.403, Network-to-Customer Installation – DS1 Metallic Interface, NY, NY, 1995.

2. ANSI T1 Recommendation T1.630, Broadband ISDN-ATM Adaptation Layer for Constant Bit Rate Services, Functionality and Specification, NY, NY, 1993.

3. ATM Forum, ATM User Network Interface (UNI) Specification, V 3.1, Foster City, CA USA, September 1994.

4. ATM Forum, Circuit Emulation Service – Interoperability Specification (CESIS), V. 2.0, Foster City, CA USA, August 1996.

5. ATM Forum, Specifications of (DBCES) Dynamic Bandwidth Utilization – in 64Kbps Time Slot Trunking Over ATM – Using CES, Foster City, CA USA, (AF-VTOA-0085) July 1997.

6. ATM Forum, UTOPIA, an ATM-PHY Layer Specification, Level 1, V. 2.01, Foster City, CA USA, March 1994.

7. ATM Forum, UTOPIA, an ATM-PHY Layer Specification, Level 2, V. 1.0, Foster City, CA USA, June 1995.

8. ITU-T Recommendation G.703, Physical/Electrical Characteristics of Hierarchical Digital Interfaces, April 1991.

9. ITU-T Recommendation I.363.1, B-ISDN ATM Adaptation Layer (AAL) Specification, July 1995.

10. ITU-T Recommendation G.823, The Control of Jitter and Wander within Digital Networks Which Are Based on the 2048 kbit/s Hierarchy, March 1993.

11. ITU-T Recommendation G.824 The Control of Jitter and Wander within Digital Networks Which Are Based on the 1544 kbit/s Hierarchy, March 1993.

12. PMC-971268, “High density T1/E1 framer with integrated VT/TU mapper AND M13 multiplexer” (TEMUX), 2000, Issue 5.

13. GO-MVIP, “MVIP-90 Standard” Release 1.1, October 1994.

14. GO-MVIP, “H-MVIP Standard” Release 1.1a, January 1997.

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6 APPLICATION EXAMPLES

An essential function for ATM networks is to emulate existing Time Division Multiplexing (TDM) circuits. Since most voice and data services are currently provided by TDM circuits, seamless interworking between TDM and ATM has become a system requirement. The ATM Forum has standardized an internetworking function that satisfies this requirement in the Circuit Emulation Service (CES) Specification. The AAL1gator-32 is a direct implementation of that service specification in silicon, including the complex Nx64 channelized service and support of CAS.

6.1 ATM Multi-service Switch

An ATM Multi-service Switch, located at the edge of the wide area network, interfaces to Frame Relay, ATM as well as TDM services and consolidates these different services to ATM cells for transport over a single high-bandwidth ATM core network.

With the AAL1gator-32 and its support for the SBITM bus, high density Any Service Any Port linecards for ATM Switches can be designed with PMC-Sierra’s

SPECTRATM, TEMUXTM, AAL1gator, S/UNI -IMA, FREEDMTM, S/UNI -APEX

and S/UNI -ATLASTM products. The design shown in Figure 1 supports a broad spectrum of existing and emerging services including Frame Relay (FR), multilink Frame Relay, multi-link PPP, Internet Protocol (IP), Dedicated Private Line and Integrated Voice and Data.

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Figure 1 Multi-service Switch Application

UTOPIA L2 /

Any-PHY

UTOPIA

Traffic

Manager

PM7326

S/UNI-APEX

PM7324

S/UNI-ATLAS

OAM and

Policing

OC-12

STS-12

SONET/SDH

Framer

PM5313

SPECTRA-

622

Telecom

T1/J1/E1 Framer

TU/VT Mapper

M13 Mux

PM8316

TEMUX-84

PM8316

TEMUX-84

PM8316

TEMUX-84

PM8316

TEMUX-84

SBI

H-MVIP

Packet

Processor

PM7389

FREEDM-84

S/UNI-IMA-84

Emulation Service

AAL1gator-32

Voice Processor

Any-PHY

IMA / UNI

PM7341

AAL1 Circuit

PM73122

DSP

Packet/Cell

Internetworking

APPI

Function

ML-PPP and

ML-Fram e Relay

IMA / UNI

Circuit

Emulation Service

VoATM

Voice Processing

RM7000

MIPS

Processor

With the dramatic reduction in board space and power, the optimized AAL1gator32 / TEMUX-84 solution enables a new generation of OC-3 and OC-12 Circuit Emulation Service and Any Service Any Port linecards.

6.2 Passive Optical Network (PON) System

The general architecture of a Passive Optical Network (PON) access network consists of two key elements: the Optical Line Termination (OLT) and the Optical Network Unit (ONU). The OLT is connected to the ONU through a point-tomultipoint Passive Optical Network that consists of fiber, splitters and other passive components. Typically, up to 32 ONUs are connected to a single OLT, depending on the splitting factor. OLTs are typically located in local exchanges and ONUs on street locations, in buildings or even in homes.

Figure 2 shows the use of the AAL1gator-32 in an OLT application supporting CES functions. Note that the PM73123 AAL1gator-8 or PM73124 AAL1gator-4 can be used in ONUs to provide the reciprocal CES functions to the OLT.

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PM73122 AAL1GATOR-32

Figure 2 Using the AAL1gator-32 in an ATM Passive Optical Network.

ATM PHY

(e.g. S/UNI-

QUAD)

ONU

ODN Interface

Function

ODN Interface

Function

...

ODN Interface

Function

Transmission

Mux/Demux

ATM Cross

Connect Function

AAL1gator-32 TEMUX

AAL1gator-32

Optical Line Termination Equipment

6.3 Digital Access Cross-connect System (DACS) with an ATM Interface

Digital Access Cross-connect systems (DACS) with an ATM uplink to a core ATM switch can use one or more AAL1gator-32s to emulate a TDM service over ATM. DACs with CES capabilities allow the service providers to consolidate legacy private line services onto a high speed ATM backbone network and reduce the number of network elements and physical connections that need to be managed. Figure 3 shows the AAL1gator-32 in a DACS application.

TEMUX

DS3

LIU

DS3

LIU

Figure 3 Using the AAL1gator-32 in a DACS application.

UTOPIA / Any-PHY

H-MVIP

DS3 LIU

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PM8316

TEMUX-84

TDM Switch

H-MVIP

PM73122

AAL1gator-32

PM73122

AAL1gator-32

PM7326

S/UNI-APEX

Cell

FIFO

UTOPIA L2

PM5349

S/UNI-QUAD

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7 BLOCK DIAGRAM

The AAL1gator-32 contains four AAL1 SAR Processors (A1SP) which work in parallel. The A1SP blocks interface to a common UTOPIA interface on one side and a Line Interface block on the other side which can be configured to support several different line protocols. Two of the A1SP blocks share one ram interface and the other two A1SP blocks share the other ram interface. The processor Interface block which also contains the external clock control interface is shared by all blocks.

Figure 4 AAL1gator-32 Internal Block Diagram

RAM2_ADSCB

RAM2_A[17:0]

RAM2_D[15:0]

RAM2_PAR[1:0]

RAM2_WEB[1:0 ]

RAM2_CSB

RAM2_OEB

Line Interface

LINE_MODE[1:0] ADETECT AACTIVE REFCLK C1FP

DDATA[7:0] DDP

DPL DV5 ADATA[7:0] ADP AJUST_REQ APL AV5

F0B

TL_DATA[15 :0] TL_SYNC[15:0] TL_SIG[15:0] RL_DATA[15:0] RL_SYNC[15:0] RL_SIG[15:0]

SBI

H-MVIP

Low Speed

High Speed

RSTB

SCAN_ENB

SCAN_MODE B

TATM_DATA[15: 0]

TATM_PAR TATM_ENB

TATM_SOC

TATM_CLAV

TATM_CLK

RPHY_ADD[4:0]

RATM_DATA[15:0]

RATM_PAR RATM_ENB

RATM_SOC

RATM_CLAV

RATM_CLK

TPHY_ADD[4:0]

SYSCLK

NCLK

TL_CLK_OE

TL_CLK[15:0]

Clock

MUX

UTOPIA Interface

RL_CLK[15:0]

CRL_CLK

CTL_CLK

RAM2

Interface

A1SP

JTAG

TDO

TRST

RAM 1

Interface

TDI

TCK

TMS

RAM1_CSB

RAM1_A[17:0]

RAM1_ADSCB

RAM1_OEB

RAM1_D[15:0]

RAM1_PAR[1:0]

RAM1_WEB[1:0]

Processor

Interface

ALE

A[19:0]

D[15:0]

WRB

External Clock

Interface

CSB

RDB

INTB

ACKB

CGC_LINE[4:0]

CGC_DOUT[3:0]

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SRTS_STB

ADAP_STB

CGC_VALID

CGC_SER_D

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PM73122 AAL1GATOR-32

8 DESCRIPTION

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9 PIN DIAGRAM

The AAL1gator-32 is manufactured in a 352 pin enhanced ball grid array (SBGA) package.

26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

vss5 vss4 TMS TDO RAM1_AD PCH RAM1_AD RAM1_AD RAM1_AD RAM1_AD RL_CLK TL_CLK vss3 vss2 RAM1_D RAM1_D PCH TL_DATA RAM1_OE RAM1_D RAM1_D TL_SYNC TL_SYNC RL_SIG [7] vss1 vss0

vss9 vdd10 vss8 SYS_CLK RAM1_AD RAM1_AD RAM1_AD RAM1_AD RAM1_AD RAM1_PA RAM1_W RL_CLK RA M1_D RAM1_D RAM1_D RL_SYNC TL_SYNC RAM1_D RAM1_D CRL_CLK RL_DATA LINE_MO TL_DATA vss7 vdd9 vss6

TATM_DA vss11 vdd12 TDI RAM1_AD RAM1_AD RAM1_AD RAM1_CS RAM1_AD RAM1_AD RAM1_PA TL_CLK RAM1_D RAM1_D SCAN_EN RL_DATA RAM1_D RAM1_D CTL_CLK RL_SYNC TL_DATA TL_SIG [7] RL_SYNC vdd11 vss10 TL_CLK

TATM_DA TATM_DA TATM_DA vdd17 TCLK RAM1_AD RAM1_AD RAM1_AD vdd16 RAM1_AD RAM1_W RAM1_D vdd15 RAM1_D RL_SIG [8] TL_SIG [8] RAM1_D vdd14 RL_SIG [9] TL_SIG [9] TL_CLK RL_CLK vdd13 RL_DATA TL_SIG [6] RL_CLK

TATM_PA TATM_DA RPHY_AD TATM_DA TL_SYNC TL_DATA RL_SYNC TL_CLK

TATM_C L RPHY_ AD TATM_DA TATM_DA RL_SIG [6] RL_DATA TL_SIG [5] RL_CLK

TATM_SO RPHY_AD RPHY_AD P CH TL_SYNC TL_DATA RL_SYNC TL_SYNC

TL_CLK RL_CLK TATM_EN RPHY_AD RL_SIG [5] RL_DATA TL_CLK RL_SIG [4]

TL_DATA TL_CLK TL_CLK vdd18 vdd19 TL_SIG [4] RL_CLK RL_DATA

TATM_D A TATM_DA TL_SYNC RL_ CLK TL_DATA RL_SYNC TL_CLK TL_DATA

PCH TATM_DA TATM_DA TL_SIG TL_SYNC TL_SIG [3] TL_SIG RL_CLK

TATM_D A TATM_DA TATM_DA TATM _CL TL_DATA RL_SIG RL_SYNC RL_DATA

Vss13 TL_CLK RL_SYNC RL_CLK vdd20 TL_SYNC TL_SIG vss12

vss15 RL_CLK vdd21 PCH RL_SIG [3] TL_DATA vss14

RATM_DA TL_CLK RL_CLK RL_CLK TL_SIG [2] TL_SYNC RL_DATA RL_SYNC

TL_CLK RATM_DA RATM_DA RATM_DA RL_DATA RL_CLK TL_DATA TL_CLK

RATM_DA RATM_EN RATM_DA RATM_CL RL_SIG [1] TL_CLK RL_SYNC RL_SIG [2]

Bottom View of

352 SBGA Package

(35 mm x 35 mm)

RATM_DA RATM_DA TPHY_AD vdd23 vdd22 RL_CLK TL_SIG [1] TL_SYNC

RATM_SO TPHY_AD TPHY_AD TPHY_AD PCH TL_SYNC RL_SYNC TL_DATA

RATM_CL RATM_PA RATM_DA RATM_DA RL_SYNC RL_DATA TL_CLK RL_DATA

PCH RATM_DA TPHY_AD RATM_DA TL_SIG [0] RL_DATA RL_SIG TL_SYNC

RATM_DA RATM_DA RATM_DA A [17]

RATM_DA A [19] SCAN_MO vdd4 D [15] A [15] D [11] A [11] vdd3 D [5] A [4] TL_SYNC TL_SIG vdd2 RDB TL_SYNC RL_SIG vdd1 CGC_DOU CGC_SER CGC_LINE TRSTB vdd0 RL_DATA RL_SIG [0] LINE_MO

A [18] vss17 vdd6 A [16] D [12] A [12] D [8] A [9] D [6] A [6] RL_DATA RL_DATA D [1] A [2] ALE ACKB TL_SIG TL_DATA CGC_DOU NCLK CGC_LINE CGC_LINE RSTB vdd5 vss16 RL_CLK

vss21 vdd8 vss19 D [13] A [13] D [9] A [10] D [7] A [7] D [3] RL_SIG RL_SYNC D [0] A [3] A [0] CSB INTB RL_DATA TL_SIG CGC_DOU TL_CLK_O CGC_LINE ADAP_ST vss20 vdd7 vss18

vss27 vss26 D [14] A [14] D [10] D [2] A [8] D [4] A [5] PCH TL_DATA RL_SIG vss25 vss24 A [1] W RB CGC_DOU TL_DATA RL_SYNC TL_SYNC PCH CGC_VALI CGC_LINE SRTS_ST vss23 vss22

RL_SYNC TL_DATA RL_SIG RL_SYNC

26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

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10 PIN DESCRIPTION

10.1 UTOPIA Interface Signals (52)

Pin Name Type Pin

Function

No.

Note signals have different meanings depending on whether the UTOPIA bus is in

ATM master mode, PHY mode or Any-PHY mode. The mode is controlled by the UTOP_MODE and ANY-PHY_EN fields in the UI_SRC_CFG and UI_SNK_CFG registers.

All outputs are tri-state when the chip is in reset or when UI_EN is disabled in the UI_COMN_CFG register.

All outputs have a maximum output current (IMAX) = 8 mA.

TATM_CLK/RPHY_CLK Input F26

ATM : Transmit UTOPIA ATM Layer Clock is the synchronization clock input for the TATM interface.

PHY: Receive UTOPIA/Any-PHY PHY Layer Clock is the synchronization clock input for the RPHY interface

Maximum frequency is 52 MHz.

TATM_SOC/RPHY_SOC /RSOP

Output G26

ATM : Transmit UTOPIA ATM Layer Start-Of-Cell is an active high signal asserted by the AAL1gator-32 when TATM_D contains the first valid byte of the cell.

PHY: Receive Any-PHY/UTOPIA PHY Layer Start-Of-Cell is an active high signal asserted by the AAL1gator-32 when RPHY_D[15:0] contains the first valid word of the cell. AAL1gator-32 drives this signal only when the ATM layer has selected it for a cell transfer.

Any-PHY: This pin is the Receive Start of Packet (RSOP) signal which functions just like RPHY_SOC.

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Pin Name Type Pin

No.

TATM_D[15]/RPHY_D[15] TATM_D[14]/RPHY_D[14] TATM_D[13]/RPHY_D[13] TATM_D[12]/RPHY_D[12] TATM_D[11]/RPHY_D[11] TATM_D[10]/RPHY_D[10] TATM_D[9]/RPHY_D[9] TATM_D[8]/RPHY_D[8] TATM_D[7]/RPHY_D[7] TATM_D[6]/RPHY_D[6] TATM_D[5]/RPHY_D[5] TATM_D[4]/RPHY_D[4] TATM_D[3]/RPHY_D[3] TATM_D[2]/RPHY_D[2] TATM_D[1]/RPHY_D[1] TATM_D[0]/RPHY_D[0]

Output D24

E23 C26 D25 F23 D26 E25 F24 K25 L24 K26 L25 P24 M24 M25 M26

Function

ATM : Transmit UTOPIA ATM Layer

Data Bits 7 to 0 form the byte-wide data driven to the PHY layer. Bit 0 is the Least Significant Bit (LSB). Bit 7 is the Most Significant Bit (MSB) and is the first bit received for the cell from the serial line.

Note that only the lower 8 bit of the bus are used in ATM master mode.

PHY: Receive UTOPIA/Any-PHY PHY Layer Data Bits 15 to 0 form the word-wide data driven to the ATM layer. This bus only driven when the ATM layer has selected the UI_SRC_INTF for a cell transfer. The upper byte is only used if 16_BIT_MODE is set in the UI_SRC_CFG register. Otherwise the upper byte is driven to 0’s. Bit 0 is the LSB. Bit 7 is the MSB of the first byte and is the first bit received for the cell from the serial line.

TATM_PAR/ RPHY_PAR Output E26

ATM : Transmit UTOPIA ATM Layer Parity is a byte parity bit covering TATM_D(7:0).

PHY: Receive UTOPIA/Any-PHY PHY Layer Parity is either a byte parity covering RPHY_D(7:0) or word parity covering RPHY_D(15:0) depending on the value of 16_BIT_MODE.

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Pin Name Type Pin

No.

TATM_ENB/RPHY_ENB

Bidi H24

/RENB

Function

ATM : Transmit UTOPIA ATM Layer

Enable is an active low signal asserted by the AAL1gator-32 during cycles when TATM_D contains valid data. It is not asserted until the AAL1gator-32 is ready to send a full cell.

PHY: Receive UTOPIA/Any-PHY PHY Layer Enable is an active low signal asserted by the ATM layer to indicate RPHY_D and RPHY_SOC will be sampled at the end of the next cycle. If UTOP_MODE in UI_SRC_CFG is set to UTOPIA Level 2 Mode then the AAL1gator32 will drive data only if RPHY_ADD matches CFG_ADDR in the UI_SRC_ADD_CFG register the cycle before RPHY_ENB goes low.

Any-PHY: This pin is the RENB input signal, which functions the same as RPHY_ENB. The only difference is that data is driven two cycles after selection instead of just one cycle.

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PM73122 AAL1GATOR-32

Pin Name Type Pin

No.

TATM_CLAV/RPHY_CLAV

Bidi M23

/RPA

Function

ATM : Transmit UTOPIA ATM Layer

Cell Available is an active high signal from the PHY layer device to indicate that there is sufficient room to accept a cell.

PHY: Receive UTOPIA/Any-PHY PHY Layer Cell Available is an active high signal asserted by the AAL1gator-32 to indicate it is ready to deliver a complete cell. In Utopia Level 2 mode, this signal is driven only when MPHY_ADD matches CFG_ADDR in the UI_SRC_ADD_CFG register in the previous cycle. A pulldown resistor is recommended.

Any-PHY: This pin is the Receive Packet Available (RPA) signal which functions the same as RPHY_CLAV except for it is activated two cycles after a matching address instead of one.

RPHY_ADD[4]/RSX RPHY_ADD[3]/RCSB RPHY_ADD[2] RPHY_ADD[1] RPHY_ADD[0]

I/O Input Input Input Input

E24 G24 F25 H23 G25

ATM : These signals are not used in ATM mode.

PHY: Receive UTOPIA PHY Layer Address (Bits 4 to 0) which selects the UTOPIA receiver. These inputs are used as an output enable for RPHY_CLAV and to validate the activation of RPHY_ENB. There are internal pull-up resistors. These pins are compared with CFG_ADDR[4:0] in the UI_SRC_CFG_ADDR register.

ANY-PHY: Receive Start Transfer(RSX) is an active high output which indicates the start of an Any-PHY packet which identifies the location of the prepended address. ANY-PHY_EN in

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PM73122 AAL1GATOR-32

Pin Name Type Pin

No.

Function

UI_SRC_CFG register needs to be set for this function.

Receive Chip Select Bar (RCSB) is an active low input which is used to select the AAL1gator-32 when polling in Any-PHY mode. This input is used to decode any Any-PHY address bits greater than RPHY_ADD[2]. This input goes low one cycle after Any-PHY address is valid.

ANY-PHY_EN and CS_MODE_EN in UI_SRC_CFG register needs to be set for this function. Otherwise this bit functions as RPHY_ADD[3].

RPHY_ADD[2:0] is the bottom three bits of the Any-PHY address and is used to select the device when polling. These pins are compared with CFG_ADDR[2:0] in the UI_SRC_CFG_ADDR register.

RATM_CLK/ TPHY_CLK Input Y26

Note these pins must be tied to ground when not used.

ATM : Receive UTOPIA ATM Layer Clock is the synchronization clock input for synchronizing the RATM interface.

PHY: Transmit UTOPIA/Any-PHY PHY Layer Clock is the synchronization clock input for synchronizing the TPHY interface.

Maximum frequency is 52 MHz.

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Pin Name Type Pin

No.

RATM_SOC/ TPHY_SOC

Input W26 This signal has two definitions

/TSOP

Function

depending on whether the UTOPIA is in ATM mode or PHY mode.

ATM : Receive UTOPIA ATM Layer Start-Of-Cell is an active high signal asserted by the PHY layer when RATM_D contains the first valid byte of a cell.

PHY: Transmit UTOPIA/Any-PHY PHY Layer Start-Of-Cell is an active high signal asserted by the ATM layer when TPHY_D contains the first valid byte of a cell.

Any-PHY: This pin is the Transmit Start of Packet (TSOP) signal which functions just like TPHY_SOC. This signal is optional in this mode. If unused, tie low.

RATM_D[15]/TPHY_D[15] RATM_D[14]/TPHY_D[14] RATM_D[13]/TPHY_D[13] RATM_D[12]/TPHY_D[12] RATM_D[11]/TPHY_D[11] RATM_D[10]/TPHY_D[10] RATM_D[9]/TPHY_D[9] RATM_D[8]/TPHY_D[8] RATM_D[7]/TPHY_D[7] RATM_D[6]/TPHY_D[6] RATM_D[5]/TPHY_D[5] RATM_D[4]/TPHY_D[4] RATM_D[3]/TPHY_D[3] RATM_D[2]/TPHY_D[2] RATM_D[1]/TPHY_D[1] RATM_D[0]/TPHY_D[0]

Input AB24

AA23 AC26 AB25 Y23 AB26 AA25 Y24 V25 U24 V26 T23 T24 U26 T25 R26

ATM : Receive UTOPIA ATM Layer Data Bits 7 to 0 form the byte-wide data from the PHY layer device. Bit 0 is the LSB. Bit 7 is the MSB. This is the first bit of the cell, which will be transmitted on the serial line. The upper byte is not used in ATM mode.

PHY: Transmit UTOPIA/Any-PHY PHY Layer Data Bits 15 to 0 form the word-wide data from the ATM layer device. Bit 0 is the LSB. Bit 7 is the MSB of the first byte. This is the first bit of the cell, which will be transmitted on the serial line. The upper byte is only used if 16_BIT_MODE is set in the UI_SNK_CFG register.

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Pin Name Type Pin

No.

RATM_PAR/ TPHY_PAR Input Y25

RATM_ENB/TPHY_ENB Bidi U25

Function

ATM : Receive UTOPIA ATM Layer

Parity is a byte odd parity bit covering RATM_D(7:0) or word odd parity covering RATM_D(15:0) depending on the value of 16_BIT_MODE.

PHY: Transmit UTOPIA/Any-PHY PHY Layer Parity is either a byte odd parity covering TPHY_D(7:0) or word odd parity covering TPHY_D(15:0) depending on the value of 16_BIT_MODE.

ATM : Receive UTOPIA ATM Layer Enable is an active low signal asserted by the AAL1gator-32 to indicate RATM_D and RATM_SOC will be sampled at the end of the next cycle. It will not be asserted until the AAL1gator-32 is ready to receive a full cell.

PHY: Transmit UTOPIA/Any-PHY PHY Layer Enable is an active low signal asserted by the ATM layer device during cycles when TPHY_D[15:0] contain valid data. The AAL1gator-32 will accept data only if TPHY_ADD matches CFG_ADDR in the UI_SNK_CFG register the cycle before TPHY_ENB goes low

Any-PHY: This pin is the TENB input signal, which functions the same as TPHY_ENB.

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PM73122 AAL1GATOR-32

Pin Name Type Pin

No.

RATM_CLAV/TPHY_CLAV Bidi U23

Function

ATM : Receive UTOPIA ATM Layer

Cell Available is an active high signal asserted by the PHY layer to indicate that there is a cell available to send.

PHY: Receive UTOPIA/Any-PHY PHY Layer Cell Available is an active high signal asserted by the AAL1gator-32 to indicate there is a cell-space available. The AAL1gator-32 drives this signal only when TPHY_ADD matches CFG_ADDR in the UI_SNK_CFG register in the previous cycle. A pulldown resistor is recommended.

Any-PHY: This pin is the Transmit Packet Available (TPA) signal which functions the same as TPHY_CLAV except for it is activated two cycles after a matching address instead of one.

TPHY_ADD[4]/TSX TPHY_ADD[3]/TCSB TPHY_ADD[2] TPHY_ADD[1] TPHY_ADD[0]

Input AA24

W23 W24 W25 V24

ATM : These signals are not used in ATM mode.

PHY: Transmit UTOPIA PHY Layer Address (Bits 4 to 0) which selects the UTOPIA transmitter. These inputs are used as an output enable for TPHY_CLAV and to validate the activation of TPHY_ENB. There are internal pull-up resistors. These pins are compared with CFG_ADDR[4:0] in the UI_SNK_CFG_ADDR register.

ANY-PHY: Transmit Start Transfer(TSX) is an active high input which indicates the start of an AnyPHY packet which identifies the location of the prepended address. ANY-PHY_EN in UI_SNK_CFG register needs to be set for this

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Pin Name Type Pin

No.

Function

function.

Transmit Chip Select Bar (TCSB) is an active low input which is used to select the AAL1gator-32 when polling in Any-PHY mode. This input is used to decode any Any-PHY address bits greater than TPHY_ADD[2]. This input goes low one cycle after Any-PHY address is valid.

ANY-PHY_EN and CS_MODE_EN in UI_SNK_CFG register needs to be set for this function. Otherwise this bit functions as TPHY_ADD[3].

TPHY_ADD[2:0] is the bottom three bits of the Any-PHY address and is used to select the device when polling. These pins are compared with CFG_ADDR[2:0] in the UI_SNK_CFG_ADDR register.

Note these pins must be tied to ground when not used.

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10.2 Microprocessor Interface Signals (43)

Pin Name Type Pin

No.

D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]

A[19] A[18] A[17] A[16] A[15] A[14] A[13] A[12] A[11] A[10] A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0]

I/O AC22

AF24 AE23 AD22 AC20 AF22 AE21 AD20 AE19 AD18 AC17 AF19 AE17 AF21 AD14 AE14

Input AC25

AD26 AB23 AD23 AC21 AF23 AE22 AD21 AC19 AE20 AD19 AF20 AE18 AD17 AF18 AC16 AE13 AD13 AF12 AE12

Function

The bi-directional data signals (D[15:0]) provide a data bus to allow the AAL1gator-32 device to interface to an external micro-processor. Both read and write transactions are supported. The microprocessor interface is used to configure and monitor the AAL1gator-32 device.

Maximum output current (IMAX) = 6 mA

The address signals (A[19:0]) provide an address bus to allow the AAL1gator-32 device to interface to an external micro-processor.

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Pin Name Type Pin

Function

No.

ALE Input AD12 The address latch enable signal (ALE) latches

the A[19:0] signals during the address phase of a bus transaction. When ALE is set high, the address latches are transparent. When ALE is set low, the address latches hold the address provided on A[19:0].

ALE has an internal pull-up resistor.

WRB Input AF11 The write strobe signal (WRB) qualifies write

accesses to the AAL1gator-32 device. When CSB is set low, the D[15:0] bus contents are clocked into the addressed register on the rising edge of WRB.

Note that if CSB, WRB and RDB are all low, all chip outputs are tristated. Therefore WRB and RDB should never be active at the same time during functional operation.

RDB Input AC12 The read strobe signal (RDB) qualifies read

accesses to the AAL1gator-32 device. When CSB is set low, the AAL1gator-32 device drives the D[15:0] bus with the contents of the addressed register on the falling edge of RDB.

Note that if CSB, WRB and RDB are all low, all chip outputs are tristated. Therefore WRB and RDB should never be active at the same time during functional operation.

CSB Input AE11 The chip select signal (CSB) qualifies read/write

accesses to the AAL1gator-32 device. The CSB signal must be set low during read and write accesses. When CSB is set high, the microprocessor interface signals are ignored by the AAL1gator-32 device.

If CSB is not required (register accesses controlled only by WRB and RDB) then CSB should be connected to an inverted version of the RSTB signal.

Note that if CSB, WRB and RDB are all low, all chip outputs are tristated.

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Pin Name Type Pin

No.

ACKB Open-

AD11 The ACKB is an active low signal which Drain Output

INTB Open-

AE10 The interrupt signal (INTB) is an active low Drain Output

Function

indicates when processor read data is valid or when a processor write operation has completed. When inactive this signal is tristated.

ACKB is an open drain output and should be pulled high externally with a fast resistor.

Maximum output current (IMAX) = 6 mA

signal indicating that an enabled bit in the MSTR_INTR_REG register was set. When INTB is set low, the interrupt is active and enabled. When INTB is tristate, there is no interrupt pending or it is disabled.

INTB is an open drain output and should be pulled high externally with a fast resistor.

Maximum output current (IMAX) = 6 mA

10.3 Ram 1 Interface Signals(41)

Pin Name Type Pin

RAM1_D[15]

I/O A7 RAM1_D[14] RAM1_D[13] RAM1_D[12] RAM1_D[11] RAM1_D[10] RAM1_D[9] RAM1_D[8] RAM1_D[7] RAM1_D[6] RAM1_D[5] RAM1_D[4] RAM1_D[3] RAM1_D[2] RAM1_D[1] RAM1_D[0]

No.

B8 C9 D10 B9 C10 A6 A11 B12 A12 D13 C13 B13 B14 C14 D15

Function

The bi-directional data signals (RAM1_D[15:0]) provide a data bus to allow the AAL1gator-32 device to access an external 256Kx16(18) RAM. RAM1 is used for A1SP blocks 0 and 1.

Maximum output current (IMAX) = 6 mA

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Pin Name Type Pin

Function

No.

RAM1_A[17] RAM1_A[16] RAM1_A[15] RAM1_A[14] RAM1_A[13] RAM1_A[12] RAM1_A[11] RAM1_A[10] RAM1_A[9] RAM1_A[8] RAM1_A[7] RAM1_A[6] RAM1_A[5] RAM1_A[4] RAM1_A[3] RAM1_A[2] RAM1_A[1] RAM1_A[0]

Output A18

C17 B18 A19 D17 C18 B19 A20 B20 A17 D19 C20 A22 D20 C21 B22 D21 C22

The address signals (RAM1_A[17:0]) provide an address bus to allow the AAL1gator-32 device to address an external 256Kx16(18) RAM.

Maximum output current (IMAX) = 6 mA

RAM1_OEB Output A8 RAM1 Output Enable is an active low signal that

enables the SRAM to drive data. Maximum output current (IMAX) = 6 mA.

RAM1_WEB[1] Output B16 RAM1 Write Enable One is an active low signal

for the high-byte write. Maximum output current (IMAX) = 6 mA.

RAM1_WEB[0] Output D16 RAM1 Write Enable Zero is an active low signal

for the low-byte write. Maximum output current (IMAX) = 6 mA.

RAM1_CSB Output C19 RAM1 Chip Select is an active low chip-select

signal for external memory. Maximum output current (IMAX) = 6 mA.

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Pin Name Type Pin

Function

No.

RAM1_ADSCB /RAM1_R/WB

Output B21 This signal has different meanings depending

upon the type of SSRAM that the AAL1gator-32 is programmed to interface to.

Pipelined Single-Cycle Deselect SSRAM: RAM1 Address Status Control is an active low output for external memory and is used to cause a new external address to be loaded into the RAM.

Pipelined ZBT SSRAM: RAM1 R/W indicates the direction of the transfer.

Maximum output current (IMAX) = 6 mA.

RAM1_PAR[1] RAM1_PAR[0]

I/O C16

B17

RAM1 Parity is a two bit bi-directional signal that indicates odd parity for the upper and lower byte of RAM1_D[15:0].

Maximum output current (IMAX) = 6 mA

Note: For different modes of the line interface the I/O is redefined. For Direct Low Speed mode there are 16 pairs of bi-directional lines, which can support links up to 2.5 Mbps. For H-MVIP mode there are eight pairs of 8 Mbps bidirectional lines, which are compatible with the H-MVIP specification. For High Speed mode there are two lines, which can support unchannelized data streams up to 45 Mbps. And lastly, there is the SBI mode, which supports one SBI interface. For H-MVIP mode, high speed (HS) mode and SBI mode the upper 8 Direct Low Speed lines become the 2

ram interface. For SBI mode the bottom

8 Direct Low Speed lines become the SBI interface.

Table 1 defines which signal tables need to be used for each possible mode. Select the mode of the line interface that will be used and refer to the tables listed. Table 2 on page 48 shows how pins are shared between the different modes.

Table 1 Line Interface Signal Table Selection

Line Mode Line Interface Table RAM2 Interface Table

Direct Low Speed Direct Low Speed No

H-MVIP H-MVIP Yes (if using upper 4 lines)

SBI SBI Yes

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Line Mode Line Interface Table RAM2 Interface Table

High Speed High Speed Yes (if using 2 lines)

10.4 Line Interface Signals(Direct Low Speed)(132)

Pin Name Type Pin

No.

LINE_MODE[1] LINE_MODE[0]

TL_SYNC[15] TL_SYNC[14] TL_SYNC[13] TL_SYNC[12] TL_SYNC[11] TL_SYNC[10] TL_SYNC[9] TL_SYNC[8] TL_SYNC[7] TL_SYNC[6] TL_SYNC[5] TL_SYNC[4] TL_SYNC[3] TL_SYNC[2] TL_SYNC[1] TL_SYNC[0]

Input B5

AC1

I/O K24

AC15 AC11 AF7 AA1 N3 A5 B10 A4 E4 G4 G1 L4 R3 V1 W3

Function

Determines the mode of operation for the line interface:

00)Direct Low Speed Mode

01)SBI Mode

10) H-MVIP Mode

11) High Speed Mode

Note: In Direct Low Speed Mode, one UDF-HS (51 Mbps) line can be supported. In High Speed Mode, two UDF-HS (51 Mbps) lines can be supported. In SBI Mode, two UDF-HS (DS3) lines can be supported.

Transmit Line Synchronization 15 to 0 are the transmit frame synchronization indicators used in SDF-MF and SDF-FR modes. Depending on the value of MF_SYNC_MODE in the LI_CFG_REG register for the line, these signals either indicate a frame boundary or a multiframe boundary. Depending on the value of GEN_SYNC in the LIN_STR_MODE register for that line, the sync signal is either received from the corresponding framer device 0 to 15 or it is generated internally The Default mode of this signal is to be a frame sync input.

When the MVIP_EN bit is set in LS_Ln_CFG_REG then TL_SYNC[0] is the F0B pin; the common frame sync.

Maximum output current (IMAX) = 6 mA

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Pin Name Type Pin

No.

TL_DATA[15] TL_DATA[14] TL_DATA[13] TL_DATA[12] TL_DATA[11] TL_DATA[10] TL_DATA[9] TL_DATA[8] TL_DATA[7] TL_DATA[6] TL_DATA[5] TL_DATA[4] TL_DATA[3] TL_DATA[2] TL_DATA[1] TL_DATA[0]

TL_SIG[15] TL_SIG[14] TL_SIG[13] TL_SIG[12] TL_SIG[11] TL_SIG[10] TL_SIG[9] TL_SIG[8] TL_SIG[7] TL_SIG[6] TL_SIG[5] TL_SIG[4] TL_SIG[3] TL_SIG[2] TL_SIG[1] TL_SIG[0]

Output J26

AF16 AF9 AD9 P2 M4 C6 A9 B4 E3 G3 K4 K1 T2 W1 AB3

Output L23

AC14 AD10 AE8 N2 L2 D7 D11 C5 D2 F2 J3 L3 R4 V2 AA4

Function

Transmit Line Serial Data 15 to 0 carry the received data to the corresponding framer devices.

Maximum output current (IMAX) = 6 mA

Transmit Line Signal 15 to 0 are the CAS signaling outputs to the corresponding framer devices in SDF-MF mode. This is the default function for this pin.

Maximum output current (IMAX) = 6 mA

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Pin Name Type Pin

No.

TL_CLK[15]/TSM[15] TL_CLK[14]/TSM[14] TL_CLK[13]/TSM[13] TL_CLK[12]/TSM[12] TL_CLK[11]/TSM[11] TL_CLK[10]/TSM[10] TL_CLK[9]/TSM[9] TL_CLK[8]/TSM[8] TL_CLK[7]/TSM[7] TL_CLK[6]/TSM[6] TL_CLK[5]/TSM[5] TL_CLK[4]/TSM[4] TL_CLK[3]/TSM[3] TL_CLK[2]/TSM[2] TL_CLK[1]/TSM[1] TL_CLK[0]/TSM[0]

I/O J25

N25 R25 T26 H26 J24 A15 C15 D6 C1 E1 H2 K2 T1 U3 Y2

Function

Transmit Line Channel Clock 15 to 0 are the clock lines for the sixteen lines. They clock the data from the AAL1gator-32 to the corresponding framer devices.

Depending on the value of the TLCLK_OE pin and the CLK_SOURCE_TX field in the LIN_STR_MODE memory register, these pins are either outputs or inputs. If TLCLK_OUTPUT_EN is high, these pins are outputs and the clock is sourced internally at power up. This can later be changed by the CLK_SOURCE_TX field.

Note that if CLK_SOURCE_TX /= “000” then this pin is an output, even if it is not driving a clock. A clock will only be driven if in E1 or T1 mode and either the internal clock synthesizer is being used or the clock is being looped. CLK_SOURCE_TX = “001”, “010, “011”, “100”, or “101”)

Note that if UDF_HS=1 in the HS_LIN_REG, TL_CLK[7:1] should be tied high.

Transmit Signaling Mirror is a copy of the TL_SIG output. In Direct Low Speed mode, if CLK_SOURCE_TX=”111” then signaling is output on this pin. This option is used with devices that share the same pin for clock and signaling. In this mode CTL_CLK is used as the line clock.

Maximum output current (IMAX) = 6 mA.

CTL_CLK Input C8 Common Transmit Line Clock is a

transmit line clock which can be shared across all lines. Whether this clock is used or not for a given line is dependent on the value of CLK_SOURCE_TX in the LINE_STR_MODE memory register for that line.

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Pin Name Type Pin

No.

RL_SYNC[15] RL_SYNC[14] RL_SYNC[13] RL_SYNC[12] RL_SYNC[11] RL_SYNC[10] RL_SYNC[9] RL_SYNC[8] RL_SYNC[7] RL_SYNC[6] RL_SYNC[5] RL_SYNC[4] RL_SYNC[3] RL_SYNC[2] RL_SYNC[1] RL_SYNC[0]

RL_DATA[15] RL_DATA[14] RL_DATA[13] RL_DATA[12] RL_DATA[11] RL_DATA[10] RL_DATA[9] RL_DATA[8] RL_DATA[7] RL_DATA[6] RL_DATA[5] RL_DATA[4] RL_DATA[3] RL_DATA[2] RL_DATA[1] RL_DATA[0]

Input N24

AE15 AF8 Y4 AB1 M2 C7 B11 C4 E2 G2 K3 R1 U2 W2 AB4

Input AD16

AD15 AE9 AA3 Y3 M1 B6 C11 D3 F3 H3 J1 R2 T4 Y1 AC3

Function

Receive Line Synchronization 15 to 0 are the receive frame synchronization indicators used in SDF-MF and SDF-FR modes. Depending on the value of MF_SYNC_MODE in the LI_CFG_REG register for the line, these signals either indicate a frame boundary or a multiframe boundary.

Tie to ground if unused.

Receive Line Serial Data 15 to 0 carries the receive data from the corresponding framer devices.

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Pin Name Type Pin

No.

RL_SIG[15] RL_SIG[14] RL_SIG[13] RL_SIG[12] RL_SIG[11] RL_SIG[10] RL_SIG[9] RL_SIG[8] RL_SIG[7] RL_SIG[6] RL_SIG[5] RL_SIG[4] RL_SIG[3] RL_SIG[2] RL_SIG[1] RL_SIG[0]

RL_CLK[15] RL_CLK[14] RL_CLK[13] RL_CLK[12] RL_CLK[11] RL_CLK[10] RL_CLK[9] RL_CLK[8] RL_CLK[7] RL_CLK[6] RL_CLK[5] RL_CLK[4] RL_CLK[3] RL_CLK[2] RL_CLK[1] RL_CLK[0]

Input AE16

AF15 AC10 AB2 AA2 M3 D8 D12 A3 F4 H4 H1 P3 U1 U4 AC2

Input N23

P25 R24 R23 K23 H25 B15 A16 D5 D1 F1 J2 L1 T3 V3 AD1

Function

Receive Line Signaling 15 to 0 carries the CAS data from the corresponding framer devices.

Receive Line Clock 15 to 0 is the clock received from the corresponding framer device used to clock in RL_DATA, RL_SIG, and RL_SYNC.

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Pin Name Type Pin

CRL_CLK Input B7 Common Receive Line Clock is a receive

10.5 Line Interface Signals(H-MVIP)(37)

Pin Name Type Pin

No.

LINE_MODE[1] LINE_MODE[0]

Input B5

AC1

Function

No.

line clock which can be shared across all lines. Whether this clock is used or not for a given line is dependent on the value of CLK_SOURCE_RX in the LIN_STR_MODE memory register for that line.

When the MVIP_EN bit is set in LS_Ln_CFG_REG then this is the C4B input; the common 4.096 MHz clock.

Function

Determines the mode of operation for the line interface:

00) Direct Low Speed Mode

01) SBI Mode

10) H-MVIP Mode

11) High Speed Mode

F0B Input W3 Frame Sync 0 is the active low frame

synchronization input signal used to indicate the start of a frame.

TL_DATA[7] TL_DATA[6] TL_DATA[5] TL_DATA[4] TL_DATA[3] TL_DATA[2] TL_DATA[1] TL_DATA[0]

Output B4

E3 G3 K4 K1 T2 W1 AB3

Transmit Line Serial Data 7 to 0 carry the received data to the corresponding framer devices. or an H_MVIP backplane.

Maximum output current (IMAX) = 6 mA

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Pin Name Type Pin

Function

No.

TL_SIG[7] TL_SIG[6] TL_SIG[5] TL_SIG[4] TL_SIG[3] TL_SIG[2] TL_SIG[1] TL_SIG[0]

Output C5

D2 F2 J3 L3 R4 V2 AA4

Transmit Line Signal 7 to 0 are the CAS signaling outputs to the corresponding framer devices in SDF-MF mode. H-MVIP does not support signaling directly, but these signals can be used to transport signaling if needed.

Maximum output current (IMAX) = 6 mA

C16B Input C8 Clock 16 MHz is the clock used to transfer data

across the H-MVIP bus. The clock runs twice as fast as the data rate. This common clock is used in both the receive and transmit direction.

RL_DATA[7] RL_DATA[6] RL_DATA[5] RL_DATA[4] RL_DATA[3] RL_DATA[2] RL_DATA[1] RL_DATA[0]

Input D3

F3 H3 J1 R2 T4 Y1 AC3

Receive Line Serial Data 7 to 0 carries the receive data from the corresponding framer devices or H-MVIP backplane.

RL_SIG[7] RL_SIG[6] RL_SIG[5] RL_SIG[4] RL_SIG[3] RL_SIG[2] RL_SIG[1] RL_SIG[0]

Input A3

F4 H4 H1 P3 U1 U4 AC2

Receive Line Signaling 15 to 0 carries the CAS data from the corresponding framer devices.

H-MVIP does not support signaling directly, but these signals can be used to transport signaling if needed.

C4B Input B7 Clock 4 MHz is the clock used for generating

and sampling F0B. This common clock is used in both the receive and transmit direction.

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10.6 SBI Interface Signals (only used in SBI mode)(64)

Pin Name Type Pin

No.

LINE_MODE[1] LINE_MODE[0]

Input B5

AC1

REFCLK Input C8

Function

Determines the mode of operation for the line interface:

00) Direct Low Speed Mode

01) SBI Mode

10) H-MVIP Mode

11) High Speed Mode

Reference Clock (REFCLK). This signal is an externally generated 19.44MHz +/-50ppm clock with a nominal 50% duty cycle. Since the ADD and DROP busses are locked together this clock is common to both the add and drop sides of the SBI BUS.

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Pin Name Type Pin

No.

TL_CLK[31] TL_CLK[30] TL_CLK[29] TL_CLK[28] TL_CLK[27] TL_CLK[26] TL_CLK[25] TL_CLK[24] TL_CLK[23] TL_CLK[22] TL_CLK[21] TL_CLK[20] TL_CLK[19] TL_CLK[18] TL_CLK[17] TL_CLK[16] TL_CLK[15] TL_CLK[14] TL_CLK[13] TL_CLK[12] TL_CLK[11] TL_CLK[10] TL_CLK[9] TL_CLK[8] TL_CLK[7] TL_CLK[6] TL_CLK[5] TL_CLK[4] TL_CLK[3] TL_CLK[2] TL_CLK[1] TL_CLK[0]

Input N23

P25 R24 R23 K23 H25 B15 A16 D5 D1 F1 J2 R1 U2 W2 AB4 J25 N25 R25 T26 H26 J24 A15 C15 D6 C1 E1 H2 K2 T1 U3 Y2

Function

Transmit Serial Clock input.

When SRTS is used in DS3 mode or a clock with better jitter characteristics is desired the TL_CLK[16] and TL_CLK[0] pins should be used to connect the externally generated transmit line clock.

When generating the TL_CLK with external logic the TL_CLK for all 32 lines can be accessed. These pins should only be used when CLK_SOURCE_TX = “000”.

Note that if CLK_SOURCE_TX is not equal to “000”, TL_CLK[15:0] is an output and must not be driven externally.

Note that if UDF_HS=1 in the A1SP0 HS_LIN_REG, TL_CLK[7:1] should be tied high, and if UDF_HS=1 in the A1SP2 HS_LIN_REG, TL_CLK[23:17] should be tied high.

RL_CLK[2] RL_CLK[0]

Input T3

AD1

When SRTS is used in DS3 mode or a clock with better jitter characteristics is desired the RL_CLK pins should be used to connect the externally recovered receive line clock.

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Pin Name Type Pin

No.

C1FP Input AB3

Function

Active High C1 Frame Pulse (C1FP). This

signal is externally generated to indicate the first C1 octet on the SBI BUS. If TWO_C1FP_EN is low then the ADD and DROP busses are locked together and this signal is common to both the ADD and DROP sides of the SBI BUS. If TWO_C1FP_EN is high, then this signal is the DROP side C1FP.

This frame pulse indicator is a single REFCLK signal long and is updated on the rising edge of REFCLK. This signal is sampled on the rising edge of REFCLK.

This signal also indicates multiframe alignment which occurs every 4 frames, therefore this signal is pulsed once every fourth C1 octet to produce a 2KHz multiframe signal. The frame pulse does not need to be repeated every 2KHz. The AAL1gator-32 will synchronize to this signal and is also be able to flywheel in its absence.

C1FP_ADD Input B4

DDATA[7] DDATA[6] DDATA[5] DDATA[4] DDATA[3] DDATA[2] DDATA[1] DDATA[0]

Input D2

E3 F2 G3 J3 K4 L3 K1

When any tributary on the SBI bus is in synchronous mode the C1FP signal is used to indicate T1 and E1 multiframe alignment and must be pulsed on 48 SBI frame boundaries.

C1 Frame Pulse for Add bus. This pin can optionally be used as the C1FP pulse for the Add bus if the Add bus and Drop bus need to be offset from each other. To use this pin the TWO_C1FP_EN bit must be set in the SBI_BUS_CFG_REG.

Drop Bus Data (DDATA[7:0]). The Drop data bus is a time division multiplexed bus which transports tributaries by assigning them to fixed octets within the SBI BUS structure.

Multiple PHY devices can drive this bus at uniquely assigned tributary columns within the SBI BUS structure.

DDATA[7:0] is sampled on the rising edge of REFCLK.

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Pin Name Type Pin

No.

DDP Input R4

DPL Input V2

Function

Drop Bus Data Parity (DDP). This signal

carries the even or odd parity for the drop bus signals. The parity calculation encompasses DDATA[7:0], DPL and DV5 signals.

The selection of even or odd parity is made via SBI_PAR_CTL bit of Extract Control Register.

Multiple PHY devices can drive this signal at uniquely assigned tributary columns within the SBI BUS structure. This parity signal is intended to detect multiple sources in the column assignment.

DDP is sampled on the rising edge of REFCLK.

Active High Drop Bus Payload (DPL). This active high signal indicates valid data within the SBI BUS structure. This signal is asserted during all octets making up a tributary. This signal goes high during the V3 octet within a tributary to accommodate negative timing adjustments between the tributary rate and the fixed SBI BUS structure. This signal goes low during the octet after the V3 octet within a tributary to accommodate positive timing adjustments between the tributary rate and the fixed SBI BUS structure.

Multiple PHY devices can drive this signal at uniquely assigned tributary columns within the SBI BUS structure.

DPL is sampled on the rising edge of REFCLK.

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Pin Name Type Pin

No.

DV5 Input T2

ADATA[7] ADATA[6] ADATA[5] ADATA[4] ADATA[3] ADATA[2] ADATA[1] ADATA[0]

Output G2

H3 H1 K3 J1 P3 R2 U1

Function

Active High Drop Bus Payload Indicator (DV5). This active high signal locates the

position of the floating payloads for each tributary within the SBI BUS structure. Timing differences between the port timing and the SBI BUS timing are indicated by adjustments of this payload pointer relative to the fixed SBI BUS structure.

Multiple PHY devices can drive this signal at uniquely assigned tributary columns within the SBI BUS structure. All movements indicated by this signal must be accompanied by appropriate adjustments in the DPL signal.

DV5 is sampled on the rising edge of REFCLK.

Add Data (ADATA[7:0]). The Add data bus is a time division multiplexed bus which transports tributaries by assigning them to fixed octets within the SBI BUS structure.

The AAL1gator-32 drives ADATA[7:0] only at uniquely assigned tributary columns within the SBI BUS structure.

ADATA[7:0] is asserted on the rising edge of REFCLK.

Maximum output current (IMAX) = 8 mA

ADP Output T4

Add Bus Data Parity (ADP). This signal carries the even or odd parity for the add bus signals. The parity calculation encompasses ADATA[7:0], APL and AV5 signals.

The selection of even or odd parity is made via SBI_PAR_CTL bit of Insert Control Register

The AAL1gator drives ADP only at uniquely assigned tributary columns within the SBI BUS structure.

ADP is asserted on the rising edge of REFCLK.

Maximum output current (IMAX) = 8 mA

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Pin Name Type Pin

No.

APL Output U4

AV5 Output Y1

Function

Active High Add Bus Payload (APL). This

active high signal indicates valid data within the SBI BUS structure. This active high signal is asserted during all octets making up a tributary. This signal goes high during the V3 or H3 octet within a tributary to accommodate negative timing adjustments between the tributary rate and the fixed SBI BUS structure. This signal goes low during the octet after the V3 or H3 octet within a tributary to accommodate positive timing adjustments between the tributary rate and the fixed SBI BUS structure.

The AAL1gator-32 drives APL only at uniquely assigned tributary columns within the SBI BUS structure.

APL is asserted on the rising edge of REFCLK.

Maximum output current (IMAX) = 8 mA

Active High Add Bus Payload Indicator (AV5). This active high signal locates the

position of the floating payload for each tributary within the add bus structure.

The AAL1gator-32 drives AV5 only at uniquely assigned tributary columns within the SBI BUS structure. All movements indicated by this signal are accompanied by appropriate adjustments in the APL signal.

AV5 is asserted on the rising edge of REFCLK.

Maximum output current (IMAX) = 8 mA

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PM73122 AAL1GATOR-32

Pin Name Type Pin

No.

AJUST_REQ Input W1

Function

Active High Add Bus Justification Request (AJUST_REQ). This signal is used to speed up

or slow down the AAL1gator-32 which is sending data to the PHY. This signal is only used when the PHY layer device is the timing master for the transmit direction.

This active high signal indicates negative timing adjustments when asserted high during the V3 or H3 octet, depending on the tributary type. In response to this the AAL1gator-32 will send an extra byte in the V3 or H3 octet of the next frame.

This signal indicates positive timing adjustments when asserted high during the octet following the V3 or H3 octet, depending on the tributary type. The AAL1gator-32 will respond to this by not sending an octet during the V3 or H3 octet of the next frame.

AACTIVE Output AC3

All timing adjustments from the AAL1gator-32 in response to the justification request will still set the payload and payload indicators appropriately for timing adjustments.

In synchronous T1 and E1 modes this signal is unused and must be held low.

AJUST_REQ is sampled on the rising edge of REFCLK.

Add Bus Active Indicator (AACTIVE). This active high signal is asserted high during all octets when driving data and control signals, ADATA[7:0], ADP, APL and AV5, onto the bus.

All other SBI Link Layer devices (e.g. other AAL1gator-32 on the common SBI bus) driving the bus listen to this signal to detect multiple sources driving the bus which can occur due to configuration problems

AACTIVE is asserted on the rising edge of REFCLK.

Maximum output current (IMAX) = 8 mA

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Pin Name Type Pin

Function

No.

ADETECT Input AA4

Add Bus Active Detector (ADETECT). This input listens to the OR of all other SBI Link Layer bus masters. The AAL1gator-32 will listen to the OR of all other Link Layer AACTIVE signals.

When the AAL1gator-32 is driving AACTIVE high and detects ADETECT is high from another device it backs off driving the bus to minimize or eliminate contention.

ADETECT is an asynchronous signal which is used to disable the tristate drivers on the ADD bus.

This input must be tied low when not used.

10.7 Line Interface Signals(High Speed)(10)

Pin Name Type Pin

Function

No.

LINE_MODE[1] LINE_MODE[0]

TL_DATA[2] TL_DATA[0]

TL_CLK[2] TL_CLK[0]

Input B5

AC1

Output T2

AB3

I/O T1

Determines the mode of operation for the line interface:

00) Direct Low Speed Mode

01) SBI Mode

10) H-MVIP Mode

11) High Speed Mode

Transmit Line Serial Data 2 and 0 carry the received data to the corresponding framer devices.

Maximum output current (IMAX) = 6 mA

Transmit Line Channel Clock 2 and 0 are the clock lines for the two high speed lines. They clock the data from the AAL1gator-32 to the corresponding framer devices.

The clock is always an input in high speed mode.

Maximum output current (IMAX) = 6 mA

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Pin Name Type Pin

Function

No.

RL_DATA[2] RL_DATA[0]

Input T4

AC3

Receive Line Serial Data 2 and 0 carries the receive data from the corresponding framer devices.

RL_CLK[2] RL_CLK[0]

Input T3

AD1

Receive Line Clock 2 and 0 is the clock received from the corresponding framer device used to clock in RL_DATA[2] and RL_DATA[0].

10.8 RAM 2 Interface Signals (only used in H-MVIP, HS, and SBI modes)(41)

Pin Name Type Pin

Function

No.

RAM2_D[15] RAM2_D[14] RAM2_D[13] RAM2_D[12] RAM2_D[11] RAM2_D[10] RAM2_D[9] RAM2_D[8] RAM2_D[7] RAM2_D[6] RAM2_D[5] RAM2_D[4] RAM2_D[3] RAM2_D[2] RAM2_D[1] RAM2_D[0]

I/O AC11

AF9 AD10 AD9 AE8 AF7 AA1 P2 N3 M4 L2 C6 D7 A5 A9 D11

The bi-directional data signals (RAM2_D[15:0]) provide a data bus to allow the AAL1gator-32 device to access an external 256Kx16(18) RAM. RAM2 is used for A1SP blocks 2 and 3.

Maximum output current (IMAX) = 6 mA

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Pin Name Type Pin

Function

No.

RAM2_A[17] RAM2_A[16] RAM2_A[15] RAM2_A[14] RAM2_A[13] RAM2_A[12] RAM2_A[11] RAM2_A[10] RAM2_A[9] RAM2_A[8] RAM2_A[7] RAM2_A[6] RAM2_A[5] RAM2_A[4] RAM2_A[3] RAM2_A[2] RAM2_A[1] RAM2_A[0]

Output AD16

AE16 AD15 AE15 AF15 AE9 AF8 AC10 AB2 AA3 Y4 AB1 AA2 Y3 M1 M2 M3 B6

The address signals (RAM2_A[17:0]) provide an address bus to allow the AAL1gator-32 device to address an external 256Kx16(18) RAM.

Maximum output current (IMAX) = 6 mA

RAM2_OEB Output C7 RAM2 Output Enable is an active low signal that

enables the SSRAM to drive data. Maximum output current (IMAX) = 6 mA.

RAM2_WEB[1] Output D8 RAM2 Write Enable One is an active low signal

for the high-byte write. Maximum output current (IMAX) = 6 mA.

RAM2_WEB[0] Output C11 RAM2 Write Enable Zero is an active low signal

for the low-byte write. Maximum output current (IMAX) = 6 mA.

RAM2_CSB Output B11 RAM2 Chip Select is an active low chip-select

signal for external memory. Maximum output current (IMAX) = 6 mA.

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Pin Name Type Pin

No.

RAM2_ADSCB

Output D12 This signal has different meanings depending RAM2_R/WB

RAM2_PAR[1] RAM2_PAR[0]

I/O N2

B10

10.9 Summary of Line Interface Signals

Function

upon the type of SSRAM that the AAL1gator-32 is programmed to interface to.

Pipelined Single-Cycle Deselect SSRAM: RAM2 Address Status Control is an active low output for external memory and is used to cause a new external address to be loaded into the RAM.

Pipelined ZBT SSRAM: RAM2 R/W indicates the direction of the transfer.

Maximum output current (IMAX) = 6 mA.

RAM2 Parity is a two bit bi-directional signal that indicates odd parity for the upper and lower byte of RAM2_D[15:0].

Maximum output current (IMAX) = 6 mA

The following table shows all modes at the same time and shows how pins are redefined for the different modes.

Table 2 Line Interface Summary

Direct Low

H-MVIP SBI High Speed Pin

Speed

TL_SYNC[15] K24

TL_SYNC[14] AC15

TL_SYNC[13] RAM2_D[15] RAM2_D[15] RAM2_D[15] AC11

TL_SYNC[12] RAM2_D[10] RAM2_D[10] RAM2_D[10] AF7

TL_SYNC[11] RAM2_D[9] RAM2_D[9] RAM2_D[9] AA1

TL_SYNC[10] RAM2_D[7] RAM2_D[7] RAM2_D[7] N3

TL_SYNC[9] RAM2_D[2] RAM2_D[2] RAM2_D[2] A5

TL_SYNC[8] RAM2_P[0] RAM2_P[0] RAM2_P[0] B10

TL_SYNC[7] A4

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Direct Low

H-MVIP SBI High Speed Pin

Speed

TL_SYNC[6] E4

TL_SYNC[5] G4

TL_SYNC[4] G1

TL_SYNC[3] L4

TL_SYNC[2] R3

TL_SYNC[1] V1

TL_SYNC[0] F0B W3

TL_DATA[15] J26

TL_DATA[14] AF16

TL_DATA[13] RAM2_D[14] RAM2_D[14] RAM2_D[14] AF9

TL_DATA[12] RAM2_D[12] RAM2_D[12] RAM2_D[12] AD9

TL_DATA[11] RAM2_D[8] RAM2_D[8] RAM2_D[8] P2

TL_DATA[10] RAM2_D[6] RAM2_D[6] RAM2_D[6] M4

TL_DATA[9] RAM2_D[4] RAM2_D[4] RAM2_D[4] C6

TL_DATA[8] RAM2_D[1] RAM2_D[1] RAM2_D[1] A9

TL_DATA[7] TL_DATA[7] C1FP_ADD B4

TL_DATA[6] TL_DATA[6] DDATA[6] E3

TL_DATA[5] TL_DATA[5] DDATA[4] G3

TL_DATA[4] TL_DATA[4] DDATA[2] K4

TL_DATA[3] TL_DATA[3] DDATA[0] K1

TL_DATA[2] TL_DATA[2] DV5 TL_DATA[2] T2

TL_DATA[1] TL_DATA[1] AJUST_REQ W1

TL_DATA[0] TL_DATA[0] C1FP TL_DATA[0] AB3

TL_SIG[15] L23

TL_SIG[14] AC14

TL_SIG[13] RAM2_D[13] RAM2_D[13] RAM2_D[13] AD10

TL_SIG[12] RAM2_D[11] RAM2_D[11] RAM2_D[11] AE8

TL_SIG[11] RAM2_P[1] RAM2_P[1] RAM2_P[1] N2

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Direct Low

H-MVIP SBI High Speed Pin

Speed

TL_SIG[10] RAM2_D[5] RAM2_D[5] RAM2_D[5] L2

TL_SIG[9] RAM2_D[3] RAM2_D[3] RAM2_D[3] D7

TL_SIG[8] RAM2_D[0] RAM2_D[0] RAM2_D[0] D11

TL_SIG[7] TL_SIG[7] C5

TL_SIG[6] TL_SIG[6] DDATA[7] D2

TL_SIG[5] TL_SIG[5] DDATA[5] F2

TL_SIG[4] TL_SIG[4] DDATA[3] J3

TL_SIG[3] TL_SIG[3] DDATA[1] L3

TL_SIG[2] TL_SIG[2] DDP R4

TL_SIG[1] TL_SIG[1] DPL V2

TL_SIG[0] TL_SIG[0] ADETECT AA4

TL_CLK[15] TL_CLK[15] J25

TL_CLK[14] TL_CLK[14] N25

TL_CLK[13] TL_CLK[13] R25

TL_CLK[12] TL_CLK[12] T26

TL_CLK[11] TL_CLK[11] H26

TL_CLK[10] TL_CLK[10] J24

TL_CLK[9] TL_CLK[9] A15

TL_CLK[8] TL_CLK[8] C15

TL_CLK[7] TL_CLK[7] D6

TL_CLK[6] TL_CLK[6] C1

TL_CLK[5] TL_CLK[5] E1

TL_CLK[4] TL_CLK[4] H2

TL_CLK[3] TL_CLK[3] K2

TL_CLK[2] TL_CLK[2] TL_CLK[2] T1

TL_CLK[1] TL_CLK[1] U3

TL_CLK[0] TL_CLK[0] TL_CLK[0] Y2

CTL_CLK C16B REFCLK C8

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Direct Low

H-MVIP SBI High Speed Pin

Speed

RL_SYNC[15] N24

RL_SYNC[14] RAM2_A[14] RAM2_A[14] RAM2_A[14] AE15

RL_SYNC[13] RAM2_A[11] RAM2_A[11] RAM2_A[11] AF8

RL_SYNC[12] RAM2_A[7] RAM2_A[7] RAM2_A[7] Y4

RL_SYNC[11] RAM2_A[6] RAM2_A[6] RAM2_A[6] AB1

RL_SYNC[10] RAM2_A[2] RAM2_A[2] RAM2_A[2] M2

RL_SYNC[9] RAM2_OEB RAM2_OEB RAM2_OEB C7

RL_SYNC[8] RAM2_CSB RAM2_CSB RAM2_CSB B11

RL_SYNC[7] C4

RL_SYNC[6] E2

RL_SYNC[5] ADATA[7] G2

RL_SYNC[4] ADATA[4] K3

RL_SYNC[3] TL_CLK[19] R1

RL_SYNC[2] TL_CLK[18] U2

RL_SYNC[1] TL_CLK[17] W2

RL_SYNC[0] TL_CLK[16] AB4

RL_DATA[15] RAM2_A[17] RAM2_A[17] RAM2_A[17] AD16

RL_DATA[14] RAM2_A[15] RAM2_A[15] RAM2_A[15] AD15

RL_DATA[13] RAM2_A[12] RAM2_A[12] RAM2_A[12] AE9

RL_DATA[12] RAM2_A[8] RAM2_A[8] RAM2_A[8] AA3

RL_DATA[11] RAM2_A[4] RAM2_A[4] RAM2_A[4] Y3

RL_DATA[10] RAM2_A[3] RAM2_A[3] RAM2_A[3] M1

RL_DATA[9] RAM2_A[0] RAM2_A[0] RAM2_A[0] B6

RL_DATA[8] RAM2_WEB[0] RAM2_WEB[0] RAM2_WEB[0] C11

RL_DATA[7] RL_DATA[7] D3

RL_DATA[6] RL_DATA[6] F3

RL_DATA[5] RL_DATA[5] ADATA[6] H3

RL_DATA[4] RL_DATA[4] ADATA[3] J1

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Direct Low

H-MVIP SBI High Speed Pin

Speed

RL_DATA[3] RL_DATA[3] ADATA[1] R2

RL_DATA[2] RL_DATA[2] ADP RL_DATA[2] T4

RL_DATA[1] RL_DATA[1] AV5 Y1

RL_DATA[0] RL_DATA[0] AACTIVE RL_DATA[0] AC3

RL_SIG[15] RAM2_A[16] RAM2_A[16] RAM2_A[16] AE16

RL_SIG[14] RAM2_A[13] RAM2_A[13] RAM2_A[13] AF15

RL_SIG[13] RAM2_A[10] RAM2_A[10] RAM2_A[10] AC10

RL_SIG[12] RAM2_A[9] RAM2_A[9] RAM2_A[9] AB2

RL_SIG[11] RAM2_A[5] RAM2_A[5] RAM2_A[5] AA2

RL_SIG[10] RAM2_A[1] RAM2_A[1] RAM2_A[1] M3

RL_SIG[9] RAM2_WEB[1] RAM2_WEB[1] RAM2_WEB[1] D8

RL_SIG[8] RAM2_ADSCB RAM2_ADSCB RAM2_ADSCB D12

RL_SIG[7] RL_SIG[7] A3

RL_SIG[6] RL_SIG[6] F4

RL_SIG[5] RL_SIG[5] H4

RL_SIG[4] RL_SIG[4] ADATA[5] H1

RL_SIG[3] RL_SIG[3] ADATA[2] P3

RL_SIG[2] RL_SIG[2] ADATA[0] U1

RL_SIG[1] RL_SIG[1] APL U4

RL_SIG[0] RL_SIG[0] AC2

RL_CLK[15] TL_CLK[31] N23

RL_CLK[14] TL_CLK[30] P25

RL_CLK[13] TL_CLK[29] R24

RL_CLK[12] TL_CLK[28] R23

RL_CLK[11] TL_CLK[27] K23

RL_CLK[10] TL_CLK[26] H25

RL_CLK[9] TL_CLK[25] B15

RL_CLK[8] TL_CLK[24] A16

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Direct Low

H-MVIP SBI High Speed Pin

Speed

RL_CLK[7] TL_CLK[23] D5

RL_CLK[6] TL_CLK[22] D1

RL_CLK[5] TL_CLK[21] F1

RL_CLK[4] TL_CLK[20] J2

RL_CLK[3] L1

RL_CLK[2] RL_CLK[2] RL_CLK[2] T3

RL_CLK[1] V3

RL_CLK[0] RL_CLK[0] RL_CLK[0] AD1

CRL_CLK C4B B7

10.10 Clock Generation Control Interface(18)

Pin Name Type Pin

Function

No.

CGC_DOUT[3] CGC _DOUT[2] CGC _DOUT[1] CGC _DOUT[0]

Output AC8

AF10 AE7 AD8

External Clock Generation Control Data Out Bits 3 to 0 form the SRTS correction code when SRTS_STBH is asserted; otherwise CGC_DOUT[3:0] bits form the channel status and frame difference when ADAP_STBH is asserted.

CGC _LINE[4] CGC _LINE[3] CGC _LINE[2] CGC _LINE[1] CGC _LINE[0]

Output AD5

AC6 AF4 AE5 AD6

CGC Line Bits 4 to 0 form the line CGC_DOUT corresponds to when SRTS_STBH is asserted; otherwise CGC_LINE[4:0] bits form the adaptive state machine index when ADAP_STBH is asserted.

SRTS_STBH Output AF3 SRTS Strobe indicates that an SRTS value is

present on CGC_DOUT[3:0]. CGC_LINE[4:0] indicates the line the SRTS code controls.

ADAP_STBH Output AE4 Adaptive Strobe indicates that the channel

status and byte difference are being played out on the CGC_DOUT[3:0]. The nibbles are identified by the values on CGC_LINE[4:0].

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Pin Name Type Pin

Function

No.

NCLK/ SRTS_DISB

Input AD7 Network Clock is the ATM network-derived

clock used for SRTS. If this signal is tied low, SRTS is disabled. Internally this clock can be divided independently for each A1SP block. This clock should be 2.43 MHz for T1 and E1mode, 38.88 MHz for E3 mode and 77.76 MHz for DS3 mode.

TL_CLK_OE Input AE6 Transmit Line Clock Output Enable controls

whether or not the TL_CLK lines are inputs or outputs between the time of hardware reset and when the CLK_SOURCE_TX bits are read. If high, all TL_CLK pins are outputs. If low, all TL_CLK pins are inputs. There is an internal pull-up resistor, so all TL_CLK pins are outputs if the pin is not connected. The value of this input is overwritten by the CLK_SOURCE_TX bits in the LIN_STR_MODE memory register.

CGC_SER_D Input AC7 External Clock Generation Control Serial Data

is an input used to allow external clock control circuitry to pass frequency information into the internal clock synthesizer.

CGC_VALID Input AF5 External Clock Generation Control Valid signal

10.11 JTAG/TEST Signals(5)

Pin Name Type Pin

TCLK Input D22 The test clock signal provides timing for

TMS Input

Internal Pull-up

is an active high input indicating that the data on CGC_SER_D is valid. This signal must transition from a low to a high at the first valid data on CGC_SER_D and must stay high through the whole clock control word.

Function

No.

test operations tat can be carried out using the JTAG test access port.

A24 The test mode select signal controls the

test operations that can be carried out using the JTAG test access port. Maintain TMS tied high when not using JTAG logic.

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Pin Name Type Pin

Function

No.

TDI Input

Internal

C23 The test data input signal is JTAG serial

input data

Pull-up

TDO Output A23 The test data output signal is JTAG serial

output data.

SCAN_ENB Input

Internal Pull-up

SCAN_MODEB Input

Internal Pull-up

TRSTB Schmitt

Trigger Input

Internal Pull-up

C12 An active low signal which, in SCAN

mode, is used to shift data. This signal should be tied high for normal operation.

AC24 When tied low enable SCAN mode. This

signal should be tied high for normal operation.

AC5 The active low test reset signal is an

asynchronous reset for the JTAG circuitry.

If JTAG logic will be used, one option is to connect TRSTB to the RSTB input, and keep TMS tied high while RSTB is high; this maintains the JTAG logic in reset during normal operation.

10.12 General Signals(3+power/gnd)

Pin Name Type Pin

No.

RSTB Schmitt

AD4 Reset is an active low asynchronous hardware Trigger Input

Internal Pull-up

If JTAG logic will not be used, use the option described above, or simply ground TRSTB.

Function

reset. When RSTB is forced low, all of the AAL1gator’s internal registers are reset to their default states.

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Pin Name Type Pin

Function

No.

SYS_CLK Input B23 System Clock. The maximum frequency is 45

MHz. This clock is used to clock the majority of the logic inside the chip and also determines the speed of the memory interface and the external clock control interface. This clock is also used for clock synthesis. When clock synthesis is enabled this clock must be 38.88 MHz.

VDD3.3

(PPH, PQH)

Power AE2

AE25

B25

Power (VDD3.3). The VDD3.3 pins should be connected to a well decoupled +3.3V DC power supply. These pins power the output ports of

the device. PQH pins are “quiet” power pads. C3 C24 D4 D9 D14 D18 D23 J4 J23 N4 P23 V4 V23 AC4 AC9 AC13 AC18 AC23 AD3 AD24

VDD2.5

(PCH)

Power A10

A21 G23 P4

Power (VDD2.5). The VDD2.5 pins should be

connected to a well decoupled +2.5V DC power

supply. These pins power the core of the

device. L26 AA26 W4 AF6 AF17

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Pin Name Type Pin

No.

VSS

(PPL, PQL, PCL)

Ground A1

A2 A13 A14 A25 A26 B1 B3 B24 B26 C2 C25 N1 N26 P1 P26 AD2 AD25 AE1 AE3 AE24 AE26 AF1 AF2 AF13 AF14 AF25 AF26

Function

Ground (VSS). The VSS pins should be

connected to GND. PPL pins are ground pins

for ports. PQL pins are “quiet” ground pins for

ports. PCL pins are core ground pins. All

grounds should be connected together.

Notes on Pin Description:

• All AAL1gator-32 inputs and bi-directionals present minimum capacitive loading and are 5V tolerant.

• The AAL1gator-32 SBI and UTOPIA/Any-PHY outputs and bi-directional pins have 8 mA drive capability. TDO, the CGC bus outputs and microprocessor bus outputs and bi-directional pins have 4 mA drive capability. Any other outputs and bi-directional pins have 6 mA drive capability.

• All AAL1gator-32 outputs can be tristated under control of the IEEE P1149.1 test access port, even those which do not tristate under normal operation. All outputs and bi-directionals are 5 V tolerant when tristated.

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• All clock inputs (except TL_CLK) are Schmitt triggered. Inputs RPHY_ADD_RSX, RL_DATA[15:0], RL_SIG[15:8], RPHY_ADDR[3:0], TPHY_ADDR[4:0], RL_CLK[15:0], RL_SYNC[15:8,3:1], TL_SYNC[15:8], TL_CLK[15:0], RATM_DATA[15:0], RATM_PAR, RATM_CLK, RATM_SOC, TATM_CLK, D[15:0], RAM1_PAR[1:0], WRB, CSB, RDB, NCLK, CRL_CLK, CTL_CLK, SCAN_ENB, SCAN_MODEB, CGC_SER_D, CGC_VALID, RSTB, ALE, TL_CLK_OE, TMS, TCLK, TDI and TRSTB have internal pull-up resistors.

• Power to the VDD3.3 pins should be applied before power to the VDD2.5 pins is applied. Similarly, power to the VDD2.5 pins should be removed before power to the VDD3.3 pins is removed.

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11 FUNCTIONAL DESCRIPTION

The AAL1gator-32 is divided into the following major blocks, all of which are explained in this section:

• UTOPIA Interface Block (UTOPIAI)

• AAL1 SAR Processing Block (A1SP)

• Processor Interface Block (PROCI)

• RAM Interface Block (RAMI)

• Line Interface Block (LINEI)

• JTAG

11.1 UTOPIA Interface Block (UI)

The UI manages and responds to all control signals on the UTOPIA bus and passes cells to and from the UTOPIA bus and the two Dual A1SP blocks. Both 8-bit and 16-bit UTOPIA interfaces with an optional single parity bit are supported. Each direction can be configured independently and has its own address configuration register.

The following UTOPIA modes are supported.

• UTOPIA Level One Master (8-bit only)

• UTOPIA Level One PHY

• UTOPIA Level Two PHY

• Any-PHY PHY

In the sink direction, the UI uses a 8-cell deep FIFO for buffering cells as they wait to be sent to the Dual A1SP blocks. In addition, each Dual A1SP contains two 8-cell deep FIFOs (one per A1SP) with separate interfaces to allow each A1SP to process data at its own pace. In the source direction, the UI uses a 4cell deep FIFOs for holding cells before they are sent out onto the UTOPIA bus. Also, each Dual A1SP contains two 8-cell deep FIFOs (one per A1SP), again with separate interfaces. The data flow showing the FIFOs is shown in Figure 5.

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Figure 5 Data Flow and Buffering in the UI and Dual A1SP Blocks

DUAL A1SP

TXA1SP 0

(8 cell FIFO)

TXA1SP 1

(8 cell FIFO)

3 Cell FIFO3 Cell FIFO

RXA1SP 0

UTOPIAI

TUFIFO (4 cells)

RUFIFO (8 cells)

3 Cell FIFO

DUAL A1SP

3 Cell FIFO

(8 cell FIFO)

RXA1SP 1

(8 cell FIFO)

TXA1SP 2

(8 cell FIFO)

TXA1SP 3

(8 cell FIFO)

RXA1SP 2

(8 cell FIFO)

RXA1SP 3

(8 cell FIFO)

In UTOPIA Level Two mode, the AAL1gator-32 generally responds on the UTOPIA bus as a single port device. However, it is possible to configure the sink direction as a 4-port device where each A1SP is a different port.

For UTOPIA to UTOPIA loopback, there is a 3-cell FIFO in the UI Block. Lineside to Line-side loopback is done in the A1SP Blocks.

The UI_EN bit in the UI_COMN_CFG register enables both the source side and sink side UTOPIA interface. This bit resets to the disabled state so that the chip resets with all UTOPIA outputs tristated. Once the modes have been configured and the interface enabled, then the outputs will drive to their correct values.

The UI block consists of 7 functions: UI Data Source Interface (SRC_INTF), UI Data Sink Interface(SNK_INTF), 8-cell FIFO (FF8CELL), 4-cell FIFO (FF4CELL), 3-cell FIFO (FF3CELL), UMUX, and UI_REG. See Figure 6 for the block diagram of the AAL1_UI block.

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Figure 6 UI Block Diagram

UTOPIA Interface (UI) Block

UMUX

SRC_INTF

FF4CELL

MUX

Signals to/from

each

1SP

block

TX UTOPIA

TXUTOPIA

SIGNALS

Interface and

FIFO

Output Logic

FF3CELL

SNK_INTF

FF8CELL

RX UTOPIA

RXUTOPIA

SIGNALS

Interface and

FIFO

Input Logic

11.1.1 UTOPIA Source Interface (SRC_INTF)

UI_REG

DEM UX

Prioritization

and FIFO Input

Logic

Signals to/from

each

1SP

block

DEMUX and FIFO

Output Logic

The SRC_INTF block (shown in Figure 6) conveys the cells received from the UMUX block to the UTOPIA interface. Depending on the value of UTOP_MODE field in the UI_SRC_CFG register, the UTOPIA interface will either act as an UTOPIA master (controls the write enable signal) or as an UTOPIA PHY device (controls the cell available signal). As a PHY device, the SRC_INTF can either be a UTOPIA Level One device, where it is the only device on the UTOPIA bus, or a UTOPIA Level Two device where other devices can coexist on the UTOPIA bus. As a master device, the SRC_INTF can only function as a UTOPIA Level One device.

If 16_BIT_MODE is set in the UI_SRC_CFG register then all 16 bits of the UTOPIA data bus are used. 16_BIT_MODE must be ‘0’ in UTOPIA master mode.

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In master mode, the SRC_INTF block sources TATM_D, TATM_PAR, TATM_SOC, and TATM_ENB while receiving TATM_CLAV. The Start-Of-Cell (SOC) indication is generated coincident with the first word (only 8-bit mode is supported) of each cell that is transmitted on TATM_D. TATM_D, TATM_PAR and TATM_SOC are driven at all times. The TATM_ENB signal indicates which clock cycles contain valid data for the UTOPIA bus. The device will not assert the TATM_ENB signal until it has a full cell to send and the target device has activated TATM_CLAV. The TATM_CLAV signal indicates whether the target device is able to accept cells or not. Only cell level handshaking is supported. If the target device is unable to accept any additional cells it must deactivate TATM_CLAV no later than byte 49 of the current cell. No additional cells will be sent until TATM_CLAV is activated.

In PHY mode, the SRC_INTF block sources RPHY_D[15:0], RPHY_PAR, RPHY_SOC, and RPHY_CLAV, while receiving RPHY_ENB. The SOC indication is generated coincident with the first word (8-bit or 16-bit) of each cell that is transmitted on RPHY_D[15:0]. In PHY mode, the RPHY_D[15:0], RPHY_PAR, and RATM_SOC signals are driven only when valid data is being sent; otherwise they are tristated.

In UTOPIA Level 1 PHY mode, RPHY_CLAV is activated whenever a complete cell is available to be sent. It remains active until the last byte has been read of the last available complete cell. A cell is sent one cycle after RPHY_ENB goes low. If RPHY_ENB goes high during the cell transfer, data is not sent each cycle following one where RPHY_ENB is high.

RPHY_ADD[4:0] is an input and is used only in UTOPIA Level Two mode. Any bus cycle following one where RPHY_ADD[4:0] matches CFG_ADDR(4:0) in the UI_SRC_ADD_CFG register, the UI Block will drive RPHY_CLAV. Otherwise RPHY_CLAV is tri-stated. If, in addition, during the previous cycle RPHY_ENB was high and it is low in the current cycle, then the device is selected and the SRC_INTF begins transmitting a cell the next cycle.

Parity is driven on TATM_PAR(RPHY_PAR) whenever TATM_D(RPHY_D[15:0]) is driven. EVEN_PAR will determine whether even parity or odd parity is generated. Since odd parity is required by the ATM Forum, EVEN_PAR is intended to be used for error checking only.

The AAL1gator-32 can tolerate temporary de-assertions of TATM_CLAV/RPHY_ENB), but it is assumed that enough UTOPIA bandwidth is present to accept the cells that the AAL1gator-32 can produce in a timely manner. Once the 4-Cell FIFO fills up in the UI, cells will begin filling up in the 8cell FIFO in each A1SP block. Anytime the UTOPIA FIFO fills up the T_UTOP_FULL interrupt will go active in the MSTR_INTR_REG if it is enabled. This FIFO can fill during normal operation and is not usually an indication of an

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error. However, the A1SP FIFOs should not normally fill. If they do fill it indicates there is some congestion, which is impacting the UTOPIA interface and the TALP_FIFO_FULL bit will go active in A1SPn_INTR_REG. When the TALP FIFO fills, then TALP is no longer able to build cells and data will start building up in the transmit buffer and the frame_advance_fifo will fill. If this continues so that the FR_ADV_FIFO_FULL bit goes active then data has been lost and the transmit queues need to be reset. The T_UTOP_FULL indicator can be used to determine when the UTOPIA Interface clears. It may also be desirable to disable UI_EN so that the stored cells can be flushed.

The SRC_INTF circuit controls when a cell is transmitted from the internal 4 cell FIFO. Since the UTOPIA can transmit cells at higher speeds than the TALP, and since it is expected to see applications in a shared UTOPIA environment, cell transmission from the SRC_INTF commences only when there is a full cell worth of data available to transmit. The cell is then transmitted to the interface at the UTOPIA TATM_CLK rate, in accordance with the TATM_FULLB/RPHY_ENB) input. The maximum supported clock rate is 52 MHz.

11.1.1.1 Any-PHY Mode

If ANY-PHY_EN is set in the UI_SRC_CFG register then the SRC_INTF operates as a single port Any-PHY slave device. In Any-PHY mode the RPHY_ADDR(4) pin becomes the RSX pin and depending on the value of CS_MODE_EN, the RPHY_ADDR(3) pin may become the RCSB signal instead.

In Any-PHY mode in-band addressing is used to allow more than the 32 possible addresses available in UTOPIA mode. One extra word is prepended to the front of each cell that is transmitted. The prepended word indicates the port address sending the cell. The SRC_INTF uses CFG_ADDR(15:0) in the UI_SRC_ADD_CFG register for the address prepend. If 16_BIT_MODE is low then only the lower 8 bits are used.

During the cycle that the prepend address is active on the bus, RSX pulses high.

Because of the large number of possible ports, in the source direction, device addresses are used for polling and device selection, instead of port addresses. (Each device may control many ports) When a device is selected to send a cell, the PHY device prepends the port address in front of the cell. Since, in this direction the AAL1gator-32 is only a single port, the device address and port address are the same. However, the AAL1gator-32 has only a limited number of address pins. To accommodate systems, which are using a mix of different port density Any-PHY devices, the RCSB signal is available to handle any additional external decoding that is required. In Any-PHY mode, PHY devices respond with RPHY_CLAV 2 cycles after their address is on the bus instead of the one cycle

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required in UTOPIA mode. However, the timing of RCSB matches UTOPIA timing so that a full cycle for external decoding is available.

Table 3 shows how the CFG_ADDR field is used in different modes.

Table 3 CFG_ADDR and PHY_ADDR Bit Usage in SRC direction

Polling Selection

MODE PHY_ADDR Pins CFG_ADDR PHY_ADDR Pins CFG_ADDR

UTOPIA-2

[4:0]=device [4:0]=device [4:0]=device [4:0]=device

Single-Addr

Any-PHY

[2:0]=device [2:0]=device [2:0]=device

with CSB

Any-PHY

[3:0]=device [3:0]=device [3:0]=device

without

CSB

Notes:

• In Any-PHY mode, in the SRC direction the AAL1gator-32 will prepend the cell with CFG_ADDR[15:0]. In 8-bit mode the cell will be prepended with CFG_ADDR[7:0]

• In Any-PHY mode, if CS_MODE_EN=’1’ then CFG_ADDR[4:3] = “00”.

• In Any-PHY mode, if CS_MODE_EN=’0’ then CFG_ADDR[4]=”0”.

11.1.2 UTOPIA Sink Interface (SNK_INTF)

[15:0]=device

CFG_ADDR is

prepended

[15:0]=device

CFG_ADDR is

prepended

The SNK_INTF block receives cells from the UTOPIA interface and sends them to the UMUX interface. Depending on the value of the UTOP_MODE field in the UI_SNK_CFG register, the UTOPIA interface acts either as an UTOPIA master (controls the read enable signal) or as an UTOPIA PHY device (controls the cell available signal). As a PHY device the SNK_INTF can either be a UTOPIA Level One device, where it is the only device on the UTOPIA bus, or a UTOPIA Level Two device where other devices can coexist on the UTOPIA bus. As a master device the SNK_INTF can only function as a UTOPIA Level One device.

If 16_BIT_MODE is set in the UI_SNK_CFG register then all 16 bits of the UTOPIA data bus are used. 16_BIT_MODE must be ‘0’ in UTOPIA master mode.

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In master mode, the SNK_INTF block receives RATM_D, RATM_PAR, RATM_SOC, and RATM_CLAV while driving RATM_ENB. Once the UI is enabled in this mode, and, if the RATM_CLAV input signal is asserted, the SNK_INTF block waits for an RATM_SOC signal from the PHY layer. Once the RATM_SOC signal arrives, the cell is accepted as soon as possible. The StartOf-Cell (SOC) indication is received coincident with the first word (only 8-bit mode is supported) of each cell that is received on RATM_D. An 8 cell FIFO allows the interface to accept data at the maximum rate. If the FIFO fills, the RATM_ENB signal will not be asserted again until the device is ready to accept an entire cell. The RATM_ENB signal depends only on the cell space and is independent of the state of the RATM_CLAV signal. The RATM_CLAV signal indicates whether the target device has a cell to send or not. Only cell level handshaking is supported.

In PHY mode, the SNK_INTF block receives TPHY_D[15:0], TPHY_SOC, and TPHY_ENB while driving TPHY_CLAV. The cell available (TPHY_CLAV) signal indicates when the device is ready to receive a complete cell. In UTOPIA Level One mode, TPHY_CLAV is always driven.

In UTOPIA Level Two mode, SNK_INTF normally responds as a single address device. However there may be situations in some systems where groups of cells targetted to a given A1SP may be clumped together. If one of the 8-cell A1SP FIFO fills up so that it backs up into the 8-cell sink UTOPIA FIFO then a head-ofline blocking problem can exist. To alleviate such a situation, the sink direction can be configured as four separate addresses, where the bottom two bits of the address indicate which A1SP is targeted to receive the cell. When polling any of the A1SP addresses, a full indication will be given when the A1SP FIFO associated with that address, reaches a 3/4 full state (room for 2 more cells) or the UI cell sink FIFO already has two cells for that address. This will always allow room for any cells that may still be queued in the sink UTOPIA FIFO and prevent head-of-line blocking. Full indications will be given for a specific port until both full conditions are cleared.

When responding as a single address, TPHY_CLAV is driven the cycle following ones in which TPHY_ADDR(4:0) matches CFG_ADDR(4:0) in UI_SNK_ADD_CFG register. When responding as 4 addresses, TPHY_CLAV is driven the cycle following ones in which TPHY_ADDR(4:2) matches CFG_ADDR(4:2) in UI_SNK_ADD_CFG register. Otherwise TPHY_CLAV is tristated. If, in addition to an address match, during the previous cycle TPHY_ENB was high and it is low in the current cycle, then the device is selected and the SRC_INTF begins accepting the cell that is being received.

The SNK_INTF block waits for an SOC. When an SOC signal arrives, a counter is started, and 53 bytes are received. If a new SOC occurs within a cell, the counter reinitializes. This means that the corrupted cell will be dropped and the

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second good cell will be received. The SNK_INTF block stores the cell in the receive FIFO. If the receive FIFO becomes full, it stops receiving cells. The bytes are written to the FIFO with RATM_CLK. RATM_CLK is an input to the AAL1gator-32. The maximum supported clock rate is 52 MHz.

Parity is always checked and a parity error will cause an interrupt if the UTOP_PAR_ERR_EN bit is set in the MSTR_INTR_EN_REG. FORCE_EVEN_PARITY will determine whether even parity or odd parity is checked. Since odd parity is required by the ATM Forum, FORCE_EVEN_PARITY is intended to be used for error checking only. If an error is detected the UTOP_PAR_ERR bit in the MSTR_INTR_REG is set, and the corresponding enable bit is set in the MSTR_INTR_EN_REG then INTB will go active. Any cell received with bad parity will still be processed as normal.

11.1.2.1 Any-PHY Mode

If ANY-PHY_EN is set in the UI_SNK_CFG register then the SNK_INTF operates as a multi port Any-PHY slave device. In Any-PHY mode the TPHY_ADDR[4] pin becomes the TSX pin and depending on the value of CS_MODE_EN, the TPHY_ADDR(3) pin may become the TCSB signal instead.

In Any-PHY mode in-band addressing is used to allow more than the 32 possible addresses available in UTOPIA mode. One extra word is prepended to the front of each cell that is transmitted. The prepended word indicates the port address to receive the cell. The SNK_INTF uses CFG_ADDR(15:2) in the UI_SNK_ADD_CFG register to match with the address prepend. If 16_BIT_MODE is low then CFG_ADDR(7:2) is used.

During the cycle that the prepend address is active on the bus, the TSX input pulses high.

In the sink direction, port addresses are used for polling and device selection, instead of device addresses. Since, in this direction the AAL1gator-32 has four ports, the AAL1gator-32 will use the upper 14 bits of the UI_SNK_ADD_CFG register for address compares and use the lower two bits to determine which A1SP is being polled or selected. However the AAL1gator-32 has only a limited number of address pins. To accommodate systems, which are using a mix of different port density Any-PHY devices, the TCSB signal is available to handle any additional external decoding that is required. In Any-PHY mode, PHY devices respond with TPHY_CLAV 2 cycles after their address is on the bus instead of the one cycle required in UTOPIA mode. However the timing of TCSB matches UTOPIA timing so that a full cycle for external decoding is available.

Table 4 shows how the CFG_ADDR field is used in different modes.

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Table 4 CFG_ADDR and PHY_ADDR Bit Usage in SNK direction

Polling Selection

MODE PHY_ADDR Pins CFG_ADDR PHY_ADDR Pins CFG_ADDR

UTOPIA-2

Single-Addr

UTOPIA-2

Multi-Addr

Any-PHY

with CSB

Any-PHY

without

CSB

Notes:

• In Any-PHY mode, if CS_MODE_EN=’1’ then CFG_ADDR[4:3] = “00”. Else if CS_MODE_EN=’0’ then CFG_ADDR[4]=”0”.

• In Any-PHY mode the upper 14 bits of the prepended address are compared with CFG_ADDR[15:2]. The bottom two bits are not compared with this field and are just used to select the target A1SP. If in 8-bit mode CFG_ADDR[7:2] is used instead.

[4:0]=device [4:0]=device [4:0]=device [4:0]=device

[4:2]=device

[1:0]=A1SP

[2]=device

[1:0]=A1SP

[4:2]=device [4:2]=device

[1:0]=A1SP

[2]=device [2]=device

[1:0]=A1SP

[4:2]=device

[15:2]=device

addr is

prepended

[3:2]=device

[1:0]=A1SP

[3:2]=device [3:2]=device

[1:0]=A1SP

[15:2]=device

addr is

prepended

11.1.3 UTOPIA Mux Block (UMUX)

The UMUX serves as the bridge between the four A1SP blocks and the SNK_INTF and SRC_INTF blocks.

In the source direction, the UMUX polls each of the four A1SP blocks and the Loopback FIFO using a least recently serviced algorithm to determine cell availability. In this algorithm, once a particular source is serviced, it is put at the lowest priority of all five sources. When a higher priority source is serviced, the lower priority sources below it move up in the priority list. Thus, excluding the initial start up, the source which has been serviced least recently will have the highest priority. Figure 7 below shows an example of the changing priority list as cells are taken from A1SP0 and A1SP2.

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Figure 7 Source Priority Servicing Example

Time 0Time 1Time 2

Priority 1

Priority 2

Priority 3

Priority 4

Priority 5

A1SP0

A1SP1

A1SP2

A1SP3

LOOPB

Initial Order

Priority 1

Priority 2

Priority 3

Priority 4

Priority 5

Order after

A1SP0 has sent

a cell

A1SP1

A1SP2

A1SP3

LOOPB

A1SP0

Priority 1

Priority 2

Priority 3

Priority 4

Priority 5

Order after

A1SP1 does not

have a cell to

send but A1SP2

has sent a cell

A1SP1

A1SP3

LOOPB

A1SP0

A1SP2

When an A1SP is operated in high-speed mode, its companion A1SP within the dual A1SP is left idle. If the remaining two A1SPs are not in high speed mode, it is advantageous to provide the high-speed A1SP with more opportunities to be serviced with a higher priority than the low-speed A1SPs. To support this, the initial value of priority list can be programmed to be different than the default and allow, for example, two entries of the five slots for the high-speed A1SP and no entry for the idle A1SP. Thus, giving the high-speed A1SP 2/5 of the available bandwidth. The initial order is loaded via the UI_Src_Poll_List register When the Utopia interface is not enabled (UI_EN=0 in the UI_COMN_CFG register), the value in the UI_Src_Poll_List register is loaded into the priority table as its initial value. During operation, the initial entries will be transferred among the priority list but the same number of entries for a particular A1SP will continue to exist indefinitely until a reset event occurs.

If the SRC_INTF FIFO has room for a cell, the UMUX polls the current highest priority A1SP block (or Loopback FIFO) to determine if it has a cell. If so, a cell is read from the selected A1SP block and transferred into the SRC_INTF FIFO. If the highest priority source does not have a cell, the next lowest priority A1SP FIFO is examined and the process continues until all sources in the list are polled. Each A1SP block has an 8-cell FIFO.

In the sink direction, the UMUX waits until the SNK_INTF FIFO has a cell to send. Once the SNK_INTF FIFO has a cell to send, the UMUX polls the A1SP associated with the cell for availability. Once the A1SP has room for the cell, the UMUX reads the cell out of the SNK_INTF FIFO and places it in the A1SP FIFO.

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To determine which A1SP to forward a received cell, the UMUX looks at the VPI and VCI bits: (Unless in UTOPIA Level 2, multi-port mode in which case, the bottom two address bits are used.)

1. If SHIFT_VCI bit in the UI_COMN_CFG register is low and VP_MODE_EN is low then VCI(10:9) are used.

2. If SHIFT_VCI bit in the UI_COMN_CFG register is set and VP_MODE_EN is low then VCI(14:13) are used.

3. If VP_MODE_EN is set then VPI(4:3) are used.

Refer to Figure 8 for details of how VPI and VCI are interpreted by UMUX.

Figure 8 Cell Header Interpretation

SHIFT_VCI=0 VP_MODE_EN

1514131211109876543210

Ignored A1SP Data Line Queue MOD 32

SHIFT_VCI=1 VP_MODE_EN=0

1514131211109876543210

Ignored A1SP Data Line Queue MOD 32 Ignored

SHIFT_VCI=X VP_MODE_EN=1

1514131211109876543210

1110987654321 0

Ignored

1110987654321 0

Ignored

1110987654321 0

Ignored A1SP Line

Ignored

The UMUX also supports two forms of UTOPIA to UTOPIA loopback; global loopback, where all cells are looped, and VC based loopback, where only a specific VC is used to loopback cells. In global loopback all cells received by the UTOPIA block are sent back out onto the UTOPIA bus. Global loopback is enabled by setting the U2U_LOOP bit in the UI_COMN_CFG register. In VC based loopback mode, any cell received with a VC that matches the loopback VC is sent back out onto the UTOPIA bus. VC based loopback is enabled by setting the VCI_U2U_LOOP bit in the UI_COMN_CFG register. The loopback

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VC is programmable by writing the U2U_LOOP_VCI register. The 3-cell FIFO is used for loopback.

11.2 AAL1 SAR Processing Block (A1SP)

The A1SP block is the main AAL1 SAR processing block. Each block processes 8 E1/T1 lines. This block is replicated four times to maintain throughput and minimize Cell Delay Variation. This block has the following major components.

• Transmit Frame Transfer Controller (TFTC) block

• Cell Service Decision (CSD) block

• Transmit Adaptation Layer Processor (TALP) block

• TALP FIFO (TFIFO) block

• Local Loopback Block (LOC_LPBK) block

• Receive Frame Transfer Controller (RFTC) block

• Receive Adaptation Layer Processor (RALP) block

• RALP FIFO (RFIFO) block

Figure 9 shows a block diagram of the AAL1gator-32 and the sequence of events used to segment and reassemble the CBR data.

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Figure 9 A1SP Block Diagram

Input from LI

Block

To External

Memory

Output to LI

Block

Transmit Frame

Transfer Controller

(TFTC)

Receive Frame

Transfer Controller

(RFTC)

Cell Service

Decision

(CSD)

Internal RAM

Microprocessor

Control Bus

Transmit Adaptation

Layer Processor

(TALP)

5 6

Local Loopback

Block (LOC_LPBK)

Receive Adaptation

Layer Processor

(RALP)

TALP FIFO Block

RALP FIFO Block

(TFIFO)

(RFIFO)

8910

Output to UI

Block

Input from UI

Block

1. TFTC stores line data into the memory 16 bits at a time.

2. When the TFTC finishes writing a complete frame into the memory, it notifies the CSD of a frame completion by writing the line and frame number into a FIFO. Idle channel detection is processed here if enabled.

3. The CSD checks a frame-based table for queues having sufficient data to generate a cell. For each queue with enough data to generate a cell, the CSD schedules the next cell generation occurrence in the table.

4. The CSD commands the TALP to generate a cell from the available data for each of the ready queues identified in step 3.

5. The TALP generates the cell from the data and signaling buffers and writes the cell into the TALP FIFO.

6. The TFIFO block buffers cells which will be transmitted out to the UTOPIA Interface block.

7. If local loopback is enabled the cell is looped to RALP.

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8. The RFIFO block buffers cells received from the UTOPIA Interface block.

9. The RALP performs pointer searches, checks for overrun and underrun conditions, detects SN mismatches, checks for OAM cells, and extracts the line data from the cells, and places the data into the receive buffer.

10. The RFTC plays the receiver buffer data onto the lines.

Four types of data are supported by the A1SP.

1. UDF-ML (Unstructured Data Format- Multi-Line). Unstructured bit stream for line speeds < 15 Mbps. (supports 8 lines per A1SP) if all are under 2.5 Mbps).

2. UDF-HS (Unstructured Data Format- High Speed). Unstructured bit stream for line speeds under 45 Mbps. (Only one line supported per A1SP).

3. SDF-FR (Structured Data Format- Frame). Channelized data without CAS signaling. (Frame based structure).

4. SDF-MF (Structured Data Format- Multi-Frame). Channelized data with CAS signaling. (Multi-Frame based structure).

11.2.1 AAL1 SAR Transmit Side (TxA1SP)

11.2.1.1 Transmit Frame Transfer Controller (TFTC)

The TFTC accepts deframed data from Line Interface Block. For structured data, the TFTC uses the synchronization supplied by the Line Interface Block to perform a serial-to-parallel conversion on the incoming data and then places this data into a multiframe buffer in the order in which it arrives.

The TFTC monitors the frame sync signals and will realign when an edge is seen on these signals that does not correspond to where it expects it to occur. It is not necessary to provide an edge at the beginning of every frame or multiframe. The AAL1gator-32 reads signaling during the last frame of every multiframe. For T1 mode, the AAL1gator-32 reads signaling on the 24th frame of the multiframe. For E1 mode, the AAL1gator-32 reads signaling on the 16th frame of the multiframe.

A special case of E1 mode exists that permits the use of T1 signaling with E1 framing. Normally an E1 multiframe consists of 16 frames of 32 timeslots, where signaling changes on multiframe boundaries. When E1_WITH_T1_SIG is set in LIN_STR_MODE and the line is in E1 mode, the TFTC will use a multiframe consisting of 24 frames of 32 timeslots. In this mode, the AAL1gator-32 reads signaling on the 24th frame of the multiframe.

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The AAL1gator-32 reads the signaling nibble for each channel when it reads the last nibble of each channel’s data unless the SHIFT_CAS bit in the LIN_STR_MODE register is set. If the SHIFT_CAS bit is set then the AAL1gator32 reads the signaling nibble for each channel when it reads the first nibble of each channel’s data. See Figure 10 for an example of a T1 frame. See Figure 11 for an example of an E1 frame.

Figure 10 Capture of T1 Signaling Bits (SHIFT_CAS=0)

Line Signals During the Last Frame of a Multiframe

RL_S ER

(t imesl o ts

)

0 1 2 21 22 23

...

XX XX

AB CD

Channel 1

XXXX

ABCD

Channel 2

...

AB CD

XXXX XX XX

...

Channel 21

XX XX

Channel 22 Channel 23

ABCD

AB CD

RL_SIG

XXXX - indicates signaling is ignored

XX XX

Channel 0

Figure 11 Capture of E1 Signaling Bits (SHIFT_CAS=0)

Line Signals During the Last Frame of a Multiframe

RL_S ER

(t imesl o ts

)

RL_SIG

XXXX - indicates signaling is ignored

0 1 2 29 30 31

AB CD

Channel 0

XX XX

AB CD

Channel 1

XXXX

ABCD

Channel 2

...

... ...

AB CD

XXXX XX XX

Channel 29

ABCD

XX XX

Channel 30 Channel 31

Note:

• AAL1gator-32 treats all 32 timeslots identically. Although E1 data streams contain 30 timeslots of channel data and 2 timeslots of control (timeslots 0 and 16), data and signaling for all 32 timeslots are stored in memory and can be sent and received in cells.

AB CD

Unstructured data is received without regard to the byte alignment of data within a frame and is placed in the frame buffer in the order in which it arrives. Figure 12 shows the basic components of the TFTC.

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Figure 12 Transmit Frame Transfer Controller

Line

Interface

•

Line 7

Line

Interface

Line 0

Receive Line

Interface

•

Line 7

Receive Line

Interface

ATTN0

DATA0

ATTN7

DATA7

Line Encoder

Line Number

ANY

Channel Pair

Line-to-Memory

Interface

Data

The receive line interface is primarily a serial-to-parallel converter. Serial data, which is derived from the RL_DATA signal from the LI Block, is supplied to a shift register. The shift register clock is the RL_CLK input from the external framer. When the data has been properly shifted in, it is transferred to a 2-byte holding register by an internally derived channel clock. This clock is derived from the line clock and the framing information.

The channel clock also informs the line-to-memory interface that two data bytes are available from the line. When the two bytes are available, a line attention signal is sent to the line encoder block. However, because the channel clock is an asynchronous input to the line-to-memory interface, it is passed through a synchronizer before it is supplied to the line encoder. Since there are eight potential lines and each of them provides its own channel clock, they are synchronized before being submitted to the line encoder.

The TFTC accommodates the T1 Super Frame (SF) mode by treating it like the Extended Super Frame (ESF) format. The TFTC ignores every other frame pulse and captures signaling data only on the last frame of odd SF multiframes. The formatting of data in the signaling buffers is highly dependent on the operating mode. Refer to section 7.6.6 “RESERVED (Transmit Signaling Buffer)” on page 136 for more information on the transmit signaling buffer.

Figure 13 shows the format of the transmit data buffer for ESF-formatted T1 data for lines that are in the SDF-MF mode.

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Figure 13 T1 ESF SDF-MF Format of the T_DATA_BUFFER

Frame Buffer Number

119

127

0 31

DS0s

MF0

MF1

MF2

MF3

Figure 14 shows the format of the transmit data buffer for SF-formatted T1 data for lines that are in the SDF-MF mode.

Figure 14 T1 SF-SDF-MF Format of the T_DATA_BUFFER

Frame Buffer Number

0 11 12 23

32 43 44

0 31

DS0s

MF0

MF1

MF2

MF3

64 75 76

10 7 10 8

11 9

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MF4

MF5

MF6

MF7

PMC PM73122-BI Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

REVISION HISTORY

CONTENTS

LIST OF REGISTERS

LIST OF FIGURES

LIST OF TABLES

1 CHANGES FROM REV. A TO REV. B

2 CHANGES FROM REV B TO REV C