PMC PM6344-RI Datasheet
STANDARD PRODUCT
PMC-Sierra, Inc.
PMC-951013 ISSUE 5 QUADRUPLE E1 FRAMER
PM6344 EQUAD
PM6344
EQUAD
QUADRUPLE E1 FRAMER
ISSUE 5: JUNE 1998
PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000
STANDARD PRODUCT
PMC-Sierra, Inc.
PMC-951013 ISSUE 5 QUADRUPLE E1 FRAMER
PM6344 EQUAD
CONTENTS
1 FEATURES ........................................................................................................................1
2 APPLICATIONS .................................................................................................................4
3 REFERENCES ..................................................................................................................5
4 APPLICATION EXAMPLES ...............................................................................................7
5 BLOCK DIAGRAM.............................................................................................................8
6 PIN DIAGRAM.................................................................................................................11
7 PIN DESCRIPTION .........................................................................................................12
8 FUNCTIONAL DESCRIPTION ........................................................................................29
8.1 DIGITAL RECEIVE INTERFACE (DRIF).............................................................29
8.2 CLOCK AND DATA RECOVERY (CDRC)...........................................................29
8.3 FRAMER (FRMR)...............................................................................................31
8.4 PERFORMANCE MONITOR COUNTERS (PMON)...........................................38
8.5 HDLC RECEIVER (RFDL)..................................................................................38
8.6 ELASTIC STORE (ELST)...................................................................................39
8.7 SIGNALING EXTRACTOR (SIGX) .....................................................................39
8.8 BACKPLANE RECEIVE INTERFACE (BRIF).....................................................40
8.9 TRANSMITTER (TRAN).....................................................................................40
8.10 TRANSMIT PER-CHANNEL SERIAL CONTROLLER (PCSC)..........................41
8.11 HDLC TRANSMITTER (XFDL) ...........................................................................41
8.12 DIGITAL JITTER ATTENUATOR (DJAT).............................................................42
8.13 TIMING OPTIONS (TOPS).................................................................................46
8.14 DIGITAL E1 TRANSMIT INTERFACE (DTIF) .....................................................46
8.15 BACKPLANE TRANSMIT INTERFACE (BTIF)...................................................47
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STANDARD PRODUCT
PMC-Sierra, Inc.
PMC-951013 ISSUE 5 QUADRUPLE E1 FRAMER
PM6344 EQUAD
8.16 MICROPROCESSOR INTERFACE (MPIF)........................................................47
9 REGISTER DESCRIPTION.............................................................................................48
10 NORMAL MODE REGISTER DESCRIPTION.................................................................52
10.1 SIGX INDIRECT REGISTERS 96 (60H) - 127 (7FH) - SEGMENT 4: TYPICAL
PER-TIMESLOT CONFIGURATION AND SIGNALING TRUNK ......................156
10.2 REGISTERS 049-04FH, 0C9H-0CFH, 149H-14FH, 1C9H-1CFH: LATCHING
PERFORMANCE DATA.....................................................................................168
11 TEST FEATURES DESCRIPTION ................................................................................176
11.1 TEST MODE 0..................................................................................................176
12 FUNCTIONAL TIMING...................................................................................................180
12.1 RECEIVE BACKPLANE INTERFACE...............................................................182
13 OPERATION ..................................................................................................................191
13.1 USING THE INTERNAL FDL TRANSMITTER .................................................192
13.2 USING THE INTERNAL FDL RECEIVER.........................................................194
13.3 USING THE LOOPBACK MODES....................................................................201
13.3.1 PAYLOAD LOOPBACK........................................................................202
13.3.2 LINE LOOPBACK................................................................................203
13.3.3 DIAGNOSTIC DIGITAL LOOPBACK...................................................203
13.4 USING THE PER-CHANNEL SERIAL CONTROLLERS..................................204
13.4.1 INITIALIZATION...................................................................................204
13.4.2 DIRECT ACCESS MODE....................................................................205
13.4.3 INDIRECT ACCESS MODE ................................................................205
13.5 USING THE DIGITAL JITTER ATTENUATOR..................................................206
13.5.1 DEFAULT APPLICATION .....................................................................206
13.5.2 DATA BURST APPLICATION...............................................................206
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STANDARD PRODUCT
PMC-Sierra, Inc.
PMC-951013 ISSUE 5 QUADRUPLE E1 FRAMER
PM6344 EQUAD
13.5.3 ELASTIC STORE APPLICATION ........................................................207
13.5.4 ALTERNATE TCLKO REFERENCE APPLICATION.............................207
13.5.5 CHANGING THE JITTER TRANSFER FUNCTION ............................208
13.5.6 RECEIVER JITTER ATTENUATION....................................................208
13.6 USING THE PERFORMANCE MONITOR COUNTER VALUES......................210
13.7 RESET PROCEDURE......................................................................................212
14 ABSOLUTE MAXIMUM RATINGS.................................................................................216
15 CAPACITANCE...............................................................................................................217
16 D.C. CHARACTERISTICS.............................................................................................218
17 MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS...............................220
18 EQUAD I/O TIMING CHARACTERISTICS ....................................................................225
19 ORDERING AND THERMAL INFORMATION...............................................................239
20 MECHANICAL INFORMATION......................................................................................240
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STANDARD PRODUCT
PMC-Sierra, Inc.
PMC-951013 ISSUE 5 QUADRUPLE E1 FRAMER
PM6344 EQUAD
LIST OF REGISTERS
REGISTER 000H, 080H, 100H, 180H: RECEIVE OPTIONS.......................................................53
REGISTER 001H, 081H, 101H, 181H: RECEIVE BACKPLANE OPTIONS.................................56
REGISTER 002H, 082H, 102H, 182H: DATALINK OPTIONS.......................................................60
REGISTER 003H, 083H, 103H, 183H: RECEIVE INTERFACE CONFIGURATION.....................63
REGISTER 004H, 084H, 104H, 184H: TRANSMIT INTERFACE CONFIGURATION ..................65
REGISTER 005H, 085H, 105H, 185H: TRANSMIT BACKPLANE OPTIONS...............................68
REGISTER 006H, 086H, 106H, 186H: TRANSMIT FRAMING OPTIONS ...................................70
REGISTER 007H, 087H, 107H, 187H: TRANSMIT TIMING OPTIONS........................................72
REGISTER 008H, 088H, 108H, 188H: INTERRUPT SOURCE....................................................77
REGISTER 009H, 089H, 109H, 189H: RECEIVE TS0 DATA LINK ENABLES .............................78
REGISTER 00AH, 08AH, 10AH, 18AH: MASTER DIAGNOSTICS..............................................80
REGISTER 00BH, 20BH: EQUAD MASTER TEST......................................................................82
REGISTER 00CH: EQUAD REVISION/CHIP ID/GLOBAL PMON UPDATE ................................84
REGISTER 00DH, 08DH, 10DH, 18DH: FRAMER RESET..........................................................85
REGISTER 00EH, 08EH, 10EH, 18EH: PHASE STATUS WORD (LSB)......................................86
REGISTER 00FH, 08FH, 10FH, 18FH: PHASE STATUS WORD (MSB)......................................88
REGISTER 010H, 090H, 110H, 190H: CDRC CONFIGURATION...............................................89
REGISTER 011H, 091H, 111H, 191H: CDRC INTERRUPT ENABLE .........................................91
REGISTER 012H, 092H, 112H, 192H: CDRC INTERRUPT STATUS ..........................................92
REGISTER 013H, 093H, 113H, 193H: CDRC ALTERNATE LOSS OF SIGNAL STATUS............94
REGISTERS 014H, 094H, 114H AND 194H: CHANNEL SELECT (0 TO 7)................................95
REGISTERS 015H, 095H, 115H AND 195H: CHANNEL SELECT (8 TO 15)..............................96
REGISTERS 016H, 096H, 116H AND 196H: CHANNEL SELECT (16 TO 23)............................97
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STANDARD PRODUCT
PMC-Sierra, Inc.
PMC-951013 ISSUE 5 QUADRUPLE E1 FRAMER
PM6344 EQUAD
REGISTERS 017H, 097H, 117H AND 197H: CHANNEL SELECT (24 TO 31)............................98
REGISTER 018H, 098H, 118H, 198H: DJAT INTERRUPT STATUS ............................................99
REGISTER 019H, 099H, 119H, 199H: DJAT REFERENCE CLOCK DIVISOR (N1) CONTROL100
REGISTER 01AH, 09AH, 11AH, 19AH: DJAT OUTPUT CLOCK DIVISOR (N2) CONTROL.....101
REGISTER 01BH, 09BH, 11BH, 19BH: DJAT CONFIGURATION..............................................102
REGISTER 01CH, 09CH, 11CH, 19CH: ELST CONFIGURATION............................................104
REGISTER 01DH, 09DH, 11DH, 19DH: ELST INTERRUPT STATUS .......................................105
REGISTER 01EH, 09EH, 11EH, 19EH: ELST IDLE CODE.......................................................106
REGISTER 020H, 0A0H, 120H, 1A0H: FRMR FRAME ALIGNMENT OPTIONS......................107
REGISTER 021H, 0A1H, 121H, 1A1H: FRMR MAINTENANCE MODE OPTIONS...................109
REGISTER 022H, 0A2H, 122H, 1A2H: FRMR FRAMING STATUS INTERRUPT ENABLE.......111
REGISTER 023H, 0A3H, 123H, 1A3H: FRMR MAINTENANCE/ALARM STATUS INTERRUPT
ENABLE.........................................................................................................................112
REGISTER 024H, 0A4H, 124H, 1A4H: FRMR FRAMING STATUS INTERRUPT INDICATION.113
REGISTER 025H, 0A5H, 125H, 1A5H: FRMR MAINTENANCE/ALARM STATUS INTERRUPT
INDICATION...................................................................................................................114
REGISTER 026H, 0A6H, 126H, 1A6H: FRMR FRAMING STATUS ...........................................115
REGISTER 027H, 0A7H, 127H, 1A7H: FRMR MAINTENANCE/ALARM STATUS ....................117
REGISTER 028H, 0A8H, 128H, 1A8H: FRMR INTERNATIONAL/NATIONAL BITS ..................119
REGISTER 029H, 0A9H, 129H, 1A9H: FRMR EXTRA BITS.....................................................120
REGISTER 02AH, 0AAH, 12AH, 1AAH: FRMR CRC ERROR COUNTER - LSB......................121
REGISTER 02BH, 0ABH, 12BH, 1ABH: FRMR CRC ERROR COUNTER - MSB.....................122
REGISTER 02CH, 0ACH, 12CH, 1ACH: TS16 AIS ALARM STATUS.........................................123
REGISTER 030H, 0B0H, 130H, 1B0H: TPSC BLOCK CONFIGURATION................................124
REGISTER 031H, 0B1H, 131H, 1B1H: TPSC BLOCK µP ACCESS STATUS............................125
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STANDARD PRODUCT
PMC-Sierra, Inc.
PMC-951013 ISSUE 5 QUADRUPLE E1 FRAMER
PM6344 EQUAD
REGISTER 032H, 0B2H, 132H, 1B2H: TPSC BLOCK TIMESLOT INDIRECT
ADDRESS/CONTROL...................................................................................................126
REGISTER 033H, 0B3H, 133H, 1B3H: TPSC BLOCK TIMESLOT INDIRECT DATA BUFFER..127
TPSC INTERNAL REGISTERS 20-3FH: DATA CONTROL BYTE..............................................129
TPSC INTERNAL REGISTERS 40-5FH: IDLE CODE BYTE.....................................................131
REGISTER 034H, 0B4H, 134H, 1B4H: XFDL BLOCK CONFIGURATION ................................132
REGISTER 035H, 0B5H, 135H, 1B5H: XFDL INTERRUPT STATUS.........................................134
REGISTER 036H, 0B6H, 136H, 1B6H: XFDL TRANSMIT DATA................................................135
REGISTER 038H, 0B8H, 138H, 1B8H: RFDL CONFIGURATION .............................................136
REGISTER 039H, 0B9H, 139H, 1B9H: RFDL INTERRUPT CONTROL/STATUS......................137
REGISTER 03AH, 0BAH, 13AH, 1BAH: RFDL STATUS ............................................................139
REGISTER 03BH, 0BBH, 13BH, 1BBH: RFDL RECEIVE DATA ................................................142
REGISTERS 03CH, 0BCH, 13CH AND 1BCH: INTERRUPT ID/CLOCK MONITOR.................143
REGISTERS 03DH, 0BDH, 13DH AND 1BDH: BACKPLANE PARITY CONFIGURATION AND
STATUS..........................................................................................................................145
REGISTER 040H, 0C0H, 140H, 1C0H: SIGX BLOCK CONFIGURATION.................................147
REGISTER 041H, 0C1H, 141H, 1C1H: SIGX BLOCK µP ACCESS STATUS ............................149
REGISTER 042H, 0C2H, 142H, 1C2H: SIGX BLOCK TIME SLOT INDIRECT
ADDRESS/CONTROL...................................................................................................150
REGISTER 043H, 0C3H, 143H, 1C3H: SIGX BLOCK TIME SLOT INDIRECT DATA BUFFER.151
SIGX INDIRECT REGISTERS 33 (21H)- 47 (2FH) - SEGMENT 2: TYPICAL TIMESLOT
SIGNALING DATA REGISTER (TSS 1-15)....................................................................153
SIGX INDIRECT REGISTERS 49 (31H)- 63 (3FH) - SEGMENT 2: TYPICAL TIMESLOT
SIGNALING DATA REGISTER (TSS 17-31)..................................................................154
SIGX INDIRECT REGISTERS 64 (40H) - 95 (5FH) - SEGMENT 3: TYPICAL PER-TIMESLOT
PCM TRUNK CONDITIONING DATA REGISTER .........................................................155
CONDITIONING DATA REGISTER.............................................................................................156
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STANDARD PRODUCT
PMC-Sierra, Inc.
PMC-951013 ISSUE 5 QUADRUPLE E1 FRAMER
PM6344 EQUAD
REGISTER 044H, 0C4H, 144H, 1C4H: TRAN CONFIGURATION.............................................158
REGISTER 045H, 0C5H, 145H, 1C5H: TRAN TRANSMIT ALARM/DIAGNOSTIC CONTROL.162
REGISTER 046H, 0C6H, 146H, 1C6H: TRAN INTERNATIONAL/NATIONAL CONTROL.........164
REGISTER 047H, 0C7H, 147H, 1C7H: TRAN EXTRA BITS CONTROL...................................166
REGISTER 048H, 0C8H, 148H, 1C8H: PMON CONTROL/STATUS..........................................167
REGISTER 049H, 0C9H, 149H, 1C9H: FRAMING BIT ERROR COUNT..................................169
REGISTER 04AH, 0CAH, 14AH, 1CAH: FAR END BLOCK ERROR COUNT LSB ...................170
REGISTER 04BH, 0CBH, 14BH, 1CBH: FAR END BLOCK ERROR COUNT MSB ..................171
REGISTER 04CH, 0CCH, 14CH, 1CCH: CRC ERROR COUNT LSB .......................................172
REGISTER 04DH, 0CDH, 14DH, 1CDH: CRC ERROR COUNT MSB ......................................173
REGISTER 04EH, 0CEH, 14EH, 1CEH: LINE CODE VIOLATION COUNT LSB.......................174
REGISTER 04FH, 0CFH, 14FH, 1CFH: LINE CODE VIOLATION COUNT MSB.......................175
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STANDARD PRODUCT
PMC-Sierra, Inc.
PMC-951013 ISSUE 5 QUADRUPLE E1 FRAMER
PM6344 EQUAD
LIST OF FIGURES
FIGURE 1 - EXAMPLE 1. DS-3 TERMINAL MULTIPLEXER/CHANNEL BANK........................7
FIGURE 2 - CDRC JITTER TOLERANCE WITH ALGSEL = 1................................................30
FIGURE 3 - CDRC JITTER TOLERANCE WITH ALGSEL = 0................................................31
FIGURE 4 - BASIC FRAMING ALGORITHM FLOWCHART...................................................34
FIGURE 5 - DJAT JITTER TOLERANCE.................................................................................44
FIGURE 6 - DJAT MINIMUM JITTER TOLERANCE VS. XCLK ACCURACY..........................45
FIGURE 7 - DJAT JITTER TRANSFER...................................................................................46
FIGURE 8 - TRANSMIT TIMING OPTIONS............................................................................76
FIGURE 9 - TS16 RECEIVE DATALINK INTERFACE............................................................180
FIGURE 10 - TS0 RECEIVE DATALINK INTERFACE..............................................................180
FIGURE 11 - TS16 TRANSMIT DATALINK INTERFACE.........................................................181
FIGURE 12 - TS0 TRANSMIT DATALINK INTERFACE...........................................................181
FIGURE 13 - ROHM=0, BRX2RAIL=0, BRXSMFP=0 AND BRXCMFP=0..............................182
FIGURE 14 - RECEIVE COMPOSITE MULTIFRAME OUTPUT (BRXSMFP=1 AND
BRXCMFP=1) ......................................................................................................183
FIGURE 15 - RECEIVE OVERHEAD OUTPUT (ROHM=1)....................................................183
FIGURE 16 - ELSTBYP=1, SRSMFP=1, SRCMFP=1, BRXSMFP=1, BRXCMFP=0 .............184
FIGURE 17 - RECEIVE CHANNEL INTERFACE....................................................................184
FIGURE 18 - TRANSMIT BACKPLANE INTERFACE .............................................................185
FIGURE 19 - TRANSMIT CHANNEL INTERFACE..................................................................185
FIGURE 20 - MULTIPLEXED RECEIVE BACKPLANE INTERFACE......................................186
FIGURE 21 - MULTIPLEXED TRANSMIT BACKPLANE INTERFACE....................................188
FIGURE 22 - MULTIPLEXED TRANSMIT BACKPLANE INTERFACE WITH BTXMFP=1......190
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STANDARD PRODUCT
PMC-Sierra, Inc.
PMC-951013 ISSUE 5 QUADRUPLE E1 FRAMER
PM6344 EQUAD
FIGURE 23 - TYPICAL DATA FRAME.....................................................................................197
FIGURE 24 - RFDL NORMAL DATA AND ABORT SEQUENCE.............................................198
FIGURE 25 - RFDL FIFO OVERRUN......................................................................................199
FIGURE 26 - XFDL NORMAL DATA SEQUENCE...................................................................200
FIGURE 27 - XFDL UNDERRUN SEQUENCE.......................................................................201
FIGURE 28 - PAYLOAD LOOPBACK ......................................................................................202
FIGURE 29 - LINE LOOPBACK..............................................................................................203
FIGURE 30 - DIAGNOSTIC DIGITAL LOOPBACK .................................................................204
FIGURE 31 - RECEIVE BACKPLANE INTERFACE WITH RCLKOSEL = 1............................209
FIGURE 32 - LCV COUNT VS. BER........................................................................................211
FIGURE 33 - FER COUNT VS. BER .......................................................................................211
FIGURE 34 - CRCE COUNT VS. BER ....................................................................................212
FIGURE 35 - MICROPROCESSOR READ ACCESS TIMING................................................221
FIGURE 36 - MICROPROCESSOR WRITE ACCESS TIMING...............................................223
FIGURE 37 - BACKPLANE TRANSMIT INPUT TIMING DIAGRAM .......................................225
FIGURE 38 - BACKPLANE TRANSMIT INPUT TIMING DIAGRAM .......................................226
FIGURE 39 - XCLK=37.056 MHZ INPUT TIMING ..................................................................227
FIGURE 40 - TCLKI INPUT TIMING........................................................................................228
FIGURE 41 - DIGITAL RECEIVE INTERFACE INPUT TIMING DIAGRAM.............................229
FIGURE 42 - TRANSMIT DATA LINK INPUT TIMING DIAGRAM...........................................230
FIGURE 43 - BACKPLANE RECEIVE TIMING DIAGRAM......................................................231
FIGURE 44 - BACKPLANE RECEIVE TIMING (RCLKOSEL = 1) DIAGRAM.........................232
FIGURE 45 - MULTIPLEXED BACKPLANE RECEIVE TIMING DIAGRAM............................233
FIGURE 46 - RECEIVE DATA LINK OUTPUT TIMING DIAGRAM..........................................234
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STANDARD PRODUCT
PMC-Sierra, Inc.
PMC-951013 ISSUE 5 QUADRUPLE E1 FRAMER
PM6344 EQUAD
FIGURE 47 - RECOVERED FRAME OUTPUT TIMING DIAGRAM........................................234
FIGURE 48 - TRANSMIT INTERFACE OUTPUT TIMING DIAGRAM.....................................235
FIGURE 49 - TRANSMIT DATA LINK DMA INTERFACE OUTPUT TIMING DIAGRAM .........236
FIGURE 50 - RECEIVE DATA LINK DMA INTERFACE OUTPUT TIMING DIAGRAM............237
FIGURE 51 - 128 PIN COPPER LEADFRAME PLASTIC QUAD FLAT PACK (R SUFFIX) ....240
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STANDARD PRODUCT
PMC-Sierra, Inc.
PMC-951013 ISSUE 5 QUADRUPLE E1 FRAMER
PM6344 EQUAD
LIST OF TABLES
TABLE 1 - NORMAL MODE REGISTER MEMORY MAP.....................................................48
TABLE 2 -..............................................................................................................................74
TABLE 3 -..............................................................................................................................87
TABLE 4 -............................................................................................................................177
TABLE 5 -............................................................................................................................177
TABLE 6 - CONFIGURING THE EQUAD FROM RESET...................................................191
TABLE 7 -............................................................................................................................210
TABLE 8 - EQUAD CAPACITANCE.....................................................................................217
TABLE 9 - EQUAD D.C. CHARACTERISTICS....................................................................218
TABLE 10 - MICROPROCESSOR READ ACCESS (FIGURE 35).......................................220
TABLE 11 - MICROPROCESSOR WRITE ACCESS (FIGURE 36)......................................222
TABLE 12 - BACKPLANE TRANSMIT INPUT TIMING, MENB INPUT HIGH (FIGURE 37).225
TABLE 13 - BACKPLANE TRANSMIT INPUT TIMING, MENB INPUT LOW (FIGURE 37)..226
TABLE 14 - XCLK=49.152 MHZ INPUT (FIGURE 39)..........................................................227
TABLE 15 - TCLKI INPUT (FIGURE 40................................................................................227
TABLE 16 - DIGITAL RECEIVE INTERFACE INPUT TIMING (FIGURE 41) ........................228
TABLE 17 - TRANSMIT DATA LINK INPUT TIMING (FIGURE 42).......................................230
TABLE 18 - BACKPLANE RECEIVE TIMING, MENB INPUT HIGH (FIGURE 43)...............231
TABLE 19 - BACKPLANE RECEIVE TIMING, MENB INPUT HIGH, RCLKOSEL = 1 (FIGURE
44)........................................................................................................................232
TABLE 20 - MULTIPLEXED BACKPLANE RECEIVE TIMING, MENB INPUT LOW (FIGURE
45)........................................................................................................................233
TABLE 21 - RECEIVE DATA LINK OUTPUT TIMING (FIGURE 46).....................................234
TABLE 22 - RECOVERED FRAME PULSE OUTPUT TIMING (FIGURE 47).......................234
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STANDARD PRODUCT
PMC-Sierra, Inc.
PMC-951013 ISSUE 5 QUADRUPLE E1 FRAMER
PM6344 EQUAD
TABLE 23 - TRANSMIT INTERFACE OUTPUT TIMING (FIGURE 48) ................................235
TABLE 24 - TRANSMIT DATA LINK DMA INTERFACE OUTPUT TIMING (FIGURE 49).....236
TABLE 25 - RECEIVE DATA LINK DMA INTERFACE OUTPUT TIMING (FIGURE 50) .......237
TABLE 26 - EQUAD ORDERING INFORMATION................................................................239
TABLE 27 - EQUAD THERMAL INFORMATION...................................................................239
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STANDARD PRODUCT
PMC-Sierra, Inc.
PMC-951013 ISSUE 5 QUADRUPLE E1 FRAMER
PM6344 EQUAD
1
FEATURES
Integrates four full-featured E1 framers and transmitters in a single device for
•
terminating duplex E1 signals.
Software and functionally compatible with the PM6341 E1XC Single E1
•
Transceiver.
Pin compatible with the PM4344 Quad T1 Framer device.
•
Provides an 8-bit microprocessor bus interface for configuration, control, and
•
status monitoring.
Low power CMOS technology
•
Available in a 128 pin PQFP package.
•
Each one of four receiver sections:
Recovers clock and data using a digital phase locked loop for high jitter
•
tolerance. A direct clock input is provided to allow clock recovery to be bypassed.
Accepts dual rail or single rail digital PCM inputs.
•
Supports HDB3 or AMI line code.
•
Accepts gapped data streams to support higher rate demultiplexing.
•
Frames to a G.704 2048 kbit/s signal within 1 ms.
•
Frames to the signaling multiframe alignment when enabled.
•
Frames to the CRC multiframe alignment when enabled.
•
Provides loss of signal detection, and indicates loss of frame alignment
•
(OOF), loss of signaling multiframe alignment and loss of CRC multiframe
alignment.
Supports line and path performance monitoring according to ITU-T
•
recommendations. Accumulators are provided for counting:
CRC-4 errors to 1000 per second;
•
1
STANDARD PRODUCT
PMC-Sierra, Inc.
PMC-951013 ISSUE 5 QUADRUPLE E1 FRAMER
PM6344 EQUAD
Far end block errors to 1000 per second;
Frame sync errors to 127 per second; and
Line code violations to 8191 per second.
• Indicates the reception of remote alarm and remote multiframe alarm.
• Indicates the reception of alarm indication signal (AIS) and time slot 16 AIS.
• Declares RED and AIS alarms using Q.516 recommended integration
periods.
• Provides an HDLC/LAPD interface for terminating a data link. Supports
polled, interrupt-driven, or DMA servicing of the HDLC interface.
• Optionally extracts the data link from timeslot 16 (64 kbit/s), which may be
used to receive common channel signaling, or from any combination of the
national bits in timeslot 0 of non-frame alignment signal frames (4 kbit/s - 20
kbit/s).
• Supports fractional E1 channel extraction.
• Provides a two-frame elastic store buffer for jitter and wander attenuation that
performs controlled slips and indicates slip occurrence and direction.
• Provides channel associated signaling extraction, with optional data inversion,
programmable idle code substitution, and up to 3 multiframes of signaling
debounce on a per-timeslot basis.
• Provides trunk conditioning which fo rces programmable trouble code
substitution and signaling conditioning on all timeslots or on selected
timeslots.
• Optionally provides dual rail digital PCM output signals to allow BPV
transparency. Also supports unframed mode.
• Supports transfer of PCM and signaling data to 2.048 Mbit/s or 16.384Mbit/s
backplane buses.
• Can be configured to attenuate jitter on the receive side by placing the digital
jitter attenuator in the receive path.
2
STANDARD PRODUCT
PMC-Sierra, Inc.
PMC-951013 ISSUE 5 QUADRUPLE E1 FRAMER
PM6344 EQUAD
Each one of four transmitter sections:
Formats data to create a G.704 2048 kbit/s signal. Optionally inserts
•
signaling multiframe alignment signal. Optionally inserts CRC multiframe
structure including optional transmission of far end block errors.
Optionally accepts dual rail digital PCM inputs to allow BPV transparency.
•
Also supports unframed mode and framing bit, CRC, or data link by-pass.
Supports transfer of PCM and signaling data from 2.048 Mbit/s or
•
16.384Mbit/s backplane buses.
Provides channel associated signaling insertion, programmable idle code
•
substitution, digital milliwatt code substitution, and data inversion on a per
timeslot basis.
Provides trunk conditioning which fo rces programmable trouble code
•
substitution and signaling conditioning on all timeslots or on selected
timeslots.
Supports transmission of the alarm indication signal (AIS), timeslot 16 AIS,
•
remote alarm signal or remote multiframe alarm signal.
Provides an HDLC/LAPD interface for generating a data link. Supports
•
polled, interrupt-driven, or DMA servicing of the HDLC interface.
Optionally inserts the data link into timeslot 16 (64 kbit/s), which may be used
•
to transmit common channel signaling, or into any combination of the national
bits in timeslot 0 of non-frame alignment signal frames (4 kbit/s - 20 kbit/s).
Supports fractional E1 channel insertion.
•
Provides a digital phase locked loop for generation of a low jitter transmit
•
clock.
Provides a FIFO buffer for jitter attenuation and rate conversion in the
•
transmitter. FIFO full or empty indication allows for bit-stuffing in higher rate
multiplexing applications.
Supports HDB3 or AMI line code.
•
Provides dual rail or single rail digital PCM output signals.
•
3
STANDARD PRODUCT
PMC-Sierra, Inc.
PMC-951013 ISSUE 5 QUADRUPLE E1 FRAMER
PM6344 EQUAD
2
APPLICATIONS
E1 Channel Service Units (CSU) and Data Service Units (DSU)
•
E1 Channel Banks and Multiplexers
•
Digital Private Branch Exchanges (PBX)
•
Digital Access and Cross-Connect Systems (DACS) and Electronic DSX
•
Cross-Connect Systems (EDSX)
E1 Frame Relay Interfaces
•
E1 ATM Interfaces
•
ISDN Primary Rate Interfaces (PRI)
•
SDH Byte Synchronous TU12 Mappers
•
Test Equipment
•
4
STANDARD PRODUCT
PMC-Sierra, Inc.
PMC-951013 ISSUE 5 QUADRUPLE E1 FRAMER
PM6344 EQUAD
3
REFERENCES
1. ITU-T Recommendation G.704, - "Synchronous Frame Structures Used at
Primary and Secondary Hierarchical Levels", Vol. III, Fascicle III.4, 1988.
2. ITU-T Recommendation G.706, - "Frame Alignment and Cyclic Redundancy
Check (CRC) Procedures Relating to Basic Frame Structures Defined in
Recommendation G.704", Vol. III, Fascicle III.4 , 1988.
3. ITU-T Recommendation G.706, - "Frame Alignment and Cyclic Redundancy
Check (CRC) Procedures Relating to Basic Frame Structures Defined in
Recommendation G.704", 1991
4. ITU-T Recommendation G.711, - "Pulse Code Modulation (PCM) of Voice
Frequencies", Volume III, Fascicle III.3, 1988.
5. ITU-T Recommendation G.732, - "Characteristics of Primary PCM Multiplex
Equipment Operating at 2048 kbit/s", Vol. III, Fascicle III.4, 1988.
6. ITU-T Recommendation G.735, - "Characteristics of Primary PCM Multiplex
Equipment Operating at 2048 kbit/s and Offering Synchronous Digital Access
at 384 kbit/s and/or 64 kbit/s", Vol. III, Fascicle III.4, 1988.
7. ITU-T Recommendation G.821, - "Error Performance of an International
Digital Connection Forming Part of an Integrated Services Digital Network",
Vol. III, Fascicle III.5, 1988.
8. ITU-T Recommendation G.823, - "The Control of Jitter and Wander Within
Digital Networks Which are Based on the 2048 kbit/s Hierarchy", Vol. III,
Fascicle III.5, 1988.
9. ITU-T Recommendation O.151, - "Error Performance Measuring Equipment
For Digital Systems at the Primary Bit Rate and Above", Vol. IV, Fascicle IV.4,
1988.
10. ITU-T Blue Book, Recommendation O.162, - "Equipment to Perform in
Service Monitoring on 2048 kbit/s Signals", Vol. IV, Fascicle IV.4, 1988.
11. ITU-T Recommendation Q.506, - "Operations and maintenance functions",
Vol. VI, Fascicle VI.5, 1984.
12. ITU-T Recommendation Q.516, - "Operations and maintenance functions",
Vol. VI, Fascicle VI.5, 1984.
5
STANDARD PRODUCT
PMC-Sierra, Inc.
PMC-951013 ISSUE 5 QUADRUPLE E1 FRAMER
PM6344 EQUAD
13. Transmission and Multiplexing (TM); Generic Functional Requirements for
SDH Transmission Equipment, Part 1: Generic Processes and Performance",
ETSI DE/TM-1015, November, 1993, Version 1.0.
6
STANDARD PRODUCT
PMC-Sierra, Inc.
PMC-951013 ISSUE 5 QUADRUPLE E1 FRAMER
PM6344 EQUAD
4
DSX-3
APPLICATION EXAMPLES
Figure 1 - Example 1. DS-3 Terminal Multiplexer/Channel Bank
PM6344
EQUAD
PM6344
EQUAD
PM6344
EQUAD
PM6344
EQUAD
PM6344
EQUAD
PM6341
E1XC
Synchronous
DS0
Backplane
DS3
LIU
PM8313
D3MX
4 E1s
4 E1s
4 E1s
4 E1s
4 E1s
1 E1
Services
Example 1 shows a DS-3 Terminal Multiplexer/Channel Bank using 5 EQUAD
devices, PMC-Sierra's PM8313 D3MX M13 Multiplexer, the PM6341 E1XC E1
Transceiver, and Silicon System's SSI 78P236 DS-3 Line Interface Unit.
21 E1 signals can be multiplexed into a DSX-3 formatted signal. Five EQUAD
devices and a single E1XC device are used to terminate these 21 signals. The
DS-0 backplane data is transmitted and received using a 2.048 MHz system
clock.
7
STANDARD PRODUCT
PMC-Sierra, Inc.
PMC-951013 ISSUE 5 QUADRUPLE E1 FRAMER
PM6344 EQUAD
5
BLOCK DIAGRAM
TCLKI[1:4]
BTPCM/BTDP[1:4]/
BTSIG/BTDN[1:4]
BTFP[1:4]/MTFP*
BTCLK[1:4]/
MTCLK*
BRCLK*/MRCLK*
BRFPI*/MRFPI*
MENB*
XCLK/VCLK*
RCLKI[1:4]
RDP/RDD[1:4]
RDN/RLCV[1:4]
MTD*
BTIF
Backplane
Transmit
Interface
DRIF
DS-1
Receive
Interface
Internal
Bus
TRAN
BasicTransmitter:
Frame Generation,
Alarm Insertion,
Trunk Conditioning
Line Coding
PCSC
Per-channel
Controller:
Signalling,
Idle Insert
CDRC
Clock and
Data
Recovery
XFDL
HDLC
Transmitter
PMON
Performance
Monitor
Counters
FRMR
Framer:
Frame
Alignment,
Alarm
Detection
TOPS
Timing Options
DJAT
Digital Jitter
Attenuator
ELST
Elastic
Store
Digital Jitter
Attenuator
Optional placement
DJAT
Signalling
Extractor,
Condition
TRANSMITTER
DTIF
Digital
Transmit
Interface
RECEIVER
SIGX
Trunk
BRIF
Backplane
Receive
Interface
TCLKO[1:4]
TDP/TDD[1:4]
TDN/TFLG[1:4]
TDLCLK/
TDLUDR[1:4]
TDLSIG/
TDLINT[1:4]
BRPCM/BRDP[1:4]
BRSIG/BRDN[1:4]
BRFPO[1:4]
MRD*
RCLKO[1:4]
RFP[1:4]
A[9:0]*
RDB*
WRB*
CSB*
ALE*
INTB*
RSTB*
D[7:0]*
MPIF
Micro-
Processor
Interface
RFDL
HDLC
Receiver
* These signals are shared between all four framers.
Optional connections are shown with dashed lines.
8
RDLSIG/
RDLINT[1:4]
RDLCLK/
RDLEOM[1:4]
STANDARD PRODUCT
PMC-Sierra, Inc.
PMC-951013 ISSUE 5 QUADRUPLE E1 FRAMER
PM6344 EQUAD
Description
The PM6344 Quadruple E1 Framer (EQUAD) is a feature-rich device suitable for
use in many E1 systems with a minimum of external circuitry. Each of the
framers and transmitters is independently software configurable, allowing feature
selection without changes to external wiring.
On the receive side, the EQUAD recovers clock and data and can be configured
to frame to a basic G.704 2048 kbit/s signal or also frame to the signaling
multiframe alignment signal and the CRC multiframe alignment signal.
The EQUAD also supports detection of various alarm conditions such as loss of
signal, loss of frame, loss of signaling multiframe, loss of CRC multiframe, and
reception of remote alarm signal, remote multiframe alarm signal, alarm
indication signal, and timeslot 16 alarm indication signal. The EQUAD detects
and indicates the presence of remote alarm and AIS patterns and also integrates
red and AIS alarms as per industry specifications.
Performance monitoring with accumulation of CRC-4 errors, far end block errors,
framing bit errors, and line code violation is provided. The EQUAD also detects
and terminates HDLC messages on a data link. The data link may be extracted
from timeslot 16 and used for common channel signaling or may be extracted
from the national bits.
An elastic store for slip buffering and adaptation to backplane timing is provided,
as is a signaling extractor that supports signaling debounce, signaling freezing,
idle code substitution, digital milliwatt tone substitution, data inversion, and
signaling bit fixing on a per-channel basis. Receive side data and signaling trunk
conditioning is also provided.
On the transmit side, the EQUAD generates framing for a basic G.704 2048
kbit/s signal, or framing can be optionally disabled. The signaling multiframe
alignment structure may be optionally inserted and the CRC multiframe structure
may be optionally inserted.
Channel associated signaling insertion, idle code substitution, digital milliwatt
tone substitution, and data inversion on a per-timeslot basis is also supported.
Transmit side data and signaling trunk conditioning is provided.
HDLC messages on a data link can be transmitted. The data link may be
inserted into timeslot 16 and used for common channel signaling or may be
inserted into the national bits. The EQUAD can generate a low jitter transmit
clock and provides a FIFO for transmit jitter attenuation. When not used for jitter
9
STANDARD PRODUCT
PMC-Sierra, Inc.
PMC-951013 ISSUE 5 QUADRUPLE E1 FRAMER
PM6344 EQUAD
attenuation, the full or empty status of this FIFO is made available to facilitate
higher order multiplexing applications by controlling bit-stuffing logic.
The EQUAD provides a parallel microprocessor interface for controlling the
operation of the EQUAD device. Serial PCM interfaces allow 2.048 Mbit/s
backplanes to be directly supported. Tolerance of gapped clocks allows other
backplane rates to be supported with a minimum of external logic. Optional bit
interleaved multiplexing of the individual serial streams supports 16.384 Mbit/s
backplanes.
10
STANDARD PRODUCT
PMC-Sierra, Inc.
PM6344 EQUAD
PMC-951013 ISSUE 5 QUADRUPLE E1 FRAMER
6
PIN DIAGRAM
The EQUAD is packaged in a 128-pin plastic QFP package having a body size of
14 mm by 20 mm and a pin pitch of 0.5 mm.
PHA[3]
BRPCM[1]/BRDP[1]
PLA[3]
BRPCM[2]/BRDP[2]
BRPCM[3]/BRDP[3]
BRPCM[4]/BRDP[4]
TDLCLK[1]/TDLUDR[1]
PIN 103
PIN 102
BRSIG[4]/BRDN[4]
BRSIG[3]/BRDN[3]
BRSIG[2]/BRDN[2]
BRSIG[1]/BRDN[1]
BRFPO[4]
BRFPO[3]
BRFPO[2]
BRFPO[1]
BRCLK/MRCLK
BRFPI/MRFPI
RCLKO[4]
RCLKO[3]
PLA[2]
PHA[2]
RCLKO[2]
RCLKO[1]
PLD[2]
PHD[2]
RFP[4]
RFP[3]
RFP[2]
RFP[1]
TCLKI[4]
TCLKI[3]
TCLKI[2]
TCLKI[1]
BTCLK[4]
BTCLK[3]
BTCLK[2]
BTCLK[1]/MTCLK
BTFP[4]
BTFP[3]
BTFP[2]
BTFP[1]/MTFP
BTSIG[4]/BTDN[4]
BTSIG[3]/BTDN[3]
BTSIG[2]/BTDN[2]
BTSIG[1]/BTDN[1]
PIN 65
PIN 1
PLA[5]
RDP[1]/RDD[1]
RDN[1]/RLCV[1]
RCLKI[1]
RDP[2]/RDD[2]
RDN[2]/RLCV[2]
RCLKI[2]
RDP[3]/RDD[3]
RDN[3]/RLCV[3]
RCLKI[3]
RDP[4]/RDD[4]
RDN[4]/RLCV[4]
RCLKI[4]
TCLKO[1]
TDP[1]/TDD[1]
TDN[1]/TFLG[1]
TCLKO[2]
PHA[0]
PLA[0]
PHD[0]
PLD[0]
TDP[2]/TDD[2]
TDN[2]/TFLG[2]
TCLKO[3]
TDP[3]/TDD[3]
TDN[3]/TFLG[3]
TCLKO[4]
TDP[4]/TDD[4]
TDN[4]/TFLG[4]
A[0]
A[1]
A[2]
A[3]
A[4]
A[5]
A[6]
A[7]
A[8]
PIN 38
PIN 128
PHA[4]
RDLCLK[3]/RDLEOM[3]
RDLCLK[4]/RDLEOM[4]
RDLSIG[1]/RDLINT[1]
PLA[4]
RDLSIG[2]/RDLINT[2]
RDLSIG[3]/RDLINT[3]
RDLSIG[4]/RDLINT[4]
Index Pin
RDLCLK[2]/RDLEOM[2]
PLD[3]
TDLCLK[4]/TDLUDR[4]
PHD[3]
TDLSIG[1]/TDLINT[1]
TDLSIG[2]TDLINT[2]
TDLSIG[3]/TDLINT[3]
TDLSIG[4]/TDLINT[4]
RDLCLK[1]/RDLEOM[1]
PM6344
EQUAD
Top
View
TDLCLK[2]/TDLUDR[2]
TDLCLK[3]/TDLUDR[3]
A[9]
RSTB
ALE
WRB
RDB
CSB
D[0]
MENB
D[1]
D[2]
D[3]
PLD[1]
PHD[1]
PHA[1]
PLA[1]
D[4]
D[5]
BTPCM[1]/BTDP[1]/MTD
XCLK/VCLK
D[7]
BTPCM[4]/BTDP[4]
BTPCM[3]/BTDP[3]
BTPCM[2]/BTDP[2]
MRD
INTB
D[6]
PIN 39 PIN 64
11
STANDARD PRODUCT
PMC-Sierra, Inc.
PMC-951013 ISSUE 5 QUADRUPLE E1 FRAMER
PM6344 EQUAD
7
PIN DESCRIPTION
Pin Name Type Pin No. Function
MENB Input 45
RDP[1]
RDP[2]
RDP[3]
RDP[4] /
Input 2
5
8
11
Multiplex Enable (MENB). When this input is asserted
low, the four sets of PCM and signaling streams are
combined into a single bit interleaved 16.384 Mbit/s
serial stream. In the transmit direction, all data is
expected on MTD with alignment indicated by MTFP.
MTD and MTFP are sampled on the rising edge of
MTCLK. In the receive direction, data is presented on
MRD aligned with MRFPI. MRFPI is sampled on the
rising edge of MRCLK and MRD is updated on t h e
falling edge of MRCLK.
When this input is deasser ted high, each PCM and
signaling stream has its own dedicated pin.
MENB has an integral pull-up.
Receive Positive Line Pulse (RDP[4:1]). These inputs
are available when the EQUAD is configured to receive
dual-rail formatted data. The RDP[4:1] inputs may be
enabled for either RZ or NRZ waveforms. When
enabled for NRZ, this input may be enabled to be
sampled on the rising or falling edge of the
corresponding RCLKI[4:1]. When enabled for RZ, the
clocks are recovered from the corresponding RDP[4:1]
and RDN[4:1] inputs.
RDD[1]
RDD[2]
RDD[3]
RDD[4]
Receive Digital E1 Signal (RDD[4:1]). W hen the
EQUAD is configured to receive single-rail data, these
inputs may be enabled to be sampled on the rising or
falling edge of the corresponding RCLKI[4:1].
12
STANDARD PRODUCT
PMC-Sierra, Inc.
PMC-951013 ISSUE 5 QUADRUPLE E1 FRAMER
PM6344 EQUAD
Pin Name Type Pin No. Function
RDN[1]
RDN[2]
RDN[3]
RDN[4] /
RLCV[1]
RLCV[2]
RLCV[3]
RLCV[4]
RCLKI[1]
RCLKI[2]
RCLKI[3]
RCLKI[4]
RCLKO[1]
RCLKO[2]
RCLKO[3]
RCLKO[4]
Input 3
6
9
12
Input 4
7
10
13
Output 87
88
91
92
Receive Digital Negative Line Pulse (RDN[4:1]). These
inputs are available when the EQUAD is configur ed to
receive dual-rail formatted data. The RDN[4:1] inputs
may be enabled for either RZ or NRZ waveforms. When
enabled for NRZ, these inputs may be enabled to be
sampled on the rising or falling edge of the
corresponding RCLKI[4:1]. When enabled for RZ, the
clocks are recovered from the corresponding RDP[4:1]
and RDN[4:1] inputs.
Receive Line Code Violation Indication (RLCV[4:1]).
When the EQUAD is configured to receive single-rail
data, this input may be enabled to be sampled on the
rising or falling edge of the corresponding RCLKI[4:1].
Receive Line Clock Inputs (RCLKI[4:1]). Each input is
an externally recovered 2.048 MHz line clock that may
be enabled to sample the RDP[x] and RDN[x] inputs on
its rising or falling edge when the input format is
enabled for dual-rail NRZ; or to sample the RDD[x] and
RLCV[x] inputs on its r ising or falling edge when the
input format is enabled for single-rail.
Recovered PCM Clock Output (RCLKO[4:1]). Each
output signal is the recovered 2.048 MHz clock,
synchronized to the XCLK signal. Each RCLKO[x]
signal is recovered from the RDP[x] and RDN[x] inputs
(if the input format is dual-rail RZ) or from the RCLKI[x ]
input (if the input format is NRZ).
When the ELST is by-passed or the RCLKOSEL
register bit is set, BRPCM[x] and BRSIG[x] are updated
on the falling edge of the associated RCLKO[x].
As an option, the digital attenuator's smooth 2.048 MHz
clock may be presented on RCLKO [ x ] . See the
Operations Section for details on this application.
13
STANDARD PRODUCT
PMC-Sierra, Inc.
PMC-951013 ISSUE 5 QUADRUPLE E1 FRAMER
PM6344 EQUAD
Pin Name Type Pin No. Function
RFP[1]
RFP[2]
RFP[3]
RFP[4]
Output 81
82
83
84
Receive Frame Pulse ( RFP[ 4:1]). The RFP[x] out puts
are intended as a timing references.
When the EQUAD is configured for receive frame pulse
output, RFP[x] pulses high for 1 RCLKO cycle during bit
1 of each 256-bit frame, indicating the frame alignment
of the receive stream.
When configured for receive signaling multiframe
output, RFP[x] pulses high for 1 RCLKO[x] cycle during
bit 1 of frame 1 of the 16 frame signaling mult if rame,
indicating the signaling multiframe alignment of t he
receive stream. (Even when signaling multiframing is
disabled, the RFP[x] output continues to indicate the
position of bit 1 of every 16th frame.)
When configured for receive CRC multiframe output,
RFP[x] pulses high for 1 RCLKO[x] cycle during bit 1 of
frame 1 of every 16 frame CRC multiframe, indicating
the CRC multiframe alignment of t he r e ceive stream.
(Even when CRC multiframing is disabled, the RFP[x]
output continues to indicate the position of bit 1 of the
FAS f ram e every 16th frame.)
When configured for composite multiframe output,
RFP[x] goes high on the falling RCLKO[x] edge marking
the beginning of bit 1 of frame 1 of every 16 frame
signaling multiframe, indicating the signaling multiframe
alignment of the receive stream, and returns low on the
falling RCLKO[x] edge marking the ending of bit 1 of
frame 1 of every 16 frame CRC multiframe, indicating
the CRC multiframe alignment of t he r e ceive stream.
This mode allows both multiframe alignments to be
decoded externally from the single RFP[x] signal. Note
that if the signaling and CRC multiframe alignm ents are
coincident, RFP[x] will pulse high for 1 RCLKO[x] cycle
every 16 frames.
Each RFP[x] is updated on the falling edge of the
associated RCLKO[x]. RFP[x] should not be used when
register bit RCLKOSEL is set to a logic 1.
14
STANDARD PRODUCT
PMC-Sierra, Inc.
PMC-951013 ISSUE 5 QUADRUPLE E1 FRAMER
PM6344 EQUAD
Pin Name Type Pin No. Function
RDLSIG[1]
RDLSIG[2]
RDLSIG[3]
RDLSIG[4]/
RDLINT[1]
RDLINT[2]
RDLINT[3]
RDLINT[4]
RDLCLK[1]
RDLCLK[2]
RDLCLK[3]
RDLCLK[4]/
Output 125
126
127
128
Output 119
120
123
124
Receive Data Link Signal (RDLSIG[4:1]). The
RDLSIG[4:1] signals are available on these outputs
when the associated inter nal HDLC receiver (RFDL) is
disabled from use, or, optionally, when fractional E1 is
extracted. RDLSIG contains the data link stream
extracted from the selected data link bits. The EQUAD
may be configured to utilize timeslot 16 as a data link or
utilize any combination of the national bits as a data link.
Each RDLSIG[x] is updated on the falling edge of the
associated RDLCLK[x].
Receive Data Link Interrupt (RDLINT[ 4: 1]). The
RDLINT[4:1] signals are available on these outputs
when the associated RFDL is enabled. Each RDLINT[x]
goes high when an event occurs which changes the
status of the associated HDLC receiver.
Receive Data Link Clock (RDLCLK[4:1]). The
RDLCLK[4:1] signals are available on these outputs
when the associated inter nal HDLC receiver (RFDL) is
disabled from use, or, optionally, when fractional E1 is
extracted. The rising edge of RDLCLK[x] can be used
to sample the data-link data or the fract ional E1 dat a on
the associated RDLSIG[x] when the internal HDLC
receiver is disabled or when fractional E1 is enabled
respectively.
RDLEOM[1]
RDLEOM[2]
RDLEOM[3]
RDLEOM[4]
Receive Data Link End of Message (RDLEOM[4:1]).
The RDLEOM[4:1] signals are available on these
outputs when the associated RFDL is enabled. Each
RDLEOM[x] goes high when the last byte of a received
sequence is read from the associated RFDL FIFO
buffer, or when the FIFO buffer is overrun.
15
STANDARD PRODUCT
PMC-Sierra, Inc.
PMC-951013 ISSUE 5 QUADRUPLE E1 FRAMER
PM6344 EQUAD
Pin Name Type Pin No. Function
BRPCM[1]
BRPCM[2]
BRPCM[3]
BRPCM[4]/
Output 103
104
107
108
BRDP[1]
BRDP[2]
BRDP[3]
BRDP[4]
MRD Output 59
Backplane Receive PCM (BRPCM[4:1]). The
BRPCM[4:1] signals are available on these outputs
when the backplane is configured for single-rail output.
Each BRPCM[x] signal contains the recovered data
stream passed through the ELST block, and the SIGX
block. When the ELST is not by-passed or the
RCLKOSEL register bit is not set, the BRPCM[x] stream
is aligned to the backplane timing and is updated on the
falling edge of the associated BRCLK. When the ELST
is by-passed or the RCLKOSEL register bit is set,
BRPCM[x] is aligned to the receive line timing and is
updated on the falling edge of the associated RCLKO[x].
Backplane Receive Positive Line Pulse (BRDP[4:1]).
The BRDP[4:1] signals are available on these outputs
when the backplane is configured for dual-rail output.
Each BRDP[x] NRZ output represents the RZ r eceive
digital positive pulse signal extracted from the input
bipolar signal. BRDP[x] is updated on the falling edge of
the associated RCLKO[x].
Multiplexed Receive Data (MRD). When the multiplex
enable (MENB) input is asserted low, the four sets of
PCM and signaling streams are bit interleaved into a
single 16.384 Mbit/s serial st r eam presented on MRD
aligned with MRFPI. MRFPI is sampled on the rising
edge of MRCLK and MRD is updated on the falling edge
of MRCLK.
When MENB input is deasserted high, each PCM and
signaling stream has its own dedicated pin and MRD is
unused.
16
STANDARD PRODUCT
PMC-Sierra, Inc.
PMC-951013 ISSUE 5 QUADRUPLE E1 FRAMER
PM6344 EQUAD
Pin Name Type Pin No. Function
BRSIG[1]
BRSIG[2]
BRSIG[3]
BRSIG[4]
BRDN[1]
BRDN[2]
BRDN[3]
BRDN[4]
Output 99
100
101
102
Backplane Receive Signaling (BRSIG[4:1]). The
BRSIG[4:1] signals are available on these outputs when
the backplane is configured for single-rail output. Each
BRSIG[x] contains the extracted signaling bits for each
channel in the frame, repeated for the entire
superframe. Each channel's signaling bits are valid in
bit locations 5,6,7,8 of the channel and are channelaligned with the BRPCM[x] data stream. When the
ELST is not by-passed or the RCLKOSEL register bit is
not set, the BRSIG[x] stream is aligned to the backplane
timing and is updated on the falling edge of BRCLK.
When the ELST is by-passed or the RCLKOSEL
register bit is set, BRSIG[x] is aligned to the receive line
timing and is updated on the falling edge of the
associated RCLKO[x].
Backplane Receive Negative Line Pulse (BRDN[4:1]).
The BRDN[4:1] signals are available on these outputs
when the backplane is configured for dual-rail output.
Each BRDN[x] NRZ output represents the RZ receive
digital negative pulse signal extracted from the input
bipolar signal. BRDN[x] is updated on the falling edge
of the associated RCLKO[x].
17
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