PMC PM5390 Datasheet
Advance
S/UNI®-9953
10 Gbit/s Physical Layer Device for POS, ATM and Ethernet
PM5390
GENERAL DESCRIPTION
• The S/UNI-9953 is a single chip ATM,
POS and 10 Gigabit Ethernet UserNetwork Interface operating at 995 3.28
Mbit/s and 10.3 Gbit/s. The S/UNI
9953 is intended for use in OC-192c
and high-density OC-48c PO S/ATM
applications as well as 10 Gigabit
Ethernet WAN and LAN PHY port
cards.
FEATURES
• Provides WAN Interface Sub-layer
(WIS), Physical Coding Sub-layer
(PCS), and Media Access Controller
(MAC) functionality for OC-192c rate
10 Gigabit E thernet WAN PHY
datastream.
• Provides PCS and MAC layer
functionality for 10.3 Gbit/s 10 Gigabit
Ethernet LAN PHY datastream.
• Supports framing, scrambli ng/
descrambling and pointer processing
for the following:
• STS-192c (STM-64-64c).
• 4 x STS-48c (4 x STM-16-16c).
• STS-192 (STM-64) channelized
down to STS-48c (STM-16c).
• Supports alarm signal
insertion/detection, B1/2/3 processing
and insertion/termination of SONET
Section/Line/Path overhead bytes (or
SDH equivalents).
• Provides ATM and POS payload
processing for:
• STS-192c (STM-64-64c)
• 4 x STS-48c (4 x STM-16-16c).
• STS-192 (STM-64) channelized
down to STS-48c (STM-16c).
INTERFACES
• Provides SATURN® POS-PHY™
Level 4 16-bit LVDS System-side
Interface (clocked at 700 MHz
nominal).
• Directly connects to optics via 16 bit by
622 MHz OIF SFI-4 (OIF99.102) or 16
bit by 622/645 MHz IEEE P802.3ae
XSBI line-side interfaces.
POS/ATM
• Implements the ATM Forum User
Network Interface Specification and
the ATM physical layer for Broadband
ISDN according to CCITT Rec. I.432.
• Implements the Poin t-to-Point Pro tocol
(PPP) over SONET/SDH specification
according to RFC 2615(1619)/1662 of
the PPP Working Group of the In ternet
Engineering Task Force (IETF).
10 GIGABIT ETHERNET
• Implements 10 Gigabit Ethernet WAN
and LAN PHY according the IEEE
P802.3ae standard currently under
development.
• Provides standard IEEE P802.3ae 10
Gigabit Ethernet Media Access
Controller (10GMAC) for frame
verification.
• Implements IEEE P802.3ae 64B/66B
Physical Coding Sub-layer (PCS).
10 GIGABIT ETHERNET MAC
• Verifies frame integrity (FCS and
length checks).
BLOCK DIAGRAM
RXDATA+/-
RXCLK+/-
TXCLK+/-
TXDATA +/-
TXCLK_SRC+/-
XSBI/
SFI-4
Rx
Interface
XSBI/
SFI-4
Tx
Interface
RTOH
Rx
Transport
O/H
Processor
Tx
Transport
O/H
Processor
Rx SONET
BER
Monitor
LVDS I/F
RPOH
Rx Path
O/H
Processor
APS
Rx Payload
Tx High-
Order Path
O/H
Processor
Aligner
IAPS+/-
LVDS I/F
APS
Rx 64B/
66B
Decoder
Rx Cell/
Frame
Processor
Tx 64B/66B
Encoder
Tx Cell/
Frame
Processor
10 Gigabit
Ethernet
MAC
10 Gigabit
Ethernet
MAC
Microprocessor
Ingress
Flexible
FIFO
Egress
Flexible
FIFO
POS-PHY
Level 4
Interface
POS-PHY
Level 4
Interface
JTAG
RSTAT
RSCLK
RCTL+/RDAT+/RDCLK +/-
PL4 REF +/-
TDCLK +/TDAT+/TCTL+/-
TSTAT
TSCLK
ALE
CSB
RDB
WRB
TTOH
PMC-2000181 (A2) PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE Copyright PMC-Sierra, Inc. 2001
OAPS+/-
TPOH
A[14:0]
D[15:0]
RSTB
TDI
TCK
TMS
TDO
INTB
TRSTB
Advance PM5390 S/UNI®-9953
10 Gbit/s Physical Layer Device for POS, ATM and Ethernet
• Provides egress Ethernet frame
encapsulation (pads to min. size, add
preamble, IFG and CRC generation).
• Supports VLAN tagged frames.
• Provides eight exact-match address
filters to filter frames based on SA, DA
or VID.
• Provides 64-bin hash based algorithm
to filter multicast addresses.
• Minimum frame size of 64 bytes.
• Provides statistics counters to support
RMON/SNMP.
• Supports jumbo frames up to
9.6 Kbytes.
• Programmable inter-packet gap (IPG).
• Implements in-band PAUSE flow-
control and provides support for out-ofband flow control.
• Upper layer device can flow-control
using dedicated pins or host signaling
to cause generation of a PAUSE
frame.
GENERAL
• Provides internal FIFOs (16 KB
ingress, 20 KB egress) to
accommodate system latencies.
• Provides line-side and system-side
loopbacks for system level diagnostic
capability.
• Provides support for automatic
protection switching (APS) via two 16bit LVDS 777.76 MHz ports.
• Provides a generic 16-bit
microprocessor bus interface for
configuration, control, and status
monitoring.
• Standard 5 signal P1149.1 JTAG test
port.
• Low power 1.8 V CMOS core logic with
3.3 V CMOS/TTL compatible digital
inputs and digital outputs.
• Industrial temperatu re r ange (- 40 °C to
+85 °C).
• 1152 pin FCBGA package.
DEVICE INTERWORKING
• Other PMC-Sierra devices that
implement the POS-PHY Level 4
interface include:
• S/UNI 1x10GE.
• S/UNI 10xGE.
• S/UNI 9953-POS.
POS-PHY LEVEL 4 INTERFACE
• Designed to transmit cells, packets or
frames between physi cal an d data-link
layer devices.
• Supports mixed traffic protocols on a
channel by channel basis.
• Requires less pins and draws less
power than other 10 Gigabit interface
options.
• Compliant with the following
standards:
• Optical Internetworking Forum -
System Physical Interface Level 4
Phase II (SPI-4 Phase II).
• ATM Forum - Frame Based ATM
Interface Level 4 (ATMF0161.00).
• SATURN® POS-PHY™ Level 4,
Issue 6, March 2001.
APPLICATIONS
• Edge and Core Routers.
• Multi-Service (Multi- Proto col )
Switches.
• Internet POP and Transport POP L2
Ethernet S witches.
• SONET/SDH add/drop multiplexers
and optical cross-connects.
• WAN and Edge ATM switches.
• Up-link cards.
• SONET/SDH ATM/POS and 10
Gigabit Ethernet test equipment.
• Emerging DPT, IPT, and GFP
applications.
TYPICAL APPLICATION
10 GIGABIT / OC-192 ROUTER PORT CARD APPLICATION
4 X OC-48 POS Line Card
Optics
Optics
Optics
Optics
1 X OC-192 POS / 10 Gigabit Ethernet
Line Card
Integrated
(Working Mate)
1 X OC-192 POS
Line Card
Integrated
(Protect Mate)
Head Office:
PMC-Sierra, Inc.
#105 - 8555 Baxter Place
Burnaby, B.C. V5A 4V7
Canada
Tel: 604.415.6000
Fax: 604.415.6200
Optics
Optics
CRSU
4x2488
SFI-4
S/UNI
9953
S/UNI
9953
S/UNI
9953
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
IP Processor
L2/L3
Processor
APS Port
APS Port
To order documentation,
send email to:
document@pmc-sierra.com
or contact the head office,
Attn: Document Coordinator
Traffic
Manager
Traffic
Manager
TT1
Multi-Gbit/s
to Terabit
Switch
Fabric
1 X OC-192 ATM Interworking Line Card
Traffic
Manager
Processor
ATM/IP
IP
Inter
Working
2 X OC-192 Ring Access Line Card
Traffic
Manager
All product documentation is available
on our web site at:
http://www.pmc-sierra.com
For corpo rate information,
send email to:
info@pmc-sierra.com
Processor
IP
GFP or DPT
Ring Access
Controller
S/UNI
SAR
9953
S/UNI
9953
S/UNI
9953
PMC-2000181 (A2)
Copyright PMC-Sierra,
Inc. 2001. All rights reserved.
SATURN and S/UNI are
registered trademarks and
POS-PHY and PMC-Sierra
are trademarks of PMCSierra, Inc.
Integrated
Optics
Integrated
Optics
Integrated
Optics
Loading...