PMC PM5371-RI Datasheet

PM5371 TUDX

DATA SHEET PMC-920525 ISSUE 6 SONET/SDH TRIBUTARY UNIT CROSS CONNECT

PM5371

TUDX

SONET/SDH TRIBUT ARY UNIT

CROSS CONNECT

DATA SHEET

ISSUE 6: SEPTEMBER 1998

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PM5371 TUDX

DATA SHEET PMC-920525 ISSUE 6 SONET/SDH TRIBUTARY UNIT CROSS CONNECT

REVISION HISTORY

Issue No. Issue Date Details of Change

6 September

1998

1. Corrected some formatting problems.

2. Corrected documentation errata from TUDX errata document (issue 1). Issue 1 errata is now obsolete.

3. Issue 5 contained two different mechanical diagrams. Incorrect diagram was removed.

4. All references to PQFP changed to MQFP which is a more technically correct description of the package.

5 July 1998 Data Sheet Reformatted — No Change in Technical

Content.

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PM5371 TUDX

DATA SHEET PMC-920525 ISSUE 6 SONET/SDH TRIBUTARY UNIT CROSS CONNECT

CONTENTS

1 FEATURES....................................................................................1

2 APPLICATIONS.............................................................................2

3 REFERENCES..............................................................................3

4 APPLICATION EXAMPLES...........................................................4

5 BLOCK DIAGRAM.........................................................................7

6 DESCRIPTION..............................................................................9

7 PIN DIAGRAM.............................................................................10

8 PIN DESCRIPTION.....................................................................11

9 FUNCTIONAL DESCRIPTION....................................................23

9.1 INPUT BUS FORMATTER................................................23

9.2 OUTPUT BUS FORMATTER............................................23

9.3 SWITCHING ELEMENT ...................................................24

9.3.1 DATA MEMORIES..................................................25

9.3.2 CONNECTION MEMORY ......................................25

9.3.3 TIMING GENERATOR ...........................................26

9.3.4 OUTPUT MULTIPLEXER.......................................26

9.3.5 COMMON BUS INTERFACE.................................26

9.4 MICROPROCESSOR INTERFACE ..................................27

10 NORMAL MODE REGISTER DESCRIPTION.............................28

11 TEST FEATURES DESCRIPTION ..............................................47

11.1 I/O TEST MODE ...............................................................51

12 OPERATION................................................................................53

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PM5371 TUDX

DATA SHEET PMC-920525 ISSUE 6 SONET/SDH TRIBUTARY UNIT CROSS CONNECT

12.1 BASIC CONNECTION MEMORY ACCESS......................53

12.1.1CONNECTION MEMORY READ...........................53

12.1.2CONNECTION MEMORY WRITE..........................53

12.2 CONNECTION SET UP....................................................54

12.3 IDLE CODE INSERTION..................................................56

13 FUNCTIONAL TIMING ................................................................58

14 ABSOLUTE MAXIMUM RATINGS...............................................66

15 D.C. CHARACTERISTICS ...........................................................67

16 MICROPROCESSOR INTERFACE TIMING

CHARACTERISTICS...................................................................70

17 TUDX TIMING CHARACTERISTICS...........................................77

18 ORDERING AND THERMAL INFORMATION .............................82

19 MECHANICAL INFORMATION....................................................83

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PM5371 TUDX

DATA SHEET PMC-920525 ISSUE 6 SONET/SDH TRIBUTARY UNIT CROSS CONNECT

LIST OF REGISTERS

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iii

PM5371 TUDX

DATA SHEET PMC-920525 ISSUE 6 SONET/SDH TRIBUTARY UNIT CROSS CONNECT

LIST OF FIGURES

FIGURE 1 - 2 X 2 TUDX SWITCH ARRAY USING SYSTOLIC

INTERCONNECT ..........................................................................4

FIGURE 2 - 2 X 2 TUDX SWITCH ARRAY USING BUSED

INTERCONNECT ..........................................................................5

FIGURE 3 - 2 X 2 TUDX SWITCH ARRAY USING HYBRID

INTERCONNECT ..........................................................................6

FIGURE 4 - OVERALL DEVICE..............................................................7

FIGURE 5 - EACH SWITCHING ELEMENT...........................................8

FIGURE 6 - SONET STS-3 CARRYING VT1.5 WITHIN STS-1............55

FIGURE 7 - SDH STM-1 CARRYING TU12 WITHIN VC3/AU3.............56

FIGURE 8 - SDH STM-1 CARRYING TU12 WITHIN TUG3..................56

FIGURE 9 - INPUT/OUTPUT BUS TIMING (SYSTOLIC DELAY

DISABLED)..................................................................................59

FIGURE 10- INPUT/OUTPUT BUS TIMING (SYSTOLIC DELAY

APPLIED TO SINL/SINR) ............................................................60

FIGURE 11- INPUT/OUTPUT BUS TIMING (SYSTOLIC DELAY

APPLIED TO DINT/DINB)............................................................61

FIGURE 12- INPUT/OUTPUT BUS TIMING (SYSTOLIC DELAY

APPLIED TO DOUTL/DOUTR)....................................................62

FIGURE 13- INPUT/OUTPUT BUS TIMING (SYSTOLIC DELAY

APPLIED TO SOUTT/SOUTB).....................................................64

FIGURE 14- PAGE TIMING....................................................................65

FIGURE 15- MICROPROCESSOR INTERFACE READ ACCESS

TIMING FOR INTEL MODE.........................................................71

FIGURE 16- MICROPROCESSOR INTERFACE READ ACCESS

TIMING FOR MOTOROLA MODE...............................................72

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PM5371 TUDX

DATA SHEET PMC-920525 ISSUE 6 SONET/SDH TRIBUTARY UNIT CROSS CONNECT

FIGURE 17- MICROPROCESSOR INTERFACE WRITE ACCESS

TIMING FOR INTEL MODE.........................................................74

FIGURE 18- MICROPROCESSOR INTERFACE WRITE ACCESS

TIMING FOR MOTOROLA MODE...............................................75

FIGURE 19- INPUT TIMING..................................................................78

FIGURE 20- OUTPUT TIMING..............................................................80

FIGURE 21- METRIC QUAD FLAT PACK – MQFP (BODY

28X28X3.49MM)..........................................................................83

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PM5371 TUDX

DATA SHEET PMC-920525 ISSUE 6 SONET/SDH TRIBUTARY UNIT CROSS CONNECT

LIST OF TABLES

TABLE 1 - REGISTER MEMORY MAP ..............................................27

TABLE 2 - SYSTOLIC DELAY CONTROL..........................................38

TABLE 3 - SYSTOLIC ARRAY DELAY CONTROL.............................39

TABLE 4 - TEST MODE REGISTER MEMORY MAP.........................47

TABLE 5 - READING INPUT PIN VALUES.........................................51

TABLE 6 - FORCING OUPUT PIN VALUES.......................................51

TABLE 7 - CONNECTION SET UP ....................................................55

TABLE 8 - IDLE CODE INSERTION...................................................57

TABLE 9 - TUDX MAXIMUM RATINGS..............................................66

TABLE 10 - TUDX D.C. CHARACTERISTICS ......................................67

TABLE 11 - MICROPROCESSOR INTERFACE READ ACCESS

(FIGURE 15, FIGURE 16) ...........................................................70

TABLE 12 - MICROPROCESSOR INTERFACE WRITE ACCESS

(FIGURE 17, FIGURE 18) ...........................................................73

TABLE 13 - TUDX INPUT (FIGURE 19)...............................................77

TABLE 14 - TUDX OUTPUT (FIGURE 20)...........................................79

TABLE 15 - SYSTOLIC OUTPUT CONFIGURATION...........................79

TABLE 16 - BUSED OUTPUT CONFIGURATION................................79

TABLE 17 - PARALLEL BUSED OUTPUT CONFIGURATION .............79

TABLE 18 - ORDERING PM5372-RI....................................................82

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PM5371 TUDX

DATA SHEET PMC-920525 ISSUE 6 SONET/SDH TRIBUTARY UNIT CROSS CONNECT

FEATURES

•

A single stage, non-blocking array of time switches for cross-connecting SONET virtual tributaries (VTs) or SDH tributary units (TUs).

•

Provides non-blocking switching between two STS-3 (STM-1) byte serial input streams and two STS-3 (STM-1) byte serial output streams.

•

Operates from a single 19.44 MHz clock.

•

Provides parity checking on input data buses and parity generation on output data buses.

•

Allows programmable idle code insertion on a per VT or per TU basis.

•

Permits switching of any combination of SONET VT1.5, VT2, VT3, VT6, or STS-1 channels. Permits switching of any combination of SDH TU11, TU12, TU2, or TU3 channels.

•

Operates in conjunction with the PM5361 TUDX SONET/SDH Tributary Unit Payload Processor which aligns SONET VTs or SDH TUs such that they can be switched by the TUDX.

•

Cascadable in a systolic or bused manner to allow larger switching arrays to be implemented. Provides control outputs that are programmable on a per timeslot basis to facilitate construction of larger switching arrays.

•

Provides programmable delay to match data skew in the systolic array application.

•

Provides a generic 8-bit microprocessor bus interface for configuration, control, and status monitoring.

•

Low power, +5 Volt, CMOS technology. Device has TTL compatible inputs and outputs.

•

160 pin metric quad flat pack (MQFP) package.

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PM5371 TUDX

DATA SHEET PMC-920525 ISSUE 6 SONET/SDH TRIBUTARY UNIT CROSS CONNECT

APPLICATIONS

•

SONET and SDH Wideband Cross-Connects

•

SONET and SDH Add-Drop and Terminal Multiplexers

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PM5371 TUDX

DATA SHEET PMC-920525 ISSUE 6 SONET/SDH TRIBUTARY UNIT CROSS CONNECT

REFERENCES

1. American National Standard for Telecommunications - Digital Hierarchy -

Optical Interface Rates and Formats Specification, ANSI T1.105-1988.

2. Bell Communications Research - SONET Transport Systems: Common

Generic Criteria, TR-TSY-000253, Issue 1, September 1989.

3. CCITT Blue Book, Recommendation G.708 - "Netwo rk Node Interface For

The Synchronous Digital Hierarchy", Volume III, Fascicle III.4, 1988.

4. CCITT Blue Book, Recommendation G.709 - "Synchronous Multiplexing

Structure", Volume III, Fascicle III.4, 1988.

5. CCITT Study Group XVIII, Report R 33 - "Recommendations Drafted By

Working Party XVIII/7" (Digital Hierarchies) To Be Approved In 1990 Including Revised Draft Recommendations G.708 and G.709", June 1990.

6. Bell Communications Research - SONET Transport Systems: Common

Generic Criteria, TA-NWT-000253, Issue 6, September 1990.

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PM5371 TUDX

DATA SHEET PMC-920525 ISSUE 6 SONET/SDH TRIBUTARY UNIT CROSS CONNECT

APPLICATION EXAMPLES

Larger switching arrays can be constructed in a variety of manners using arrays of TUDX devices. Systolic or bused interconnect methods can be used, or a hybrid of the two approaches.

Figure 1 - 2 X 2 TUDX Switch Array Using Systolic Interconnect

SINL

TUDX

DOUTL

SINL

TUDX

DOUTL

'0'

SINR

IFP

OFP

'15'

ODEB

DOUTR

SINR

IFP

OFP

'15'

ODEB

DOUTR

'0'

SINL

SINR

SCLK SFP

TUDX

DINT SOUTT DINB SOUTB OFSEB SOBEB AOBEB

DOUTL

IFP

OFP

ODEB

DOUTR

'5' '10'

SINL

SINR

SCLK SFP

TUDX

DINT SOUTT DINB SOUTB OFSEB SOBEB AOBEB

DOUTL

IFP

OFP

ODEB

DOUTR

'5'

'10'

SCLK SFP DINT SOUTT DINB SOUTB OFSEB SOBEB AOBEB

'15'

Systolic interconnect of TUDX devices is illustrated above. In this 2 x 2 array of devices, PCM data is distributed left to right and gathered top to bottom with the PCM data being re-timed as it passes through each device. Each PCM data bus drives a single device, regardless of the size of the array and thus systolic interconnect allows large arrays to be implemented without the use of additional devices. In this example no systolic delay is required for the upper left hand and lower right hand TUDX in the array. The Systolic Delay Control Register of the lower left hand TUDX is programmed to insert a 5 clock period delay in the DINT/DINB buses, and a 5 clock period delay in the DOUTL/DOUTR bu ses. The

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PM5371 TUDX

DATA SHEET PMC-920525 ISSUE 6 SONET/SDH TRIBUTARY UNIT CROSS CONNECT

Systolic Delay Control Register of the upper right hand TUDX is programmed to insert a 5 clock period delay in the SINL/SINR buses, and the SOUTT/SOUTB buses.

Figure 2 - 2 X 2 TUDX Switch Array Using Bused Interconnect

'5'

'0'

SINL

DOUTL

TUDX

SINR

OFP

IFP

ODEB

DOUTR

SCLK SFP DINT SOUTT DINB SOUTB OFSEB SOBEB AOBEB

SINL

DOUTL

SINR

TUDX

DOUTR

SCLK SFP DINT SOUTT DINB SOUTB OFSEB SOBEB AOBEB

'0'

SINL

DOUTL

SINR

TUDX

DOUTR

SINL

DOUTL

TUDX

SINR

OFP

IFP

ODEB

DOUTR

SCLK SFP DINT SOUTT DINB SOUTB OFSEB SOBEB AOBEB

'5'

'0'

OFP

IFP

ODEB

'0'

OFP

IFP

ODEB

'5''5'

Bused interconnect of TUDX devices is illustrated above. In this 2 x 2 array of devices, PCM data is distributed left to right on a common bus and gathered top to bottom using a wired-OR type bus. Using this interconnect approach, additional devices must be used to drive the distribution bus and sample the wired-OR bus. To maximize the size of array that can be achieved using a wiredOR bus, the AOUTL and AOUTR buses may be parallel connected with the DOUTL and DOUTR buses on a bit by bit basis in order to provide higher drive levels. Due to the higher fan out of these buses, and the RC delay on the wiredOR bus, this approach cannot be extended to very large arrays without additional circuitry. This bused array approach provides the minimum data delay through the array (when a cross connection is made between the DINT/DINB buses and

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PM5371 TUDX

DATA SHEET PMC-920525 ISSUE 6 SONET/SDH TRIBUTARY UNIT CROSS CONNECT

the DOUTL/DOUTR buses) of nominally 275 clock periods versus 285 clock periods using the systolic array approach.

Figure 3 - 2 X 2 TUDX Switch Array Using Hybrid Interconnect

'0'

SINL

SINR

SCLK SFP DINT SOUTT DINB SOUTB OFSEB SOBEB AOBEB

TUDX

DOUTL

OFP

IFP

ODEB

DOUTR

'5'

SINL

SINR

SCLK SFP DINT SOUTT DINB OFSEB SOBEB AOBEB

TUDX

DOUTL

OFP

IFP

SOUTB

ODEB

DOUTR

'0'

SINL

SINR

SCLK SFP DINT SOUTT DINB SOUTB OFSEB SOBEB AOBEB

TUDX

DOUTL

OFP

IFP

ODEB

DOUTR

'5'

SINL

SINR

SCLK SFP DINT SOUTT DINB OFSEB SOBEB AOBEB

TUDX

DOUTL

OFP

IFP

SOUTB

ODEB

DOUTR

'0'

'10''10'

A hybrid approach using a mix of bused and systolic interconnect of TUDX devices is illustrated above. In this 2 x 2 array of devices, PCM data is distributed left to right on a common bus and gathered top to bottom with the PCM data being re-timed as it passes through each device. Using this interconnect approach, additional devices must be used to drive the distribution buses. This approach overcomes the RC delay of the wired-OR bus by using systolic interconnect from top to bottom. In this example the Systolic Delay Control registers in the two bottom TUDX devices are programmed to delay the DINT/DINB buses by five clock periods to match the delay seen at the SINL/SINR inputs to these devices.

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PM5371 TUDX

DATA SHEET PMC-920525 ISSUE 6 SONET/SDH TRIBUTARY UNIT CROSS CONNECT

BLOCK DIAGRAM

Figure 4 - Overall Device

INPUT BUS FORMATTER

INPUT

DINT[8:0]

DINB[8:0]

SCLK

PAGE

SOBEB

SFP

OFSEB

BUS FORMATTER

SWITCHING

TIME

SWITCH

ELEMENT

TIME

SWITCH

SINL[8:0]

SINR[8:0]

SOUTT[8:0]

SWITCHING

TIME

SWITCH

ELEMENT

TIME

SWITCH

SOUTB[8:0]

IFP

OFP

MBEB

RSTB

CS1B CS2B

RDB

WRB

ALE

A[4:0]

D[7:0]

INTB

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MICRO

INTERFACE

OUTPUT BUS FORMATTER

ODEB

AOBEB

DOUTL[8:0]

AOUTL[8:0]

COUTL

AOUTR[8:0]

DOUTR[8:0]

COUTR

PM5371 TUDX

DATA SHEET PMC-920525 ISSUE 6 SONET/SDH TRIBUTARY UNIT CROSS CONNECT

Figure 5 - Each Switching Element

DINT[7:0]

DINB[7:0]

SCLK

SFP

PAGE

RSTB

TSTB

BSB

RDB

WRB

TRSB

A[1:0]

PCM

TIMING

GENERATOR

READ ADDRESS

COMMON

BUS

INTERFACE

DATA

MEMORY

WRITE ADDRESS

CONNECTION

MEMORY

DATA

MEMORY

READ ADDRESS

PCM

IDLE CODE

OUTPUT

MUX

CONTROL

DOUT[7:0]

MAKE COUT

D[7:0]

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PM5371 TUDX

DATA SHEET PMC-920525 ISSUE 6 SONET/SDH TRIBUTARY UNIT CROSS CONNECT

DESCRIPTION

The PM5371 TUDX SONET/SDH Tributary Unit Cross-Connect is a monolithic integrated circuit that allows non-blocking switching of tributaries within two SONET STS-3 or SDH STM-1 streams. Any tributary entering on either stream can be connected to any same size tributary within either outgoing stream. The TUDX can be programmed to cross-connect a mix of SONET VT1.5, VT2, VT3, VT6, or STS-1 channels or SDH TU11, TU12, TU2, or TU3 channels. Programmable idle code can also be inserted into any of these channels. The TUDX allows cross-connection of up to 168 VT1.5 or TU11 streams, up to 126 VT2 or TU12 streams, or up to 42 VT6 or TU2 streams or any legal mix as permitted by the SONET or SDH mappings.

The TUDX operates in conjunction with the PM5361 TUPP SONET/SDH Tributary Unit Payload Processor which aligns SONET VTs or SDH TUs such that they can be switched by the TUDX. Larger switches can be constructed using arrays of TUDX devices. The TUDX is cascadable in a systolic or bused manner and provides programmable control outputs that are useful in constructing larger switching arrays.

No high speed clocks are required as the TUDX operates from a single 19.44 MHz clock. Parity checking is provided on input data buses and parity generation is provided on output data buses. The TUDX is configured, controlled and monitored via a generic 8-bit microprocessor bus interface.

The TUDX is implemented in low power, +5 Volt, CMOS technology. It has TTL compatible inputs and outputs and is packaged in a 160 pin metric quad flat pack (MQFP) package.

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PM5371 TUDX

DATA SHEET PMC-920525 ISSUE 6 SONET/SDH TRIBUTARY UNIT CROSS CONNECT

PIN 1

ODEB AOBEB DINT[0] DINT[1] DINT[2] DINT[3] DINT[4] DINT[5] DINT[6] DINT[7] DINT[8]

CS1B CS2B

DINB[0]

VDDI

VSSI DINB[1] DINB[2] DINB[3] DINB[4] DINB[5] DINB[6] DINB[7] DINB[8]

SOBEB

VSSO VDDO

PIN 40

PIN DIAGRAM

The TUDX is packaged in an 160 pin MQFP package having a body size of 28 mm by 28 mm and a pin pitch of 0.65 mm.

PIN 160

A[0] A[1]

A[2] A[3]

A[4]

Index

PIN 121

PM5371

TUDX

(TOP VIEW)

D[0] D[1] D[2] D[3]

D[4] D[5] D[6] D[7]

PIN 120

COUTL

VDDO

VSSO SOUTT[0] SOUTT[1] SOUTT[2] SOUTT[3] SOUTT[4] SOUTT[5] SOUTT[6] SOUTT[7] SOUTT[8] VDDO

VSSO

INTB MBEB RSTB

ALE RDB_E WRB_RWB VDDI

VSSI

VSSO

SCLK VDDO SOUTB[0] SOUTB[1] SOUTB[2] SOUTB[3] SOUTB[4] SOUTB[5] SOUTB[6]

SOUTB[7] SOUTB[8]

VDDO

VSSO

COUTR

OFP

IFP VSSO

PIN 81

PIN 41

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PIN 80

PM5371 TUDX

DATA SHEET PMC-920525 ISSUE 6 SONET/SDH TRIBUTARY UNIT CROSS CONNECT

PIN DESCRIPTION

Pin Name Type Pin

Function

No.

SCLK Input 97 The system clock (SCLK) provides timing for TUDX

internal operation. SCLK is a 19.44 MHz, nominally 50% duty cycle clock.

VCLK The test vector clock (VCLK) provides timing for TUDX

production test.

SFP Input 42 The system frame pulse (SFP) determines the frame

boundaries on the DINT[8:0] and DINB[8:0] buses (and SINL[8:0] and SINR[8:0] buses) when OFSEB is high. SFP determines the frame boundaries on the SOUTT[8:0] and SOUTB[8:0] buses when OFSEB is low. SFP must be brought high once every frame (125 µs) to mark the first C1 byte of the transport envelope frame of the buses in question. In systolic applications where OFSEB is high, SFP marks the C1 byte of the SINL[8:0] and SINR[8:0] buses (or the DINT[8:0] and DINB[8:0] buses) after the programmable systolic delay has been inserted. See the Application Examples and Functional Timing sections for more information. SFP is sampled on the rising edge of SCLK.

OFSEB Input 160 The active low output frame synchronization enable

(OFSEB) signal selects the system frame alignment marked by SFP. When OFSEB is high, SFP is coincident with the input frame pulse (IFP). When OFSEB is low, SFP is coincident with the output frame pulse (OFP). In most applications, OFSEB should be held high. The OFSEB input has an integral pull up resistor.

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PM5371 TUDX

DATA SHEET PMC-920525 ISSUE 6 SONET/SDH TRIBUTARY UNIT CROSS CONNECT

Pin Name Type Pin

Function

No.

IFP Output 82 The input frame pulse (IFP) marks the frame

boundaries on the DINT[8:0] and DINB[8:0] buses (or SINL[8:0] and SINR[8:0] buses). IFP pulses high for a single SCLK period to mark the first C1 byte of the transport envelope frame of the buses in question. In systolic array applications, IFP marks the frame boundaries of the SINL[8:0] and SINR[8:0] buses (or the DINT[8:0] and DINB[8:0] buses) after the programmable systolic delay has been inserted. See the Application Examples and Functional Timing sections for more information. IFP is updated on the rising edge of SCLK.

OFP Output 83 The output frame pulse (OFP) marks the frame

boundaries on the SOUTT[8:0] and SOUTB[8:0] buses. OFP pulses high for a single SCLK period to mark the first C1 byte of the transport envelope frame.

OFP is updated on the rising edge of SCLK. DINT[0] DINT[1] DINT[2] DINT[3]

Input 3

The top data input bus (DINT[8:0]) carries

4 5 6

SONET/SDH frame data in byte serial format. The

DINT[8] bit is a parity bit which is not passed through

the TUDX. The TUDX may be configured to check for

even or odd input bus parity and generate interrupts

when parity errors occur. The DINT[8:0] bus is DINT[4]

DINT[5]

sampled on the rising edge of SCLK.

8 DINT[6] DINT[7] DINT[8]

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PM5371 TUDX

DATA SHEET PMC-920525 ISSUE 6 SONET/SDH TRIBUTARY UNIT CROSS CONNECT

Pin Name Type Pin

No.

DINB[0] DINB[1] DINB[2] DINB[3] DINB[4] DINB[5] DINB[6] DINB[7] DINB[8] DOUTL[0] DOUTL[1] DOUTL[2] DOUTL[3] DOUTL[4] DOUTL[5] DOUTL[6]

Input 19

Output/ OD Output

128

131

133

137

139

145

147

Function

The bottom data input bus (DINB[8:0]) carries SONET/SDH frame data in byte serial format. The DINT[8] bit is a parity bit which is not passed through the TUDX. The TUDX may be configured to check for even or odd input bus parity and generate interrupts when parity errors occur. The DINB[8:0] bus is sampled on the rising edge of SCLK.

The left data output bus (DOUTL[8:0]) carries SONET/SDH frame data in byte serial format. The DOUTL[8] bit is a parity bit which is generated by the TUDX. The TUDX may be configured to generate even or odd parity. The DOUTL[8:0] bus is updated on the rising edge of SCLK. DOUTL may be configured as a normal output or as an open drain output, the latter mode being useful for constructing larger switching arrays.

DOUTL[7] DOUTL[8] DOUTR[0] DOUTR[1] DOUTR[2] DOUTR[3] DOUTR[4] DOUTR[5] DOUTR[6] DOUTR[7] DOUTR[8]

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Output/ OD Output

151

153

The right data output bus (DOUTR[8:0]) carries SONET/SDH frame data in byte serial format. The DOUTR[8] bit is a parity bit which is generated by the TUDX. The TUDX may be configured to generate even or odd parity. The DOUTR[8:0] bus is updated on the rising edge of SCLK. DOUTR may be configured as a normal output or as an open drain output, the latter mode being useful for constructing larger switching arrays.

PM5371 TUDX

DATA SHEET PMC-920525 ISSUE 6 SONET/SDH TRIBUTARY UNIT CROSS CONNECT

Pin Name Type Pin

No.

AOUTL[0] AOUTL[1] AOUTL[2] AOUTL[3] AOUTL[4] AOUTL[5] AOUTL[6] AOUTL[7] AOUTL[8]

AOUTR[0] AOUTR[1] AOUTR[2] AOUTR[3] AOUTR[4] AOUTR[5] AOUTR[6] AOUTR[7] AOUTR[8]

Output/ OD Output

127

130

132

136

138

144

146

150

152

Function

The left auxiliary data output bus (AOUTL[8:0]) carries SONET/SDH frame data in byte serial format. The AOUTL[8] bit is a parity bit which is generated by the TUDX. The TUDX may be configured to generate even or odd parity. The AOUTL[8:0] bus is updated on the rising edge of SCLK. AOUTL may be configured as a normal output or as an open drain output, the latter mode being useful for constructing larger switching arrays. The AOUTL output bus carries the same information as the DOUTL bus and the two buses may be parallel connected on a bit by bit basis when additional output drive is required. The AOUTL bus is held in a high impedance mode to save power when not enabled.

The right auxiliary data output bus (AOUTR[8:0]) carries SONET/SDH frame data in byte serial format. The AOUTR[8] bit is a parity bit which is generated by the TUDX. The TUDX may be configured to generate even or odd parity. The AOUTR[8:0] bus is updated on the rising edge of SCLK. AOUTR may be configured as a normal output or as an open drain output, the latter mode being useful for constructing larger switching arrays. The AOUTR output bus carries the same information as the DOUTR bus and the two buses may be parallel connected on a bit by bit basis when additional output drive is required. The AOUTR bus is held in a high impedance mode to save power when not enabled.

AOBEB Input 2 The active low auxiliary output bus enable (AOBEB)

signal enables the AOUTL and AOUTR when low. When AOBEB is high, the AOUTL and AOUTR output buses are held in a high impedance mode to save power. The AOBEB input has an integral pull up resistor.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

PM5371 TUDX

DATA SHEET PMC-920525 ISSUE 6 SONET/SDH TRIBUTARY UNIT CROSS CONNECT

Pin Name Type Pin

No.

SINL[0] SINL[1] SINL[2] SINL[3] SINL[4] SINL[5] SINL[6] SINL[7] SINL[8] SINR[0] SINR[1] SINR[2] SINR[3] SINR[4] SINR[5] SINR[6] SINR[7]

Input 121

122

123

124

125

156

157

158

159

Input 80

Function

The left systolic input bus (SINL[8:0]) carries SONET/SDH frame data in byte serial format. The SINL[8] bit is a parity bit which is not passed through the TUDX. The TUDX may be configured to check for even or odd input bus parity and generate interrupts when parity errors occur. The SINL[8:0] bus is sampled on the rising edge of SCLK. Data on the SINL[8:0] bus is re-timed and may be routed to the DOUTL[8:0] in place of information switched from the DINT[8:0] bus, and is provided for constructing larger switching arrays using systolic data flow.

The right systolic input bus (SINR[8:0]) carries SONET/SDH frame data in byte serial format. The SINR[8] bit is a parity bit which is not passed through the TUDX. The TUDX may be configured to check for even or odd input bus parity and generate interrupts when parity errors occur. The SINR[8:0] bus is sampled on the rising edge of SCLK. Data on the SINR[8:0] bus is re-timed and may be routed to the DOUTR[8:0] in place of information switched from the DINB[8:0] bus, and is provided for constructing larger

switching arrays using systolic data flow. SINR[8] SOUTT[0] SOUTT[1] SOUTT[2] SOUTT[3] SOUTT[4] SOUTT[5] SOUTT[6] SOUTT[7] SOUTT[8]

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

Output 117

116 115 114 113 112 111 110 109

The left systolic output bus (SOUTT[8:0]) carries

SONET/SDH frame data in byte serial format. The

SOUTT[8] bit is a parity bit which is generated by the

TUDX. The TUDX may be configured to generate

even or odd parity. The SOUTT[8:0] bus is updated on

the rising edge of SCLK. The SOUTT[8:0] bus carries

a re-timed copy of the information sampled on the

DINT[8:0] bus and is provided for constructing larger

switching arrays using systolic data flow. The SOUTT

bus can be disabled to save power when not used.

PM5371 TUDX

DATA SHEET PMC-920525 ISSUE 6 SONET/SDH TRIBUTARY UNIT CROSS CONNECT

Pin Name Type Pin

Function

No.

SOUTB[0] SOUTB[1] SOUTB[2] SOUTB[3]

Output 95

94 93 92

The right systolic output bus (SOUTB[8:0]) carries

SONET/SDH frame data in byte serial format. The

SOUTB[8] bit is a parity bit which is generated by the

TUDX. The TUDX may be configured to generate

even or odd parity. The SOUTB[8:0] bus is updated

on the rising edge of SCLK. The SOUTB[8:0] bus SOUTB[4]

SOUTB[5]

91 90

carries a re-timed copy of the information sampled on

the DINB[8:0] bus and is provided for constructing

larger switching arrays using systolic data flow. The SOUTB[6]

SOUTB[7] SOUTB[8]

89 88 87

SOUTB bus can be disabled to save power when not

used.

SOBEB Input 30 The active low systolic output bus enable (SOBEB)

signal enables the SOUTT and SOUTB output buses

when low. When SOBEB is high, the SOUTT and

SOUTB output buses are held in a high impedance

mode to save power. The SOBEB input has an

integral pull up resistor. COUTL Output 120 The left control output signal (COUTL) is a software

programmable control stream (on a per timeslot basis)

that can be used for controlling external hardware

when constructing larger switching arrays. After reset,

COUTL defaults to always high until otherwise

programmed. COUTL is updated on the rising edge of

SCLK. COUTR Output 84 The right control output bus (COUTR) is a software

programmable control stream (on a per timeslot basis)

that can be used for controlling external hardware

when constructing larger switching arrays. After reset,

COUTR defaults to always high until otherwise

programmed. COUTR is updated on the rising edge

of SCLK.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

PM5371 TUDX

DATA SHEET PMC-920525 ISSUE 6 SONET/SDH TRIBUTARY UNIT CROSS CONNECT

Pin Name Type Pin

Function

No.

ODEB Input 1 The active low open drain enable (ODEB) signal

configures the DOUTL and DOUTR output buses as

open drain outputs when low. When ODEB is high,

the DOUTL and DOUTR output buses are configured

as normal outputs. The ODEB input has an integral

pull up resistor. PAGE Input 41 The page select (PAGE) signal selects the connection

memory pages that are used to control connections

within the TUDX. When PAGE is low, connection

memory page 0 of each switching element is used.

When PAGE is high, connection memory page 1 of

each switching element is used. The PAGE input is

sampled on the rising edge of SCLK. Internally, a

change in the active connection memory page is held

off until the next switching frame boundary (a delay of

up to approximately 14 us). While such a page swap

is pending, accesses to the connection memory by

the microprocessor should be avoided. Such a

pending page swap results in a connection memory

busy indication which can be polled. The PAGE input

has an integral pull down resistor. MBEB Input 105 The active low Motorola bus enable (MBEB) signal

configures the TUDX for Motorola bus mode where

the RDB/E signal functions as E, and the WRB/RWB

signal functions as RWB. When MBEB is high, the

TUDX is configured for Intel bus mode where the

RDB/E signal functions as RDB. The MBEB input has

an integral pull up resistor. CS1B Input 17 The active low chip select #1 (CS1B) signal is low

during TUDX register accesses.

If CS1B and CS2B are not required (i.e., registers

accesses are controlled using the RDB and WRB

signals only), CS1B and CS2B must be connected to

an inverted version of the RSTB input.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

PM5371 TUDX

DATA SHEET PMC-920525 ISSUE 6 SONET/SDH TRIBUTARY UNIT CROSS CONNECT

Pin Name Type Pin

Function

No.

CS2B Input 18 The active low chip select #2 (CS2B) signal is low

during TUDX register accesses.

If CS1B and CS2B are not required (i.e., registers

accesses are controlled using the RDB and WRB

signals only), CS1B and CS2B must be connected to

an inverted version of the RSTB input.

RDB Input 102 The active low read enable (RDB) signal is low during

TUDX register read accesses while in Intel bus mode

(MBEB = 1). The TUDX drives the D[7:0] bus with the

contents of the addressed register while RDB, CS1B,

and CS2B are low. E Input 102 The active high external access (E) signal is high

during TUDX register access while in Motorola bus

mode (MBEB = 0). WRB Input 101 The active low write strobe (WRB) signal is low during

a TUDX register write accesses while in In tel bus

mode (MBEB = 1). The D[7:0] bus contents are

clocked into the addressed register on the rising WRB

edge while CS1B and CS2B are low. RWB The read/write select (RWB) signal selects between

TUDX register read and write accesses while in

Motorola bus mode (MBEB = 0). The TUDX drives the

D[7:0] bus with the contents of the addressed register

while CS1B and CS2B are low and RWB and E are

high. The D[7:0] bus contents are clocked into the

addressed register on the falling E edge while CS1B

and CS2B and RWB are low.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

PM5371 TUDX

DATA SHEET PMC-920525 ISSUE 6 SONET/SDH TRIBUTARY UNIT CROSS CONNECT

Pin Name Type Pin

No.

D[0] D[1] D[2] D[3] D[4] D[5] D[6] D[7] A[0] A[1] A[2] A[3] A[4]/TRS

I/O 31

32 33 34 37 38 39 40

Input 12

13 14 15 16

Function

The bidirectional data bus (D[7:0]) is used during

TUDX register read and write accesses.

The address bus (A[4:0]) selects specific registers

during TUDX register accesses.

The test register select (TRS) signal discriminates

between normal and test mode register accesses.

TRS is high during test mode register accesses, and

is low during normal mode register accesses. The

TRS input has an integral pull down resistor. RSTB Input 104 The active low reset (RSTB) signal provides an

asynchronous TUDX reset. RSTB is a Schmitt

triggered input with an integral pull up resistor. ALE Input 103 The address latch enable (ALE) is active high and

latches the address bus (A[4:0]) and TRS when low.

When ALE is high, the internal address latches are

transparent. It allows the TUDX to interface to a

multiplexed address/data bus. The ALE input has an

integral pull up resistor. INTB OD

Output

106 The active low interrupt (INTB) signal goes low when

a TUDX interrupt source is active. INTB returns high

when the interrupt is acknowledged via an appropriate

output.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

PM5371 TUDX

DATA SHEET PMC-920525 ISSUE 6 SONET/SDH TRIBUTARY UNIT CROSS CONNECT

Pin Name Type Pin

No.

VDDI1 VDDI2 VDDI3 VDDI4 VSSI1 VSSI2 VSSI3 VSSI4 VDDO1 VDDO2 VDDO3 VDDO4 VDDO5

Power 20

60 100 140

Ground 21

59 99 141

Power 36

47 55 63 69

Function

The core power (VDDI) pins should be connected to a

well decoupled +5 V DC in common with VDDO.

The core ground (VSSI) pins should be connected to

GND in common with VSSO.

The pad ring power (VDDO) pins should be connected

to a well decoupled +5 V DC in common with VDDI.

VDDO6 VDDO7 VDDO8 VDDO9 VDDO10 VDDO11 VDDO12 VDDO13 VDDO14

86 96 108 119 126 135 143 148 154

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PMC PM5371-RI Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual