PMC PM5363-BI Datasheet

PM5363 TUPP+622

TUPP+622

DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

PM5363

TUPP+622

SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR

FOR 622 MBIT/S INTERFACES

DATASHEET

RELEASED

ISSUE 4: JULY 2000

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

PM5363 TUPP+622

TUPP+622

DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

REVISION HISTORY

Issue

Issue Date Details of Change

No.

Issue 4 July 2000 Update for revision B device.

De-document TU3 Inband Error feature. Added changes to timing and operating conditions. All Input Hold Times for SCLK (19.44MHz) are changed from 1ns to

1.5ns. All Output Max Prop Delays for HSCLK (77.76MHz) changed from 8ns to 9ns. All Output Min Prop Delay for SCLK (19.44MHz) changed from 2ns to 3.5ns. Operating Condition for V

DD3.3

changed

from 3.3V ± 10% to 3.3V ±

0.3V and operating condition for V

changed from 2.5V

DD2.5

± 10% to 2.5V ± 0.2V. TUGEN Bit and TUGBYP Bit description changed. Device ID Revision Number, SOS Bit description and Boundary Scan ID changed.

Issue 3 Nov 1999 Update Data-sheet portion to

preliminary.

Issue 2 May 1999 Update pin and register

description.

Issue 1 December

Document created.

1998

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

PM5363 TUPP+622

TUPP+622

DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

LIST OF REGISTERS

REGISTER 00H: STP INCOMING CONFIGURATION ................................. 118

REGISTER 01H: STP OUTGOING CONFIGURATION ................................120

REGISTER 02H: STP INPUT SIGNAL ACTIVITY MONITOR #1,

ACCUMULATION TRIGGER .............................................................122

REGISTER 03H: STP RESET AND IDENTITY.............................................124

REGISTER 04H: STP VTPP #1 CONFIGURATION #1 ................................125

REGISTER 05H: STP VTPP #2 CONFIGURATION #1 ................................128

REGISTER 06H: STP VTPP #3 CONFIGURATION #1 ................................131

REGISTER 07H: STP TRIBUTARY PAYLOAD PROCESSOR AND

LOM INTERRUPT ENABLE...............................................................134

REGISTER 08H: STP TRIBUTARY PAYLOAD PROCESSOR

INTERRUPT AND LOM STATUS .......................................................136

REGISTER 09H: STP PARITY ERROR AND LOM INTERRUPT .................138

REGISTER 0AH: STP RTOP AND RTTB INTERRUPT ENABLE.................140

REGISTER 0BH: STP RTOP AND RTTB INTERRUPT STATUS .................142

REGISTER 0CH: STP RTOP #1 AND RTTB #1 CONFIGURATION ............144

REGISTER 0DH: STP RTOP #2 AND RTTB #2 CONFIGURATION ............146

REGISTER 0EH: STP RTOP #3 AND RTTB #3 CONFIGURATION.............148

REGISTER 10H: STP TRIBUTARY ALARM AIS CONTROL........................150

REGISTER 11H: STP TRIBUTARY REMOTE DEFECT

INDICATION CONTROL ....................................................................152

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE v

PM5363 TUPP+622

TUPP+622

DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

REGISTER 12H: STP TRIBUTARY AUXILIARY REMOTE DEFECT

INDICATION CONTROL ....................................................................154

REGISTER 13H: STP TRIBUTARY PATH DEFECT INDICATION

CONTROL .........................................................................................157

REGISTER 14H: STP INPUT SIGNAL ACTIVITY MONITOR #2..................159

REGISTER 15H: STP OUTGOING POINTER LSB......................................161

REGISTER 17H: STP VTPP #1 CONFIGURATION #2 ................................163

REGISTER 18H: STP VTPP #2 CONFIGURATION #2 ................................165

REGISTER 19H: STP VTPP #3 CONFIGURATION #2 ................................167

REGISTER 20H, 40H, 60H: VTPP, TU3 OR TU #1 IN TUG2 #1,

CONFIGURATION AND STATUS ......................................................169

REGISTER 21H-26H, 41H-46H, 61H-66H: VTPP, TU #1 IN TUG2

#2 TO TUG2 #7, CONFIGURATION AND STATUS ...........................172

REGISTER 27H, 47H, 67H: VTPP, TU3 OR TU #1 IN TUG2 #1 TO

TUG2 #7, LOP INTERRUPT..............................................................174

REGISTER 28H-2EH, 48H-4EH, 68H-6EH: VTPP, TU #2 IN TUG2

#1 TO TUG2 #7, CONFIGURATION AND STATUS ...........................176

REGISTER 2FH, 4FH, 6FH: VTPP, TU #2 IN TUG2 #1 TO TUG2

#7, LOP INTERRUPT ........................................................................178

REGISTER 30H-36H, 50H-56H, 70H-76H: VTPP, TU #3 IN TUG2

#1 TO TUG2 #7, CONFIGURATION AND STATUS ...........................179

REGISTER 37H, 57H, 77H: VTPP, TU #3 IN TUG2 #1 TO TUG2

#7, LOP INTERRUPT ........................................................................181

REGISTER 38H-3EH, 58H-5EH, 78H-7EH: VTPP, TU #4 IN TUG2

#1 TO TUG2 #7, CONFIGURATION AND STATUS ...........................182

REGISTER 3FH, 5FH, 7FH: VTPP, TU #4 IN TUG2 #1 TO TUG2

#7, LOP INTERRUPT ........................................................................184

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE vi

PM5363 TUPP+622

TUPP+622

DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

REGISTER A0H, C0H, E0H: VTPP, TU3 OR TU #1 IN TUG2 #1,

ALARM STATUS ................................................................................185

REGISTER A1H-A6H, C1H-C6H, E1H-E6H: VTPP, TU #1 IN TUG2

#2 TO TUG2 #7, ALARM STATUS .....................................................188

REGISTER A7H, C7H, E7H: VTPP, TU3 OR TU #1 IN TUG2 #1 TO

TUG2 #7, AIS INTERRUPT ...............................................................191

REGISTER A8H-AEH, C8H-CEH, E8H-EEH: VTPP, TU #2 IN TUG2

#1 TO TUG2 #7, ALARM STATUS .....................................................193

REGISTER AFH, CFH, EFH: VTPP, TU #2 IN TUG2 #1 TO TUG2

#7 AIS INTERRUPT ...........................................................................196

REGISTER B0H-B6H, D0H-D6H, F0H-F6H: VTPP, TU #3 IN TUG2

#1 TO TUG2 #7, ALARM STATUS .....................................................197

REGISTER B7H, D7H, F7H: VTPP, TU #3 IN TUG2 #1 TO TUG2

#7, AIS INTERRUPT ..........................................................................200

REGISTER B8H-BEH, D8H-DEH, F8H-FEH: VTPP, TU #4 IN TUG2

#1 TO TUG2 #7, ALARM STATUS .....................................................201

REGISTER BFH, DFH, FFH: VTPP, TU #4 IN TUG2 #1 TO TUG2

#7, AIS INTERRUPT ..........................................................................204

REGISTER 100H, 200H, 300H: RTOP, TU3 OR TU #1 IN TUG2 #1,

CONFIGURATION .............................................................................205

REGISTER 101H, 201H, 301H: RTOP, TU3 OR TU #1 IN TUG2 #1,

CONFIGURATION AND ALARM STATUS .........................................208

REGISTER 102H, 202H, 302H: RTOP, TU3 OR TU #1 IN TUG2 #1,

EXPECTED PATH SIGNAL LABEL....................................................211

REGISTER 103H, 203H, 303H: RTOP, TU3 OR TU #1 IN TUG2 #1,

ACCEPTED PATH SIGNAL LABEL ...................................................212

REGISTER 104H, 204H, 304H: RTOP, TU3 OR TU #1 IN TUG2 #1,

BIP-2/BIP-8 ERROR COUNT LSB.....................................................213

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE vii

PM5363 TUPP+622

TUPP+622

DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

REGISTER 105H, 205H, 305H: RTOP, TU3 OR TU #1 IN TUG2 #1,

BIP-2/BIP-8 ERROR COUNT MSB....................................................213

REGISTER 106H, 206H, 306H: RTOP, TU3 OR TU #1 IN TUG2 #1,

REI ERROR COUNT LSB..................................................................215

REGISTER 107H, 207H, 307H: RTOP, TU3 OR TU #1 IN TUG2 #1,

REI ERROR COUNT MSB.................................................................215

REGISTER 108H, 110H, 118H, 120H, 128H, 130H: REGISTER

208H, 210H, 218H, 220H, 228H, 230H: REGISTER 308H, 310H, 318H, 320H, 328H, 330H: RTOP, TU #1 IN TUG2 #2

TO TUG2 #7, CONFIGURATION.......................................................217

REGISTER 109H, 111H, 119H, 121H, 129H, 131H: REGISTER

209H, 211H, 219H, 221H, 229H, 231H: REGISTER 309H, 311H, 319H, 321H, 329H, 331H: RTOP, TU #1 IN TUG2 #2

TO TUG2 #7, CONFIGURATION AND ALARM STATUS ...................220

REGISTER 10AH, 112H, 11AH, 122H, 12AH, 132H: REGISTER

20AH, 212H, 21AH, 222H, 22AH, 232H: REGISTER 30AH, 312H, 31AH, 322H, 32AH, 332H: RTOP, TU #1 IN TUG2 #2

TO TUG2 #7, EXPECTED PATH SIGNAL LABEL .............................223

REGISTER 10BH, 113H, 11BH, 123H, 12BH, 133H: REGISTER

20BH, 213H, 21BH, 223H, 22BH, 233H: REGISTER 30BH, 313H, 31BH, 323H, 32BH, 333H: RTOP, TU #1 IN TUG2 #2

TO TUG2 #7, ACCEPTED PATH SIGNAL LABEL .............................224

REGISTER 10CH, 114H, 11CH, 124H, 12CH, 134H: REGISTER

20CH, 214H, 21CH, 224H, 22CH, 234H: REGISTER 30CH, 314H, 31CH, 324H, 32CH, 334H: RTOP, TU #1 IN TUG2 #2

TO TUG2 #7, BIP-2 ERROR COUNT LSB ........................................225

REGISTER 10DH, 115H, 11DH, 125H, 12DH, 135H: REGISTER

20DH, 215H, 21DH, 225H, 22DH, 235H: REGISTER 30DH, 315H, 31DH, 325H, 32DH, 335H: RTOP, TU #1 IN TUG2 #2

TO TUG2 #7, BIP-2 ERROR COUNT MSB .......................................225

REGISTER 10EH, 116H, 11EH, 126H, 12EH, 136H: REGISTER

20EH, 216H, 21EH, 226H, 22EH, 236H: REGISTER 30EH,

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE viii

PM5363 TUPP+622

TUPP+622

DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

316H, 31EH, 326H, 32EH, 336H: TU #1 IN TUG2 #2 TO

TUG2 #7, REI ERROR COUNT LSB .................................................227

REGISTER 10FH, 117H, 11FH, 127H, 12FH, 137H: REGISTER

20FH, 217H, 21FH, 227H, 22FH, 237H: REGISTER 30FH, 317H, 31FH, 327H, 32FH, 337H: TU #1 IN TUG2 #2 TO

TUG2 #7, REI ERROR COUNT MSB ................................................227

REGISTER 138H, 238H, 338H: RTOP, TU3 OR TU #1 IN TUG2 #1

TO TUG2 #7, COPSL INTERRUPT ...................................................229

REGISTER 139H, 239H, 339H: RTOP, TU3 OR TU #1 IN TUG2 #1

TO TUG2 #7, PSLM INTERRUPT .....................................................231

REGISTER 13AH, 23AH, 33AH: RTOP, TU3 OR TU #1 IN TUG2 #1

TO TUG2 #7, PSLU INTERRUPT......................................................233

REGISTER 13BH, 23BH, 33BH: RTOP, TU3 OR TU #1 IN TUG2 #1

TO TUG2 #7, RDI INTERRUPT .........................................................235

REGISTER 13CH, 23CH, 33CH: RTOP, TU3 AUXILIARY RDI

INTERRUPT OR TU #1 IN TUG2 #1 TO TUG2 #7 RFI

INTERRUPT ......................................................................................237

REGISTER 13DH, 23DH, 33DH: RTOP, TU #1 IN TUG2 #1 TO

TUG2 #7, IN BAND ERROR REPORTING

CONFIGURATION .............................................................................239

REGISTER 13EH, 23EH, 33EH: RTOP, TU3 OR TU #1 IN TUG2 #1

TO TUG2 #7, CONTROLLABLE OUTPUT

CONFIGURATION .............................................................................240

REGISTER 140H, 148H, 150H, 158H, 160H, 168H, 170H:

REGISTER 240H, 248H, 250H, 258H, 260H, 268H, 270H: REGISTER 340H, 348H, 350H, 358H, 360H, 368H, 370H:

RTOP, TU #2 IN TUG2 #1 TO TUG2 #7, CONFIGURATION.............241

REGISTER 141H, 149H, 151H, 159H, 161H, 169H, 171H:

REGISTER 241H, 249H, 251H, 259H, 261H, 269H, 271H: REGISTER 341H, 349H, 351H, 359H, 361H, 369H, 371H:

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ix

PM5363 TUPP+622

TUPP+622

DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

RTOP, TU #2 IN TUG2 #1 TO TUG2 #7, CONFIGURATION

AND ALARM STATUS........................................................................244

REGISTER 142H, 14AH, 152H, 15AH, 162H, 16AH, 172H:

REGISTER 242H, 24AH, 252H, 25AH, 262H, 26AH, 272H: REGISTER 342H, 34AH, 352H, 35AH, 362H, 36AH, 372H: RTOP, TU #2 IN TUG2 #1 TO TUG2 #7, EXPECTED PATH

SIGNAL LABEL ..................................................................................247

REGISTER 143H, 14BH, 153H, 15BH, 163H, 16BH, 173H:

REGISTER 243H, 24BH, 253H, 25BH, 263H, 26BH, 273H: REGISTER 343H, 34BH, 353H, 35BH, 363H, 36BH, 373H: RTOP, TU #2 IN TUG2 #1 TO TUG2 #7, ACCEPTED PATH

SIGNAL LABEL ..................................................................................248

REGISTER 144H, 14CH, 154H, 15CH, 164H, 16CH, 174H:

REGISTER 244H, 24CH, 254H, 25CH, 264H, 26CH, 274H: REGISTER 344H, 34CH, 354H, 35CH, 364H, 36CH, 374H: RTOP, TU #2 IN TUG2 #1 TO TUG2 #7, BIP-2 ERROR

COUNT LSB.......................................................................................249

REGISTER 145H, 14DH, 155H, 15DH, 165H, 16DH, 175H:

REGISTER 245H, 24DH, 255H, 25DH, 265H, 26DH, 275H: REGISTER 345H, 34DH, 355H, 35DH, 365H, 36DH, 375H: RTOP, TU #2 IN TUG2 #1 TO TUG2 #7, BIP-2 ERROR

COUNT MSB......................................................................................249

REGISTER 146H, 14EH, 156H, 15EH, 166H, 16EH, 176H:

REGISTER 246H, 24EH, 256H, 25EH, 266H, 26EH, 276H: REGISTER 346H, 34EH, 356H, 35EH, 366H, 36EH, 376H: RTOP, TU #2 IN TUG2 #1 TO TUG2 #7, REI ERROR

COUNT LSB.......................................................................................251

REGISTER 147H, 14FH, 157H, 15FH, 167H, 16FH, 177H:

REGISTER 247H, 24FH, 257H, 25FH, 267H, 26FH, 277H: REGISTER 347H, 34FH, 357H, 35FH, 367H, 36FH, 377H: RTOP, TU #2 IN TUG2 #1 TO TUG2 #7, REI ERROR

COUNT MSB......................................................................................251

REGISTER 178H, 278H, 378H: RTOP, TU #2 IN TUG2 #1 TO

TUG2 #7, COPSL INTERRUPT .........................................................253

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE x

PM5363 TUPP+622

TUPP+622

DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

REGISTER 179H, 279H, 379H: RTOP, TU #2 IN TUG2 #1 TO

TUG2 #7, PSLM INTERRUPT ...........................................................254

REGISTER 17AH, 27AH, 37AH: RTOP, TU #2 IN TUG2 #1 TO

TUG2 #7, PSLU INTERRUPT............................................................255

REGISTER 17BH, 27BH, 37BH: RTOP, TU #2 IN TUG2 #1 TO

TUG2 #7, RDI INTERRUPT...............................................................256

REGISTER 17CH, 27CH, 37CH: RTOP, TU #2 IN TUG2 #1 TO

TUG2 #7, RFI INTERRUPT ...............................................................257

REGISTER 17DH, 27DH, 37DH: RTOP, TU #2 IN TUG2 #1 TO

TUG2 #7, IN BAND ERROR REPORTING

CONFIGURATION .............................................................................258

REGISTER 17EH, 27EH, 37EH: TU #2 IN TUG2 #1 TO TUG2 #7,

CONTROLLABLE OUTPUT CONFIGURATION ................................259

REGISTER 180H, 188H, 190H, 198H, 1A0H, 1A8H, 1B0H:

REGISTER 280H, 288H, 290H, 298H, 2A0H, 2A8H, 2B0H: REGISTER 380H, 388H, 390H, 398H, 3A0H, 3A8H, 3B0H:

RTOP, TU #3 IN TUG2 #1 TO TUG2 #7, CONFIGURATION.............260

REGISTER 181H, 189H, 191H, 199H, 1A1H, 1A9H, 1B1H:

REGISTER 281H, 289H, 291H, 299H, 2A1H, 2A9H, 2B1H: REGISTER 381H, 389H, 391H, 399H, 3A1H, 3A9H, 3B1H: RTOP, TU #3 IN TUG2 #1 TO TUG2 #7, CONFIGURATION

AND ALARM STATUS........................................................................263

REGISTER 182H, 18AH, 192H, 19AH, 1A2H, 1AAH, 1B2H:

REGISTER 282H, 28AH, 292H, 29AH, 2A2H, 2AAH, 2B2H: REGISTER 382H, 38AH, 392H, 39AH, 3A2H, 3AAH, 3B2H: RTOP, TU #3 IN TUG2 #1 TO TUG2 #7, EXPECTED PATH

SIGNAL LABEL ..................................................................................266

REGISTER 183H, 18BH, 193H, 19BH, 1A3H, 1ABH, 1B3H:

REGISTER 283H, 28BH, 293H, 29BH, 2A3H, 2ABH, 2B3H: REGISTER 383H, 38BH, 393H, 39BH, 3A3H, 3ABH, 3B3H: RTOP, TU #3 IN TUG2 #1 TO TUG2 #7, ACCEPTED PATH

SIGNAL LABEL ..................................................................................267

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE xi

PM5363 TUPP+622

TUPP+622

DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

REGISTER 184H, 18CH, 194H, 19CH, 1A4H, 1ACH, 1B4H:

REGISTER 284H, 28CH, 294H, 29CH, 2A4H, 2ACH, 2B4H: REGISTER 384H, 38CH, 394H, 39CH, 3A4H, 3ACH, 3B4H: RTOP, TU #3 IN TUG2 #1 TO TUG2 #7, BIP-2 ERROR

COUNT LSB.......................................................................................268

REGISTER 185H, 18DH, 195H, 19DH, 1A5H, 1ADH, 1B5H:

REGISTER 285H, 28DH, 295H, 29DH, 2A5H, 2ADH, 2B5H: REGISTER 385H, 38DH, 395H, 39DH, 3A5H, 3ADH, 3B5H: RTOP, TU #3 IN TUG2 #1 TO TUG2 #7, BIP-2 ERROR

COUNT MSB......................................................................................268

REGISTER 186H, 18EH, 196H, 19EH, 1A6H, 1AEH, 1B6H:

REGISTER 286H, 28EH, 296H, 29EH, 2A6H, 2AEH, 2B6H: REGISTER 386H, 38EH, 396H, 39EH, 3A6H, 3AEH, 3B6H:

TU #3 IN TUG2 #1 TO TUG2 #7, REI ERROR COUNT LSB.............270

REGISTER 187H, 18FH, 197H, 19FH, 1A7H, 1AFH, 1B7H:

REGISTER 287H, 28FH, 297H, 29FH, 2A7H, 2AFH, 2B7H: REGISTER 387H, 38FH, 397H, 39FH, 3A7H, 3AFH, 3B7H: RTOP, TU #3 IN TUG2 #1 TO TUG2 #7, REI ERROR

COUNT MSB......................................................................................270

REGISTER 1B8H, 2B8H, 3B8H: RTOP, TU #3 IN TUG2 #1 TO

TUG2 #7, COPSL INTERRUPT .........................................................272

REGISTER 1B9H, 2B9H, 3B9H: RTOP, TU #3 IN TUG2 #1 TO

TUG2 #7, PSLM INTERRUPT ...........................................................273

REGISTER 1BAH, 2BAH, 3BAH: RTOP, TU #3 IN TUG2 #1 TO

TUG2 #7, PSLU INTERRUPT............................................................274

REGISTER 1BBH, 2BBH, 3BBH: RTOP, TU #3 IN TUG2 #1 TO

TUG2 #7, RDI INTERRUPT...............................................................275

REGISTER 1BCH, 2BCH, 3BCH: RTOP, TU #3 IN TUG2 #1 TO

TUG2 #7, RFI INTERRUPT ...............................................................276

REGISTER 1BDH, 2BDH, 3BDH: RTOP, TU #3 IN TUG2 #1 TO

TUG2 #7, IN BAND ERROR REPORTING

CONFIGURATION .............................................................................277

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE xii

PM5363 TUPP+622

TUPP+622

DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

REGISTER 1BEH, 2BEH, 3BEH: RTOP, TU #3 IN TUG2 #1 TO

TUG2 #7, CONTROLLABLE OUTPUT CONFIGURATION................278

REGISTER 1C0H, 1C8H, 1D0H, 1D8H, 1E0H, 1E8H, 1F0H:

REGISTER 2C0H, 2C8H, 2D0H, 2D8H, 2E0H, 2E8H, 2F0H: REGISTER 3C0H, 3C8H, 3D0H, 3D8H, 3E0H, 3E8H, 3F0H:

RTOP, TU #4 IN TUG2 #1 TO TUG2 #7, CONFIGURATION.............279

REGISTER 1C1H, 1C9H, 1D1H, 1D9H, 1E1H, 1E9H, 1F1H:

REGISTER 2C1H, 2C9H, 2D1H, 2D9H, 2E1H, 2E9H, 2F1H: REGISTER 3C1H, 3C9H, 3D1H, 3D9H, 3E1H, 3E9H, 3F1H: RTOP, TU #4 IN TUG2 #1 TO TUG2 #7, CONFIGURATION

AND ALARM STATUS........................................................................281

REGISTER 1C2H, 1CAH, 1D2H, 1DAH, 1E2H, 1EAH, 1F2H:

REGISTER 2C2H, 2CAH, 2D2H, 2DAH, 2E2H, 2EAH, 2F2H: REGISTER 3C2H, 3CAH, 3D2H, 3DAH, 3E2H, 3EAH, 3F2H: RTOP, TU #4 IN TUG2 #1 TO TUG2 #7, EXPECTED PATH

SIGNAL LABEL ..................................................................................284

REGISTER 1C3H, 1CBH, 1D3H, 1DBH, 1E3H, 1EBH, 1F3H:

REGISTER 2C3H, 2CBH, 2D3H, 2DBH, 2E3H, 2EBH, 2F3H: REGISTER 3C3H, 3CBH, 3D3H, 3DBH, 3E3H, 3EBH, 3F3H: RTOP, TU #4 IN TUG2 #1 TO TUG2 #7, PATH SIGNAL

LABEL................................................................................................285

REGISTER 1C4H, 1CCH, 1D4H, 1DCH, 1E4H, 1ECH, 1F4H:

REGISTER 2C4H, 2CCH, 2D4H, 2DCH, 2E4H, 2ECH, 2F4H: REGISTER 3C4H, 3CCH, 3D4H, 3DCH, 3E4H, 3ECH, 3F4H: RTOP, TU #4 IN TUG2 #1 TO TUG2 #7, BIP-2

ERROR COUNT LSB.........................................................................286

REGISTER 1C5H, 1CDH, 1D5H, 1DDH, 1E5H, 1EDH, 1F5H:

REGISTER 2C5H, 2CDH, 2D5H, 2DDH, 2E5H, 2EDH, 2F5H: REGISTER 3C5H, 3CDH, 3D5H, 3DDH, 3E5H, 3EDH, 3F5H: RTOP, TU #4 IN TUG2 #1 TO TUG2 #7, BIP-2

ERROR COUNT MSB........................................................................286

REGISTER 1C6H, 1CEH, 1D6H, 1DEH, 1E6H, 1EEH, 1F6H:

REGISTER 2C6H, 2CEH, 2D6H, 2DEH, 2E6H, 2EEH, 2F6H: REGISTER 3C6H, 3CEH, 3D6H, 3DEH, 3E6H, 3EEH, 3F6H:

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE xiii

PM5363 TUPP+622

TUPP+622

DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

RTOP, TU #4 IN TUG2 #1 TO TUG2 #7, REI ERROR

COUNT LSB.......................................................................................288

REGISTER 1C7H, 1CFH, 1D7H, 1DFH, 1E7H, 1EFH, 1F7H:

REGISTER 2C7H, 2CFH, 2D7H, 2DFH, 2E7H, 2EFH, 2F7H: REGISTER 3C7H, 3CFH, 3D7H, 3DFH, 3E7H, 3EFH, 3F7H: RTOP, TU #4 IN TUG2 #1 TO TUG2 #7, REI ERROR

COUNT MSB......................................................................................288

REGISTER 1F8H, 2F8H, 3F8H: RTOP, TU #4 IN TUG2 #1 TO

TUG2 #7, COPSL INTERRUPT .........................................................290

REGISTER 1F9H, 2F9H, 3F9H: RTOP, TU #4 IN TUG2 #1 TO

TUG2 #7, PSLM INTERRUPT ...........................................................291

REGISTER 1FAH, 2FAH, 3FAH: RTOP, TU #4 IN TUG2 #1 TO

TUG2 #7, PSLU INTERRUPT............................................................292

REGISTER 1FBH, 2FBH, 3FBH: RTOP, TU #4 IN TUG2 #1 TO

TUG2 #7, RDI INTERRUPT...............................................................293

REGISTER 1FCH, 2FCH, 3FCH: RTOP, TU #4 IN TUG2 #1 TO

TUG2 #7, RFI INTERRUPT ...............................................................294

REGISTER 1FDH, 2FDH, 3FDH: RTOP, TU #4 IN TUG2 #1 TO

TUG2 #7, IN BAND ERROR REPORTING

CONFIGURATION .............................................................................295

REGISTER 1FEH, 2FEH, 3FEH: RTOP, TU #4 IN TUG2 #1 TO

TUG2 #7, CONTROLLABLE OUTPUT CONFIGURATION................296

REGISTER 1FFH, 2FFH, 3FFH: RTOP STATUS .........................................297

REGISTER 400H, 440H, 480H: RTTB, TU3 OR TU #1 IN TUG2 #1,

CONFIGURATION AND STATUS ......................................................298

REGISTER 401H-406H, 441H-446H, 481H-486H: RTTB, TU #1 IN

TUG2 #2 TO TUG2 #7, CONFIGURATION AND STATUS.................300

REGISTER 408H-40EH, 448H-44EH, 488H-48EH: RTTB, TU #2 IN

TUG2 #1 TO TUG2 #7, CONFIGURATION AND STATUS.................302

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REGISTER 410H-416H, 450H-456H, 490H-496H: RTTB, TU #3 IN

TUG2 #1 TO TUG2 #7, CONFIGURATION AND STATUS.................304

REGISTER 418H-41EH, 458H-45EH, 498H-49EH: RTTB, TU #4 IN

TUG2 #1 TO TUG2 #7, CONFIGURATION AND STATUS.................306

REGISTER 420H, 460H, 4A0H: RTTB, TU3 OR TU #1 IN TUG2 #1

TO TUG2 #7, TIM INTERRUPT .........................................................308

REGISTER 421H, 461H, 4A1H: RTTB, TU #2 IN TUG2 #1 TO

TUG2 #7, TIM INTERRUPT...............................................................310

REGISTER 422H, 462H, 4A2H: RTTB, TU #3 IN TUG2 #1 TO

TUG2 #7, TIM INTERRUPT............................................................... 311

REGISTER 423H, 463H, 4A3H: RTTB, TU #4 IN TUG2 #1 TO

TUG2 #7, TIM INTERRUPT...............................................................312

REGISTER 424H, 464H, 4A4H: RTTB, TU3 OR TU #1 IN TUG2 #1

TO TUG2 #7, TIU INTERRUPT .........................................................313

REGISTER 425H, 465H, 4A5H: RTTB, TU #2 IN TUG2 #1 TO

TUG2 #7, TIU INTERRUPT ...............................................................315

REGISTER 426H, 466H, 4A6H: RTTB, TU #3 IN TUG2 #1 TO

TUG2 #7, TIU INTERRUPT ...............................................................316

REGISTER 427H, 467H, 4A7H: RTTB, TU #4 IN TUG2 #1 TO

TUG2 #7, TIU INTERRUPT ...............................................................317

REGISTER 428H, 468H, 4A8H: RTTB, TIU THRESHOLD...........................318

REGISTER 429H, 469H, 4A9H: RTTB, INDIRECT TRIBUTARY

SELECT .............................................................................................320

REGISTER 42AH, 46AH, 4AAH: RTTB, INDIRECT ADDRESS

SELECT .............................................................................................322

REGISTER 42BH, 46BH, 4ABH: RTTB, INDIRECT DATA SELECT ............324

REGISTER 2000H: MASTER TEST.............................................................329

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REGISTER 2001H: STP SELECT ................................................................331

TEST REGISTER 2002H: (WRITE IN I/O TEST MODE)..............................333

TEST REGISTER 2003H: (WRITE IN I/O TEST MODE)..............................334

TEST REGISTER 2004H: (WRITE IN I/O TEST MODE)..............................335

TEST REGISTER 2005H: (WRITE IN I/O TEST MODE)..............................336

TEST REGISTER 2006H: (WRITE IN I/O TEST MODE)..............................337

TEST REGISTER 2802H: (WRITE IN I/O TEST MODE)..............................338

TEST REGISTER 2803H: (WRITE IN I/O TEST MODE)..............................339

TEST REGISTER 2804H: (WRITE IN I/O TEST MODE)..............................340

TEST REGISTER 2805H: (WRITE IN I/O TEST MODE)..............................341

TEST REGISTER 2806H: (WRITE IN I/O TEST MODE)..............................342

TEST REGISTER 3002H: (WRITE IN I/O TEST MODE)..............................343

TEST REGISTER 3003H: (WRITE IN I/O TEST MODE)..............................344

TEST REGISTER 3004H: (WRITE IN I/O TEST MODE)..............................345

TEST REGISTER 3005H: (WRITE IN I/O TEST MODE)..............................346

TEST REGISTER 3006H: (WRITE IN I/O TEST MODE)..............................347

TEST REGISTER 3802H: (WRITE IN I/O TEST MODE)..............................348

TEST REGISTER 3803H: (WRITE IN I/O TEST MODE)..............................349

TEST REGISTER 3804H: (WRITE IN I/O TEST MODE)..............................350

TEST REGISTER 3805H: (WRITE IN I/O TEST MODE)..............................351

TEST REGISTER 3806H: (WRITE IN I/O TEST MODE)..............................352

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DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

TEST REGISTER 2002H: (READ IN I/O TEST MODE) ...............................353

TEST REGISTER 2003H: (READ IN I/O TEST MODE) ...............................354

TEST REGISTER 2004H: (READ IN I/O TEST MODE) ...............................355

TEST REGISTER 2802H: (READ IN I/O TEST MODE) ...............................356

TEST REGISTER 2803H: (READ IN I/O TEST MODE) ...............................357

TEST REGISTER 2804H: (READ IN I/O TEST MODE) ...............................358

TEST REGISTER 3002H: (READ IN I/O TEST MODE) ...............................359

TEST REGISTER 3003H: (READ IN I/O TEST MODE) ...............................360

TEST REGISTER 3004H: (READ IN I/O TEST MODE) ...............................361

TEST REGISTER 3802H: (READ IN I/O TEST MODE) ...............................362

TEST REGISTER 3803H: (READ IN I/O TEST MODE) ...............................363

TEST REGISTER 3804H: (READ IN I/O TEST MODE) ...............................364

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PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

LIST OF FIGURES

FIGURE 1 - STS-12 (STM-4) AGGREGATE INTERFACE WITH

TRIBUTARY PROCESSING AND PERFORMANCE MONITORING................9

FIGURE 2 - QUAD STS-3 (STM-1) AGGREGATE INTERFACE WITH TRIBUTARY PROCESSING AND PERFORMANCE

MONITORING ................................................................................................10

FIGURE 3 - STS-48 (STM-16) AGGREGATE INTERFACE WITH

TRIBUTARY PROCESSING AND PERFORMANCE MONITORING.............. 11

FIGURE 4 - STM-4 (STS-12) ORDER OF BYTE TRANSMISSION ..............89

FIGURE 5 - POINTER INTERPRETATION STATE DIAGRAM......................93

FIGURE 6 - POINTER GENERATION STATE DIAGRAM.............................98

FIGURE 7 - INPUT OBSERVATION CELL (INPUT, CLOCK INPUT) ..........374

FIGURE 8 - OUTPUT CELL (OUTPUT, CLOCK OUTPUT,

OUTPUT ENABLE).......................................................................................374

FIGURE 9 - BIDIRECTIONAL CELL (IO_CELL)..........................................375

FIGURE 10- I/O CELL (I/O WITH OE PAIR).................................................375

FIGURE 11 - SONET STS-3 CARRYING VT1.5 WITHIN STS-1 ..................378

FIGURE 12- SDH STM-1 CARRYING TU12 WITHIN VC3/AU3 ..................379

FIGURE 13- SDH STM-1 CARRYING TU12 WITHIN TUG3/AU4 ................379

FIGURE 14- SDH STM-1 CARRYING TU3 WITHIN TUG3..........................380

FIGURE 15- SDH STM-1 CARRYING MIX OF TU11, TU12, TU3

WITHIN TUG3/AU4.......................................................................................381

FIGURE 16- BOUNDARY SCAN ARCHITECTURE.....................................383

FIGURE 17- TAP CONTROLLER FINITE STATE MACHINE.......................385

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INTERFACES

FIGURE 18- STM-1 INPUT BUS TIMING - SIMPLE STS-1/AU3 CASE 390

FIGURE 19- STM-1 INPUT BUS TIMING - COMPLEX STS-1 / AU3 CASE 391

FIGURE 20- STM-1 INPUT BUS TIMING - STS-1 / AU3 (VT/TU

POINTER INTERPRETATION DISABLED) ..................................................392

FIGURE 21- STM-1 INPUT BUS TIMING - AU4 CASE................................393

FIGURE 22- STM-4 INPUT BUS TIMING - STS-1/AU3 CASE.....................394

FIGURE 23- STM-1 OUTPUT BUS TIMING - STS-1 SPES / AU3 VCS CASE 396

FIGURE 24- STM-1 OUTPUT BUS TIMING - AU4 VC CASE......................398

FIGURE 25- STM-4 OUTPUT BUS TIMING - STS-1 SPES / AU3 VCS CASE 399

FIGURE 26- STM-1 (STS-3) INTERFACE, BY-PASSED AND

NORMAL TRANSPORT FRAME DELAY FUNCTIONAL TIMING.................400

FIGURE 27- STM-4 (STS-12) INTERFACE, BY-PASSED AND

NORMAL TRANSPORT FRAME DELAY FUNCTIONAL TIMING.................401

FIGURE 28- TRIBUTARY PATH OVERHEAD SERIALIZATION

FUNCTIONAL TIMING..................................................................................404

FIGURE 29- RECEIVE ALARM PORT FUNCTIONAL TIMING....................407

FIGURE 30- MICROPROCESSOR INTERFACE READ ACCESS

TIMING (INTEL MODE)................................................................................413

FIGURE 31- MICROPROCESSOR INTERFACE READ ACCESS

TIMING (MOTOROLA MODE)......................................................................414

FIGURE 32- MICROPROCESSOR INTERFACE WRITE ACCESS

TIMING (INTEL MODE)................................................................................417

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DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

FIGURE 33- MICROPROCESSOR INTERFACE WRITE ACCESS

TIMING (MOTOROLA MODE)......................................................................418

FIGURE 34- INPUT TIMING.........................................................................422

FIGURE 35- STREAM OUTPUT TIMING .....................................................425

FIGURE 36- PATH OVERHEAD OUTPUT TIMING......................................427

FIGURE 37- JTAG PORT INTERFACE TIMING...........................................429

FIGURE 38- THETA JA VS. AIRFLOW PLOT ..............................................432

FIGURE 39- MECHANICAL DRAWING 304 PIN SUPER BALL

GRID ARRAY (SBGA)...................................................................................434

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DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

LIST OF TABLES

TABLE 1 - PATH SIGNAL LABEL MISMATCH STATE..............................102

TABLE 2 - REGISTER MEMORY MAP.....................................................107

TABLE 3 - TEST MODE REGISTER MEMORY MAP ...............................325

TABLE 4 - INSTRUCTION REGISTER (LENGTH – 3 BITS) ....................364

TABLE 5 -IDENTIFICATION REGISTER ..................................................365

TABLE 6 BOUNDARY SCAN REGISTER (LENGTH – 218 BITS)............365

TABLE 7 -TUPP+622 ABSOLUTE MAXIMUM RATINGS .............................408

TABLE 8 -TUPP+622 D.C. CHARACTERISTICS.........................................409

TABLE 9 - MICROPROCESSOR INTERFACE READ ACCESS...............412

TABLE 10 - MICROPROCESSOR INTERFACE WRITE ACCESS .............416

TABLE 11 - TUPP+622 INPUT TIMING FOR SCLK (FIGURE 34) .............420

TABLE 12 - TUPP+622 INPUT TIMING HSCLK (FIGURE 34) ...................421

TABLE 13 - TUPP+622 STREAM OUTPUT................................................424

TABLE 14 - TUPP+622 PATH OVERHEAD OUTPUT (FIGURE 36)...........426

TABLE 15 - JTAG PORT INTERFACE (FIGURE 37) ..................................428

TABLE 16 - ORDERING INFORMATION....................................................431

TABLE 17 - THERMAL INFORMATION – THETA JC..................................431

TABLE 18 - MAXIMUM JUNCTION TEMPERATURE.................................431

TABLE 19 - THERMAL INFORMATION – THETA JA VS. AIRFLOW 432

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PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

1 FEATURES

• Configurable, multi-channel, payload processor for aligning SONET virtual tributaries (VTs) (SDH tributary units, TUs) in an STS-12 or four STS-3 (an STM-4 or four STM-1) byte serial data streams.

• Four TUPP+622 may be used in parallel to support STS-48 (STM-16) applications.

• Transfers all incoming tributaries in the twelve STS-1 synchronous payload envelopes of an STS-12 or four STS-3 byte serial streams to the corresponding twelve STS-1 synchronous payload envelopes of an outgoing STS-12 or four outgoing STS-3 byte serial streams.

• Transfers all incoming tributaries in the four AU4 or twelve AU3 administrative units of an STM-4 or four STM-1 byte serial streams to the corresponding four AU4 or twelve AU3 administrative units of an outgoing STM-4 or four outgoing STM-1 byte serial streams.

• Compensates for pleisiochronous relationships between incoming and outgoing higher level (STS-1, AU4, AU3) payload frame rates through processing of the lower level (VT6, VT3, VT2, VT1.5, TU3, TU2, TU12, or TU11) tributary pointers.

• Provides software configurable offset between the payload frame boundaries and the transport frame boundary on a per STS-3 or STM-1 basis.

• Optionally bypasses the tributary pointer interpretation function. Tributary payload frame boundaries and payload bytes are identified by signals coincident with the incoming data stream.

• Configurable to process any legal mix of VT1.5, VT2, VT3, VT6, TU11, TU12, TU2, or TU3 tributaries. Each VT group or TUG2 can be configured to carry one of four tributary types. TUG2s can be multiplexed into VC3s or TUG3s. Each TUG3 can also be configured to carry a single TU3.

• Independently configurable for AU3 or AU4 frame format on incoming and outgoing interfaces.

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DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

• Configurable to process 16-byte or 64-byte format tributary path trace messages (tributary trail trace identifiers).

• Optionally frames to the H4 byte in the path overhead to determine tributary multiframe boundaries. Inserts internally generated H4 bytes with leading logic 1 bits into the outgoing administrative units.

• Extracts and serializes the entire tributary path overhead of each tributary into lower speed serial streams.

• Extracts tributary size (SS) bits of each tributary into internal registers.

• Detects loss of pointer (LOP) and re-acquisition for each tributary and

optionally generates interrupts.

• Detects tributary path alarm indication signal (AIS) and return to normal state for each tributary and optionally generates interrupts.

• Detects tributary elastic store underflow and overflow errors and optionally generates interrupts.

• Extracts tributary path trace message (trail trace identifier) of each tributary into internal buffers.

• Provides individual tributary path trace message buffer that holds the expected message and detects tributary path trace mismatch (trail trace identifier mismatch) alarms (TIM) and return to matched state for each tributary and optionally generates interrupts.

• Detects tributary path trace unstable (trail trace identifier unstable) alarms (TIU) and return to stable state for each tributary and optionally generates interrupts.

• Extracts tributary path signal label for each tributary into internal registers and detects change of tributary path signal label events (COPSL) of each tributary and optionally generates interrupts.

• Provides individual tributary path signal label register that hold the expected label and detects tributary path signal label mismatch alarms (PSLM) and return to matched state for each tributary and optionally generates interrupts.

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DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

• Detects tributary path signal label unstable alarms (PSLU) and return to stable state for each tributary and optionally generates interrupts.

• Detects tributary unequipped defect (UNEQ) and tributary path defect indication (PDI-V).

• Detects assertion and removal of tributary extended remote defect indications (RDI) for each tributary and optionally generates interrupts.

• Calculates and compares the tributary path BIP-2 error detection code for each tributary and configurable to accumulate the BIP-2 errors, on block or bit basis, in internal registers.

• Calculates and compares the TU3 path BIP-8 error detection code for each TU3 stream and accumulates the BIP-8 errors, on block or bit basis, in internal registers.

• Accumulates TU3 tributary remote error indications (REI) on a bit or a block basis, in internal registers.

• Allows insertion of all-zeros or all-ones tributary idle code with unequipped indication and valid pointer into any tributary under software control. Idle tributaries are identified by an output signal.

• Identifies outgoing tributaries that are in AIS state by an output signal. Allows software to force the AIS insertion on a per tributary basis.

• Inserts valid H4 byte and all-zeros fixed stuff bytes on the outgoing stream. Remaining path overhead bytes (J1, B3, C2, G1, F2, Z3, Z4, and Z5) can be configured to be set to all-zeros or to reflect the value of the corresponding POH bytes in the incoming stream.

• Inserts valid pointers (H1, H2), framing bytes (A1, A2), and all-zeros transport overhead bytes on the outgoing stream with valid "TeleCombus" control signals.

• Supports in-band error reporting by updating the REI, RDI and auxiliary RDI bits in the V5 byte (G1 in TU3) with the status of the incoming stream.

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PM5363 TUPP+622

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DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

• Provides low maximum tributary processing delay of 33 µs for VT1.5, 25 µs for VT2, 17 µs for VT3, and 9 µs for VT6 streams.

• Verifies parity on the IC1J1 and IPL signals and on the incoming data stream and generates parity on the outgoing data stream.

• May be used for multiframe synchronization or ring closure at the head-end node of a SONET/SDH ring.

• Operates in conjunction with the PM5313 SPECTRA-622 SONET/SDH Payload Extractor/Aligner For 622 Mbit/s or the PM5342 SPECTRA-155 SONET/SDH Payload Extractor/Aligner to align tributaries such that they can be switched by the PM5371 TUDX SONET/SDH Tributary Unit CrossConnect. Provides backwards compatibility with the PM5362 TUPP SONET/SDH Tributary Unit Payload Processor / Performance Monitor.

• Independently configurable incoming and outgoing interfaces that operate in the19.44 MHz STM-1 (STS-3) or the 77.76 MHz STM-4 (STS-12) byte interface modes.

• Provides a generic 8-bit microprocessor bus interface for configuration, control, and status monitoring.

• Provides a standard 5 signal IEEE P1149.1 JTAG test port for boundary scan test purposes.

• Low power, +2.5 Volt, CMOS technology, +3.3 Volt TTL compatible inputs and outputs (5V tolerant).

• 304 pin Super BGA package.

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PM5363 TUPP+622

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DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

2 APPLICATIONS

• SONET/SDH Digital Cross-Connect

• SONET/SDH Add-Drop Multiplexer

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TUPP+622

DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

3 REFERENCES

1. American National Standard for Telecommunications – Synchronous Optical Network (SONET) – Basic Description Including Multiplex Structures, Rates, and Formats, ANSI T1.105-1995.

2. Committee T1 Contribution, "Draft of T1.105 - SONET Rates and Formats", T1X1.5/94-033R2-1994.

3. Committee T1 Contribution, "Payload Defect Indication (PDI): triggers, Switch Priorities, Timing and Proposed Text", T1X1.5/94-135R1, 1994.

4. Committee T1 Contribution, "Proposed ITU-T Contribution on Enhanced Path RDI for SDH", T1X1.5/94-117, 1994.

5. ITU, Recommendation G.708 - "Network Node Interface For The Synchronous Digital Hierarchy", 1993.

6. ITU, Recommendation G.709 - "Synchronous Multiplexing Structure", 1993.

7. ITU, Recommendation G.782 - "Types and general characteristics of synchronous digital hierarchy (SDH) equipment", January 1994.

8. ITU, Recommendation G.783 - "Characteristics of synchronous digital hierarchy (SDH) equipment functional blocks", April 1997.

9. Bell Communications Research - SONET Transport Systems: Common Generic Criteria, TR-TSY-000253, Issue 2, December 1991.

10. Bell Communications Research - SONET Transport Systems: Common Generic Criteria, GR-253-CORE, Issue 2, Rev. 1, December 1997.

11. Bell Communications Research - SONET Add-Drop Multiplex Equipment (SONET ADM) Generic Criteria, GR-496, Issue 1, December 1998.

12. Bell Communications Research - SONET Dual-Fed Unidirectional Path Switched Ring (UPSR) Equipment Generic Criteria, GR-1400-CORE, Issue 2, January 1999.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 6

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DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

13. European Telecommunications Standards Institute, Transmission and Multiplexing (TM); Generic Functional Requirements for SDH Transmission Equipment, Part 1, Generic Process and Performance, ETS 300 417-1-1, January 1996.

14. PMC-981215 “PM669 (0.25um RAM test chip) and P25 (Galax! I/O test chip) Rev. A Characterization Report”. Issue 1. February 9, 1999.

15. PMC-1991211 “PM5363-BI Rev. A (TUPP+622) Characterization Report”. Issue 1. March 27, 2000.

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PMC PM5363-BI Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

REVISION HISTORY

CONTENTS

LIST OF REGISTERS

LIST OF FIGURES