Datasheet PM5363-BI Datasheet (PMC)

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PM5363 TUPP+622

TUPP+622

DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

PM5363

TUPP+622

SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR

FOR 622 MBIT/S INTERFACES

DATASHEET

RELEASED

ISSUE 4: JULY 2000

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

PM5363 TUPP+622

TUPP+622

DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

REVISION HISTORY

Issue

Issue Date Details of Change

No.

Issue 4 July 2000 Update for revision B device.

De-document TU3 Inband Error feature. Added changes to timing and operating conditions. All Input Hold Times for SCLK (19.44MHz) are changed from 1ns to

1.5ns. All Output Max Prop Delays for HSCLK (77.76MHz) changed from 8ns to 9ns. All Output Min Prop Delay for SCLK (19.44MHz) changed from 2ns to 3.5ns. Operating Condition for V

DD3.3

changed

from 3.3V ± 10% to 3.3V ±

0.3V and operating condition for V

changed from 2.5V

DD2.5

± 10% to 2.5V ± 0.2V. TUGEN Bit and TUGBYP Bit description changed. Device ID Revision Number, SOS Bit description and Boundary Scan ID changed.

Issue 3 Nov 1999 Update Data-sheet portion to

preliminary.

Issue 2 May 1999 Update pin and register

description.

Issue 1 December

Document created.

1998

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

PM5363 TUPP+622

TUPP+622

DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

1 FEATURES ............................................................................................1

2 APPLICATIONS .....................................................................................5

3 REFERENCES.......................................................................................6

4 DEFINITIONS ........................................................................................8

5 APPLICATION EXAMPLES ...................................................................9

5.1 STS-12 (STM-4) AGGREGATE INTERFACE..............................9

5.2 QUAD STS-3 (STM-1) AGGREGATE INTERFACE ..................10

5.3 STS-48 (STM-16) AGGREGATE INTERFACE..........................11

5.4 TUPP-PLUS COMPATIBILITY AND TUPP+622

FEATURE ENHANCEMENTS...................................................12

6 DESCRIPTION.....................................................................................13

7 PIN DIAGRAM .....................................................................................15

8 BLOCK DIAGRAM ...............................................................................16

9 PIN DESCRIPTION (304) ....................................................................17

10 FUNCTIONAL DESCRIPTION.............................................................88

10.1 INPUT BUS DEMULTIPLEXER ................................................89

10.2 OUTPUT BUS MULTIPLEXER..................................................90

10.3 TRIBUTARY PAYLOAD PROCESSOR (VTPP).........................91

10.3.1 CLOCK GENERATOR....................................................91

10.3.2 INCOMING TIMING GENERATOR.................................91

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TUPP+622

DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

10.3.3 INCOMING MULTIFRAME DETECTOR.........................92

10.3.4 POINTER INTERPRETER .............................................92

10.3.5 PAYLOAD BUFFER........................................................96

10.3.6 OUTGOING TIMING GENERATOR ...............................96

10.3.7 POINTER GENERATOR ................................................97

10.4 TRIBUTARY PATH OVERHEAD PROCESSOR

(RTOP)....................................................................................100

10.4.1 CLOCK GENERATOR..................................................101

10.4.2 TIMING GENERATOR .................................................101

10.4.3 ERROR MONITOR.......................................................101

10.4.4 IN-BAND ERROR REPORT .........................................103

10.4.5 EXTRACT.....................................................................104

10.5 TRIBUTARY TRACE BUFFER (RTTB) ...................................104

10.5.1 CLOCK GENERATOR..................................................104

10.5.2 TIMING GENERATOR .................................................105

10.5.3 EXTRACT.....................................................................105

10.5.4 ALARM MONITOR .......................................................105

10.5.5 BUFFER .......................................................................106

10.6 JTAG TEST ACCESS PORT...................................................106

10.7 MICROPROCESSOR INTERFACE ........................................107

11 NORMAL MODE REGISTER DESCRIPTION ................................... 117

11.1 TOP LEVEL CONFIGURATION REGISTERS......................... 118

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TUPP+622

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PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

11.2 VTPP #1, VTPP #2 AND VTPP #3 REGISTERS ....................169

11.3 RTOP #1, RTOP #2 AND RTOP #3 REGISTERS ...................205

11.4 RTTB #1, RTTB #2 AND RTTB #3 REGISTERS.....................298

12 TEST FEATURES DESCRIPTION.....................................................325

12.1 I/O TEST MODE......................................................................332

12.2 JTAG TEST PORT ..................................................................364

13 OPERATION ......................................................................................376

13.1 CONFIGURATION OPTIONS .................................................376

13.2 STS-1 MODE ..........................................................................378

13.3 AU3 MODE..............................................................................378

13.4 AU4 MODE..............................................................................379

13.5 BYPASS OPTIONS .................................................................381

13.6 POWER SEQUENCING..........................................................382

13.7 JTAG SUPPORT .....................................................................382

13.7.1 TAP CONTROLLER .....................................................384

13.7.2 BOUNDARY SCAN INSTRUCTIONS...........................387

14 FUNCTIONAL TIMING.......................................................................389

15 ABSOLUTE MAXIMUM RATINGS .....................................................408

16 D.C. CHARACTERISTICS .................................................................409

17 MICROPROCESSOR INTERFACE TIMING

CHARACTERISTICS .........................................................................412

18 TUPP+622 TIMING CHARACTERISTICS .........................................420

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DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

19 ORDERING AND THERMAL INFORMATION....................................431

20 MECHANICAL INFORMATION ..........................................................434

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PM5363 TUPP+622

TUPP+622

DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

LIST OF REGISTERS

ACCUMULATION TRIGGER .............................................................122

LOM INTERRUPT ENABLE...............................................................134

INTERRUPT AND LOM STATUS .......................................................136

INDICATION CONTROL ....................................................................152

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TUPP+622

DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

INDICATION CONTROL ....................................................................154

CONTROL .........................................................................................157

CONFIGURATION AND STATUS ......................................................169

#2 TO TUG2 #7, CONFIGURATION AND STATUS ...........................172

TUG2 #7, LOP INTERRUPT..............................................................174

#1 TO TUG2 #7, CONFIGURATION AND STATUS ...........................176

#7, LOP INTERRUPT ........................................................................178

#1 TO TUG2 #7, CONFIGURATION AND STATUS ...........................179

#7, LOP INTERRUPT ........................................................................181

#1 TO TUG2 #7, CONFIGURATION AND STATUS ...........................182

#7, LOP INTERRUPT ........................................................................184

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TUPP+622

DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

ALARM STATUS ................................................................................185

#2 TO TUG2 #7, ALARM STATUS .....................................................188

TUG2 #7, AIS INTERRUPT ...............................................................191

#1 TO TUG2 #7, ALARM STATUS .....................................................193

#7 AIS INTERRUPT ...........................................................................196

#1 TO TUG2 #7, ALARM STATUS .....................................................197

#7, AIS INTERRUPT ..........................................................................200

#1 TO TUG2 #7, ALARM STATUS .....................................................201

#7, AIS INTERRUPT ..........................................................................204

CONFIGURATION .............................................................................205

CONFIGURATION AND ALARM STATUS .........................................208

EXPECTED PATH SIGNAL LABEL....................................................211

ACCEPTED PATH SIGNAL LABEL ...................................................212

BIP-2/BIP-8 ERROR COUNT LSB.....................................................213

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PM5363 TUPP+622

TUPP+622

DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

BIP-2/BIP-8 ERROR COUNT MSB....................................................213

REI ERROR COUNT LSB..................................................................215

REI ERROR COUNT MSB.................................................................215

208H, 210H, 218H, 220H, 228H, 230H: REGISTER 308H, 310H, 318H, 320H, 328H, 330H: RTOP, TU #1 IN TUG2 #2

TO TUG2 #7, CONFIGURATION.......................................................217

209H, 211H, 219H, 221H, 229H, 231H: REGISTER 309H, 311H, 319H, 321H, 329H, 331H: RTOP, TU #1 IN TUG2 #2

TO TUG2 #7, CONFIGURATION AND ALARM STATUS ...................220

20AH, 212H, 21AH, 222H, 22AH, 232H: REGISTER 30AH, 312H, 31AH, 322H, 32AH, 332H: RTOP, TU #1 IN TUG2 #2

TO TUG2 #7, EXPECTED PATH SIGNAL LABEL .............................223

20BH, 213H, 21BH, 223H, 22BH, 233H: REGISTER 30BH, 313H, 31BH, 323H, 32BH, 333H: RTOP, TU #1 IN TUG2 #2

TO TUG2 #7, ACCEPTED PATH SIGNAL LABEL .............................224

20CH, 214H, 21CH, 224H, 22CH, 234H: REGISTER 30CH, 314H, 31CH, 324H, 32CH, 334H: RTOP, TU #1 IN TUG2 #2

TO TUG2 #7, BIP-2 ERROR COUNT LSB ........................................225

20DH, 215H, 21DH, 225H, 22DH, 235H: REGISTER 30DH, 315H, 31DH, 325H, 32DH, 335H: RTOP, TU #1 IN TUG2 #2

TO TUG2 #7, BIP-2 ERROR COUNT MSB .......................................225

20EH, 216H, 21EH, 226H, 22EH, 236H: REGISTER 30EH,

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PM5363 TUPP+622

TUPP+622

DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

316H, 31EH, 326H, 32EH, 336H: TU #1 IN TUG2 #2 TO

TUG2 #7, REI ERROR COUNT LSB .................................................227

20FH, 217H, 21FH, 227H, 22FH, 237H: REGISTER 30FH, 317H, 31FH, 327H, 32FH, 337H: TU #1 IN TUG2 #2 TO

TUG2 #7, REI ERROR COUNT MSB ................................................227

TO TUG2 #7, COPSL INTERRUPT ...................................................229

TO TUG2 #7, PSLM INTERRUPT .....................................................231

TO TUG2 #7, PSLU INTERRUPT......................................................233

TO TUG2 #7, RDI INTERRUPT .........................................................235

INTERRUPT OR TU #1 IN TUG2 #1 TO TUG2 #7 RFI

INTERRUPT ......................................................................................237

TUG2 #7, IN BAND ERROR REPORTING

CONFIGURATION .............................................................................239

TO TUG2 #7, CONTROLLABLE OUTPUT

CONFIGURATION .............................................................................240

RTOP, TU #2 IN TUG2 #1 TO TUG2 #7, CONFIGURATION.............241

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PM5363 TUPP+622

TUPP+622

DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

RTOP, TU #2 IN TUG2 #1 TO TUG2 #7, CONFIGURATION

AND ALARM STATUS........................................................................244

REGISTER 242H, 24AH, 252H, 25AH, 262H, 26AH, 272H: REGISTER 342H, 34AH, 352H, 35AH, 362H, 36AH, 372H: RTOP, TU #2 IN TUG2 #1 TO TUG2 #7, EXPECTED PATH

SIGNAL LABEL ..................................................................................247

REGISTER 243H, 24BH, 253H, 25BH, 263H, 26BH, 273H: REGISTER 343H, 34BH, 353H, 35BH, 363H, 36BH, 373H: RTOP, TU #2 IN TUG2 #1 TO TUG2 #7, ACCEPTED PATH

SIGNAL LABEL ..................................................................................248

REGISTER 244H, 24CH, 254H, 25CH, 264H, 26CH, 274H: REGISTER 344H, 34CH, 354H, 35CH, 364H, 36CH, 374H: RTOP, TU #2 IN TUG2 #1 TO TUG2 #7, BIP-2 ERROR

COUNT LSB.......................................................................................249

REGISTER 245H, 24DH, 255H, 25DH, 265H, 26DH, 275H: REGISTER 345H, 34DH, 355H, 35DH, 365H, 36DH, 375H: RTOP, TU #2 IN TUG2 #1 TO TUG2 #7, BIP-2 ERROR

COUNT MSB......................................................................................249

REGISTER 246H, 24EH, 256H, 25EH, 266H, 26EH, 276H: REGISTER 346H, 34EH, 356H, 35EH, 366H, 36EH, 376H: RTOP, TU #2 IN TUG2 #1 TO TUG2 #7, REI ERROR

COUNT LSB.......................................................................................251

REGISTER 247H, 24FH, 257H, 25FH, 267H, 26FH, 277H: REGISTER 347H, 34FH, 357H, 35FH, 367H, 36FH, 377H: RTOP, TU #2 IN TUG2 #1 TO TUG2 #7, REI ERROR

COUNT MSB......................................................................................251

TUG2 #7, COPSL INTERRUPT .........................................................253

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TUPP+622

DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

TUG2 #7, PSLM INTERRUPT ...........................................................254

TUG2 #7, PSLU INTERRUPT............................................................255

TUG2 #7, RDI INTERRUPT...............................................................256

TUG2 #7, RFI INTERRUPT ...............................................................257

TUG2 #7, IN BAND ERROR REPORTING

CONFIGURATION .............................................................................258

CONTROLLABLE OUTPUT CONFIGURATION ................................259

RTOP, TU #3 IN TUG2 #1 TO TUG2 #7, CONFIGURATION.............260

REGISTER 281H, 289H, 291H, 299H, 2A1H, 2A9H, 2B1H: REGISTER 381H, 389H, 391H, 399H, 3A1H, 3A9H, 3B1H: RTOP, TU #3 IN TUG2 #1 TO TUG2 #7, CONFIGURATION

AND ALARM STATUS........................................................................263

REGISTER 282H, 28AH, 292H, 29AH, 2A2H, 2AAH, 2B2H: REGISTER 382H, 38AH, 392H, 39AH, 3A2H, 3AAH, 3B2H: RTOP, TU #3 IN TUG2 #1 TO TUG2 #7, EXPECTED PATH

SIGNAL LABEL ..................................................................................266

REGISTER 283H, 28BH, 293H, 29BH, 2A3H, 2ABH, 2B3H: REGISTER 383H, 38BH, 393H, 39BH, 3A3H, 3ABH, 3B3H: RTOP, TU #3 IN TUG2 #1 TO TUG2 #7, ACCEPTED PATH

SIGNAL LABEL ..................................................................................267

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PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

REGISTER 284H, 28CH, 294H, 29CH, 2A4H, 2ACH, 2B4H: REGISTER 384H, 38CH, 394H, 39CH, 3A4H, 3ACH, 3B4H: RTOP, TU #3 IN TUG2 #1 TO TUG2 #7, BIP-2 ERROR

COUNT LSB.......................................................................................268

REGISTER 285H, 28DH, 295H, 29DH, 2A5H, 2ADH, 2B5H: REGISTER 385H, 38DH, 395H, 39DH, 3A5H, 3ADH, 3B5H: RTOP, TU #3 IN TUG2 #1 TO TUG2 #7, BIP-2 ERROR

COUNT MSB......................................................................................268

TU #3 IN TUG2 #1 TO TUG2 #7, REI ERROR COUNT LSB.............270

REGISTER 287H, 28FH, 297H, 29FH, 2A7H, 2AFH, 2B7H: REGISTER 387H, 38FH, 397H, 39FH, 3A7H, 3AFH, 3B7H: RTOP, TU #3 IN TUG2 #1 TO TUG2 #7, REI ERROR

COUNT MSB......................................................................................270

TUG2 #7, COPSL INTERRUPT .........................................................272

TUG2 #7, PSLM INTERRUPT ...........................................................273

TUG2 #7, PSLU INTERRUPT............................................................274

TUG2 #7, RDI INTERRUPT...............................................................275

TUG2 #7, RFI INTERRUPT ...............................................................276

TUG2 #7, IN BAND ERROR REPORTING

CONFIGURATION .............................................................................277

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE xii

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TUPP+622

DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

TUG2 #7, CONTROLLABLE OUTPUT CONFIGURATION................278

RTOP, TU #4 IN TUG2 #1 TO TUG2 #7, CONFIGURATION.............279

REGISTER 2C1H, 2C9H, 2D1H, 2D9H, 2E1H, 2E9H, 2F1H: REGISTER 3C1H, 3C9H, 3D1H, 3D9H, 3E1H, 3E9H, 3F1H: RTOP, TU #4 IN TUG2 #1 TO TUG2 #7, CONFIGURATION

AND ALARM STATUS........................................................................281

REGISTER 2C2H, 2CAH, 2D2H, 2DAH, 2E2H, 2EAH, 2F2H: REGISTER 3C2H, 3CAH, 3D2H, 3DAH, 3E2H, 3EAH, 3F2H: RTOP, TU #4 IN TUG2 #1 TO TUG2 #7, EXPECTED PATH

SIGNAL LABEL ..................................................................................284

REGISTER 2C3H, 2CBH, 2D3H, 2DBH, 2E3H, 2EBH, 2F3H: REGISTER 3C3H, 3CBH, 3D3H, 3DBH, 3E3H, 3EBH, 3F3H: RTOP, TU #4 IN TUG2 #1 TO TUG2 #7, PATH SIGNAL

LABEL................................................................................................285

REGISTER 2C4H, 2CCH, 2D4H, 2DCH, 2E4H, 2ECH, 2F4H: REGISTER 3C4H, 3CCH, 3D4H, 3DCH, 3E4H, 3ECH, 3F4H: RTOP, TU #4 IN TUG2 #1 TO TUG2 #7, BIP-2

ERROR COUNT LSB.........................................................................286

REGISTER 2C5H, 2CDH, 2D5H, 2DDH, 2E5H, 2EDH, 2F5H: REGISTER 3C5H, 3CDH, 3D5H, 3DDH, 3E5H, 3EDH, 3F5H: RTOP, TU #4 IN TUG2 #1 TO TUG2 #7, BIP-2

ERROR COUNT MSB........................................................................286

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TUPP+622

DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

RTOP, TU #4 IN TUG2 #1 TO TUG2 #7, REI ERROR

COUNT LSB.......................................................................................288

REGISTER 2C7H, 2CFH, 2D7H, 2DFH, 2E7H, 2EFH, 2F7H: REGISTER 3C7H, 3CFH, 3D7H, 3DFH, 3E7H, 3EFH, 3F7H: RTOP, TU #4 IN TUG2 #1 TO TUG2 #7, REI ERROR

COUNT MSB......................................................................................288

TUG2 #7, COPSL INTERRUPT .........................................................290

TUG2 #7, PSLM INTERRUPT ...........................................................291

TUG2 #7, PSLU INTERRUPT............................................................292

TUG2 #7, RDI INTERRUPT...............................................................293

TUG2 #7, RFI INTERRUPT ...............................................................294

TUG2 #7, IN BAND ERROR REPORTING

CONFIGURATION .............................................................................295

TUG2 #7, CONTROLLABLE OUTPUT CONFIGURATION................296

CONFIGURATION AND STATUS ......................................................298

TUG2 #2 TO TUG2 #7, CONFIGURATION AND STATUS.................300

TUG2 #1 TO TUG2 #7, CONFIGURATION AND STATUS.................302

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DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

TUG2 #1 TO TUG2 #7, CONFIGURATION AND STATUS.................304

TUG2 #1 TO TUG2 #7, CONFIGURATION AND STATUS.................306

TO TUG2 #7, TIM INTERRUPT .........................................................308

TUG2 #7, TIM INTERRUPT...............................................................310

TUG2 #7, TIM INTERRUPT............................................................... 311

TUG2 #7, TIM INTERRUPT...............................................................312

TO TUG2 #7, TIU INTERRUPT .........................................................313

TUG2 #7, TIU INTERRUPT ...............................................................315

TUG2 #7, TIU INTERRUPT ...............................................................316

TUG2 #7, TIU INTERRUPT ...............................................................317

SELECT .............................................................................................320

SELECT .............................................................................................322

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PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

TEST REGISTER 2002H: (WRITE IN I/O TEST MODE)..............................333

TEST REGISTER 2003H: (WRITE IN I/O TEST MODE)..............................334

TEST REGISTER 2004H: (WRITE IN I/O TEST MODE)..............................335

TEST REGISTER 2005H: (WRITE IN I/O TEST MODE)..............................336

TEST REGISTER 2006H: (WRITE IN I/O TEST MODE)..............................337

TEST REGISTER 2802H: (WRITE IN I/O TEST MODE)..............................338

TEST REGISTER 2803H: (WRITE IN I/O TEST MODE)..............................339

TEST REGISTER 2804H: (WRITE IN I/O TEST MODE)..............................340

TEST REGISTER 2805H: (WRITE IN I/O TEST MODE)..............................341

TEST REGISTER 2806H: (WRITE IN I/O TEST MODE)..............................342

TEST REGISTER 3002H: (WRITE IN I/O TEST MODE)..............................343

TEST REGISTER 3003H: (WRITE IN I/O TEST MODE)..............................344

TEST REGISTER 3004H: (WRITE IN I/O TEST MODE)..............................345

TEST REGISTER 3005H: (WRITE IN I/O TEST MODE)..............................346

TEST REGISTER 3006H: (WRITE IN I/O TEST MODE)..............................347

TEST REGISTER 3802H: (WRITE IN I/O TEST MODE)..............................348

TEST REGISTER 3803H: (WRITE IN I/O TEST MODE)..............................349

TEST REGISTER 3804H: (WRITE IN I/O TEST MODE)..............................350

TEST REGISTER 3805H: (WRITE IN I/O TEST MODE)..............................351

TEST REGISTER 3806H: (WRITE IN I/O TEST MODE)..............................352

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE xvi

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DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

TEST REGISTER 2002H: (READ IN I/O TEST MODE) ...............................353

TEST REGISTER 2003H: (READ IN I/O TEST MODE) ...............................354

TEST REGISTER 2004H: (READ IN I/O TEST MODE) ...............................355

TEST REGISTER 2802H: (READ IN I/O TEST MODE) ...............................356

TEST REGISTER 2803H: (READ IN I/O TEST MODE) ...............................357

TEST REGISTER 2804H: (READ IN I/O TEST MODE) ...............................358

TEST REGISTER 3002H: (READ IN I/O TEST MODE) ...............................359

TEST REGISTER 3003H: (READ IN I/O TEST MODE) ...............................360

TEST REGISTER 3004H: (READ IN I/O TEST MODE) ...............................361

TEST REGISTER 3802H: (READ IN I/O TEST MODE) ...............................362

TEST REGISTER 3803H: (READ IN I/O TEST MODE) ...............................363

TEST REGISTER 3804H: (READ IN I/O TEST MODE) ...............................364

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PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

LIST OF FIGURES

FIGURE 1 - STS-12 (STM-4) AGGREGATE INTERFACE WITH

TRIBUTARY PROCESSING AND PERFORMANCE MONITORING................9

FIGURE 2 - QUAD STS-3 (STM-1) AGGREGATE INTERFACE WITH TRIBUTARY PROCESSING AND PERFORMANCE

MONITORING ................................................................................................10

FIGURE 3 - STS-48 (STM-16) AGGREGATE INTERFACE WITH

TRIBUTARY PROCESSING AND PERFORMANCE MONITORING.............. 11

FIGURE 4 - STM-4 (STS-12) ORDER OF BYTE TRANSMISSION ..............89

FIGURE 5 - POINTER INTERPRETATION STATE DIAGRAM......................93

FIGURE 6 - POINTER GENERATION STATE DIAGRAM.............................98

FIGURE 7 - INPUT OBSERVATION CELL (INPUT, CLOCK INPUT) ..........374

FIGURE 8 - OUTPUT CELL (OUTPUT, CLOCK OUTPUT,

OUTPUT ENABLE).......................................................................................374

FIGURE 9 - BIDIRECTIONAL CELL (IO_CELL)..........................................375

FIGURE 10- I/O CELL (I/O WITH OE PAIR).................................................375

FIGURE 11 - SONET STS-3 CARRYING VT1.5 WITHIN STS-1 ..................378

FIGURE 12- SDH STM-1 CARRYING TU12 WITHIN VC3/AU3 ..................379

FIGURE 13- SDH STM-1 CARRYING TU12 WITHIN TUG3/AU4 ................379

FIGURE 14- SDH STM-1 CARRYING TU3 WITHIN TUG3..........................380

FIGURE 15- SDH STM-1 CARRYING MIX OF TU11, TU12, TU3

WITHIN TUG3/AU4.......................................................................................381

FIGURE 16- BOUNDARY SCAN ARCHITECTURE.....................................383

FIGURE 17- TAP CONTROLLER FINITE STATE MACHINE.......................385

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INTERFACES

FIGURE 18- STM-1 INPUT BUS TIMING - SIMPLE STS-1/AU3 CASE 390

FIGURE 19- STM-1 INPUT BUS TIMING - COMPLEX STS-1 / AU3 CASE 391

FIGURE 20- STM-1 INPUT BUS TIMING - STS-1 / AU3 (VT/TU

POINTER INTERPRETATION DISABLED) ..................................................392

FIGURE 21- STM-1 INPUT BUS TIMING - AU4 CASE................................393

FIGURE 22- STM-4 INPUT BUS TIMING - STS-1/AU3 CASE.....................394

FIGURE 23- STM-1 OUTPUT BUS TIMING - STS-1 SPES / AU3 VCS CASE 396

FIGURE 24- STM-1 OUTPUT BUS TIMING - AU4 VC CASE......................398

FIGURE 25- STM-4 OUTPUT BUS TIMING - STS-1 SPES / AU3 VCS CASE 399

FIGURE 26- STM-1 (STS-3) INTERFACE, BY-PASSED AND

NORMAL TRANSPORT FRAME DELAY FUNCTIONAL TIMING.................400

FIGURE 27- STM-4 (STS-12) INTERFACE, BY-PASSED AND

NORMAL TRANSPORT FRAME DELAY FUNCTIONAL TIMING.................401

FIGURE 28- TRIBUTARY PATH OVERHEAD SERIALIZATION

FUNCTIONAL TIMING..................................................................................404

FIGURE 29- RECEIVE ALARM PORT FUNCTIONAL TIMING....................407

FIGURE 30- MICROPROCESSOR INTERFACE READ ACCESS

TIMING (INTEL MODE)................................................................................413

FIGURE 31- MICROPROCESSOR INTERFACE READ ACCESS

TIMING (MOTOROLA MODE)......................................................................414

FIGURE 32- MICROPROCESSOR INTERFACE WRITE ACCESS

TIMING (INTEL MODE)................................................................................417

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INTERFACES

FIGURE 33- MICROPROCESSOR INTERFACE WRITE ACCESS

TIMING (MOTOROLA MODE)......................................................................418

FIGURE 34- INPUT TIMING.........................................................................422

FIGURE 35- STREAM OUTPUT TIMING .....................................................425

FIGURE 36- PATH OVERHEAD OUTPUT TIMING......................................427

FIGURE 37- JTAG PORT INTERFACE TIMING...........................................429

FIGURE 38- THETA JA VS. AIRFLOW PLOT ..............................................432

FIGURE 39- MECHANICAL DRAWING 304 PIN SUPER BALL

GRID ARRAY (SBGA)...................................................................................434

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LIST OF TABLES

TABLE 1 - PATH SIGNAL LABEL MISMATCH STATE..............................102

TABLE 2 - REGISTER MEMORY MAP.....................................................107

TABLE 3 - TEST MODE REGISTER MEMORY MAP ...............................325

TABLE 4 - INSTRUCTION REGISTER (LENGTH – 3 BITS) ....................364

TABLE 5 -IDENTIFICATION REGISTER ..................................................365

TABLE 6 BOUNDARY SCAN REGISTER (LENGTH – 218 BITS)............365

TABLE 7 -TUPP+622 ABSOLUTE MAXIMUM RATINGS .............................408

TABLE 8 -TUPP+622 D.C. CHARACTERISTICS.........................................409

TABLE 9 - MICROPROCESSOR INTERFACE READ ACCESS...............412

TABLE 10 - MICROPROCESSOR INTERFACE WRITE ACCESS .............416

TABLE 11 - TUPP+622 INPUT TIMING FOR SCLK (FIGURE 34) .............420

TABLE 12 - TUPP+622 INPUT TIMING HSCLK (FIGURE 34) ...................421

TABLE 13 - TUPP+622 STREAM OUTPUT................................................424

TABLE 14 - TUPP+622 PATH OVERHEAD OUTPUT (FIGURE 36)...........426

TABLE 15 - JTAG PORT INTERFACE (FIGURE 37) ..................................428

TABLE 16 - ORDERING INFORMATION....................................................431

TABLE 17 - THERMAL INFORMATION – THETA JC..................................431

TABLE 18 - MAXIMUM JUNCTION TEMPERATURE.................................431

TABLE 19 - THERMAL INFORMATION – THETA JA VS. AIRFLOW 432

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1 FEATURES

• Configurable, multi-channel, payload processor for aligning SONET virtual tributaries (VTs) (SDH tributary units, TUs) in an STS-12 or four STS-3 (an STM-4 or four STM-1) byte serial data streams.

• Four TUPP+622 may be used in parallel to support STS-48 (STM-16) applications.

• Transfers all incoming tributaries in the twelve STS-1 synchronous payload envelopes of an STS-12 or four STS-3 byte serial streams to the corresponding twelve STS-1 synchronous payload envelopes of an outgoing STS-12 or four outgoing STS-3 byte serial streams.

• Transfers all incoming tributaries in the four AU4 or twelve AU3 administrative units of an STM-4 or four STM-1 byte serial streams to the corresponding four AU4 or twelve AU3 administrative units of an outgoing STM-4 or four outgoing STM-1 byte serial streams.

• Compensates for pleisiochronous relationships between incoming and outgoing higher level (STS-1, AU4, AU3) payload frame rates through processing of the lower level (VT6, VT3, VT2, VT1.5, TU3, TU2, TU12, or TU11) tributary pointers.

• Provides software configurable offset between the payload frame boundaries and the transport frame boundary on a per STS-3 or STM-1 basis.

• Optionally bypasses the tributary pointer interpretation function. Tributary payload frame boundaries and payload bytes are identified by signals coincident with the incoming data stream.

• Configurable to process any legal mix of VT1.5, VT2, VT3, VT6, TU11, TU12, TU2, or TU3 tributaries. Each VT group or TUG2 can be configured to carry one of four tributary types. TUG2s can be multiplexed into VC3s or TUG3s. Each TUG3 can also be configured to carry a single TU3.

• Independently configurable for AU3 or AU4 frame format on incoming and outgoing interfaces.

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• Configurable to process 16-byte or 64-byte format tributary path trace messages (tributary trail trace identifiers).

• Optionally frames to the H4 byte in the path overhead to determine tributary multiframe boundaries. Inserts internally generated H4 bytes with leading logic 1 bits into the outgoing administrative units.

• Extracts and serializes the entire tributary path overhead of each tributary into lower speed serial streams.

• Extracts tributary size (SS) bits of each tributary into internal registers.

• Detects loss of pointer (LOP) and re-acquisition for each tributary and

optionally generates interrupts.

• Detects tributary path alarm indication signal (AIS) and return to normal state for each tributary and optionally generates interrupts.

• Detects tributary elastic store underflow and overflow errors and optionally generates interrupts.

• Extracts tributary path trace message (trail trace identifier) of each tributary into internal buffers.

• Provides individual tributary path trace message buffer that holds the expected message and detects tributary path trace mismatch (trail trace identifier mismatch) alarms (TIM) and return to matched state for each tributary and optionally generates interrupts.

• Detects tributary path trace unstable (trail trace identifier unstable) alarms (TIU) and return to stable state for each tributary and optionally generates interrupts.

• Extracts tributary path signal label for each tributary into internal registers and detects change of tributary path signal label events (COPSL) of each tributary and optionally generates interrupts.

• Provides individual tributary path signal label register that hold the expected label and detects tributary path signal label mismatch alarms (PSLM) and return to matched state for each tributary and optionally generates interrupts.

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INTERFACES

• Detects tributary path signal label unstable alarms (PSLU) and return to stable state for each tributary and optionally generates interrupts.

• Detects tributary unequipped defect (UNEQ) and tributary path defect indication (PDI-V).

• Detects assertion and removal of tributary extended remote defect indications (RDI) for each tributary and optionally generates interrupts.

• Calculates and compares the tributary path BIP-2 error detection code for each tributary and configurable to accumulate the BIP-2 errors, on block or bit basis, in internal registers.

• Calculates and compares the TU3 path BIP-8 error detection code for each TU3 stream and accumulates the BIP-8 errors, on block or bit basis, in internal registers.

• Accumulates TU3 tributary remote error indications (REI) on a bit or a block basis, in internal registers.

• Allows insertion of all-zeros or all-ones tributary idle code with unequipped indication and valid pointer into any tributary under software control. Idle tributaries are identified by an output signal.

• Identifies outgoing tributaries that are in AIS state by an output signal. Allows software to force the AIS insertion on a per tributary basis.

• Inserts valid H4 byte and all-zeros fixed stuff bytes on the outgoing stream. Remaining path overhead bytes (J1, B3, C2, G1, F2, Z3, Z4, and Z5) can be configured to be set to all-zeros or to reflect the value of the corresponding POH bytes in the incoming stream.

• Inserts valid pointers (H1, H2), framing bytes (A1, A2), and all-zeros transport overhead bytes on the outgoing stream with valid "TeleCombus" control signals.

• Supports in-band error reporting by updating the REI, RDI and auxiliary RDI bits in the V5 byte (G1 in TU3) with the status of the incoming stream.

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INTERFACES

• Provides low maximum tributary processing delay of 33 µs for VT1.5, 25 µs for VT2, 17 µs for VT3, and 9 µs for VT6 streams.

• Verifies parity on the IC1J1 and IPL signals and on the incoming data stream and generates parity on the outgoing data stream.

• May be used for multiframe synchronization or ring closure at the head-end node of a SONET/SDH ring.

• Operates in conjunction with the PM5313 SPECTRA-622 SONET/SDH Payload Extractor/Aligner For 622 Mbit/s or the PM5342 SPECTRA-155 SONET/SDH Payload Extractor/Aligner to align tributaries such that they can be switched by the PM5371 TUDX SONET/SDH Tributary Unit CrossConnect. Provides backwards compatibility with the PM5362 TUPP SONET/SDH Tributary Unit Payload Processor / Performance Monitor.

• Independently configurable incoming and outgoing interfaces that operate in the19.44 MHz STM-1 (STS-3) or the 77.76 MHz STM-4 (STS-12) byte interface modes.

• Provides a generic 8-bit microprocessor bus interface for configuration, control, and status monitoring.

• Provides a standard 5 signal IEEE P1149.1 JTAG test port for boundary scan test purposes.

• Low power, +2.5 Volt, CMOS technology, +3.3 Volt TTL compatible inputs and outputs (5V tolerant).

• 304 pin Super BGA package.

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2 APPLICATIONS

• SONET/SDH Digital Cross-Connect

• SONET/SDH Add-Drop Multiplexer

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3 REFERENCES

1. American National Standard for Telecommunications – Synchronous Optical Network (SONET) – Basic Description Including Multiplex Structures, Rates, and Formats, ANSI T1.105-1995.

2. Committee T1 Contribution, "Draft of T1.105 - SONET Rates and Formats", T1X1.5/94-033R2-1994.

3. Committee T1 Contribution, "Payload Defect Indication (PDI): triggers, Switch Priorities, Timing and Proposed Text", T1X1.5/94-135R1, 1994.

4. Committee T1 Contribution, "Proposed ITU-T Contribution on Enhanced Path RDI for SDH", T1X1.5/94-117, 1994.

5. ITU, Recommendation G.708 - "Network Node Interface For The Synchronous Digital Hierarchy", 1993.

6. ITU, Recommendation G.709 - "Synchronous Multiplexing Structure", 1993.

7. ITU, Recommendation G.782 - "Types and general characteristics of synchronous digital hierarchy (SDH) equipment", January 1994.

8. ITU, Recommendation G.783 - "Characteristics of synchronous digital hierarchy (SDH) equipment functional blocks", April 1997.

9. Bell Communications Research - SONET Transport Systems: Common Generic Criteria, TR-TSY-000253, Issue 2, December 1991.

10. Bell Communications Research - SONET Transport Systems: Common Generic Criteria, GR-253-CORE, Issue 2, Rev. 1, December 1997.

11. Bell Communications Research - SONET Add-Drop Multiplex Equipment (SONET ADM) Generic Criteria, GR-496, Issue 1, December 1998.

12. Bell Communications Research - SONET Dual-Fed Unidirectional Path Switched Ring (UPSR) Equipment Generic Criteria, GR-1400-CORE, Issue 2, January 1999.

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INTERFACES

13. European Telecommunications Standards Institute, Transmission and Multiplexing (TM); Generic Functional Requirements for SDH Transmission Equipment, Part 1, Generic Process and Performance, ETS 300 417-1-1, January 1996.

14. PMC-981215 “PM669 (0.25um RAM test chip) and P25 (Galax! I/O test chip) Rev. A Characterization Report”. Issue 1. February 9, 1999.

15. PMC-1991211 “PM5363-BI Rev. A (TUPP+622) Characterization Report”. Issue 1. March 27, 2000.

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4 DEFINITIONS

The following table defines the abbreviations for the TUPP+622.

VTPP Tributary Payload Processor

RTOP Tributary Overhead Processor

RTTB Tributary Trace Buffer

STP STM-1 (STS-3) Tributary Processor

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5 APPLICATION EXAMPLES

The TUPP+622 can be used in SONET/SDH network elements including switches, terminal multiplexers, and add-drop multiplexers. In such applications, the TUPP+622 performs VT (TU) pointer processing to align the virtual tributaries to facilitate cross-connecting and SONET ring closure. The TUPP+622 also performs performance monitoring of any legal mix of tributaries to implement intermediate performance monitoring. The TUPP+622 is well suited to process data from one STS-12 (STM-4), four STS-3’s (STM-1’s) or one quarter of an STS-48 (STM-16).

5.1 STS-12 (STM-4) AGGREGATE INTERFACE

Figure 1 shows how the TUPP+622 is used to implement a single 77.76 MHz STS-12 (STM-4) aggregate interface. In this application, the PM5313 SPECTRA622 performs SONET/SDH section, line and path termination and the PM5363 TUPP+622 performs tributary pointer processing and performance monitoring.

Figure 1 - STS-12 (STM-4) Aggregate Interface with Tributary Processing and Performance Monitoring

622 Mbit/s Optical Interface

Optical

Transceiver

RXD+/SD TXD+/-

PM5313

SPECTRA-622

ACK

AD[7:0], ADP[1]

AC1J1V1[1]

APL[1]

DD[7:0], DDP[1]

DC1J1V1[1]

DPL[1]

DCK

ID[7:0], IDP[1]

IC1J1[1]

IPL[1]

HSCLK

PM5363

TUPP+622

OD[7:0], ODP[1]

OC1J1V1[1]

OPL[1]

77.76 MHz 8-bit

High Speed

Telecombus

Interface

Drop Add

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5.2 QUAD STS-3 (STM-1) AGGREGATE INTERFACE

The system side interface of the TUPP+622 can be configured to interface to four SPECTRA-155's Telecombus interface. Figure 2 shows how the TUPP+622 is connected to quad STS-3 (STM-1) aggregate interface using four 19.44 MHz Telecom buses on the system side interface. In this application, the PM5342 SPECTRA-155's perform SONET/SDH section, line and path termination and the PM5363 TUPP+622 performs tributary pointer processing and performance monitoring.

Figure 2 - Quad STS-3 (STM-1) Aggregate Interface with Tributary Processing and Performance Monitoring

155 Mbit/s Optical Interface

Optical

Transceiver

Optical

Transceiver

Optical

Transceiver

Optical

Transceiver

RXD+/SD TXD+/-

PM5342

SPECTRA-155

PM5342

SPECTRA-155

PM5342

SPECTRA-155

PM5342

SPECTRA-155

AD[7:0], ADP

AC1J1V1

DD[7:0], DDP

DC1J1V1

AD[7:0], ADP

AC1J1V1

DD[7:0], DDP

DC1J1V1

AD[7:0], ADP

AC1J1V1

DD[7:0], DDP

DC1J1V1

AD[7:0], ADP

AC1J1V1

DD[7:0], DDP

DC1J1V1

ACK

APL

DPL

DCK

ACK

APL

DPL

DCK

ACK

ID[31:24], IDP[4]

IC1J1[4]

IPL[4]

ID[23:16], IDP[3]

IC1J1[3]

IPL[3]

PM5363

TUPP+622

OD[31:24], ODP[4]

OC1J1V1[4]

OPL[4]

OD[23:16], ODP[3]

OC1J1V1[3]

OPL[3]

Four 19.44 MHz

8-bit

High Speed

Telecombus

APL

ID[15:8], IDP[2]

DPL

DCK

ACK

APL

DPL

DCK

IC1J1[2]

IPL[2]

ID[31:23], IDP[4]

ID[7:0], IDP[1]

IC1J1[4]

IC1J1[1]

IPL[4]

IPL[1]

SCLK

OD[15:8], ODP[2]

OC1J1V1[2]

OPL[2]

OD[7:0], ODP[1]

OC1J1V1[1]

OPL[1]

Interface

SCLK

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5.3 STS-48 (STM-16) AGGREGATE INTERFACE

Four PM5363 TUPP+622 devices can be connected to four PM5313 SPECTRA622 devices and an OC-48 front end transceiver device to implement an STS-48 (STM-16) aggregate interface. Figure 3 shows a block diagram for the STS-48 (STM-16) application. In this application, the OC-48 transceiver performs SONET/SDH section and line processing, the SPECTRA-622 devices perform SONET/SDH path processing, line rate decoupling, and pointer processing, and the TUPP+622 devices perform VT (TU) pointer processing and performance monitoring.

Figure 3 - STS-48 (STM-16) Aggregate Interface with Tributary Processing and Performance Monitoring

2488 Mbit/s Optical Interface

OC-48 Clock

Recovery

OC-48

Serial to

Parallel and

Parallel to

Serial

Conversion

POUT[7:0]

PIN[7:0]

OC-48 Front End

TOUT[7:0]

ROUT[7:0]

TOUT[7:0]

ROUT[7:0]

TOUT[7:0]

ROUT[7:0]

TOUT[7:0]

ROUT[7:0]

PM5313

SPECTRA-622

TFPO

TFPI

TD[7:0]

PIN[7:0]

ROFP

FPIN

PM5313

SPECTRA-622

TFPI

TD[7:0]

PIN[7:0]

ROFP

FPIN

PM5313

SPECTRA-622

TFPI

TD[7:0]

PIN[7:0]

ROFP

FPIN

PM5313

SPECTRA-622

TFPI

TD[7:0]

PIN[7:0]

ROFP

FPIN

AD[7:0], ADP[1]

AC1J1V1[1]

APL[1]

DD[7:0], DDP[1]

DC1J1V1[1]

DPL[1]

AD[7:0], ADP[1]

AC1J1V1[1]

APL[1]

DD[7:0], DDP[1]

DC1J1V1[1]

DPL[1]

AD[7:0], ADP[1]

AC1J1V1[1]

APL[1]

DD[7:0], DDP[1]

DC1J1V1[1]

DPL[1]

AD[7:0], ADP[1]

AC1J1V1[1]

APL[1]

DD[7:0], DDP[1]

DC1J1V1[1]

DPL[1]

ACK

PM5363

TUPP+622

OD[7:0], ODP[1]

ID[7:0], IDP[1]

IC1J1[1]

IPL[1]

DCK

HSCLK

ACK

ID[7:0], IDP[1]

IC1J1[1]

IPL[1]

DCK

HSCLK

ACK

ID[7:0], IDP[1]

IC1J1[1]

IPL[1]

DCK

HSCLK

ACK

ID[7:0], IDP[1]

IC1J1[1]

IPL[1]

DCK

HSCLK

PM5363

TUPP+622

PM5363

TUPP+622

PM5363

TUPP+622

OC1J1V1[1]

OPL[1]

GSCLK_FP

OD[7:0], ODP[1]

OC1J1V1[1]

OPL[1]

GSCLK_FP

OD[7:0], ODP[1]

OC1J1V1[1]

OPL[1]

GSCLK_FP

OD[7:0], ODP[1]

OC1J1V1[1]

OPL[1]

GSCLK_FP

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5.4 TUPP-PLUS Compatibility and TUPP+622 Feature Enhancements

The TUPP+622 (PM5363) supports software configuration of the payload frame alignment in the outgoing data stream. The high order path active offset may be set to any alignment on a per-STM-1 (STS-3) basis. For example, by setting the outgoing stream active offset contained in the STP Outgoing Pointer MSB and LSB registers in STM-1 (STS-3) Tributary Processor #1 (STP #1) to zero, the J1 byte(s) of the outgoing AU3/AU4 in STM-1 (STS-3) #1 will be aligned to the first payload byte(s) immediately following the H3 bytes. Similarly, the J1 byte(s) can be aligned to the payload byte(s) immediately after the J0/Z0 bytes of the section overhead by setting the outgoing stream active offset to 522. In the TUPP-PLUS (PM5362), arbitrary placement of payload frame boundaries, is supported by placing the device in floating mode and supplying the device with an outgoing payload active signal (OPL) and a payload frame alignment signal (J1 portion of OC1J1). Since the TUPP+622 supports this feature in software, floating mode is no longer required. Consequently, the OC1J1 and OPL signals are deleted. The transport frame alignment of the outgoing data stream corresponds to a delayed version of the incoming data stream. To improve signal naming consistency in the TUPP+622, the TUPP-PLUS equivalent LC1J1V1 and LPL signals are renamed to OC1J1V1 and OPL, respectively. An input generated system clock frame position (GSCLK_FP) signal is added to the TUPP+622 to enable externally alignment of the GSCLK generation and related internal operation of the device when the 77.76 MHz STM-4 interface mode is selected for the incoming or outgoing interface. This feature allows a deterministic transport frame delay through the TUPP+622 to be set. This is essential when multiple TUPP+622 devices have to be aligned in processing data streams with aggregate bandwidth greater than an STM-4.

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6 DESCRIPTION

The PM5363 TUPP+622 SONET/SDH Tributary Unit Payload Processor For 622 Mbit/s Interfaces is a monolithic integrated circuit that implements a configurable, multi-channel, payload processor that aligns and monitors performance of SONET virtual tributaries (VTs) or SDH tributary units (TUs.).

When configured for SONET compatible operation, the TUPP+622 transfers all incoming tributaries in the twelve STS-1 synchronous payload envelopes of an STS-12 or four STS-3 byte serial streams to the corresponding twelve STS-1 synchronous payload envelopes of an outgoing STS-12 or four outgoing STS-3 byte serial streams. Similarly, when configured for SDH compatible operation, the TUPP+622 transfers all incoming tributaries in the four AU4 or twelve AU3 administrative units of an STM-4 or four STM-1 byte serial streams to the corresponding four AU4 or twelve AU3 administrative units of an outgoing STM-4 or four outgoing STM-1 byte serial streams. The TUPP+622 compensates for pleisiochronous relationships between incoming and outgoing higher level (STS1, AU4, AU3) synchronous payload envelope frame rates through processing of the lower level (VT6, VT3, VT2, VT1.5, TU3, TU2, TU12, TU11) tributary pointers. The incoming and outgoing data streams are configurable independently.

The TUPP+622 is configurable to process any legal mix of tributaries. Each VT group can be configured to carry any one of the four tributary types (VT1.5, VT2, VT3, or VT6) and each TUG2 can be configured to carry any one of three tributary types (TU11, TU12, or TU2). TUG2s can be multiplexed into a VC3 or a TUG3. Alternatively, each TUG3 can be configured to carry a TU3.

The TUPP+622 operates in conjunction with the PM5313 SPECTRA-622 SONET/SDH Payload Extractor/Aligner For 622 Mbit/s or the PM5342 SPECTRA-155 SONET/SDH Payload Extractor/Aligner to align tributaries such that they can be switched by the PM5371 TUDX SONET/SDH Tributary Unit Cross-Connect.

The TUPP+622 provides useful maintenance functions. They include, for each tributary, detection of loss of pointer, detection of AIS alarm, detection of tributary path signal label mismatch and unstable alarms, detection of tributary path trace mismatch and unstable alarms. Optionally, interrupts can be generated due to the assertion and removal of any of the above alarm conditions. The TUPP+622 counts received tributary path BIP-2 (BIP-8 for TU3) errors on a block or bit basis

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 13

PM5363 TUPP+622

TUPP+622

DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

and counts REI indications. The TUPP+622 also allows insertion of tributary path AIS as a consequence of any of the above alarm conditions. In addition, the TUPP+622 may insert tributary idle (unequipped) into any tributary. Incoming tributary path trace messages and path signal labels are stored in a set of microprocessor accessible registers. The TUPP+622 can also insert inverted new data flag fields that can be used to diagnose downstream pointer processing elements.

No auxiliary high speed clocks are required as the TUPP+622 operates from either a single 19.44 MHz or a single 77.76 MHz line rate clock. The TUPP+622 is configured, controlled and monitored via a generic 8-bit microprocessor bus interface.

The TUPP+622 is implemented in low power, +2.5 Volt Core and +3.3 Volt I/O, CMOS technology. It has TTL compatible inputs and outputs and is packaged in a 304 pin SBGA package.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 14

PM5363 TUPP+622

TUPP+622

DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

7 PIN DIAGRAM

The TUPP+622 is packaged in a 304 pin SBGA package having a body size of 31 mm by 31 mm and a pin pitch of 1.27 mm.

2322212019181716151413121110987654321

VDD VSS POH[4] IAIS[2] IDP[2] VSS ID[12] VSS IC1J1[2] D[7] D[3] VSS D[0] A[11] A[8] VSS A[3] VSS ALE CSB TDO VSS VDD

VSS VDD VSS

POHFP

VSS VDD

[6]

OTMF[2] POH[6] POH[5] VDD

OD[8] VDDI12

VSS OD[9]

OD[14] OD[12] OD[10] OPL[2] OD[6] OTV5[1] VDDI1 AIS[1]

VSS OD[15] OD[13] OD[11] OTPL[1] IDLE[1] TPOH[1] VSS

OTPL[2] VDDI11 ODP[2] VDD VDD COUT[1] OTMF[1]

TPOH[2] IDLE[2] AIS[2] OTV5[2] HSCLK RAD[1] VDDI2

OC1J1V1

OPL[3]

[3]

VSS OD[16] OD[17] VDD VDD POH[2]

OD[18] VDDI10 OD[19] OD[20]

OD[21] OD[22] OD[23] OTV5[3] IPL[1]

ODP[3] OTPL[3] AIS[3] VDD VDD ID[1] ID[0] IC1J1[1]

VSS IDLE[3] TPOH[3] RAD[3] ID[5] ID[4] ID[2] VSS

COUT[3] VDDI9

VSS POH[7] POH[8] VDD VDD ITV5[1] ID[7] VSS

POHEN

[7]

[8]

POHFP

POHEN

[9]

IAIS[3] VSS VDD ITMF[3] ID[21] ID[18] IC1J1[3] COUT[4] AIS[4] OD[31] OD[27] OD[24] OTMF[4]

VSS VDD VSS ID[22] ID[19] IPL[3] VDDI8 IDLE[4] OTPL[4] OD[30] VDDI7 OD[25]

VDD VSS ID[23] ID[20] ID[16] VSS TPOH[4] VSS ODP[4] OD[29] OD[26] VSS OPL[4] POH[12]

2322212019181716151413121110987654321

POHFP

ITPL[2] ID[15] VDDI13 ID[10] ID[8] VDDI14 D[4] D[1] VDDI15 A[10] A[6] A[4] A[1] RDB VDDI16 TDI VSS VDD VSS

[4]

POHFP

RAD[2] ITV5[2] ID[14] ID[11] ID[9] INTB D[5] D[2] A[13] A[9] A[5] A[2] WRB MBEB TCK TMS VDD VSS OD[0]

[5]

POHEN

VDD ITMF[2] ID[13] VDD IPL[2] D[6] VDD A[12] A[7] VDD A[0] RSTB VDD TRSTB VDD

[4]

POHEN

[6]

[5]

OC1J1V1

VDD VDD OD[5] ODP[1] VSS

[2]

OTMF[3] COUT[2]

PM5363 TUPP+622

BOTTOM VIEW

POHFP

[7]

[8]

POH[9] ITPL[3] IPL[4]

ITV5[3] VDD IDP[3] VDD ID[17] NC2 VDD OTV5[4] OD[28] VDD

POHEN

POH[11] VDD IAIS[4] NC1 VDD ID[26] VDD ID[24]

[12]

POHFP

POHEN

POHFP

ITPL[4] IDP[4] ID[29] ID[25] VDD VSS IC1J1[4]

[10]

POH[10] VDDI5 ITV5[4] ID[31] ID[28] VSS VDD VSS

VSS RAD[4] VSS ITMF[4] ID[30] ID[27] VSS VDD

OC1J1V1

[4]

[12]

VDDI6

[10]

POHFP

[11]

POHEN

[11]

OPL[1] OD[2] OD[4] OD[7]

POH[1]

GSCLK

[1]

ITMF[1] ID[6] VDDI4 ID[3]

OC1J1V1

[1]

POHEN

[1]

GSCLK

[0]

POHEN

[3]

IHSMODEB

OD[1] OD[3]

GSCLK_FP

POHFP

[1]

POHFP

POHCK

[2]

POHEN

VSS

[2]

POHFP

VDDI3

[3]

POH[3] SCLK

ITPL[1] IDP[1]

OHSMODEB

IAIS[1]

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 15

PM5363 TUPP+622

TUPP+622

DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

8 BLOCK DIAGRAM

TCK

TMS

TDI

TRSTB

SCLK

HSCLK

IHSMODEB

OHSMODEB

GSCLK[1:0]

IC1J1[4:1]

IP L [4:1 ]

ITMF[4 :1]

ITPL[4:1]

ITV5[4:1]

IAIS [4:1]

IDP [4 :1 ]

ID[3 1:0 ]

JTAG

Controller

Inp u t

Demux

Tributary

Payload

Processor

(VTP P)

Tributary

Payload

Processor

(VTP P)

Tributary

Payload

Processor

(VTPP)

Tributary

Path

Overhead

Processor

(RTO P)

Tributary

Trace

Buffer

(RTTB)

Tributary

Path

Overhead

Processor

(RTO P)

Tributary

Trace Buffer

(RTTB)

Tributary

Path

Overhead Processor

(RTO P)

Tributary

Trace Buffer

(RTTB)

Output

Mux

TDO

OT M F[4:1] GSCLK_FP

ODP[4:1]

OT PL[4:1]

OT V5[4:1]

OD[31:0]

AIS[4:1]

IDLE[4:1]

COUT[4:1]

TPOH[4:1]

OC1J1V1[4:1]

OPL[4:1]

POH[12 :1]

POHFP[12:1]

POHEN[12:1]

POHCK

RAD[4:1]

MBEB

RSTB

CSB

RDB

WRB

ALE

Microprocessor

Inte rfac e

ST M -1 (STS-3) TRIBUTARY PROCESSOR (STP) #1, #2, #3, #4

INTB

A[13:0]

D[7:0]

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 16

PM5363 TUPP+622

TUPP+622

DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

9 PIN DESCRIPTION (304)

Pin Name Type Pin

Function

No.

SCLK/ Input P1 The system clock (SCLK) provides timing for

TUPP+622 internal operations. SCLK is a

19.44 MHz, nominally 50% duty cycle, clock. When either incoming interface is in STM-4 mode (IHSMODEB set low) or the outgoing interface is in STM-4 mode (OHSMODEB set low), SCLK must be connected to GSCLK[0] externally.

In incoming STM-1 (STS-3) interface mode (IHSMODEB set high), IC1J1[4:1], IPL[4:1], ITMF[4:1], IDP[4:1], ID[31:0], ITV5[4:1], ITPL[4:1], IAIS[4:1] and OTMF[4:1] are sampled on the rising edge of SCLK. In outgoing STM-1 (STS-3) interface mode (OHSMODEB set high), ODP[4:1], OTPL[4:1], OTV5[4:1], OD[31:0], AIS[4:1], IDLE[4:1], TPOH[4:1], OC1J1V1[4:1] and OPL[4:1] are updated on the rising edge of SCLK.

VCLK The test vector clock (VCLK) signal is used

during TUPP+622 production testing to verify manufacture.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 17

PM5363 TUPP+622

TUPP+622

DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

Pin Name Type Pin

Function

No.

HSCLK Input K4 The High-Speed STM-4 (STS-12) interface

mode system clock (HSCLK) provides timing for TUPP+622 internal operations in incoming or outgoing STM-4 (STS-12) interface mode (IHSMODEB or OHSMODEB set low). HSCLK is a 77.76 MHz, nominally 50% duty cycle, clock.

In incoming STM-4 (STS-12) interface mode (IHSMODEB set low), IC1J1[1], IPL[1], ITMF[1], IDP[1], ID[7:0], ITV5[1], ITPL[1] and IAIS[1] are sampled on the rising edge of HSCLK. In outgoing STM-4 (STS-12) interface mode (OHSMODEB set low), OTMF[1] and GSCLK_FP are sampled on the rising edge of HSCLK, and ODP[1], OTPL[1], OTV5[1], OD[7:0], AIS[1], IDLE[1], TPOH[1], OC1J1V1[1] and OPL[1] are updated on the rising edge of HSCLK. When the incoming and the outgoing interfaces are in STM-1 mode (IHSMODEB and OHSMODEB both set high), HSCLK may be left unconnected. HSCLK has an integral pull-up resistor.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 18

PM5363 TUPP+622

TUPP+622

DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

Pin Name Type Pin

Function

No.

IHSMODEB Input W3 The active low incoming High-Speed interface

mode signal (IHSMODEB) configures the incoming interface mode of the TUPP+622. When IHSMODEB is set low, the 77.76 MHz STM-4 (STS-12) interface mode is selected. SCLK must be connected to GSCLK[0]. IC1J1[1], IPL[1], ITMF[1], IDP[1], ID[7:0], ITV5[1], ITPL[1], IAIS[1] are sampled on the rising edge of HSCLK. When IHSMODEB is set high, the 19.44 MHz STM-1 (STS-3) interface mode is selected. IC1J1[4:1], IPL[4:1], ITMF[4:1], IDP[4:1], ID[31:0], ITV5[4:1], ITPL[4:1], IAIS[4:1] are sampled on the rising edge of SCLK. IHSMODEB has an integral pullup resistor.

OHSMODEB

Input Y2 The outgoing High-Speed interface mode signal

(OHSMODEB) configures the outgoing interface mode of the TUPP+622. When OHSMODEB is set low, the 77.76 MHz STM-4 (STS-12) interface mode is selected. SCLK must be connected to GSCLK[0]. OTMF[1] and GSCLK_FP are sampled on the rising edge of HSCLK. ODP[1], OTPL[1], OTV5[1], OD[7:0], AIS[1], IDLE[1], OC1J1V1[1] and OPL[1] are updated on the rising edge of HSCLK. When OHSMODEB is set high, the 19.44 MHz STM-1 (STS-3) interface mode is selected. OTMF[4:1] are sampled on the rising edge of SCLK. ODP[4:1], OTPL[4:1], OTV5[4:1], OD[31:0], AIS[4:1], IDLE[4:1], OC1J1V1[4:1] and OPL[4:1] are updated on the rising edge of SCLK. OHSMODEB has an integral pull-up resistor.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 19

PM5363 TUPP+622

TUPP+622

DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

Pin Name Type Pin

No.

GSCLK[1]

GSCLK[0]

Output N4

Function

The generated system clock (GSCLK[1:0]) signals provide timing for the TUPP+622 when STM-4 (STS-12) interface mode is selected at the incoming or outgoing interface (IHSMODEB or OHSMODEB set low). GSCLK[1:0] are a divide by four of HSCLK. GSCLK[0] must only be connected to SCLK externally when IHSMODEB or OHSMODEB is set low. GSCLK[1] is a exact replica of GSCLK[0] and can be used to supply timing to external devices that are operating in the 19.44 MHz STM-1 (STS-3) interface timing domain. GSCLK[1:0] are updated on the rising edge of HSCLK.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 20

PM5363 TUPP+622

TUPP+622

DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

Pin Name Type Pin

Function

No.

IC1J1[1] Input R1 The input C1/J1 frame pulse #1 (IC1J1[1])

identifies the transport envelope and synchronous payload envelope frame boundaries on the incoming STM-4 or STM-1 #1 stream (ID[7:0]).

In incoming STM-1 (STS-3) interface mode (IHSMODEB set high), IC1J1[1] is set high while IPL[1] is low to mark the first C1 byte of the STM-1 #1 transport envelope frame on the ID[7:0] bus. The C1 byte position must be coincident to the C1 byte positions of the STM-1 streams on ID[15:8], ID[23:16] and ID[31:24]. IC1J1[1] is set high while IPL[1] is high to mark each J1 byte of the synchronous payload envelope(s) on the ID[7:0] bus. IC1J1[1] must be present at every occurrence of the first C1 and all J1 bytes. The TUPP+622 will ignore a pulse on IC1J1[1] at the byte position of the V1 byte of the first tributary of each VC3 or the top byte of the first fixed stuff column of each TUG3. IC1J1[1] is sampled on the rising edge of SCLK.

In incoming STM-4 (STS-12) interface mode (IHSMODEB set low), IC1J1[1] is set high while IPL[1] is low to mark the first C1 byte of the STM-4 transport envelope frame on the ID[7:0] bus. IC1J1[1] is set high while IPL[1] is high to mark each J1 byte of the synchronous payload envelopes on the ID[7:0] bus. IC1J1[1] must be present at every occurrence of the first C1 and all J1 bytes. The TUPP+622 will ignore a pulse on IC1J1[1] at the byte position of the V1 byte of the first tributary of each VC3 or the top byte of the first fixed stuff column of each TUG3. IC1J1[1] is sampled on the rising edge of HSCLK.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 21

PM5363 TUPP+622

TUPP+622

DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

Pin Name Type Pin

Function

No.

IC1J1[2] Input A15 The input C1/J1 frame pulse #2 (IC1J1[2])

identifies the transport envelope and synchronous payload envelope frame boundaries on the incoming STM-1 #2 stream (ID[15:8]).

In incoming STM-1 (STS-3) interface mode (IHSMODEB set high), IC1J1[2] is set high while IPL[2] is low to mark the first C1 byte of the STM-1 #2 transport envelope frame on the ID[15:8] bus. The C1 byte position must be coincident to the C1 byte positions of the STM-1 streams on ID[7:0], ID[23:16] and ID[31:24]. IC1J1[2] is set high while IPL[2] is high to mark each J1 byte of the synchronous payload envelope(s) on the ID[15:8] bus. IC1J1[2] must be present at every occurrence of the first C1 and all J1 bytes. The TUPP+622 will ignore a pulse on IC1J1[2] at the byte position of the V1 byte of the first tributary of each VC3 or the top byte of the first fixed stuff column of each TUG3. IC1J1[2] is sampled on the rising edge of SCLK.

In incoming STM-4 (STS-12) interface mode (IHSMODEB set low), IC1J1[2] is unused and must be strapped low.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 22

PM5363 TUPP+622

TUPP+622

DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

Pin Name Type Pin

No.

IC1J1[3] Input

AA17

Function

The input C1/J1 frame pulse #3 (IC1J1[3]) identifies the transport envelope and synchronous payload envelope frame boundaries on the incoming STM-1 #3 stream (ID[23:16]).

In incoming STM-1 (STS-3) interface mode (IHSMODEB set high), IC1J1[3] is set high while IPL[3] is low to mark the first C1 byte of the STM-1 #3 transport envelope frame on the ID[23:16] bus. The C1 byte position must be coincident to the C1 byte positions of the STM-1 streams on ID[7:0], ID[15:8] and ID[31:24]. IC1J1[3] is set high while IPL[3] is high to mark each J1 byte of the synchronous payload envelope(s) on the ID[23:16] bus. IC1J1[3] must be present at every occurrence of the first C1 and all J1 bytes. The TUPP+622 will ignore a pulse on IC1J1[3] at the byte position of the V1 byte of the first tributary of each VC3 or the top byte of the first fixed stuff column of each TUG3. IC1J1[3] is sampled on the rising edge of SCLK.

In incoming STM-4 (STS-12) interface mode (IHSMODEB set low), IC1J1[3] is unused and must be strapped low.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 23

PM5363 TUPP+622

TUPP+622

DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

Pin Name Type Pin

Function

No.

IC1J1[4] Input AA1 The input C1/J1 frame pulse #4 (IC1J1[4])

identifies the transport envelope and synchronous payload envelope frame boundaries on the incoming STM-1 #4 stream (ID[31:24]).

In incoming STM-1 (STS-3) interface mode (IHSMODEB set high), IC1J1[4] is set high while IPL[4] is low to mark the first C1 byte of the STM-1 #4 transport envelope frame on the ID[31:24] bus. The C1 byte position must be coincident to the C1 byte positions of the STM-1 streams on ID[7:0], ID[15:8] and ID[23:16]. IC1J1[4] is set high while IPL[4] is high to mark each J1 byte of the synchronous payload envelope(s) on the ID[31:24] bus. IC1J1[4] must be present at every occurrence of the first C1 and all J1 bytes. The TUPP+622 will ignore a pulse on IC1J1[4] at the byte position of the V1 byte of the first tributary of each VC3 or the top byte of the first fixed stuff column of each TUG3. IC1J1[4] is sampled on the rising edge of SCLK.

In incoming STM-4 (STS-12) interface mode (IHSMODEB set low), IC1J1[4] is unused and must be strapped low.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 24

PM5363 TUPP+622

TUPP+622

DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

Pin Name Type Pin

Function

No.

IPL[1] Input P4 The active high incoming payload active #1

(IPL[1]) signal identifies the bytes within the transport envelope frame on the incoming STM4 or STM-1 #1 stream that carry VC3 or VC4 virtual containers, or STS-1 synchronous payload envelopes.

In incoming STM-1 (STS-3) interface mode (IHSMODEB set high), IPL[1] must be brought high to mark each payload byte on ID[7:0]. IPL[1] is sampled on the rising edge of SCLK.

In incoming STM-4 (STS-12) interface mode (IHSMODEB set low), IPL[1] must be brought high to mark each payload byte on ID[7:0]. IPL[1] is sampled on the rising edge of HSCLK.

IPL[2] Input D14 The active high incoming payload active #2

(IPL[2]) signal identifies the bytes within the transport envelope frame on the incoming STM1 #2 stream that carry VC3 or VC4 virtual containers, or STS-1 synchronous payload envelopes.

In incoming STM-1 (STS-3) interface mode (IHSMODEB set high), IPL[2] must be brought high to mark each payload byte on ID[15:8]. IPL[2] is sampled on the rising edge of SCLK.

In incoming STM-4 (STS-12) interface mode (IHSMODEB set low), IPL[2] is unused and must be strapped low.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 25

PM5363 TUPP+622

TUPP+622

DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

Pin Name Type Pin

Function

No.

IPL[3] Input

AB18

The active high incoming payload active #3 (IPL[3]) signal identifies the bytes within the transport envelope frame on the incoming STM1 #3 stream that carry VC3 or VC4 virtual containers, or STS-1 synchronous payload envelopes.

In incoming STM-1 (STS-3) interface mode (IHSMODEB set high), IPL[3] must be brought high to mark each payload byte on ID[23:16]. IPL[3] is sampled on the rising edge of SCLK.

In incoming STM-4 (STS-12) interface mode (IHSMODEB set low), IPL[3] is unused and must be strapped low.

IPL[4] Input W4 The active high incoming payload active #4

(IPL[4]) signal identifies the bytes within the transport envelope frame on the incoming STM1 #4 stream that carry VC3 or VC4 virtual containers, or STS-1 synchronous payload envelopes.

In incoming STM-1 (STS-3) interface mode (IHSMODEB set high), IPL[4] must be brought high to mark each payload byte on ID[31:24]. IPL[4] is sampled on the rising edge of SCLK.

In incoming STM-4 (STS-12) interface mode (IHSMODEB set low), IPL[4] is unused and must be strapped low.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 26

PM5363 TUPP+622

TUPP+622

DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

Pin Name Type Pin

Function

No.

ITMF[1] Input U4 The active high incoming tributary multiframe #1

(ITMF[1]) signal identifies the first frame of the tributary multiframe for each STS-1 synchronous payload envelope, AU3, or AU4 administrative unit in the STM-4 or STM-1 #1 stream (ID[7:0]). ITMF[1] is enabled by setting the corresponding ITMFEN register bit high. When ITMFEN bit is low, the path overhead H4 byte is used to determine tributary multiframe boundaries. ITMF[1] is selectable to pulse high during the third byte after J1 of the first frame of the tributary multiframe or during the H4 byte which indicates that the next frame is the first frame of the tributary multiframe. Selection between marking each H4 or the third byte after each J1 is controlled by the corresponding ITMFH4 register bit. Pulses on ITMF[1] are only effective during the H4 or third byte after each J1 byte positions, as appropriate. When ITMFH4 is low, ITMF[1] can be set high for the entire first frame of the tributary multiframe. ITMF[1] must be low for the 2nd, 3rd, and 4th frame of the tributary multiframe. When ITMFH4 is high, ITMF[1] can be set high for the entire fourth frame of the tributary multiframe. ITMF[1] must be low for the 1st, 2nd and 3rd frame of the tributary multiframe.

In incoming STM-1 (STS-3) interface mode (IHSMODEB set high), ITMF[1] is sampled on the rising edge of SCLK.

In incoming STM-4 (STS-12) interface mode (IHSMODEB set low), ITMF[1] is sampled on the rising edge of HSCLK.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 27

PM5363 TUPP+622

TUPP+622

DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

Pin Name Type Pin

Function

No.

ITMF[2] Input D17 The active high incoming tributary multiframe #2

(ITMF[2]) signal identifies the first frame of the tributary multiframe for each STS-1 synchronous payload envelope, AU3, or AU4 administrative unit in the STM-1 #2 stream (ID[15:8]). ITMF[2] is enabled by setting the corresponding ITMFEN register bit high. When ITMFEN bit is low, the path overhead H4 byte is used to determine tributary multiframe boundaries. ITMF[2] is selectable to pulse high during the third byte after J1 of the first frame of the tributary multiframe or during the H4 byte which indicates that the next frame is the first frame of the tributary multiframe. Selection between marking each H4 or the third byte after each J1 is controlled by the corresponding ITMFH4 register bit. Pulses on ITMF[2] are only effective during the H4 or third byte after each J1 byte positions, as appropriate. When ITMFH4 is low, ITMF[2] can be set high for the entire first frame of the tributary multiframe. ITMF[2] must be low for the 2nd, 3rd, and 4th frame of the tributary multiframe. When ITMFH4 is high, ITMF[2] can be set high for the entire fourth frame of the tributary

multiframe. ITMF[2] must be low for the 1

, 2

and 3rd frame of the tributary multiframe.

In incoming STM-1 (STS-3) interface mode (IHSMODEB set high), ITMF[2] is sampled on the rising edge of SCLK.

In incoming STM-4 (STS-12) interface mode (IHSMODEB set low), ITMF[2] is unused and must be strapped low.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 28

PM5363 TUPP+622

TUPP+622

DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

Pin Name Type Pin

No.

ITMF[3] Input

AA20

Function

The active high incoming tributary multiframe #3 (ITMF[3]) signal identifies the first frame of the tributary multiframe for each STS-1 synchronous payload envelope, AU3, or AU4 administrative unit in the STM-1 #3 stream (ID[23:16]). ITMF[3] is enabled by setting the corresponding ITMFEN register bit high. When ITMFEN bit is low, the path overhead H4 byte is used to determine tributary multiframe boundaries. ITMF[3] is selectable to pulse high during the third byte after J1 of the first frame of the tributary multiframe or during the H4 byte which indicates that the next frame is the first frame of the tributary multiframe. Selection between marking each H4 or the third byte after each J1 is controlled by the corresponding ITMFH4 register bit. Pulses on ITMF[3] are only effective during the H4 or third byte after each J1 byte positions, as appropriate. When ITMFH4 is low, ITMF[3] can be set high for the entire first frame of the tributary multiframe. ITMF[3] must be low for the 2nd, 3rd, and 4th frame of the tributary multiframe. When ITMFH4 is high, ITMF[3] can be set high for the entire fourth frame of the tributary

multiframe. ITMF[3] must be low for the 1

, 2

and 3rd frame of the tributary multiframe.

In incoming STM-1 (STS-3) interface mode (IHSMODEB set high), ITMF[3] is sampled on the rising edge of SCLK.

In incoming STM-4 (STS-12) interface mode (IHSMODEB set low), ITMF[3] is unused and must be strapped low.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 29

PM5363 TUPP+622

TUPP+622

DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

Pin Name Type Pin

Function

No.

ITMF[4] Input AC5 The active high incoming tributary multiframe #4

(ITMF[4]) signal identifies the first frame of the tributary multiframe for each STS-1 synchronous payload envelope, AU3, or AU4 administrative unit in the STM-1 #4 stream (ID[31:24]). ITMF[4] is enabled by setting the corresponding ITMFEN register bit high. When ITMFEN bit is low, the path overhead H4 byte is used to determine tributary multiframe boundaries. ITMF[4] is selectable to pulse high during the third byte after J1 of the first frame of the tributary multiframe or during the H4 byte which indicates that the next frame is the first frame of the tributary multiframe. Selection between marking each H4 or the third byte after each J1 is controlled by the corresponding ITMFH4 register bit. Pulses on ITMF[4] are only effective during the H4 or third byte after each J1 byte positions, as appropriate. When ITMFH4 is low, ITMF[4] can be set high for the entire first frame of the tributary multiframe. ITMF[4] must be low for the 2nd, 3rd, and 4th frame of the tributary multiframe. When ITMFH4 is high, ITMF[4] can be set high for the entire fourth frame of the tributary

multiframe. ITMF[4] must be low for the 1

, 2

and 3rd frame of the tributary multiframe.

In incoming STM-1 (STS-3) interface mode (IHSMODEB set high), ITMF[4] is sampled on the rising edge of SCLK.

In incoming STM-4 (STS-12) interface mode (IHSMODEB set low), ITMF[4] is unused and must be strapped low.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 30

PM5363 TUPP+622

TUPP+622

DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

Pin Name Type Pin

Function

No.

ITPL[1] Input W2 The incoming tributary payload active #1

(ITPL[1]) signal marks the bytes carrying the tributary payload for the STM-4 or STM-1 #1 stream when pointer interpreter bypass is enabled (PIBYP bit set high). When pointer interpreter bypass is disabled (PIBYP bit set low), ITPL[1] is ignored. Also, ITPL[1] is ignored when IPL[1] is low.

In incoming STM-1 (STS-3) interface mode (IHSMODEB set high), ITPL[1] is set high to mark each tributary payload byte of the STM-1 #1 stream on the ID[7:0] bus. ITPL[1] is sampled on the rising edge of SCLK.

In incoming STM-4 (STS-12) interface mode (IHSMODEB set low), ITPL[1] is set high to mark each tributary payload byte of the STM-4 stream on the ID[7:0] bus. ITPL[1] is sampled on the rising edge of HSCLK.

ITPL[2] Input B19 The incoming tributary payload active #2

(ITPL[2]) signal marks the bytes carrying the tributary payload for the STM-1 #2 stream when pointer interpreter bypass is enabled (PIBYP bit set high). When pointer interpreter bypass is disabled (PIBYP bit set low), ITPL[2] is ignored. Also, ITPL[2] is ignored when IPL[2] is low.

In incoming STM-1 (STS-3) interface mode (IHSMODEB set high), ITPL[2] is set high to mark each tributary payload byte on the ID[15:8] bus. ITPL[2] is sampled on the rising edge of SCLK.

In incoming STM-4 (STS-12) interface mode (IHSMODEB set low), ITPL[2] is unused and must be strapped low.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 31

PM5363 TUPP+622

TUPP+622

DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

Pin Name Type Pin

Function

No.

ITPL[3] Input W20 The incoming tributary payload active #3

(ITPL[3]) signal marks the bytes carrying the tributary payload for the STM-1 #3 stream when pointer interpreter bypass is enabled (PIBYP bit set high). When pointer interpreter bypass is disabled (PIBYP bit set low), ITPL[3] is ignored. Also, ITPL[3] is ignored when IPL[3] is low.

In incoming STM-1 (STS-3) interface mode (IHSMODEB set high), ITPL[3] is set high to mark each tributary payload byte on the ID[23:16] bus. ITPL[3] is sampled on the rising edge of SCLK.

In incoming STM-4 (STS-12) interface mode (IHSMODEB set low), ITPL[3] is unused and must be strapped low.

ITPL[4] Input AA7 The incoming tributary payload active #4

(ITPL[4]) signal marks the bytes carrying the tributary payload for the STM-1 #4 stream when pointer interpreter bypass is enabled (PIBYP bit set high). When pointer interpreter bypass is disabled (PIBYP bit set low), ITPL[4] is ignored. Also, ITPL[4] is ignored when IPL[4] is low.

In incoming STM-1 (STS-3) interface mode (IHSMODEB set high), ITPL[4] is set high to mark each tributary payload byte on the ID[31:24] bus. ITPL[4] is sampled on the rising edge of SCLK.

In incoming STM-4 (STS-12) interface mode (IHSMODEB set low), ITPL[4] is unused and must be strapped low.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 32

PM5363 TUPP+622

TUPP+622

DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

Pin Name Type Pin

Function

No.

ITV5[1] Input V3 The incoming tributary V5 byte #1 (ITV5[1])

signal marks the tributary V5 bytes of the STM-4 or STM-1 #1 stream when pointer interpreter bypass is enabled (PIBYP bit set high). When pointer interpreter bypass is disabled (PIBYP bit set low), ITV5[1] is ignored. Also, ITV5[1] is ignored when IPL[1] is low.

In incoming STM-1 (STS-3) interface mode (IHSMODEB set high), ITV5[1] is set high to mark each tributary V5 byte of the STM-1 #1 stream on the ID[7:0] bus. When the incoming tributary is a TU3, ITV5[1] marks the J1 byte of the TU3. ITV5[1] is sampled on the rising edge of SCLK.

In incoming STM-4 (STS-12) interface mode (IHSMODEB set low), ITV5[1] is set high to mark each tributary V5 byte of the STM-4 stream on the ID[7:0] bus. When the incoming tributary is a TU3, ITV5[1] marks the J1 byte of the TU3. ITV5[1] is sampled on the rising edge of HSCLK.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 33

PM5363 TUPP+622

TUPP+622

DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

Pin Name Type Pin

Function

No.

ITV5[2] Input C18 The incoming tributary V5 byte #2 (ITV5[2])

signal marks the tributary V5 bytes of the STM-1 #2 stream when pointer interpreter bypass is enabled (PIBYP bit set high). When pointer interpreter bypass is disabled (PIBYP bit set low), ITV5[2] is ignored. Also, ITV5[2] is ignored when IPL[2] is low.

In incoming STM-1 (STS-3) interface mode (IHSMODEB set high), ITV5[2] is set high to mark each tributary V5 byte on the ID[15:8] bus. When the incoming tributary is a TU3, ITV5[2] marks the J1 byte of the TU3. ITV5[2] is sampled on the rising edge of SCLK.

In incoming STM-4 (STS-12) interface mode (IHSMODEB set low), ITV5[2] is unused and must be strapped low.

ITV5[3] Input Y21 The incoming tributary V5 byte #3 (ITV5[3])

signal marks the tributary V5 bytes of the STM-1 #3 stream when pointer interpreter bypass is enabled (PIBYP bit set high). When pointer interpreter bypass is disabled (PIBYP bit set low), ITV5[3] is ignored. Also, ITV5[3] is ignored when IPL[3] is low.

In incoming STM-1 (STS-3) interface mode (IHSMODEB set high), ITV5[3] is set high to mark each tributary V5 byte on the ID[23:16] bus. When the incoming tributary is a TU3, ITV5[3] marks the J1 byte of the TU3. ITV5[3] is sampled on the rising edge of SCLK.

In incoming STM-4 (STS-12) interface mode (IHSMODEB set low), ITV5[3] is unused and must be strapped low.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 34

PM5363 TUPP+622

TUPP+622

DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

Pin Name Type Pin

Function

No.

ITV5[4] Input AB6 The incoming tributary V5 byte #4 (ITV5[4])

signal marks the tributary V5 bytes of the STM-1 #4 stream when pointer interpreter bypass is enabled (PIBYP bit set high). When pointer interpreter bypass is disabled (PIBYP bit set low), ITV5[4] is ignored. Also, ITV5[4] is ignored when IPL[4] is low.

In incoming STM-1 (STS-3) interface mode (IHSMODEB set high), ITV5[4] is set high to mark each tributary V5 byte on the ID[31:24] bus. When the incoming tributary is a TU3, ITV5[4] marks the J1 byte of the TU3. ITV5[4] is sampled on the rising edge of SCLK.

In incoming STM-4 (STS-12) interface mode (IHSMODEB set low), ITV5[4] is unused and must be strapped low.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 35

PM5363 TUPP+622

TUPP+622

DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

Pin Name Type Pin

Function

No.

IAIS[1] Input Y1 The incoming tributary alarm indication signal #1

(IAIS[1]) marks tributaries on the incoming STM4 or STM-1 #1 stream that are in AIS state when pointer interpreter bypass is enabled (PIBYP bit set high). When pointer interpreter bypass is disabled (PIBYP bit set low), IAIS[1] is ignored. Also, IAIS[1] is ignored when IPL[1] is low.

In incoming STM-1 (STS-3) interface mode (IHSMODEB set high), IAIS[1] is set high when the associated tributary of the STM-1 #1 stream on the ID[7:0] is in AIS state and is set low when the associated tributary is operating normally. IAIS[1] is sampled on the rising edge of SCLK.

In incoming STM-4 (STS-12) interface mode (IHSMODEB set low), IAIS[1] is set high when the associated tributary of the STM-4 stream on the ID[7:0] is in AIS state and is set low when the associated tributary is operating normally. IAIS[1] is sampled on the rising edge of HSCLK.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 36

PM5363 TUPP+622

TUPP+622

DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

Pin Name Type Pin

Function

No.

IAIS[2] Input A20 The incoming tributary alarm indication signal #2

(IAIS[2]) marks tributaries on the incoming STMSTM-1 #2 stream that are in AIS state when pointer interpreter bypass is enabled (PIBYP bit set high). When pointer interpreter bypass is disabled (PIBYP bit set low), IAIS[2] is ignored. Also, IAIS[2] is ignored when IPL[2] is low.

In incoming STM-1 (STS-3) interface mode (IHSMODEB set high), IAIS[2] is set high when the associated tributary on the ID[15:8] is in AIS state and is set low when the associated tributary is operating normally. IAIS[2] is sampled on the rising edge of SCLK.

In incoming STM-4 (STS-12) interface mode (IHSMODEB set low), IAIS[2] is unused and must be strapped low.

IAIS[3] Input

AA23

The incoming tributary alarm indication signal #3 (IAIS[3]) marks tributaries on the incoming STMSTM-1 #3 stream that are in AIS state when pointer interpreter bypass is enabled (PIBYP bit set high). When pointer interpreter bypass is disabled (PIBYP bit set low), IAIS[3] is ignored. Also, IAIS[3] is ignored when IPL[3] is low.

In incoming STM-1 (STS-3) interface mode (IHSMODEB set high), IAIS[3] is set high when the associated tributary on the ID[23:16] is in AIS state and is set low when the associated tributary is operating normally. IAIS[3] is sampled on the rising edge of SCLK.

In incoming STM-4 (STS-12) interface mode (IHSMODEB set low), IAIS[3] is unused and must be strapped low.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 37

PM5363 TUPP+622

TUPP+622

DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

Pin Name Type Pin

Function

No.

IAIS[4] Input Y8 The incoming tributary alarm indication signal #4

(IAIS[4]) marks tributaries on the incoming STMSTM-1 #4 stream that are in AIS state when pointer interpreter bypass is enabled (PIBYP bit set high). When pointer interpreter bypass is disabled (PIBYP bit set low), IAIS[4] is ignored. Also, IAIS[4] is ignored when IPL[4] is low.

In incoming STM-1 (STS-3) interface mode (IHSMODEB set high), IAIS[4] is set high when the associated tributary on the ID[31:24] is in AIS state and is set low when the associated tributary is operating normally. IAIS[4] is sampled on the rising edge of SCLK.

In incoming STM-4 (STS-12) interface mode (IHSMODEB set low), IAIS[4] is unused and must be strapped low.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 38

PM5363 TUPP+622

TUPP+622

DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

Pin Name Type Pin

Function

No.

IDP[1] Input W1 The incoming data parity #1 (IDP[1]) signal

carries the parity of the incoming signals for the STM-4 or STM-1 #1 stream.

In incoming STM-1 (STS-3) interface mode (IHSMODEB set high), the parity calculation encompasses the ID[7:0] bus and optionally the IC1J1[1] and the IPL[1] signals. IC1J1[1] and IPL[1] can be included in the parity calculation by setting the corresponding INCIC1J1 and INCIPL register bits high, respectively. Odd parity is selected by setting the corresponding IOP register bit high, and even parity is selected by setting the IOP bit low. IDP[1] is sampled on the rising edge of SCLK.

In incoming STM-4 (STS-12) interface mode (IHSMODEB set low), the parity calculation encompasses the ID[7:0] bus and optionally the IC1J1[1] and the IPL[1] signals. IC1J1[1] and IPL[1] can be included in the parity calculation by setting the corresponding INCIC1J1 and INCIPL register bits high, respectively. Odd parity is selected by setting the corresponding IOP register bit high, and even parity is selected by setting the IOP bit low. IDP[1] is sampled on the rising edge of HSCLK.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 39

PM5363 TUPP+622

TUPP+622

DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

Pin Name Type Pin

Function

No.

IDP[2] Input A19 The incoming data parity #2 (IDP[2]) signal

carries the parity of the incoming signals for the STM-1 #2 stream.

In incoming STM-1 (STS-3) interface mode (IHSMODEB set high), the parity calculation encompasses the ID[15:8] bus and optionally the IC1J1[2] and the IPL[2] signals. IC1J1[2] and IPL[2] can be included in the parity calculation by setting the corresponding INCIC1J1 and INCIPL register bits high, respectively. Odd parity is selected by setting the corresponding IOP register bit high, and even parity is selected by setting the IOP bit low. IDP[2] is sampled on the rising edge of SCLK.

In incoming STM-4 (STS-12) interface mode (IHSMODEB set low), IDP[2] is unused and must be strapped low.

IDP[3] Input Y19 The incoming data parity #3 (IDP[3]) signal

carries the parity of the incoming signals for the STM-1 #3 stream.

In incoming STM-1 (STS-3) interface mode (IHSMODEB set high), the parity calculation encompasses the ID[23:16] bus and optionally the IC1J1[3] and the IPL[3] signals. IC1J1[3] and IPL[3] can be included in the parity calculation by setting the corresponding INCIC1J1 and INCIPL register bits high, respectively. Odd parity is selected by setting the corresponding IOP register bit high, and even parity is selected by setting the IOP bit low. IDP[3] is sampled on the rising edge of SCLK.

In incoming STM-4 (STS-12) interface mode (IHSMODEB set low), IDP[3] is unused and must be strapped low.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 40

PM5363 TUPP+622

TUPP+622

DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

Pin Name Type Pin

Function

No.

IDP[4] Input AA6 The incoming data parity #4 (IDP[4]) signal

carries the parity of the incoming signals for the STM-1 #4 stream.

In incoming STM-1 (STS-3) interface mode (IHSMODEB set high), the parity calculation encompasses the ID[31:24] bus and optionally the IC1J1[4] and the IPL[4] signals. IC1J1[4] and IPL[4] can be included in the parity calculation by setting the corresponding INCIC1J1 and INCIPL register bits high, respectively. Odd parity is selected by setting the corresponding IOP register bit high, and even parity is selected by setting the IOP bit low. IDP[4] is sampled on the rising edge of SCLK.

In incoming STM-4 (STS-12) interface mode (IHSMODEB set low), IDP[4] is unused and must be strapped low.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 41

PM5363 TUPP+622

TUPP+622

DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

Pin Name Type Pin

No.

ID[0]

ID[1]

ID[2]

ID[3]

ID[4]

ID[5]

ID[6]

ID[7]

Input R2

Function

The incoming data bus (ID[7:0]) carries the STM-4 or STM-1 #1 SONET/SDH frame data in byte serial format.

In incoming STM-1 (STS-3) interface mode (IHSMODEB set high), the ID[7:0] bus carries the STM-1 #1 stream. ID[7] is the most significant bit, corresponding to bit 1 of each serial word, the bit transmitted first. ID[0] is the least significant bit, corresponding to bit 8 of each serial word, the last bit transmitted. The ID[7:0] bus is sampled on the rising edge of SCLK.

In incoming STM-4 (STS-12) interface mode (IHSMODEB set low), the ID[7:0] bus carries the STM-4 stream. ID[7] is the most significant bit, corresponding to bit 1 of each serial word, the bit transmitted first. ID[0] is the least significant bit, corresponding to bit 8 of each serial word, the last bit transmitted. The ID[7:0] bus is sampled on the rising edge of HSCLK.

ID[8]

ID[9]

ID[10]

ID[11]

ID[12]

Input B15

C15

B16

C16

A17

The incoming data bus (ID[15:8]) carries the STM-1 #2 SONET/SDH frame data in byte serial format.

In incoming STM-1 (STS-3) interface mode (IHSMODEB set high), ID[15] is the most significant bit, corresponding to bit 1 of each serial word, the bit transmitted first. ID[8] is the

ID[13]

ID[14]

D16

C17

least significant bit, corresponding to bit 8 of each serial word, the last bit transmitted. The ID[15:8] bus is sampled on the rising edge of

ID[15]

B18

SCLK.

In incoming STM-4 (STS-12) interface mode (IHSMODEB set low), the ID[15:8] bus is unused and all bus signals must be strapped low.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 42

PM5363 TUPP+622

TUPP+622

DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

Pin Name Type Pin

No.

ID[16]

ID[17]

ID[18]

ID[19]

ID[20]

ID[21]

ID[22]

ID[23]

ID[24]

ID[25]

ID[26]

ID[27]

ID[28]

ID[29]

ID[30]

ID[31]

Input

Input Y3

AC19

Y17

AA18

AB19

AC20

AA19

AB20

AC21

AA4

AC3

AB4

AA5

AC4

AB5

Function

The incoming data bus (ID[23:16]) carries the STM-1 #3 SONET/SDH frame data in byte serial format.

In incoming STM-1 (STS-3) interface mode (IHSMODEB set high), ID[23] is the most significant bit, corresponding to bit 1 of each serial word, the bit transmitted first. ID[16] is the least significant bit, corresponding to bit 8 of each serial word, the last bit transmitted. The ID[23:16] bus is sampled on the rising edge of SCLK.

In incoming STM-4 (STS-12) interface mode (IHSMODEB set low), the ID[23:16] bus is unused and all bus signals must be strapped low.

The incoming data bus (ID[31:24]) carries the STM-1 #4 SONET/SDH frame data in byte serial format.

In incoming STM-1 (STS-3) interface mode (IHSMODEB set high), ID[31] is the most significant bit, corresponding to bit 1 of each serial word, the bit transmitted first. ID[24] is the least significant bit, corresponding to bit 8 of each serial word, the last bit transmitted. The ID[31:24] bus is sampled on the rising edge of SCLK.

In incoming STM-4 (STS-12) interface mode (IHSMODEB set low), the ID[31:24] bus is unused and all bus signals must be strapped low.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 43

PM5363 TUPP+622

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DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

Pin Name Type Pin

Function

No.

GSCLK_FP Input J1

The active high generated system clock frame position (GSCLK_FP) signal aligns the HSCLK divide by four logic which generates the GSCLK[1:0] signals when STM-4 (STS-12) interface mode is selected at the incoming or outgoing interface (IHSMODEB or OHSMODEB set low). GSCLK_FP should be set high for one HSCLK period at an interval of four or multiples of four HSCLK periods.

GSCLK_FP is sampled on the rising edge of HSCLK.

OTMF[1] Input J2 The active high outgoing tributary multiframe #1

(OTMF[1]) signal identifies the first frame of the tributary multiframe for each AU3, or AU4 administrative unit, or STS-1 synchronous payload envelope in the outgoing STM-4 or STM-1 #1 stream.

In outgoing STM-1 (STS-3) interface mode (OHSMODEB set high), the OTMF[1] identifies the first frame of the tributary multiframe in the STM-1 stream on the OD[7:0] bus. OTMF[1] is selectable to pulse high during the third byte after J1 of the first STS-1 stream or during the H4 byte of the path overhead which indicates that the next frame is the first frame of the tributary multiframe. Selection between marking the third byte after each J1 or H4 bytes is controlled by the corresponding OTMFH4 register bit. Pulses on OTMF[1] are only effective during the H4 or third byte after each J1 byte positions, as appropriate. OTMF[1] is ignored at other byte positions. OTMF[1] is sampled on the rising edge of SCLK.

In outgoing STM-4 (STS-12) interface mode (OHSMODEB set low), the OTMF[1] identifies

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 44

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DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

Pin Name Type Pin

No.

Function

the first frame of the tributary multiframe in each STM-1 within the STM-4 (OD[7:0]) stream. OTMF[1] is selectable to pulse high during the third byte after J1 of the first STS-1 in each STM-1 or during the H4 byte of the path overhead which indicates that the next frame is the first frame of the tributary multiframe. Selection between marking the third byte after each J1 or H4 bytes is controlled by the corresponding OTMFH4 register bit. Pulses on OTMF[1] are only effective during the H4 or third byte after each J1 byte positions, as appropriate. OTMF[1] is ignored at other byte positions. OTMF[1] is sampled on the rising edge of HSCLK.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 45

PM5363 TUPP+622

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DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

Pin Name Type Pin

Function

No.

OTMF[2] Input D23 The active high outgoing tributary multiframe #2

(OTMF[2]) signal identifies the first frame of the tributary multiframe for each AU3, or AU4 administrative unit, or STS-1 synchronous payload envelope in the outgoing STM-1 #2 stream.

In outgoing STM-1 (STS-3) interface mode (OHSMODEB set high), the OTMF[2] identifies the first frame of the tributary multiframe in the STM-1 stream on the OD[15:8] bus. OTMF[2] is selectable to pulse high during the third byte after J1 of the first STS-1 stream or during the H4 byte of the path overhead which indicates that the next frame is the first frame of the tributary multiframe. Selection between marking the third byte after each J1 or H4 bytes is controlled by the corresponding OTMFH4 register bit. Pulses on OTMF[2] are only effective during the H4 or third byte after each J1 byte positions, as appropriate. OTMF[2] is ignored at other byte positions. OTMF[2] is sampled on the rising edge of SCLK.

In outgoing STM-4 (STS-12) interface mode (OHSMODEB set low), the OTMF[2] is unused and must be strapped low.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 46

PM5363 TUPP+622

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DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

Pin Name Type Pin

Function

No.

OTMF[3] Input L21 The active high outgoing tributary multiframe #3

(OTMF[3]) signal identifies the first frame of the tributary multiframe for each AU3, or AU4 administrative unit, or STS-1 synchronous payload envelope in the outgoing STM-1 #3 stream.

In outgoing STM-1 (STS-3) interface mode (OHSMODEB set high), the OTMF[3] identifies the first frame of the tributary multiframe in the STM-1 stream on the OD[23:16] bus. OTMF[3] is selectable to pulse high during the third byte after J1 of the first STS-1 stream or during the H4 byte of the path overhead which indicates that the next frame is the first frame of the tributary multiframe. Selection between marking the third byte after each J1 or H4 bytes is controlled by the corresponding OTMFH4 register bit. Pulses on OTMF[3] are only effective during the H4 or third byte after each J1 byte positions, as appropriate. OTMF[3] is ignored at other byte positions. OTMF[3] is sampled on the rising edge of SCLK.

In outgoing STM-4 (STS-12) interface mode (OHSMODEB set low), the OTMF[3] is unused and must be strapped low.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 47

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DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

Pin Name Type Pin

No.

OTMF[4] Input

AA11

Function

The active high outgoing tributary multiframe #4 (OTMF[4]) signal identifies the first frame of the tributary multiframe for each AU3, or AU4 administrative unit, or STS-1 synchronous payload envelope in the outgoing STM-1 #4 stream.

In outgoing STM-1 (STS-3) interface mode (OHSMODEB set high), the OTMF[4] identifies the first frame of the tributary multiframe in the STM-1 stream on the OD[31:24] bus. OTMF[4] is selectable to pulse high during the third byte after J1 of the first STS-1 stream or during the H4 byte of the path overhead which indicates that the next frame is the first frame of the tributary multiframe. Selection between marking the third byte after each J1 or H4 bytes is controlled by the corresponding OTMFH4 register bit. Pulses on OTMF[4] are only effective during the H4 or third byte after each J1 byte positions, as appropriate. OTMF[4] is ignored at other byte positions. OTMF[4] is sampled on the rising edge of SCLK.

In outgoing STM-4 (STS-12) interface mode (OHSMODEB set low), the OTMF[4] is unused and must be strapped low.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 48

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DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

Pin Name Type Pin

Function

No.

COUT[1] Output J3 The controlled output signal #1 (COUT[1]) is a

software programmable output that is controlled by the COUTx register bit associated with each tributary in the STM-4 or STM-1 #1 stream.

In outgoing STM-1 (STS-3) interface mode (OHSMODEB set high), COUT[1] is synchronized to the STM-1 #1 stream on OD[7:0] bus. COUT[1] is updated on the rising edge of SCLK.

In outgoing STM-4 (STS-12) interface mode (OHSMODEB set low), COUT[1] is synchronized to the STM-4 stream on OD[7:0] bus. COUT[1] is updated on the rising edge of HSCLK.

COUT[2] Output L20 The controlled output signal #2 (COUT[2]) is a

software programmable output that is controlled by the COUTx register bit associated with each tributary in the STM-1 #2 stream.

In outgoing STM-1 (STS-3) interface mode (OHSMODEB set high), COUT[2] is synchronized to the OD[15:8] bus. COUT[2] is updated on the rising edge of SCLK.

In outgoing STM-4 (STS-12) interface mode (OHSMODEB set low), COUT[2] is invalid.

COUT[3] Output U23 The controlled output signal #3 (COUT[3]) is a

software programmable output that is controlled by the COUTx register bit associated with each tributary in the STM-1 #3 stream.

In outgoing STM-1 (STS-3) interface mode (OHSMODEB set high), COUT[3] is synchronized to the OD[23:16] bus. COUT[3] is updated on the rising edge of SCLK.

In outgoing STM-4 (STS-12) interface mode (OHSMODEB set low), COUT[3] is invalid.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 49

PM5363 TUPP+622

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DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

Pin Name Type Pin

No.

COUT[4] Output

AA16

Function

The controlled output signal #4 (COUT[4]) is a software programmable output that is controlled by the COUTx register bit associated with each tributary in the STM-1 #4 stream.

In outgoing STM-1 (STS-3) interface mode (OHSMODEB set high), COUT[4] is synchronized to the OD[31:24] bus. COUT[4] is updated on the rising edge of SCLK.

In outgoing STM-4 (STS-12) interface mode (OHSMODEB set low), COUT[4] is invalid.

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PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

Pin Name Type Pin

No.

OD[0]

OD[1]

OD[2]

OD[3]

OD[4]

OD[5]

OD[6]

OD[7]

Output C1

Function

The outgoing data bus (OD[7:0]) carries the STM-4 or STM-1 #1 SONET/SDH frame data in byte serial format.

In outgoing STM-1 (STS-3) interface mode (OHSMODEB set high), the OD[7:0] bus carries the STM-1 #1 stream. OD[7] is the most significant bit, corresponding to bit 1 of each serial word, the bit transmitted first. OD[0] is the least significant bit, corresponding to bit 8 of each serial word, the last bit transmitted. OD[7:0] is set to all-zeros at transport overhead bytes, except for the A1 and A2 framing bytes and the H1 and H2 pointer bytes. Pointer offset is determined by the STP Outgoing Pointer MSB and LSB registers. The OD[7:0] bus is updated on the rising edge of SCLK.

In outgoing STM-4 (STS-12) interface mode (OHSMODEB set low), the ID[7:0] bus carries the STM-4 stream. OD[7] is the most significant bit, corresponding to bit 1 of each serial word, the bit transmitted first. OD[0] is the least significant bit, corresponding to bit 8 of each serial word, the last bit transmitted. OD[7:0] is set to all-zeros at transport overhead bytes, except for the A1 and A2 framing bytes and the H1 and H2 pointer bytes. Pointer offset is determined by the STP Outgoing Pointer MSB and LSB registers. The OD[7:0] bus is updated on the rising edge of HSCLK.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 51

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DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

Pin Name Type Pin

No.

OD[8]

OD[9]

OD[10]

OD[11]

OD[12]

OD[13]

OD[14]

OD[15]

Output E23

F22

G21

H20

G22

H21

G23

H22

Function

The outgoing data bus (OD[15:8]) carries the STM-1 #2 SONET/SDH frame data in byte serial format.

In outgoing STM-1 (STS-3) interface mode (OHSMODEB set high), OD[15] is the most significant bit, corresponding to bit 1 of each serial word, the bit transmitted first. OD[8] is the least significant bit, corresponding to bit 8 of each serial word, the last bit transmitted. OD[15:8] is set to all-zeros at transport overhead bytes, except for the A1 and A2 framing bytes and the H1 and H2 pointer bytes. Pointer offset is determined by the STP Outgoing Pointer MSB and LSB registers. The OD[15:8] bus is updated on the rising edge of SCLK.

In outgoing STM-4 (STS-12) interface mode (OHSMODEB set low), the OD[15:8] bus is unused and all bus signals are invalid.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 52

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DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

Pin Name Type Pin

No.

OD[16]

OD[17]

OD[18]

OD[19]

OD[20]

OD[21]

OD[22]

OD[23]

Output M22

M21

N23

N21

N20

P23

P22

P21

Function

The outgoing data bus (OD[23:16]) carries the STM-1 #3 SONET/SDH frame data in byte serial format.

In outgoing STM-1 (STS-3) interface mode (OHSMODEB set high), OD[23] is the most significant bit, corresponding to bit 1 of each serial word, the bit transmitted first. OD[16] is the least significant bit, corresponding to bit 8 of each serial word, the last bit transmitted. OD[23:16] is set to all-zeros at transport overhead bytes, except for the A1 and A2 framing bytes and the H1 and H2 pointer bytes. Pointer offset is determined by the STP Outgoing Pointer MSB and LSB registers. The OD[23:16] bus is updated on the rising edge of SCLK.

In outgoing STM-4 (STS-12) interface mode (OHSMODEB set low), the OD[23:16] bus is unused and all bus signals are invalid.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 53

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DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

Pin Name Type Pin

No.

OD[24]

OD[25]

OD[26]

OD[27]

OD[28]

OD[29]

OD[30]

OD[31]

Output

AA12

AB12

AC13

AA13

Y13

AC14

AB14

AA14

Function

The outgoing data bus (OD[31:24]) carries the STM-1 #4 SONET/SDH frame data in byte serial format.

In outgoing STM-1 (STS-3) interface mode (OHSMODEB set high), OD[31] is the most significant bit, corresponding to bit 1 of each serial word, the bit transmitted first. OD[24] is the least significant bit, corresponding to bit 8 of each serial word, the last bit transmitted. OD[31:24] is set to all-zeros at transport overhead bytes, except for the A1 and A2 framing bytes and the H1 and H2 pointer bytes. Pointer offset is determined by the STP Outgoing Pointer MSB and LSB registers. The OD[31:24] bus is updated on the rising edge of SCLK.

In outgoing STM-4 (STS-12) interface mode (OHSMODEB set low), the OD[31:24] bus is unused and all bus signals are invalid.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 54

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DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

Pin Name Type Pin

Function

No.

ODP[1] Output F2 The outgoing data parity #1 (ODP[1]) signal

carries the parity of the outgoing STM-4 or STM1 #1 data stream on OD[7:0] and optionally including the OC1J1V1[1] and the OPL[1] signals. OC1J1V1[1] and OPL[1] can be included in the parity calculation by setting the corresponding INCOC1J1 and INCOPL register bits high, respectively. Odd parity is selected by setting the corresponding OOP register bit high, and even parity is selected by setting the OOP bit low.

In outgoing STM-1 (STS-3) interface mode (OHSMODEB set high), ODP[1] is updated on the rising edge of SCLK.

In outgoing STM-4 (STS-12) interface mode (OHSMODEB set low), ODP[1] is updated on the rising edge of HSCLK.

ODP[2] Output J21 The outgoing data parity #2 (ODP[2]) signal

carries the parity of the outgoing STM-1 #2 data stream on OD[15:8] and optionally including the OC1J1V1[2] and the OPL[2] signals. OC1J1V1[2] and OPL[2] can be included in the parity calculation by setting the corresponding INCOC1J1 and INCOPL register bits high, respectively. Odd parity is selected by setting the corresponding OOP register bit high, and even parity is selected by setting the OOP bit low.

In outgoing STM-1 (STS-3) interface mode (OHSMODEB set high), ODP[2] is updated on the rising edge of SCLK.

In outgoing STM-4 (STS-12) interface mode (OHSMODEB set low), ODP[2] is invalid.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 55

PM5363 TUPP+622

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DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

Pin Name Type Pin

Function

No.

ODP[3] Output R23 The outgoing data parity #3 (ODP[3]) signal

carries the parity of the outgoing STM-1 #3 data stream on OD[23:16] and optionally including the OC1J1V1[3] and the OPL[3] signals. OC1J1V1[3] and OPL[3] can be included in the parity calculation by setting the corresponding INCOC1J1 and INCOPL register bits high, respectively. Odd parity is selected by setting the corresponding OOP register bit high, and even parity is selected by setting the OOP bit low.

In outgoing STM-1 (STS-3) interface mode (OHSMODEB set high), ODP[3] is updated on the rising edge of SCLK.

In outgoing STM-4 (STS-12) interface mode (OHSMODEB set low), ODP[3] is invalid.

ODP[4] Output

AC15

The outgoing data parity #4 (ODP[4]) signal carries the parity of the outgoing STM-1 #4 data stream on OD[31:24] and optionally including the OC1J1V1[4] and the OPL[4] signals. OC1J1V1[4] and OPL[4] can be included in the parity calculation by setting the corresponding INCOC1J1 and INCOPL register bits high, respectively. Odd parity is selected by setting the corresponding OOP register bit high, and even parity is selected by setting the OOP bit low.

In outgoing STM-1 (STS-3) interface mode (OHSMODEB set high), ODP[4] is updated on the rising edge of SCLK.

In outgoing STM-4 (STS-12) interface mode (OHSMODEB set low), ODP[4] is invalid.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 56

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DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

Pin Name Type Pin

Function

No.

OTPL[1] Output H4 The outgoing tributary payload active #1

(OTPL[1]) signal marks the bytes carrying the tributary payload for the STM-4 or STM-1 #1 stream.

In outgoing STM-1 (STS-3) interface mode (OHSMODEB set high), OTPL[1] is set high to mark each tributary payload byte of the STM-1 #1 stream on the OD[7:0] bus. OTPL[1] is updated on the rising edge of SCLK.

In outgoing STM-4 (STS-12) interface mode (OHSMODEB set low), OTPL[1] is set high to mark each tributary payload byte of the STM-4 stream on the OD[7:0] bus. OTPL[1] is updated on the rising edge of HSCLK.

OTPL[2] Output J23 The outgoing tributary payload active #2

(OTPL[2]) signal marks the bytes carrying the tributary payload for the STM-1 #2 stream.

In outgoing STM-1 (STS-3) interface mode (OHSMODEB set high), OTPL[2] is set high to mark each tributary payload byte on the OD[15:8] bus. OTPL[2] is updated on the rising edge of SCLK.

In outgoing STM-4 (STS-12) interface mode (OHSMODEB set low), OTPL[2] is invalid.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 57

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DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

Pin Name Type Pin

Function

No.

OTPL[3] Output R22 The outgoing tributary payload active #3

(OTPL[3]) signal marks the bytes carrying the tributary payload for the STM-1 #3 stream.

In outgoing STM-1 (STS-3) interface mode (OHSMODEB set high), OTPL[3] is set high to mark each tributary payload byte on the OD[23:16] bus. OTPL[3] is updated on the rising edge of SCLK.

In outgoing STM-4 (STS-12) interface mode (OHSMODEB set low), OTPL[3] is invalid.

OTPL[4] Output

AB15

The outgoing tributary payload active #4 (OTPL[4]) signal marks the bytes carrying the tributary payload for the STM-1 #4 stream.

In outgoing STM-1 (STS-3) interface mode (OHSMODEB set high), OTPL[4] is set high to mark each tributary payload byte on the OD[31:24] bus. OTPL[4] is updated on the rising edge of SCLK.

In outgoing STM-4 (STS-12) interface mode (OHSMODEB set low), OTPL[4] is invalid.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 58

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DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

Pin Name Type Pin

Function

No.

OTV5[1] Output G3 The outgoing tributary V5 byte #1 (OTV5[1])

signal marks the tributary V5 bytes of the STM-4 or STM-1 #1 stream.

In outgoing STM-1 (STS-3) interface mode (OHSMODEB set high), OTV5[1] is set high to mark each tributary V5 byte of the STM-1 #1 stream on the OD[7:0] bus. When the outgoing tributary is a TU3, OTV5[1] marks the J1 byte of the TU3. OTV5[1] is updated on the rising edge of SCLK.

In outgoing STM-4 (STS-12) interface mode (OHSMODEB set low), OTV5[1] is set high to mark each tributary V5 byte of the STM-4 stream on the OD[7:0] bus. When the outgoing tributary is a TU3, OTV5[1] marks the J1 byte of the TU3. OTV5[1] is updated on the rising edge of HSCLK.

OTV5[2] Output K20 The outgoing tributary V5 byte #2 (OTV5[2])

signal marks the tributary V5 bytes of the STM-1 #2 stream.

In outgoing STM-1 (STS-3) interface mode (OHSMODEB set high), OTV5[2] is set high to mark each tributary V5 byte on the OD[15:8] bus. When the outgoing tributary is a TU3, OTV5[2] marks the J1 byte of the TU3. OTV5[2] is updated on the rising edge of SCLK.

In outgoing STM-4 (STS-12) interface mode (OHSMODEB set low), OTV5[2] is invalid.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 59

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DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

Pin Name Type Pin

Function

No.

OTV5[3] Output P20 The outgoing tributary V5 byte #3 (OTV5[3])

signal marks the tributary V5 bytes of the STM-1 #3 stream.

In outgoing STM-1 (STS-3) interface mode (OHSMODEB set high), OTV5[3] is set high to mark each tributary V5 byte on the OD[23:16] bus. When the outgoing tributary is a TU3, OTV5[3] marks the J1 byte of the TU3. OTV5[3] is updated on the rising edge of SCLK.

In outgoing STM-4 (STS-12) interface mode (OHSMODEB set low), OTV5[3] is invalid.

OTV5[4] Output Y14 The outgoing tributary V5 byte #4 (OTV5[4])

signal marks the tributary V5 bytes of the STM-1 #4 stream.

In outgoing STM-1 (STS-3) interface mode (OHSMODEB set high), OTV5[4] is set high to mark each tributary V5 byte on the OD[31:24] bus. When the outgoing tributary is a TU3, OTV5[4] marks the J1 byte of the TU3. OTV5[4] is updated on the rising edge of SCLK.

In outgoing STM-4 (STS-12) interface mode (OHSMODEB set low), OTV5[4] is invalid.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 60

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DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

Pin Name Type Pin

Function

No.

AIS[1] Output G1 The tributary alarm indication signal output #1

(AIS[1]) marks tributaries on the outgoing STM-4 or STM-1 #1 stream that are in AIS state.

In outgoing STM-1 (STS-3) interface mode (OHSMODEB set high), AIS[1] is set high when AIS is inserted in the associated tributary of the STM-1 #1 stream on the OD[7:0] and is set low when the AIS is not inserted. AIS[1] is updated on the rising edge of SCLK.

In outgoing STM-4 (STS-12) interface mode (OHSMODEB set low), AIS[1] is set high when AIS is inserted in the associated tributary of the STM-4 stream on the OD[7:0] and is set low when the AIS is not inserted. AIS[1] is set low for transport overhead bytes. AIS[1] is updated on the rising edge of HSCLK.

AIS[2] Output K21 The tributary alarm indication signal output #2

(AIS[2]) marks tributaries on the outgoing STM-4 or STM-1 #2 stream that are in AIS state.

In outgoing STM-1 (STS-3) interface mode (OHSMODEB set high), AIS[2] is set high when AIS is inserted in the associated tributary on the OD[15:8] and is set low when the AIS is not inserted. AIS[2] is updated on the rising edge of SCLK.

In outgoing STM-4 (STS-12) interface mode (OHSMODEB set low), AIS[2] is invalid.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 61

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DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

Pin Name Type Pin

Function

No.

AIS[3] Output R21 The tributary alarm indication signal output #3

(AIS[3]) marks tributaries on the outgoing STM-4 or STM-1 #3 stream that are in AIS state.

In outgoing STM-1 (STS-3) interface mode (OHSMODEB set high), AIS[3] is set high when AIS is inserted in the associated tributary on the OD[23:16] and is set low when the AIS is not inserted. AIS[3] is updated on the rising edge of SCLK.

In outgoing STM-4 (STS-12) interface mode (OHSMODEB set low), AIS[3] is invalid.

AIS[4] Output

AA15

The tributary alarm indication signal output #4 (AIS[4]) marks tributaries on the outgoing STM-4 or STM-1 #4 stream that are in AIS state.

In outgoing STM-1 (STS-3) interface mode (OHSMODEB set high), AIS[4] is set high when AIS is inserted in the associated tributary on the OD[31:24] and is set low when the AIS is not inserted. AIS[4] is updated on the rising edge of SCLK.

In outgoing STM-4 (STS-12) interface mode (OHSMODEB set low), AIS[4] is invalid.

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PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

Pin Name Type Pin

Function

No.

IDLE[1] Output H3 The tributary idle indication signal output #1

(IDLE[1]) marks tributaries on the outgoing STM4 or STM-1 #1 stream that are in idle state.

In outgoing STM-1 (STS-3) interface mode (OHSMODEB set high), IDLE[1] is set high when idle code is inserted in the associated tributary of the STM-1 #1 stream on the OD[7:0] and is set low when the idle code is not inserted. IDLE[1] is updated on the rising edge of SCLK.

In outgoing STM-4 (STS-12) interface mode (OHSMODEB set low), IDLE[1] is set high when idle code is inserted in the associated tributary of the STM-4 stream on the OD[7:0] and is set low when the idle code is not inserted. IDLE[1] is updated on the rising edge of HSCLK.

IDLE[2] Output K22 The tributary idle indication signal output #2

(IDLE[2]) marks tributaries on the outgoing STM1 #2 stream that are in idle state.

In outgoing STM-1 (STS-3) interface mode (OHSMODEB set high), IDLE[2] is set high when idle code is inserted in the associated tributary on the OD[15:8] and is set low when the idle code is not inserted. IDLE[2] is updated on the rising edge of SCLK.

In outgoing STM-4 (STS-12) interface mode (OHSMODEB set low), IDLE[2] is invalid.

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PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

Pin Name Type Pin

Function

No.

IDLE[3] Output T22 The tributary idle indication signal output #3

(IDLE[3]) marks tributaries on the outgoing STM1 #3 stream that are in idle state.

In outgoing STM-1 (STS-3) interface mode (OHSMODEB set high), IDLE[3] is set high when idle code is inserted in the associated tributary on the OD[23:16] and is set low when the idle code is not inserted. IDLE[3] is updated on the rising edge of SCLK.

In outgoing STM-4 (STS-12) interface mode (OHSMODEB set low), IDLE[3] is invalid.

IDLE[4] Output

AB16

The tributary idle indication signal output #4 (IDLE[4]) marks tributaries on the outgoing STM1 #4 stream that are in idle state.

In outgoing STM-1 (STS-3) interface mode (OHSMODEB set high), IDLE[4] is set high when idle code is inserted in the associated tributary on the OD[31:24] and is set low when the idle code is not inserted. IDLE[4] is updated on the rising edge of SCLK.

In outgoing STM-4 (STS-12) interface mode (OHSMODEB set low), IDLE[4] is invalid.

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PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

Pin Name Type Pin

Function

No.

TPOH[1] Output H2 The outgoing tributary path overhead byte #1

(TPOH[1]) signal marks the tributary path overhead bytes in the outgoing STM-4 or STM-1 #1 stream. For streams in TU3 mode, the J1, B3, C2, G1, F2, H4, Z3, Z4 and Z5 bytes are marked. For streams out of TU3 mode, V5, J2, Z6 an Z7 bytes are marked.

In outgoing STM-1 (STS-3) interface mode (OHSMODEB set high), TPOH[1] is set high to mark each tributary path overhead byte of the STM-1 #1 stream on the OD[7:0] bus. TPOH[1] is updated on the rising edge of SCLK.

In outgoing STM-4 (STS-12) interface mode (OHSMODEB set low), TPOH[1] is set high to mark each tributary path overhead byte of the STM-4 stream on the OD[7:0] bus. TPOH[1] is set low for transport overhead bytes. TPOH[1] is updated on the rising edge of HSCLK.

TPOH[2] Output K23 The outgoing tributary path overhead byte #2

(TPOH[2]) signal marks the tributary path overhead bytes in the outgoing STM-1 #2 stream. For streams in TU3 mode, the J1, B3, C2, G1, F2, H4, Z3, Z4 and Z5 bytes are marked. For streams out of TU3 mode, V5, J2, Z6 an Z7 bytes are marked.

In outgoing STM-1 (STS-3) interface mode (OHSMODEB set high), TPOH[2] is set high to mark each tributary path overhead byte on the OD[15:8] bus. TPOH[2] is updated on the rising edge of SCLK.

In outgoing STM-4 (STS-12) interface mode (OHSMODEB set low), TPOH[2] is invalid.

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DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

Pin Name Type Pin

Function

No.

TPOH[3] Output T21 The outgoing tributary path overhead byte #3

(TPOH[3]) signal marks the tributary path overhead bytes in the outgoing STM-1 #3 stream. For streams in TU3 mode, the J1, B3, C2, G1, F2, H4, Z3, Z4 and Z5 bytes are marked. For streams out of TU3 mode, V5, J2, Z6 an Z7 bytes are marked.

In outgoing STM-1 (STS-3) interface mode (OHSMODEB set high), TPOH[3] is set high to mark each tributary path overhead byte on the OD[23:16] bus. TPOH[3] is updated on the rising edge of SCLK.

In outgoing STM-4 (STS-12) interface mode (OHSMODEB set low), TPOH[3] is invalid.

TPOH[4] Output

AC17

The outgoing tributary path overhead byte #4 (TPOH[4]) signal marks the tributary path overhead bytes in the outgoing STM-1 #4 stream. For streams in TU3 mode, the J1, B3, C2, G1, F2, H4, Z3, Z4 and Z5 bytes are marked. For streams out of TU3 mode, V5, J2, Z6 an Z7 bytes are marked.

In outgoing STM-1 (STS-3) interface mode (OHSMODEB set high), TPOH[4] is set high to mark each tributary path overhead byte on the OD[31:24] bus. TPOH[4] is updated on the rising edge of SCLK.

In outgoing STM-4 (STS-12) interface mode (OHSMODEB set low), TPOH[4] is invalid.

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PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

Pin Name Type Pin

Function

No.

OC1J1V1[1] Output D3 The outgoing composite frame pulse #1

(OC1J1V1[1]) marks the transport, synchronous payload envelope and tributary multiframe frame boundaries on the outgoing STM-4 or STM-1 #1 stream.

In outgoing STM-1 (STS-3) interface mode (OHSMODEB set high), OC1J1V1[1] pulses high to mark the first C1 byte of the STM-1 #1 transport envelope frame on the OD[7:0] bus. It also pulses high to mark the J1 byte(s). When AU3/TUG3 bypass is disabled (TUGEN set high and TUGBYP set low), the AU3/AU4 pointer offset (J1 position relative to C1) is determined by the corresponding STP Outgoing Pointer MSB and LSB registers. Optionally, OC1J1V1[1] also marks the third byte after J1 of the first tributary in each STS-1 (TUG3) stream when the corresponding OV1EN register bit is set high. When AU3/TUG3 bypass is enabled (TUGEN set low or TUGBYP set high), the J1 and V1 byte position pulses are delayed versions from the IC1J1[1] input. OC1J1V1[1] is updated on the rising edge of SCLK.

In outgoing STM-4 (STS-12) interface mode (OHSMODEB set low), OC1J1V1[1] pulses high to mark the first C1 byte of the STM-4 transport envelope frame on the OD[7:0] bus. It also pulses high to mark the STM-1 J1 bytes. When AU3/TUG3 bypass is disabled (TUGEN set high and TUGBYP set low), the AU3/AU4 pointer offset (J1 position relative to C1) of each STM-1 is determined by the corresponding STP Outgoing Pointer MSB and LSB registers. Optionally, OC1J1V1[1] also marks the third byte after J1 of the first tributary in each STS-1 (TUG3) stream when the corresponding OV1EN

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DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

Pin Name Type Pin

Function

No.

register bit is set high. When AU3/TUG3 bypass is enabled (TUGEN set low or TUGBYP set high), the J1 and V1 byte position pulses are delayed versions from the IC1J1[1] input. OC1J1V1[1] is updated on the rising edge of HSCLK.

OC1J1V1[2] Output F21 The outgoing composite frame pulse #2

(OC1J1V1[2]) marks the transport, synchronous payload envelope and tributary multiframe frame boundaries on the outgoing STM-1 #2 stream.

In outgoing STM-1 (STS-3) interface mode (OHSMODEB set high), OC1J1V1[2] pulses high to mark the first C1 byte of the STM-1 #2 transport envelope frame on the OD[15:8] bus. It also pulses high to mark the J1 byte(s). When AU3/TUG3 bypass is disabled (TUGEN set high and TUGBYP set low), the AU3/AU4 pointer offset (J1 position relative to C1) is determined by the corresponding STP Outgoing Pointer MSB and LSB registers. Optionally, OC1J1V1[2] also marks the third byte after J1 of the first tributary in each STS-1 (TUG3) stream when the corresponding OV1EN register bit is set high. When AU3/TUG3 bypass is enabled (TUGEN set low or TUGBYP set high), the J1 and V1 byte position pulses are delayed versions from the IC1J1[2] input. OC1J1V1[2] is updated on the rising edge of SCLK.

In outgoing STM-4 (STS-12) interface mode (OHSMODEB set low), OC1J1V1[2] is invalid.

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DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

Pin Name Type Pin

Function

No.

OC1J1V1[3] Output L22 The outgoing composite frame pulse #3

(OC1J1V1[3]) marks the transport, synchronous payload envelope and tributary multiframe frame boundaries on the outgoing STM-1 #3 stream.

In outgoing STM-1 (STS-3) interface mode (OHSMODEB set high), OC1J1V1[3] pulses high to mark the first C1 byte of the STM-1 #3 transport envelope frame on the OD[23:16] bus. It also pulses high to mark the J1 byte(s). When AU3/TUG3 bypass is disabled (TUGEN set high and TUGBYP set low), the AU3/AU4 pointer offset (J1 position relative to C1) is determined by the corresponding STP Outgoing Pointer MSB and LSB registers. Optionally, OC1J1V1[3] also marks the third byte after J1 of the first tributary in each STS-1 (TUG3) stream when the corresponding OV1EN register bit is set high. When AU3/TUG3 bypass is enabled (TUGEN set low or TUGBYP set high), the J1 and V1 byte position pulses are delayed versions from the IC1J1[3] input. OC1J1V1[3] is updated on the rising edge of SCLK.

In outgoing STM-4 (STS-12) interface mode (OHSMODEB set low), OC1J1V1[3] is invalid.

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PM5363 TUPP+622

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DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

Pin Name Type Pin

No.

OC1J1V1[4] Output

AB11

Function

The outgoing composite frame pulse #4 (OC1J1V1[4]) marks the transport, synchronous payload envelope and tributary multiframe frame boundaries on the outgoing STM-1 #4 stream.

In outgoing STM-1 (STS-3) interface mode (OHSMODEB set high), OC1J1V1[4] pulses high to mark the first C1 byte of the STM-1 #4 transport envelope frame on the OD[31:24] bus. It also pulses high to mark the J1 byte(s). When AU3/TUG3 bypass is disabled (TUGEN set high and TUGBYP set low), the AU3/AU4 pointer offset (J1 position relative to C1) is determined by the corresponding STP Outgoing Pointer MSB and LSB registers. Optionally, OC1J1V1[4] also marks the third byte after J1 of the first tributary in each STS-1 (TUG3) stream when the corresponding OV1EN register bit is set high. When AU3/TUG3 bypass is enabled (TUGEN set low or TUGBYP set high), the J1 and V1 byte position pulses are delayed versions from the IC1J1[4] input. OC1J1V1[4] is updated on the rising edge of SCLK.

In outgoing STM-4 (STS-12) interface mode (OHSMODEB set low), OC1J1V1[4] is invalid.

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DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

Pin Name Type Pin

Function

No.

OPL[1] Output E4 The outgoing payload active #1 (OPL[1]) signal

identifies synchronous payload envelope bytes on the outgoing STM-4 or STM-1 #1 stream. When AU3/TUG3 bypass is disabled (TUGEN set high and TUGBYP set low), OPL[1] is set high to mark synchronous payload envelop bytes and set low to mark transport overhead bytes. When AU3/TUG3 bypass is enabled (TUGEN set low or TUGBYP set high), OPL[1] is a delayed version of IPL[1].

In outgoing STM-1 (STS-3) interface mode (OHSMODEB set high), OPL[1] is updated on the rising edge of SCLK.

In outgoing STM-4 (STS-12) interface mode (OHSMODEB set low), OPL[1] is updated on the rising edge of HSCLK.

OPL[2] Output G20 The outgoing payload active #2 (OPL[2]) signal

identifies synchronous payload envelope bytes on the outgoing STM-1 #2 stream. When AU3/TUG3 bypass is disabled (TUGEN set high and TUGBYP set low), OPL[2] is set high to mark synchronous payload envelop bytes and set low to mark transport overhead bytes. When AU3/TUG3 bypass is enabled (TUGEN set low or TUGBYP set high), OPL[2] is a delayed version of IPL[2].

In outgoing STM-1 (STS-3) interface mode (OHSMODEB set high), OPL[2] is updated on the rising edge of SCLK.

In outgoing STM-4 (STS-12) interface mode (OHSMODEB set low), OPL[2] is invalid.

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PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

Pin Name Type Pin

Function

No.

OPL[3] Output L23 The outgoing payload active #3 (OPL[3]) signal

identifies synchronous payload envelope bytes on the outgoing STM-1 #3 stream. When AU3/TUG3 bypass is disabled (TUGEN set high and TUGBYP set low), OPL[3] is set high to mark synchronous payload envelop bytes and set low to mark transport overhead bytes. When AU3/TUG3 bypass is enabled (TUGEN set low or TUGBYP set high), OPL[3] is a delayed version of IPL[3].

In outgoing STM-1 (STS-3) interface mode (OHSMODEB set high), OPL[3] is updated on the rising edge of SCLK.

In outgoing STM-4 (STS-12) interface mode (OHSMODEB set low), OPL[3] is invalid.

OPL[4] Output

AC11

The outgoing payload active #4 (OPL[4]) signal identifies synchronous payload envelope bytes on the outgoing STM-1 #4 stream. When AU3/TUG3 bypass is disabled (TUGEN set high and TUGBYP set low), OPL[4] is set high to mark synchronous payload envelop bytes and set low to mark transport overhead bytes. When AU3/TUG3 bypass is enabled (TUGEN set low or TUGBYP set high), OPL[4] is a delayed version of IPL[4].

In outgoing STM-1 (STS-3) interface mode (OHSMODEB set high), OPL[4] is updated on the rising edge of SCLK.

In outgoing STM-4 (STS-12) interface mode (OHSMODEB set low), OPL[4] is invalid.

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DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

Pin Name Type Pin

Function

No.

POHCK Output L2 The tributary path overhead clock (POHCK)

signal provides timing to sample the extracted tributary path overhead stream and the receive alarm port for STM-1 #1, #2, #3 and #4. POHCK is a nominally 9.72 MHz clock. The POH[12:1], POHEN[12:1], POHFP[12:1] and RAD[4:1] outputs are updated on the falling edge of POHCK.

POH[1]

POH[2]

POH[3]

Output L4

The tributary path overhead (POH[3:1]) signals contain the tributary path overhead bytes (V5, J2, Z6 and Z7) extracted from the incoming STM-1 #1 stream. POH[1], POH[2] and POH[3] contain the tributary path overhead bytes from STS-1 (AU3) #1, #2 and #3, respectively. In AU4 mode, POH[1], POH[2] and POH[3] contain the tributary path overhead bytes from TUG3 #1, #2 and #3, respectively. All four tributary overhead bytes of each tributary is shifted out once per payload frame. The corresponding POHEN signal is set high to identify overhead bytes that are presented for the first time. Each POH signal is updated on the falling edge of POHCK.

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PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

Pin Name Type Pin

No.

POH[4]

POH[5]

POH[6]

POH[7]

POH[8]

POH[9]

Output A21

D21

D22

Output V22

V21

W21

Function

The tributary path overhead (POH[6:4]) signals contain the tributary path overhead bytes (V5, J2, Z6 and Z7) extracted from the incoming STM-1 #2 stream. POH[4], POH[5] and POH[6] contain the tributary path overhead bytes from STS-1 (AU3) #1, #2 and #3, respectively. In AU4 mode, POH[4], POH[5] and POH[6] contain the tributary path overhead bytes from TUG3 #1, #2 and #3, respectively. All four tributary overhead bytes of each tributary is shifted out once per payload frame. The corresponding POHEN signal is set high to identify overhead bytes that are presented for the first time. Each POH signal is updated on the falling edge of POHCK.

The tributary path overhead (POH[9:7]) signals contain the tributary path overhead bytes (V5, J2, Z6 and Z7) extracted from the incoming STM-1 #3 stream. POH[7], POH[8] and POH[9] contain the tributary path overhead bytes from STS-1 (AU3) #1, #2 and #3, respectively. In AU4 mode, POH[7], POH[8] and POH[9] contain the tributary path overhead bytes from TUG3 #1, #2 and #3, respectively. All four tributary overhead bytes of each tributary is shifted out once per payload frame. The corresponding POHEN signal is set high to identify overhead bytes that are presented for the first time. Each POH signal is updated on the falling edge of POHCK.

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DATASHEET

PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

Pin Name Type Pin

No.

POH[10]

POH[11]

POH[12]

POHFP[1]

POHFP[2]

POHFP[3]

Output AB8

Y10

AC10

Output K1

Function

The tributary path overhead (POH[12:10]) signals contain the tributary path overhead bytes (V5, J2, Z6 and Z7) extracted from the incoming STM-1 #4 stream. POH[10], POH[11] and POH[12] contain the tributary path overhead bytes from STS-1 (AU3) #1, #2 and #3, respectively. In AU4 mode, POH[10], POH[11] and POH[12] contain the tributary path overhead bytes from TUG3 #1, #2 and #3, respectively. All four tributary overhead bytes of each tributary is shifted out once per payload frame. The corresponding POHEN signal is set high to identify overhead bytes that are presented for the first time. Each POH signal is updated on the falling edge of POHCK.

The tributary path overhead frame pulse (POHFP[3:1]) signals may be used to locate the individual path overhead bits of each tributary for the corresponding STS-1 (TUG3) in the incoming STM-1 #1 stream. Each POHFP signal is set high to mark bit 1 (the most significant bit) of the V5 byte of the first tributary. POHFP[1], POHFP[2] and POHFP[3] identify frame boundaries of the tributary path overhead bytes from STS-1 (AU3) #1, #2 and #3, respectively. In AU4 mode, POHFP[1], POHFP[2] and POHFP[3] identify frame boundaries of TUG3 #1, #2 and #3, respectively. Each POHFP signal is updated on the falling edge of POHCK.

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PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

Pin Name Type Pin

No.

POHFP[4]

POHFP[5]

POHFP[6]

POHFP[7]

POHFP[8]

POHFP[9]

Output B20

C20

C23

Output U21

U20

Y23

Function

The tributary path overhead frame pulse (POHFP[6:4]) signals may be used to locate the individual path overhead bits of each tributary for the corresponding STS-1 (TUG3) in the incoming STM-1 #2 stream. Each POHFP signal is set high to mark bit 1 (the most significant bit) of the V5 byte of the first tributary. POHFP[4], POHFP[5] and POHFP[6] identify frame boundaries of the tributary path overhead bytes from STS-1 (AU3) #1, #2 and #3, respectively. In AU4 mode, POHFP[4], POHFP[5] and POHFP[6] identify frame boundaries of TUG3 #1, #2 and #3, respectively. Each POHFP signal is updated on the falling edge of POHCK.

The tributary path overhead frame pulse (POHFP[9:7]) signals may be used to locate the individual path overhead bits of each tributary for the corresponding STS-1 (TUG3) in the incoming STM-1 #3 stream. Each POHFP signal is set high to mark bit 1 (the most significant bit) of the V5 byte of the first tributary. POHFP[7], POHFP[8] and POHFP[9] identify frame boundaries of the tributary path overhead bytes from STS-1 (AU3) #1, #2 and #3, respectively. In AU4 mode, POHFP[7], POHFP[8] and POHFP[9] identify frame boundaries of TUG3 #1, #2 and #3, respectively. Each POHFP signal is updated on the falling edge of POHCK.

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PMC-1981421 ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S

INTERFACES

Pin Name Type Pin

No.

POHFP[10]

POHFP[11]

POHFP[12]

POHEN[1]

POHEN[2]

POHEN[3]

Output AA8

AB9

AA10

Output L3

Function

The tributary path overhead frame pulse (POHFP[12:10]) signals may be used to locate the individual path overhead bits of each tributary for the corresponding STS-1 (TUG3) in the incoming STM-1 #4 stream. Each POHFP signal is set high to mark bit 1 (the most significant bit) of the V5 byte of the first tributary. POHFP[10], POHFP[11] and POHFP[12] identify frame boundaries of the tributary path overhead bytes from STS-1 (AU3) #1, #2 and #3, respectively. In AU4 mode, POHFP[10], POHFP[11] and POHFP[12] identify frame boundaries of TUG3 #1, #2 and #3, respectively. Each POHFP signal is updated on the falling edge of POHCK.

The tributary path overhead enable (POHEN[3:1]) signals may be used to identify tributary path overhead bytes that are being presented on the corresponding POH stream of STM-1 #1 for the first time. Each POHEN signal is set high when a fresh overhead byte is available on the corresponding POH stream. POHEN is set low when the tributary path overhead byte available on the corresponding POH stream has already been shifted out in a previous frame. POHEN[1], POHEN[2] and POHEN[3] identify the status of tributary path overhead bytes from STS-1 (AU3) #1, #2 and #3, respectively. In AU4 mode, POHEN[1], POHEN[2] and POHEN[3] identify the status of tributary path overhead bytes from TUG3 #1, #2 and #3, respectively. Each POHEN signal is updated on the falling edge of POHCK.

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Datasheet PM5363-BI Datasheet (PMC)

Specifications and Main Features

Frequently Asked Questions

User Manual

REVISION HISTORY

CONTENTS

LIST OF REGISTERS

LIST OF FIGURES

9 PIN DESCRIPTION (304)