PMC PM5357-BI Datasheet
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S/UNI-622-MAX
DATASHEET
PMC-1980589 ISSUE 6 SATURN USER NETWORK INTERFACE (622-MAX)
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PM5356
S/UNI-622-MAX
PM5356
S/UNI-622-MAX
SATURN
USER NETWORK INTERFACE
(622-MAX)
R
S/
UNI -
622-MAX
DATASHEET
ISSUE 6: JUNE 2000
PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000
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PMC-1980589 ISSUE 6 SATURN USER NETWORK INTERFACE (622-MAX)
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S/UNI-622-MAX
REVISION HISTORY
ISSUE DATE DETAIL
6 June 2000 Corrected block diagram.
Corrected function name errors in Register 0x03: S/UNI-622
MAX Clock Monitors. Changed PTCLKI to PTCLK, REFCLKI
to REFCLK, RFCLKI to RFCLK, RCLKI to RCLK and TCLKI to
TCLK.
Added line loopback operation information to RXDINV and
TXDINV in Register 0x07: S/UNI-622-MAX Miscellaneous
Configuration.
Rewrote IINVCNT bit functionality for clarity. Register 0x30
(EXTD=1): RPOP Status/Control.
Rewrote DOOLI bit functionality to indicate change to DOOLV
bit and CRU out of lock conditions in Register 0.5C: CRSI
Configuration.
Rewrote DOOLE bit functionality to indicate change to DOOLV
register events in Register 0x5D: CRSI Status.
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ISSUE DATE DETAIL
5 Dec, 1999
#1 Modified section 9.4 (UTOPIA pin description) and
section 14.2 (Functional timing) to reflect operation of the RCA
signal
#2 DC characteristics update (Section 16)
#3 Registers updated with correct defaults and descriptions:
Register 0X01, Bit 4 (TFPEN), Defaults To 1, Not 0
Register 0X08, Description Incorrect
Register 0X09 Description Incorrect
New Register 0XFC: Concatenation Status And Enable
New Register 0XFD: Concatenation Interrupt Status
New Register Bit Required For OC-3 Operation (Register 0X07)
Register 0X5E Bit 5 (RTYPE) should be set to zero for
improved Jitter Tolerance
Register 0X00 Type Bits Incorrect
Loss Of Multi-frame Tributary AIS (LOMTUAIS) Bit 2 Incorrectly
Stated In Register 0X0D
#4 APS pin description modified
#6 Updated TFCLK timing specifications, RFCLK timing
specifications
#7 Diagnostic Loop-back Clarification
#8 Bit Error Rate Monitor Table Update
#9 Receive Data Requires 3 RFCLK Cycles Before
Becoming Valid (Utopia Level 3 Only)
#11 Receive Line AIS Insertion Is Not Gated By ALLONES
#12 Large Power Supply Glitch (Beyond Specification) Can
Cause Clock Synthesis Unit To Lose Lock To Reference.
4 January 4,
Corrected wrong pin number assignments in pin description.
1999
3 Dec 15,
General update
1999
2 Aug 30,
1998
Re-organized registers. Removed UDF. Update pin list and
block diagram. Add preliminary simulation and test sections
text.
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PMC-1980589 ISSUE 6 SATURN USER NETWORK INTERFACE (622-MAX)
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ISSUE DATE DETAIL
1 Jan 5, 1998 Created document
PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000
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CONTENTS
1 FEATURES..................................................................................................................................... 1
1.1 GENERAL ........................................................................................................................ 1
1.2 THE SONET RECEIVER.................................................................................................. 2
1.3 THE RECEIVE ATM PROCESSOR.................................................................................. 2
1.4 THE SONET TRANSMITTER........................................................................................... 3
1.5 THE TRANSMIT ATM PROCESSOR ............................................................................... 4
2 APPLICATIONS.............................................................................................................................. 5
3 REFERENCES ............................................................................................................................... 6
4 DEFINITIONS................................................................................................................................. 7
5 APPLICATION EXAMPLES.......................................................................................................... 10
6 BLOCK DIAGRAM........................................................................................................................ 13
7 DESCRIPTION ............................................................................................................................. 14
8 PIN DIAGRAM.............................................................................................................................. 16
9 PIN DESCRIPTION ...................................................................................................................... 17
9.1 SERIAL LINE SIDE INTERFACE SIGNALS................................................................... 17
9.2 PARALLEL LINE SIDE INTERFACE SIGNALS - CRU AND CSU BYPASS................... 19
9.3 CLOCKS AND ALARMS SIGNALS................................................................................. 22
9.4 ATM (UTOPIA) SYSTEM INTERFACE........................................................................... 24
9.5 MICROPROCESSOR INTERFACE SIGNALS ............................................................... 31
9.6 JTAG TEST ACCESS PORT (TAP) SIGNALS................................................................ 33
9.7 ANALOG SIGNALS........................................................................................................ 34
9.8 POWER AND GROUND................................................................................................. 35
10 FUNCTIONAL DESCRIPTION...................................................................................................... 41
10.1 RECEIVE LINE INTERFACE (CRSI-622)....................................................................... 41
10.2 RECEIVE SECTION OVERHEAD PROCESSOR (RSOP)............................................. 43
10.3 RECEIVE LINE OVERHEAD PROCESSOR (RLOP)..................................................... 45
10.4 THE RECEIVE APS, SYNCHRONIZATION EXTRACTOR AND BIT ERROR MONITOR
(RASE) ........................................................................................................................... 46
10.5 RECEIVE PATH OVERHEAD PROCESSOR (RPOP)....................................................47
10.6 RECEIVE ATM CELL PROCESSOR (RXCP)................................................................. 52
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10.7 TRANSMIT LINE INTERFACE (CSPI-622) .................................................................... 56
10.8 TRANSMIT SECTION OVERHEAD PROCESSOR (TSOP)........................................... 57
10.9 TRANSMIT LINE OVERHEAD PROCESSOR (TLOP)................................................... 58
10.10 TRANSMIT PATH OVERHEAD PROCESSOR (TPOP) ................................................. 58
10.11 TRANSMIT ATM CELL PROCESSOR (TXCP)............................................................... 60
10.12 ATM UTOPIA SYSTEM INTERFACES........................................................................... 61
10.13 JTAG TEST ACCESS PORT.......................................................................................... 63
10.14 MICROPROCESSOR INTERFACE................................................................................ 63
11 NORMAL MODE REGISTER DESCRIPTION.............................................................................. 69
12 TEST FEATURES DESCRIPTION.............................................................................................. 227
12.1 MASTER TEST AND T EST CONFIGURATION REGISTERS...................................... 227
12.2 JTAG TEST PORT........................................................................................................ 230
13 OPERATION............................................................................................................................... 237
13.1 SONET/SDH FRAME MAPPINGS AND OVERHEAD BYTE USAGE .......................... 237
13.2 ATM CELL DATA STRUCTURE.................................................................................... 242
13.3 SETTING SONET OR SDH MODE OF OPERATION................................................... 243
13.4 BIT ERROR RATE MONITOR...................................................................................... 245
13.5 AUTO ALARM CONTROL CONFIGURATION.............................................................. 246
13.6 CLOCKING OPTIONS.................................................................................................. 247
13.7 LOOPBACK OPERATION............................................................................................ 248
13.8 1+1 APS SUPPORT ..................................................................................................... 252
13.9 JTAG SUPPORT .......................................................................................................... 253
13.10 BOARD DESIGN RECOMMENDATIONS .................................................................... 258
13.11 POWER SUPPLIES ..................................................................................................... 259
13.12 INTERFACING TO ECL OR PECL DEVICES............................................................... 262
13.13 CLOCK SYNTHESIS AND RECOVERY....................................................................... 264
13.14 SYSTEM INTERFACE DLL OPERATION..................................................................... 265
14 FUNCTIONAL TIMING................................................................................................................ 267
14.1 PARALLEL LINE INTERFACE...................................................................................... 267
14.2 ATM UTOPIA LEVEL 2 SYSTEM INTERFACE............................................................. 268
14.3 ATM UTOPIA LEVEL 3 SYSTEM INTERFACE............................................................. 269
15 ABSOLUTE MAXIMUM RATINGS .............................................................................................. 272
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16 D.C. CHARACTERISTICS..........................................................................................................273
17 MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS............................................ 276
18 A.C. TIMING CHARACTERISTICS............................................................................................. 280
18.1 SYSTEM RESET TIMING............................................................................................. 280
18.2 PARALLEL LINE INTERFACE TIMING ........................................................................ 281
18.3 SERIAL LINE INTERFACE TIMING.............................................................................. 283
18.4 UTOPIA LEVEL 2 SYSTEM INTERFACE TIMING ....................................................... 284
18.5 UTOPIA LEVEL 3 SYSTEM INTERFACE TIMING ....................................................... 288
18.6 CLOCK AND FRAME PULSE INTERFACE TIMING.................................................... 291
18.7 JTAG TEST PORT TIMING.......................................................................................... 292
19 ORDERING AND THERMAL INFORMATION............................................................................. 294
20 MECHANICAL INFORMATION................................................................................................... 295
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LIST OF TABLES
TABLE 1: POINTER INTERPRETER EVENT (INDICATIONS) DESCRIPTION......................................... 48
TABLE 2: POINTER INTERPRETER TRANSITION DESCRIPTION......................................................... 50
TABLE 3: REGISTER MEMORY MAP....................................................................................................... 63
TABLE 4: TEST MODE REGISTER MEMORY MAP ............................................................................... 227
TABLE 5: INSTRUCTION REGISTER (LENGTH - 3 BITS) ..................................................................... 230
TABLE 6: S/UNI-622-MAX IDENTIFICATION REGISTER....................................................................... 230
TABLE 7: S/UNI-622-MAX BOUNDARY SCAN REGISTER .................................................................... 230
TABLE 8: SETTINGS FOR SONET OR SDH OPERATION..................................................................... 244
TABLE 9: RECOMMENDED BERM SETTINGS...................................................................................... 246
TABLE 10: PATH RDI AND EXTENDED RDI REGISTER SETTINGS..................................................... 246
TABLE 11: 1+1 APS REGISTER 0X06 SETTINGS.................................................................................. 253
TABLE 12: ABSOLUTE MAXIMUM RATINGS ......................................................................................... 272
TABLE 13: D.C CHARACTERISTICS ...................................................................................................... 273
TABLE 14: MICROPROCESSOR INTERFACE READ ACCESS (FIGURE 35)....................................... 276
TABLE 15: MICROPROCESSOR INTERFACE WRITE ACCESS (FIGURE 36) ..................................... 278
TABLE 16: RSTB TIMING (FIGURE 37).................................................................................................. 280
TABLE 17: TRANSMIT PARALLEL LINE INTERFACE TIMING (FIGURE 38)......................................... 281
TABLE 18: RECEIVE PARALLEL LINE INTERFACE TIMING (FIGURE 39)........................................... 282
TABLE 19: RECEIVE SERIAL LINE INTERFACE TIMING (FIGURE 40)................................................. 283
TABLE 20: TRANSMIT UTOPIA LEVEL 2 SYSTEM INTERFACE TIMING (FIGURE 41)........................ 284
TABLE 21: RECEIVE UTOPIA LEVEL 2 SYSTEM INTERFACE TIMING (FIGURE 42) .......................... 286
TABLE 22: TRANSMIT UTOPIA LEVEL 3 SYSTEM INTERFACE TIMING (FIGURE 43)........................ 288
TABLE 23: RECEIVE UTOPIA LEVEL 3 SYSTEM INTERFACE TIMING (FIGURE 44) .......................... 290
TABLE 24: CLOCK AND FRAME PULSE INTERFACE TIMING (FIGURE 45)........................................ 291
TABLE 25: JTAG PORT INTERFACE (FIGURE 46)................................................................................. 292
TABLE 26: ORDERING INFORMATION.................................................................................................. 294
TABLE 27: THERMAL INFORMATION..................................................................................................... 294
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LIST OF FIGURES
FIGURE 1: TYPICAL STS-12C/STM-4-4C ATM (UTOPIA LEVEL 2) SWITCH PORT APPLICATION........11
FIGURE 2: TYPICAL STS-12C/STM-4-4C ATM (UTOPIA LEVEL 3) SWITCH PORT APPLICATION........11
FIGURE 3: TYPICAL STS-12C/STM-4-4C S/UNI-622-MAX JITTER TOLERANCE .................................. 42
FIGURE 4: POINTER INTERPRETATION STATE DIAGRAM.................................................................... 48
FIGURE 5: CELL DELINEATION STATE DIAGRAM.................................................................................. 53
FIGURE 6: HCS VERIFICATION STATE DIAGRAM.................................................................................. 55
FIGURE 7: INPUT OBSERVATION CELL (IN_CELL).............................................................................. 235
FIGURE 8: OUTPUT CELL (OUT_CELL) ................................................................................................ 235
FIGURE 9: BIDIRECTIONAL CELL (IO_CELL) ....................................................................................... 236
FIGURE 10: LAYOUT OF OUTPUT ENABLE AND BIDIRECTIONAL CELLS......................................... 236
FIGURE 11: ATM MAPPING INTO THE STS-12C/STM-4-4C SPE..........................................................237
FIGURE 12: STS-12C/STM-4-4C OVERHEAD ....................................................................................... 238
FIGURE 13: 16-BIT WIDE, 27 WORD ATM CELL STRUCTURE............................................................. 242
FIGURE 14: 8-BIT WIDE, 54 BYTE ATM CELL STRUCTURE................................................................. 243
FIGURE 15: CLOCKING STRUCTURE................................................................................................... 247
FIGURE 16: LINE LOOPBACK MODE.................................................................................................... 249
FIGURE 17: SERIAL DIAGNOSTIC LOOPBACK MODE......................................................................... 250
FIGURE 18: PARALLEL DIAGNOSTIC LOOPBACK MODE................................................................... 250
FIGURE 19: PATH DIAGNOSTIC LOOPBACK MODE............................................................................ 251
FIGURE 20: DATA DIAGNOSTIC LOOPBACK MODE............................................................................ 251
FIGURE 21: 1+1 APS ARCHITECTURE.................................................................................................. 252
FIGURE 22: BOUNDARY SCAN ARCHITECTURE................................................................................. 254
FIGURE 23: TAP CONTROLLER FINITE STATE MACHINE................................................................... 255
FIGURE 24: POWER SUPPLY FILTERING AND DECOUPLING............................................................ 261
FIGURE 25: POWER SUPPLY COMPONENT LAYOUT......................................................................... 262
FIGURE 26: INTERFACING S/UNI-622-MAX PECL PINS TO 3.3V DEVICES........................................ 263
FIGURE 27: INTERFACING S/UNI-622-MAX PECL PINS TO 5.0V DEVICES........................................ 264
FIGURE 28: IN FRAME DECLARATION TIMING.................................................................................... 267
FIGURE 29: OUT OF FRAME DECLARATION TIMING .......................................................................... 268
FIGURE 30: PARALLEL TRANSMIT INTERFACE TIMING ..................................................................... 268
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FIGURE 31: TRANSMIT UTOPIA LEVEL 2 SYSTEM INTERFACE TIMING............................................ 269
FIGURE 32: RECEIVE UTOPIA LEVEL 2 SYSTEM INTERFACE TIMING............................................... 269
FIGURE 33: TRANSMIT UTOPIA LEVEL 3 SYSTEM INTERFACE TIMING............................................ 270
FIGURE 34: RECEIVE UTOPIA LEVEL 3 SYSTEM INTERFACE TIMING............................................... 271
FIGURE 35: MICROPROCESSOR INTERFACE READ TIMING............................................................. 276
FIGURE 36: MICROPROCESSOR INTERFACE WRITE TIMING........................................................... 278
FIGURE 37: RSTB TIMING DIAGRAM.................................................................................................... 280
FIGURE 38: TRANSMIT PARALLEL LINE INTERFACE TIMING DIAGRAM........................................... 281
FIGURE 39: RECEIVE PARALLEL LINE INTERFACE TIMING DIAGRAM ............................................. 282
FIGURE 40: RECEIVE SERIAL LINE INTERFACE TIMING DIAGRAM.................................................. 283
FIGURE 41: TRANSMIT UTOPIA LEVEL 2 SYSTEM INTERFACE TIMING DIAGRAM.......................... 285
FIGURE 42: RECEIVE UTOPIA LEVEL 2 SYSTEM INTERFACE TIMING DIAGRAM............................ 287
FIGURE 43: TRANSMIT UTOPIA LEVEL 3 SYSTEM INTERFACE TIMING DIAGRAM.......................... 289
FIGURE 44: RECEIVE UTOPIA LEVEL 3 SYSTEM INTERFACE TIMING DIAGRAM............................ 290
FIGURE 45: CLOCK AND FRAME PULSE INTERFACE TIMING........................................................... 291
FIGURE 46: JTAG PORT INTERFACE TIMING....................................................................................... 292
FIGURE 47: MECHANICAL DRAWING 304 PIN SUPER BALL GRID ARRAY (SBGA) .......................... 295
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1 FEATURES
1.1 General
• Single chip ATM over SONET/SDH Physical Layer Device operating at 622.08
Mbit/s.
• Implements the ATM Forum User Network Interface Specification and the ATM
physical layer for Broadband ISDN according to CCITT Recommendation I.432.
• Processes duplex bit-serial 622.08 Mbit/s STS-12c/STM-4-4c data streams with
on-chip clock and data recovery and clock synthesis.
• Supports a duplex byte-serial 77.76 Mbyte/s STS-12c/STM-4-4c line side
interface for use in applications where by-passing clock recovery, clock
synthesis, and serializer-deserializer functionality is desired.
• Supports a byte-serial 19.44 Mbyte/s STS-3c/STM-1 line side interface on the
transmit and/or receive interface for use in applications where a 155.52 Mbit/s
data rate is desired.
• Supports clock recovery by-pass for use in applications where external clock
recovery is desired.
• Provides UTOPIA Level 2 16-bit wide System Interface (clocked up to 50 MHz)
with parity support for ATM applications.
• Provides UTOPIA Level 3 compatible 8-bit wide System Interface (clocked up to
100 MHz) with parity support for ATM applications.
• Provides support functions for a two chip solution for 1+1 APS operation.
• Provides a standard 5 signal IEEE 1149.1 JTAG test port for boundary scan
board test purposes.
• Provides a generic 8-bit microprocessor bus interface for configuration, control,
and status monitoring.
• Low power 3.3V CMOS with TTL compatible digital inputs and CMOS/TTL digital
outputs. PECL inputs and outputs are 3.3V and 5V compatible.
• Industrial temperature range (-40°C to +85°C).
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• 304 pin Super BGA package.
1.2 The SONET Receiver
• Provides a serial interface at 622.08 Mbit/s with clock and data recovery.
• Frames to and de-scrambles the received STS-12c/STM-4-4c stream.
• Optionally frames to and de-scrambles a received STS-3c/STM-1 stream.
• Interprets the received payload pointer (H1, H2) and extracts the STS-12c/STM-
4-4c or STS-3c/STM-1 synchronous payload envelope and path overhead.
• Filters and captures the automatic protection switch channel (APS) bytes in
readable registers and detects APS byte failure.
• Captures and de-bounces the synchronization status (S1) nibble in a readable
register.
• Detects signal degrade (SD) and signal fail (SF) threshold crossing alarms based
on received B2 errors.
• Extracts the 16-byte or 64-byte section trace (J0/Z0) sequence and the 16-byte
or 64-byte path trace (J1) sequence into internal register banks.
• Detects loss of signal (LOS), out of frame (OOF), loss of frame (LOF), line alarm
indication signal (AIS-L), line remote defect indication (RDI-L), loss of pointer
(LOP), path alarm indication signal (AIS-P), path remote defect indication (RDIP), path extended remote defect indicator (extended RDI-P).
• Counts received section BIP-8 (B1) errors, received line BIP-96 (B2) errors, line
remote error indicates (REI-L), received path BIP-8 (B3) errors and path remote
error indications (REI-P) for performance monitoring purposes.
1.3 The Receive AT M Processor
• Extracts ATM cells from the received STS-12c/STM-4-4c or STS-3c/STM-1
payload using ATM cell delineation.
• Provides ATM cell payload de-scrambling.
• Performs header check sequence (HCS) error detection and correction, and
idle/unassigned cell filtering.
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• Detects out of cell Delineation (OCD) and loss of cell delineation (LCD) alarms.
• Counts number of received cells, idle cells, errored cells and dropped cells.
• Provides a UTOPIA Level 2 compliant 16-bit wide datapath interface (clocked up
to 50 MHz) with parity support to read extracted cells from an internal four-cell
FIFO buffer.
• Provides a UTOPIA Level 3 compatible 8-bit wide datapath interface (clocked up
to 100 MHz) with parity support to read extracted cells from an internal four-cell
FIFO buffer.
1.4 The SONET Transmitter
• Synthesizes the 622.08 MHz transmit clock from a 77.76 MHz reference.
• Provides a differential PECL bit-serial interface at 622.08 Mbit/s.
• Inserts a register programmable path signal label (C2).
• Generates the transmit payload pointer (H1, H2) and inserts the path overhead.
• Optionally inserts the 16-byte or 64-byte section trace (J0/Z0) sequence and the
16-byte or 64-byte path trace (J1) sequence from internal register banks.
• Optionally inserts externally generated data communication channels (D1-D3,
D4-D12) via a 192 kbit/s (D1-D3) serial stream and a 576 kbit/s (D4-D12) serial
stream.
• Scrambles the t ransmitted STS-12c/STM-4-4c or STS -3c/STM-1 stream and
inserts the framing bytes (A1, A2).
• Optionally inserts register programmable APS bytes.
• Provides a byte-serial transmit path data stream allowing two devices to
implement 1+1 APS.
• Inserts path BIP-8 codes (B3), path remote error indications (REI-P ), line BIP-96
codes (B2), line remote error indications (REI-L), and section BIP-8 codes (B1) to
allow performance monitor i ng at the far end.
• Allows forced insertion of all-zeros data (after scrambling) and the corruption of
the section, line, or path BIP-8 codes for diagnostic purposes.
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• Inserts ATM cells into the transmitted STS-12c/STM-4-4c or STS-3c/STM-1
payload.
1.5 The Transmit ATM Processor
• Provides idle/unassigned cell insertion.
• Provides HCS generation/insertion, and ATM cell payload scrambling.
• Counts number of transmitted and idle cells.
• Provides a UTOPIA Level 2 compliant 16-bit wide datapath interface (clocked up
to 50 MHz) with parity support for writing cells into an internal four-cell FIFO.
• Provides a UTOPIA Level 3 compatible 8-bit wide datapath interface (clocked up
to 100 MHz) with parity support for writing cells into an internal four-cell FIFO.
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2 APPLICATIONS
• WAN and Edge ATM switches.
• LAN switches and hubs.
• Routers and Layer 3 Switches
• Network Interface Cards and Uplinks
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3 REFERENCES
• ATM Forum - ATM User-Network Interface Specification, V3.1, October, 1995.
• ATM Forum - “UTOPIA, An ATM PHY Interface Specification, Level 2, Version 1”,
June, 1995.
• Bell Communications Research - GR-253-CORE “SONET Transport Systems:
Common Generic Criteria”, Issue 2, December 1995.
• Bell Communications Resea rch - GR-436-CORE “Digital Network
Synchronization Plan”, Issue 1 Revision 1, June 1996..
• ETS 300 417-1-1, "Generic Functional Requirements for Synchronous Digital
Hierarchy (SDH) Equipment", January, 1996.
• ITU-T Recommendation G.703 - "Physical/Electrical Characteristics of
Hierarchical Digital Interfaces", 1991.
• ITU-T Recommendation G.704 - "General Aspects of Digital Transmission
Systems; Terminal Equipment - Synchronous Frame Structures Used At 1544,
6312, 2048, 8488 and 44 736 kbit/s Hierarchical Levels", July, 1995.
• ITU, Recommendation G.707 - "Network Node Interface For The Synchronous
Digital Hierarchy", 1996.
• ITU Recommendation G781, “Structure of Recommendations on Equipment for
the Synchronous Design Hierarchy (SDH)”, January 1994.
• ITU, Recommendation G.783 - "Characteristics of Synchronous Digital Hierarchy
(SDH) Equipment Functional Blocks", 1996.
• ITU Recommendation I.432, “ISDN User Network Interfaces”, March 93.
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4 DEFINITIONS
The following table defines the abbreviations for the S/UNI-622-MAX.
AIS Alarm Indication Signal
APS Automatic Protection Switching
ASSP Application Specific Standard Product
ATM Asynchronous Transfer Mode
BER Bit Error Rate
BIP Byte Interleaved Parity
CBI Common Bus Interface
CMOS Complementary Metal Oxide Semiconductor
CRC Cyclic Redundancy Check
CRSI CRU and Serial-In Parallel-Out
CRU Clock Recovery Unit
CSPI CSU and Parallel-In Serial-Out
CSU Clock Synthesis Unit
ECL Emitter Controlled Logic
ERDI Enhanced Remote Defect Indication
ESD Electrostatic Discharge
FEBE Far-End Block Error
FIFO First-In First-Out
GFC Generic Flow Control
HCS Header Check Sequence
LAN Local Area Network
LCD Loss of Cell Delineation
LOF Loss of Frame
LOH Line Overhead
LOP Loss of Pointer
LOS Loss of Signal
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LOT Loss of Transition
NC No Connect, indicates an unused pin
NDF New Data Flag
NNI Network-Network Interface
ODL Optical Data Link
OOF Out of Frame
PECL Pseudo-ECL
PLL Phase-Locked Loop
PSL Path Signal Label
PSLM Path Signal Label Mismatch
RASE Receive APS, Synchronization Extractor and Bit
Error Monitor
RDI Remote Defect Indication
RLOP Receive Line Overhead Processor
RPOP Receive Path Overhead Processor
RSOP Receive Section Overhead Processor
RXCP Receive ATM Cell Processor
SBGA Super Ball Grid Array
SD Signal Degrade (alarm), Signal Detect (pin)
SDH Synchronous Digital Hierarchy
SF Signal Fail
SOH Section Overhead
SONET Synchronous Optical Network
SPE Synchronous Payload Envelope
TLOP Transmit Line Overhead Processor
TOH Transport Overhead
TPOP Transmit Path Overhead Processor
TSOP Transmit Section Overhead Processor
TXCP Transmit ATM Cell Processor
UI Un it Interval
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PM5356
S/UNI-622-MAX
UNI User-Network Interface
VCI Virtual Connection Indicator
VPI Virtual Path Indicator
WAN Wide Area Network
XOR Exclusive OR logic operator
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5 APPLICATION EXAMPLES
The PM5357 S/UNI-622-MAX is applicable to equipment implementing
Asynchronous Transfer Mode (ATM) User-Network Interfaces (UNI) and ATM
Network-Network Interfaces (NNI).
The S/UNI-622-MAX may find application at either end of switch-to-switch links
or switch-to-terminal links, both in public network (WAN) and private network
(LAN) situations. The S/UNI-622-MAX performs the mapping of ATM cells into
the SONET/SDH STS-12c/STM-4-4c synchronous payload envelope (SPE) and
processes applicable SONET/SDH section, line and path overheads.
In a typical STS-12c/STM-4-4c ATM application, the S/UNI-622-MAX performs
clock and data recovery in the receive direction and clock synthesis in the
transmit direction of the line interface. The S/UNI-622-MAX can also be
configured to by-pass the clock recovery, clock synthesis, and serializer/deserializer functions. In this mode, an external clock and data recovery/serial-toparallel converter device is required in the receive direction, and an external
serial-to-parallel converter/clock synthesis device is required in the transmit
direction.
On the system side, the S/UNI-622-MAX interfaces directly with ATM layer
processors and switching or adaptation functions using a UTOPIA Level 2
compliant 16-bit (clocked up to 50 MHz) or an UTOPIA Level 3 8-bit (clocked up
to 100 MHz) synchronous FIFO style interface.
An application with a UTOPIA Level 2 system side interface is shown in Figure 1.
An application with a UTOPIA Level 3 system side is shown in Figure 2. The
initial configuration and ongoing control and monitoring of the S/UNI-622-MAX
are normally provided via a generic microprocessor interface.
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Figure 1: Typical STS-12c/STM-4-4c ATM (UTOPIA Level 2) Switch Port
Application
UTOPIA Level 2
Interface
ATM Layer Device
PM5356
S/UNI-622-MAX
TxClk
TxEnb
TxClav
TxSOC
TxPrty
TxData[15:0]
RxClk
RxEnb
RxClav
RxSOC
RxPrty
RxData[15:0]
TFCLK
TENB
TCA
TSOC
TPRTY
TDAT[15:0]
RFCLK
RENB
RCA
RSOC
RPRTY
RDAT[15:0]
LIFSEL
RXD+/-
SD
TXD+/-
SYSSEL
0
Optical
Transceiver
0
ure 2: Typical STS-12c/STM-4-4c ATM (UTOPIA Level 3) Switch Port
Application
Fig
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S/UNI-622-MAX
UTOPIA Level 3
Interface
ATM Layer Device
PM5356
S/UNI-622-MAX
TxClk
TxEnb
TxClav
TxSOC
TxPrty
TxData[7:0]
RxClk
RxEnb
RxVal
RxSOC
RxPrty
RxData[7:0]
TFCLK
TENB
TCA
TSOC
TPRTY
TDAT[7:0]
RFCLK
RENB
RVAL
RSOC
RPRTY
RDAT[7:0]
LIFSEL
RXD+/-
SD
TXD+/-
SYSSEL
0
Optical
Transceiver
1
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6 BLOCK DIAGRAM
PMC-1980589 ISSUE 6 SATURN USER NETWORK INTERFACE (622-MAX)
RELEASED
S/UNI-622-MAX
DATASHEET
TXD+/-
TDREF1, TDREF0
ATP[0]
PTCLK
POUT[7:0]
FPOUT
RBYP
PECLV
REFCLK+/-
RXD+/-
RRCLK+/-
SD
ATP[1]
PICLK
PIN[7:0]
FPIN
OOF
Tx Line
I/F
Rx Line
I/F
LIFSEL
TFPO
TFPI
Tx
Section O/H
Processor
Rx
Section O/H
Processor
TCLK
Tx
Line O/H
Processor
Rx
Line O/H
Processor
TRSTB
TMS
TCK
JTAG Test
Access Port
Tx
Path O/H
Processor
Rx
Path O/H
Processor
Rx APS,
Sync Status,
BERM
TDI
TDO
Tx
ATM Cell
Processor
Rx
ATM Cell
Processor
Microprocessor
Interface
SYSSEL
UTOPIA ATM Level 2
UTOPIA ATM Level 3
System Interface
TFCLK
TENB
TCA
TSOC
TPRTY
TDAT[15:0]
PMC-Sierra, Inc.
RFCLK
RENB
RCA
RSOC
RPRTY
RVAL
RDAT[15:0]
RFPO
RALARM
RCLK
APSP[4:0]
D[7:0]
A[8:0]
ALE
CSB
WRB
RDB
RSTB
INTB
S/UNI-622-MAX
PM5356
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7 DESCRIPTION
The PM5357 S/UNI-622-MAX SATURN User Network Interface is a monolithic
integrated circuit that implements SONET/SDH processing, ATM mapping over
SONET/SDH mapping functions at the STS-12c/STM-4-4c 622.08 Mbit/s rate.
The S/UNI-622-MAX receives SONET/SDH streams using a bit serial interface,
recovers the clock and data and processes section, line, and path overhead. The
S/UNI-622-MAX can also be configured for clock and data recovery and clock
synthesis by-pass where it receives SONET/SDH frames via a byte-serial
interface. The S/UNI-622-MAX performs framing (A1, A2), de-scrambling,
detects alarm conditions, and monitors section, line, and path bit interleaved
parity (B1, B2, B3), accumulating error counts at each level for performance
monitoring purposes. Line and path remote error indications (M1, G1) are also
accumulated. The S/UNI-622-MAX interprets the received payload pointers (H1,
H2) and extracts the synchronous payload envelope which carries the received
ATM cell payload.
When used to implement an ATM UNI or NNI, the S/UNI-622-MAX f r ames to the
ATM payload using cell delineation. HCS error correction is provided.
Idle/unassigned cells may be optionally dropped. Cells are also dropped upon
detection of an uncorrectable header check sequence error. The ATM cell
payloads are descrambled and are written to a four-cell FIFO buffer. The
received cells are read from the FIFO using a 16-bit wide UTOPIA Level 2
(clocked up to 50 MHz) or an 8-bit wide UTOPIA Level 3 (clocked up to 100 MHz)
datapath interface. Counts of received ATM cell headers that are errored and
uncorrectable and those that are errored and correctable are accumulated
independently for performance monitoring purposes.
The S/UNI-622-MAX transmits SONET/SDH streams using a bit serial interface.
The S/UNI-622-MAX can also be configured for clock and data recovery and
clock synthesis by-pass where it transmits the SONET/SDH frames via a byteserial interface. The S/UNI-622-MAX synthesizes the transmit clock from a
77.76MHz frequency reference and performs framing pattern insertion (A1, A2),
scrambling, alarm signal insertion, and creates section, line, and path bit
interleaved parity codes (B1, B2, B3) as required to allow performance
monitoring at the far end. Line and path remote error indications (M1, G1) are
also inserted. The S/UNI-622-MAX also supports the insertion of a large variety
of errors into the transmit stream, such as framing pattern errors, bit interleaved
parity errors, and illegal pointers, which are useful for system diagno stics and
tester applications.
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When used to im plement an ATM UNI or NNI, ATM cells are writte n to an internal
four cell FIFO using a 16-bit wide UTOPIA Level 2 (clocked up to 50 MHz) or an
8-bit wide UTOPIA Level 3 (clocked up to 100 MHz) datapath interface.
Idle/unassigned cells are automatically inserted when the internal FIFO contains
less than one complete cell. The S/UNI-622-MAX provides generation of the
header check sequence and scrambles the payload of the ATM cells. Each of
these transmit ATM cell processing functions can be enabled or bypassed.
No line rate clocks are required directly by the S/UNI-622-MAX as it synthesizes
the transmit clock and recovers the receive clock using a 77.76 MHz reference
clock. The S/UNI-622-MAX outputs a differential PECL line data (TXD+/-).
The S/UNI-622-MAX is configured, controlled and monitored via a generic 8-bit
microprocessor bus interface. The S/UNI-622-MAX also provides a standard 5
signal IEEE 1149.1 JTAG test port for boundary scan board test purposes.
The S/UNI-622-MAX is implemented in low power, +3.3 Volt, CMOS technology.
It has TTL compatible digital inputs and TTL/CMOS compatible digital outputs.
High speed inputs and outputs support 3.3V and 5.0V compatible pseudo-ECL
(PECL). The S/UNI-622-MAX is packaged in a 304 pin SBGA package.
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S/UNI-622-MAX
8 PIN DIAGRAM
The S/UNI-622-MAX is available in a 304 pin SBGA package having a body size
of 31 mm by 31 mm and a ball pitch of 1.27 mm.
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9 PIN DESCRIPTION
9.1 Serial Line Side Interface Signals
Pin Name Type Pin
Function
No.
RBYP Input E21 The receive bypass (RBYP) input disables clock
recovery. If RBYP is high, RXD+/- is sampled on the
rising edge of RRCLK+/-. If RBYP is low, the receive
clock is recovered from the RXD+/- bit stream.
Please refer to the Operation section for a discussion
of the operating modes.
PECLV Input D22 The PECL signal voltage select (PELCV) selects
between 3.3V PECL signaling and 5V PECL signaling
for the PECL inputs. When PECLV is low, the PECL
inputs expect a 5V PECL signal. When PECLV is
high, the PECL inputs expect a 3.3V PECL signal.
The PECL biasing pins PBIAS should be set to the
appropriate voltage to prevent latchup.
Please refer to the Operation section for a discussion
of PECL interfacing issues.
REFCLK+
REFCLK-
Differential
PECL
Input
Y2
AA1
The differential reference clock inputs (REFCLK+/-)
provides a jitter-free 77.76 MHz reference clock for
both the clock recovery and the clock synthesis
circuits. REFCLK+/- is not required if the clock
recovery and clock synthesis features are not used.
Please refer to the Operation section for a discussion
of PECL interfacing issues and reference clocks.
RXD+
RXD-
Differential
PECL
Input
W1
V2
The receive differential data PECL inputs (RXD+/-)
contain the NRZ bit serial receive stream. The
receive clock is recovered from the RXD+/- bit stream
when RBYP is set low. RXD+/- is sampled on the
rising edge of RRCLK+/- when RBYP is set high.
Please refer to the Operation section for a discussion
of PECL interfacing issues.
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S/UNI-622-MAX
Pin Name Type Pin
No.
RRCLK+
RRCLK-
Differential
PECL
U1
U2
Input
SD PECL
R2 The receive signal detect PECL input (SD) indicates
Input
TXD+
TXD-
Differential
PECL
L2
L1
Output
Function
When cloc k recovery is bypassed (RBYP set high),
RRCLK+/- is nominally a 622.08 MHz 50% duty cycle
clock and provides timing for the S/UNI-622-MAX
receive functions. In this case, RXD+/- is sampled on
the rising edge of RRCLK+/-. RRCLK+/- is ignored
when RBYP is set low.
Please refer to the Operation section for a discussion
of PECL interfacing issues.
the presence of valid receive signal power from the
Optical Physical Medium Dependent Device. A PECL
logic high indicates the presence of valid data. A
PECL logic low indicates a loss of signal.
Please refer to the Operation section for a discussion
of PECL interfacing issues
The transmit differential data PECL outputs (TXD+/-)
contain the 622.08 Mbit/s transmit stream. The
TXD+/- outputs are driven using the synthesized
clock from the CSU-622.
Please refer to the Operation section for a discussion
of PECL interfacing issues.
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9.2 Parallel Line Side Interface Signals - CRU and CSU Bypass
Pin Name Type Pin
Function
No.
LIFSEL Input C23 T he line interface select (LIFSEL) selects between
serial and parallel line interface modes of operation.
When tied high, the parallel mode is selected by-
passing the clock and data recovery, clock synthesis
and the serializer/de-serializer functions.
When tied lo w, serial mode is se lected, enabling clock
and data recovery, clock synthesis and the
serializer/de-serializer functions. During this
operation, the parallel interface may be used for 1+1
APS operation. See the Operation section for more
discussion of 1+1 APS support.
PICLK Input AC19 The parallel input clock (PICLK) provides timing for
S/UNI-622-MAX receive function operation when the
device is configured for the parallel interface mode of
operation.
When the RS OC3 bit is set high , PICLK is a 19. 44
MHz nominally 50% duty cycle clock. When the
RSOC3 bit is set low, PICLK is a 77.76 MHz
nominally 50% duty cycle clock.
When parallel operation is not used, PICLK may be
used for 1+1 APS operation. See the Operation
section for more discussion of 1+1 APS.
OOF Output AA18 The out of frame (OOF) signal is high while the
S/UNI-622-MAX is out of frame. OOF is set low while
the S/UNI-622-MAX is in-frame. An out of frame
declaration occurs when four consecutive errored
framing patterns (A1 and A2 bytes) have been
received.
OOF is intended to enable an upstream framing
pattern detector to search for the framing pattern.
This alarm indication is also available via register
access. OOF is an asynchronous output with a
minimum period of one PICLK clock.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 19
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S/UNI-622-MAX
Pin Name Type Pin
Function
No.
FPIN Input AB17 The active-high framing position input (FPIN) signal
indicates the SONET/SDH frame position on the
PIN[7:0] bus. In parallel interface operation, the byte
on the PIN[7:0] bus indicated by FPIN is the third A2
of the SONET/SDH framing pattern. FPIN is sampled
on the rising edge of PICLK.
When parallel inte rface operation is not used, FPIN
may be used for 1+1 APS operation. In this mode,
FPIN marks the first synchronous payload envelope
byte after the J0/Z0 bytes on PIN[7:0]. See the
Operation section for more discussion of 1+1 APS.
PIN[0]
PIN[1]
PIN[2]
PIN[3]
PIN[4]
PIN[5]
PIN[6]
PIN[7]
Input AB18
AA17
AB16
AA16
Y16
AC15
AB15
AA15
In parallel interface operation, the data input
(PIN[7:0]) bus carries the byte-serial STS-12c/STM-44c or STS-3c/STM-1 stream. PIN[7] is the most
significant bit (corresponding to bit 1 of each serial
byte, the first bit received). PIN[0] is the least
significant bit (corresponding to bit 8 of each serial
byte, the last bit received). PIN[7:0] is sampled on
the rising edge of PICLK.
When parallel inte rface operation is not used,
PIN[7:0] may be used for 1+1 APS operation. In this
mode, PIN[7:0] carries the byte-serial STS-12c/STM4-4c transmit path. See the Operation section for
more discussion of 1+1 APS.
PTCLK Input Y14 The parallel transmit clock (PTCLK) provides timing
for S/UNI-622-MAX transmit function operation when
the device is configured for the parallel interface
mode of operation.
When TOC3 is low, PTCLK should be a 77.76 MHz
nominally 50% duty cycle clock free-running (non
gapped) clock. When TOC3 is high, PTCLK should
be a 19.44 MHz nominally 50% duty cycle clock.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 20
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