PMC PM5355-SI Datasheet
PM5355 S/UNI-622
DATA SHEET
PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
PM5355
TM
622
S/
UNI-
S/UNI-622
SATURN USER NETWORK INTERFACE
(622-MBIT/S) STANDARD PRODUCT
DATA SHEET
ISSUE 3: JUNE 1998
PM5355 S/UNI-622
DATA SHEET
PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
PUBLIC REVISION HISTORY
Issue No. Issue Date Details of Change
3 June 1998 Data Sheet Reformatted — No Change in Technical
Content.
Generated R3 data sheet from PMC-930527, R8.
2 April 3,
1996
Update to Eng Doc Issue 7
1 October
1994
Creation of Document
PM5355 S/UNI-622
DATA SHEET
PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
i
CONTENTS
1 FEATURES...............................................................................................1
1.1 THE RECEIVER SECTION: ..........................................................1
1.2 THE TRANSMITTER SECTION:....................................................2
2 APPLICATIONS .......................................................................................4
3 REFERENCES.........................................................................................5
4 APPLICATION EXAMPLES......................................................................6
5 BLOCK DIAGRAM....................................................................................8
6 DESCRIPTION.......................................................................................10
7 PIN DIAGRAM........................................................................................12
8 PIN DESCRIPTION................................................................................13
9 FUNCTIONAL DESCRIPTION...............................................................29
9.1 RECEIVE SECTION OVERHEAD PROCESSOR........................29
9.1.1 FRAMER...........................................................................29
9.1.2 DESCRAMBLE .................................................................30
9.1.3 ERROR MONITOR............................................................30
9.1.4 LOSS OF SIGNAL ............................................................30
9.1.5 LOSS OF FRAME.............................................................30
9.2 RECEIVE LINE OVERHEAD PROCESSOR ...............................31
9.2.1 LINE RDI DETECT............................................................31
9.2.2 LINE AIS DETECT............................................................31
9.2.3 AUTOMATIC PROTECTION SWITCH CONTRO L BLOCK31
9.2.4 ERROR MONITOR............................................................32
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9.3 BYTE INTERLEAVED DEMULTIPLEXER....................................32
9.4 TRANSPORT OVERHEAD EXTRACT PORT..............................32
9.5 RECEIVE PATH OVERHEAD PROCESSOR...............................32
9.5.1 POINTER INTERPRETER................................................33
9.5.2 SPE TIMING......................................................................38
9.5.3 ERROR MONITOR............................................................38
9.6 PATH OVERHEAD EXTRACT......................................................39
9.7 RECEIVE ATM CELL PROCESSOR...........................................39
9.7.1 CELL DELINEATION.........................................................39
9.7.2 DESCRAMBLER...............................................................40
9.7.3 CELL FILTER AND HCS VERIFICATION..........................40
9.7.4 PERFORMANCE MONITOR.............................................42
9.7.5 GFC EXTRACTION PORT................................................42
9.7.6 RECEIVE FIFO.................................................................42
9.8 TRANSMIT SECTION OVERHEAD PROCESSOR.....................43
9.8.1 LINE AIS INSERT.............................................................43
9.8.2 BIP-8 INSERT...................................................................43
9.8.3 FRAMING AND IDENTITY INSERT..................................44
9.8.4 SCRAMBLER....................................................................44
9.9 TRANSMIT LINE OVERHEAD PROCESSOR.............................44
9.9.1 APS INSERT..................................................................... 44
9.9.2 LINE BIP CALCULATE......................................................44
9.9.3 LINE RDI INSERT.............................................................45
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9.9.4 LINE FEBE INSERT..........................................................45
9.10 BYTE INTERLEAVED MULTIPLEXER ........................................45
9.11 TRANSPORT OVERHEAD INSERT PORT.................................45
9.12 TRANSMIT PATH OVERHEAD PROCESSOR............................46
9.12.1POINTER GENERATOR...................................................47
9.12.2BIP-8 CALCULATE...........................................................48
9.12.3FEBE CALCULATE...........................................................48
9.12.4SPE MULTIPLEXER..........................................................48
9.13 PATH OVERHEAD INSERT.........................................................48
9.14 TRANSMIT ATM CELL PROCESSOR.........................................50
9.14.1IDLE/UNASSIGNED CELL GENERATOR.........................50
9.14.2SCRAMBLER....................................................................50
9.14.3HCS GENERATOR............................................................ 50
9.14.4GFC INSERTION PORT ...................................................50
9.14.5TRANSMIT FIFO...............................................................51
9.15 SONET/SDH SECTION AND PATH TRACE BUFFERS...............51
9.15.1RECEIVE TRACE BUFFER (RTB)....................................51
9.15.2TRANSMIT TRACE BUFFER (TTB)..................................54
9.16 LINE SIDE INTERFACE...............................................................54
9.16.1RECEIVE INTERFACE......................................................54
9.16.2TRANSMIT INTERFACE...................................................55
9.17 DROP SIDE INTERFACE ............................................................55
9.17.1RECEIVE INTERFACE......................................................55
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9.17.2TRANSMIT INTERFACE...................................................56
9.18 PARALLEL I/O PORT...................................................................56
9.19 JTAG TEST ACCESS PORT........................................................56
9.20 MICROPROCESSOR INTERFACE.............................................56
9.21 REGISTER MEMORY MAP.........................................................56
10 NORMAL MODE REGISTER DESCRIPTION........................................62
11 TEST FEATURES DESCRIPTION .......................................................194
11.1 TEST MODE REGISTER MEMORY MAP.................................194
11.2 TEST MODE 0 DETAILS...........................................................199
11.3 JTAG TEST PORT......................................................................202
12 OPERATION.........................................................................................207
13 FUNCTIONAL TIMING .........................................................................223
13.1 LINE SIDE RECEIVE INTERFACE............................................223
13.2 LINE SIDE TRANSMIT INTERFACE..........................................227
13.3 OVERHEAD ACCESS...............................................................229
13.4 GFC ACCESS............................................................................237
13.5 DROP SIDE RECEIVE INTERFACE..........................................238
13.6 DROP SIDE TRANSMIT INTERFACE .......................................241
14 ABSOLUTE MAXIMUM RATINGS........................................................242
15 D.C. CHARACTERISTICS ....................................................................243
16 MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS......246
17 S/UNI-622 TIMING CHARACTERISTICS.............................................250
18 ORDERING AND THERMAL INFORMATION ......................................270
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19 MECHANICAL INFORMATION.............................................................271
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LIST OF REGISTERS
REGISTER 0X00: S/UNI-622 MASTER RESET AND IDENTITY / LOAD
PERFORMANCE METERS....................................................................63
REGISTER 0X01: S/UNI-622 MASTER CONFIGURATION..............................64
REGISTER 0X02: S/UNI-622 MASTER INTERRUPT STATUS.........................67
REGISTER 0X03: PISO INTERRUPT...............................................................69
REGISTER 0X04: S/UNI-622 MASTER CONTROL/MONITOR........................70
REGISTER 0X05: S/UNI-622 MASTER AUTO ALARM ....................................73
REGISTER 0X06: S/UNI-622 PARALLEL OUTPUT PORT...............................74
REGISTER 0X07: S/UNI-622 PARALLEL INPUT PORT ...................................75
REGISTER 0X08: S/UNI-622 PARALLEL INPUT PORT VALUE.......................76
REGISTER 0X09: S/UNI-622 PARALLEL INPUT PORT ENABLE....................77
REGISTER 0X0A: S/UNI-622 TRANSMIT C1...................................................78
REGISTER 0X0B: S/UNI-622 APS CONTROL/STATUS...................................79
REGISTER 0X0C: S/UNI-622 RECEIVE K1 .....................................................81
REGISTER 0X0D: S/UNI-622 RECEIVE K2 .....................................................82
REGISTER 0X0E: S/UNI-622 RECEIVE Z1......................................................83
REGISTER 0X0F: S/UNI-622 TRANSMIT Z1....................................................84
REGISTER 0X10: RSOP CONTROL/INTERRUPT ENABLE............................85
REGISTER 0X11: RSOP STATUS/INTERRUPT STATUS.................................87
REGISTER 0X12: RSOP SECTION BIP-8 LSB................................................89
REGISTER 0X13: RSOP SECTION BIP-8 MSB...............................................90
REGISTER 0X14: TSOP CONTROL................................................................. 9 1
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REGISTER 0X15: TSOP DIAGNOSTIC............................................................92
REGISTER 0X18: RLOP CONTROL/STATUS...................................................93
REGISTER 0X19: RLOP INTERRUPT ENABLE/INTERRUPT STATUS ...........95
REGISTER 0X1A: RLOP LINE BIP-96/24/8 LSB..............................................97
REGISTER 0X1B: RLOP LINE BIP-96/24/8......................................................98
REGISTER 0X1C: RLOP LINE BIP-96/24/8 MSB............................................. 99
REGISTER 0X1D: RLOP LINE FEBE LSB .....................................................100
REGISTER 0X1E: RLOP LINE FEBE .............................................................101
REGISTER 0X1F: RLOP LINE FEBE MSB.....................................................102
REGISTER 0X20: TLOP CONTROL...............................................................103
REGISTER 0X21: TLOP DIAGNOSTIC ..........................................................104
REGISTER 0X22: TLOP TRANSMIT K1.........................................................105
REGISTER 0X23: TLOP TRANSMIT K2.........................................................106
REGISTER 0X28 SSTB CONTROL................................................................107
REGISTER 0X29: SSTB SECTION TRACE IDENTIFIER STATUS.................109
REGISTER 0X2A: SSTB INDIRECT ADDRESS REGISTER..........................111
REGISTER 0X2B: SSTB INDIRECT DATA REGISTER...................................112
REGISTER 0X2C: SSTB EXPECTED CLOCK SYNCHRONIZATION MESSAGE
..............................................................................................................113
REGISTER 0X2D: SSTB CLOCK SYNCHRONIZATION MESSAGE STATUS114
REGISTER 0X30: RPOP STATUS/CONTROL................................................116
REGISTER 0X31: RPOP INTERRUPT STATUS .............................................117
REGISTER 0X32: RPOP POINTER INTERRUPT STATUS ............................118
REGISTER 0X33: RPOP INTERRUPT ENABLE............................................120
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REGISTER 0X34: RPOP POINTER INTERRUPT ENABLE...........................122
REGISTER 0X35: RPOP POINTER LSB........................................................124
REGISTER 0X36: RPOP POINTER MSB.......................................................125
REGISTER 0X37: RPOP PATH SIGNAL LABEL.............................................126
REGISTER 0X38: RPOP PATH BIP-8 LSB .....................................................127
REGISTER 0X39: RPOP PATH BIP-8 MSB ....................................................128
REGISTER 0X3A: RPOP PATH FEBE LSB.....................................................129
REGISTER 0X3B: RPOP PATH FEBE MSB....................................................130
REGISTER 0X3C: RPOP RDI.........................................................................131
REGISTER 0X3D: RPOP RING CONTROL....................................................132
REGISTER 0X40: TPOP CONTROL/DIAGNOSTIC........................................134
REGISTER 0X41: TPOP POINTER CONTROL..............................................136
REGISTER 0X43: TPOP CURRENT POINTER LSB......................................139
REGISTER 0X44: TPOP CURRENT POINTER MSB.....................................140
REGISTER 0X45: TPOP ARBITRARY POINTER LSB ...................................141
REGISTER 0X46: TPOP ARBITRARY POINTER MSB ..................................142
REGISTER 0X47: TPOP PATH TRACE...........................................................143
REGISTER 0X48: TPOP PATH SIGNAL LABEL .............................................144
REGISTER 0X49: TPOP PATH STATUS..........................................................145
REGISTER 0X4A: TPOP PATH USER CHANNEL ..........................................147
REGISTER 0X4B: TPOP PATH GROWTH #1 (Z3)..........................................148
REGISTER 0X4C: TPOP PATH GROWTH #2 (Z4)..........................................149
REGISTER 0X4D TPOP PATH GROWTH #3 (Z5)..........................................150
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REGISTER 0X50: RACP CONTROL...............................................................151
REGISTER 0X51: RACP INTERRUPT STATUS..............................................153
REGISTER 0X52: RACP INTERRUPT ENABLE/CONTROL..........................155
REGISTER 0X53: RACP MATCH HEADER PATTERN ...................................157
REGISTER 0X54: RACP MATCH HEADER MASK.........................................158
REGISTER 0X55: RACP CORRECTABLE HCS ERROR COUNT (LSB) .......159
REGISTER 0X56: RACP CORRECTABLE HCS ERROR COUNT (MSB) ......160
REGISTER 0X57: RACP UNCORRECTABLE HCS ERROR COUNT (LSB)..161
REGISTER 0X58: RACP UNCORRECTABLE HCS ERROR COUNT (MSB).162
REGISTER 0X59: RACP RECEIVE CELL COUNTER (LSB) .........................163
REGISTER 0X5A: RACP RECEIVE CELL COUNTER...................................164
REGISTER 0X5B: RACP RECEIVE CELL COUNTER (MSB)........................165
REGISTER 0X5C: GFC CONTROL/MISC. CONTROL ...................................166
REGISTER 0X60: TACP CONTROL/STATUS..................................................168
REGISTER 0X61: TACP IDLE/UNASSIGNED CELL HEADER PATTERN......170
REGISTER 0X62: TACP IDLE/UNASSIGNED CELL PAYLOAD OCTET
PATTERN..............................................................................................171
REGISTER 0X63: TACP FIFO CONTROL.......................................................172
REGISTER 0X64: TACP TRANSMIT CELL COUNTER (LSB) ........................174
REGISTER 0X65: TACP TRANSMIT CELL COUNTER ..................................175
REGISTER 0X66: TACP TRANSMIT CELL COUNTER (MSB).......................176
REGISTER 0X67: TACP FIXED STUFF / GFC ...............................................177
REGISTER 0X68 SPTB CONTROL................................................................179
REGISTER 0X69: SPTB PATH TRACE IDENTIFIER STATUS........................181
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REGISTER 0X6A: SPTB INDIRECT ADDRESS REGISTER..........................183
REGISTER 0X6B: SPTB INDIRECT DATA REGISTER...................................184
REGISTER 0X6C: SPTB EXPECTED PATH SIGNAL LABEL.........................185
REGISTER 0X6D: SPTB PATH SIGNAL LABEL STATUS...............................186
REGISTER 0X70: BERM CONTROL..............................................................188
REGISTER 0X71: BERM INTERRUPT...........................................................189
REGISTER 0X72: BERM LINE BIP ACCUMULATION PERIOD LSB .............190
REGISTER 0X73: BERM LINE BIP ACCUMULATION PERIOD MSB ............191
REGISTER 0X74: BERM LINE BIP THRESHOLD LSB..................................192
REGISTER 0X75: BERM LINE BIP THRESHOLD MSB.................................193
REGISTER 0X80: MASTER TEST..................................................................198
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PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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LIST OF FIGURES
FIGURE 1 - TYPICAL STS-12C/3C ATM INTERFACE......................................6
FIGURE 2 - TYPICAL STS-1 ATM INTERFACE.................................................7
FIGURE 3 - NORMAL OPERATING MODE.......................................................8
FIGURE 4 - LOOPBACK MODES......................................................................9
FIGURE 5 - ......................................................................................................12
FIGURE 6 - POINTER INTERPRETATION STATE DIAGRAM.........................34
FIGURE 7 - ITU G.783 CONCATENATION INDICATOR STATE DIAGRAM....37
FIGURE 8 - ITU G.783 CONCATENATION INDICATOR IMPLEMENTATION.38
FIGURE 9 - CELL DELINEATION STATE DIAGRAM.......................................40
FIGURE 10- HCS VERIFICATION STATE DIAGRAM.......................................41
FIGURE 11- STS-12C (STM-4C) DEFAULT TRANSPORT OVERHEAD VALUES
.......................................................................................................46
FIGURE 12- DEFAULT PATH OVERHEAD VALUES.........................................49
FIGURE 13- INPUT OBSERVATION CELL (IN_CELL)...................................204
FIGURE 14- OUTPUT CELL (OUT_CELL).....................................................205
FIGURE 15- BIDIRECTIONAL CELL (IO_CELL)............................................205
FIGURE 16- LAYOUT OF OUTPUT ENABLE AND BIDIRECTIONAL CELLS206
FIGURE 17- STS-1 MAPPING........................................................................207
FIGURE 18- STS-3C (STM-1) MAPPING.......................................................208
FIGURE 19- STS-12C (STM-4C) ATM MAPPING ..........................................209
FIGURE 20-16- BIT WIDE, 27-WORD STRUCTURE.....................................214
FIGURE 21- BOUNDARY SCAN ARCHITECTURE........................................217
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FIGURE 22- TAP CONTROLLER FINITE STATE MACHINE ..........................219
FIGURE 23- IN FRAME DECLARATION ........................................................223
FIGURE 24- OUT OF FRAME DECLARATION ..............................................224
FIGURE 25- LOSS OF SIGNAL DECLARATION/REMOVAL.......................... 224
FIGURE 26- LOSS OF FRAME DECLARATION/REMOVAL ..........................225
FIGURE 27- LINE AIS AND LINE RDI DECLARATION/REMOVAL................225
FIGURE 28- LOSS OF POINTER DECLARATION/REMOVAL.......................226
FIGURE 29- PATH AIS DECLARATION/REMOVAL........................................226
FIGURE 30- PATH REMOTE DEFECT INDICATION DECLARATION/REMOVAL
.....................................................................................................227
FIGURE 31- STS-1 BIT-SERIAL TRANSMIT FRAME ALIGNMENT...............227
FIGURE 32- STS-12C BYTE-SERIAL TRANSMIT FRAME ALIGNMENT......228
FIGURE 33- STS-3C/1 BYTE-SERIAL TRANSMIT FRAME ALIGNMENT.....228
FIGURE 34- TRANSPORT OVERHEAD EXTRACTION.................................229
FIGURE 35- TRANSPORT OVERHEAD ORDERWIRE AND USER CHANNEL
EXTRACTION.................................................................................................230
FIGURE 36- TRANSPORT OVERHEAD DATA LINK CLOCK AND DATA
EXTRACTION.................................................................................................231
FIGURE 37- PATH OVERHEAD EXTRACTION..............................................232
FIGURE 38- TRANSPORT OVERHEAD INSERTION....................................233
FIGURE 39- TRANSPORT OVERHEAD ORDERWIRE AND USER CHANNEL
INSERTION.....................................................................................................234
FIGURE 40- TRANSPORT OVERHEAD DATA LINK CLOCK AND DATA
INSERTION.....................................................................................................235
FIGURE 41- PATH OVERHEAD INSERTION..................................................236
FIGURE 42- GFC EXTRACTION PORT.........................................................237
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FIGURE 43- GFC INSERTION PORT.............................................................238
FIGURE 44- RECEIVE SYNCHRONOUS FIFO, TSEN=0, RCALEVEL0=1 ...238
FIGURE 45- RECEIVE SYNCHRONOUS FIFO, TSEN=0, RCALEVEL0=0 ...239
FIGURE 46- RECEIVE SYNCHRONOUS FIFO, TSEN=1, RCALEVEL0=1 ...240
FIGURE 47- TRANSMIT SYNCHRONOUS FIFO...........................................241
FIGURE 48- MICROPROCESSOR INTERFACE READ TIMING....................247
FIGURE 49- MICROPROCESSOR INTERFACE WRITE TIMING..................249
FIGURE 50- LINE SIDE RECEIVE INTERFACE TIMING ...............................251
FIGURE 51- RECEIVE ALARM OUTPUT TIMING .........................................253
FIGURE 52- RECEIVE OVERHEAD ACCESS TIMING..................................255
FIGURE 53- RECEIVE GFC ACCESS TIMING..............................................257
FIGURE 54- LINE SIDE TRANSMIT INTERFACE TIMING.............................258
FIGURE 55- TRANSMIT ALARM INPUT TIMING...........................................259
FIGURE 56- TRANSMIT OVERHEAD ACCESS TIMING................................261
FIGURE 57- TRANSMIT GFC ACCESS TIMING............................................264
FIGURE 58- DROP SIDE RECEIVE INTERFACE TIMING.............................265
FIGURE 59- DROP SIDE TRANSMIT INTERFACE........................................267
FIGURE 60- JTAG PORT INTERFACE TIMING..............................................268
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xiv
LIST OF TABLES
TABLE 1 - ......................................................................................................13
TABLE 2 - ......................................................................................................53
TABLE 3 - ......................................................................................................56
TABLE 4 - ......................................................................................................64
TABLE 5 - ......................................................................................................65
TABLE 6 - ....................................................................................................155
TABLE 7 - ....................................................................................................173
TABLE 8 - ....................................................................................................177
TABLE 9 - ....................................................................................................194
TABLE 10 - ....................................................................................................199
TABLE 11 - ....................................................................................................201
TABLE 12 - INSTRUCTION REGISTER........................................................202
TABLE 13 - ....................................................................................................215
TABLE 14 - ....................................................................................................215
TABLE 15 - ....................................................................................................216
TABLE 16 - ABSOLUTE MAXIMUM RATINGS..............................................242
TABLE 17 - ....................................................................................................243
TABLE 18 - MICROPROCESSOR INTERFACE READ ACCESS (FIGURE 48) .
.....................................................................................................246
TABLE 19 - MICROPROCESSOR INTERFACE WRITE ACCESS (FIGURE 49)
.....................................................................................................248
TABLE 20 - LINE SIDE RECEIVE INTERFACE (FIGURE 50).......................250
TABLE 21 - RECEIVE ALARM OUTPUT (FIGURE 51).................................251
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TABLE 22 - RECEIVE OVERHEAD ACCESS (FIGURE 52).........................254
TABLE 23 - RECEIVE OVERHEAD ACCESS (FIGURE 53).........................256
TABLE 24 - LINE SIDE TRANSMIT INTERFACE (FIGURE 54)....................257
TABLE 25 - TRANSMIT ALARM INPUT (FIGURE 55) ..................................258
TABLE 26 - TRANSMIT OVERHEAD ACCESS (FIGURE 56).......................260
TABLE 27 - TRANSMIT GFC ACCESS (FIGURE 57)...................................263
TABLE 28 - DROP SIDE RECEIVE INTERFACE (FIGURE 58)....................264
TABLE 29 - DROP SIDE TRANSMIT INTERFACE (FIGURE 59)..................266
TABLE 30 - JTAG PORT INTERFACE (FIGURE 60).....................................267
TABLE 31 - ....................................................................................................270
TABLE 32 - ....................................................................................................270
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PM5355 S/UNI-622
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PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
1
1
FEATURES
•
Monolithic Saturn User Network Interface that implements the ATM physical
layer for Broadband ISDN according to CCITT Recommendation I.432 and
the ATM Forum BISDN Inter Carrier Interface (B-ICI) Specification.
•
Supports a 77.76 Mbyte/s STS-12c (STM-4c), a 19.44 Mbyte/s STS-3c
(STM-1), a 6.48 Mbyte/s STS-1, or a 51.84 Mbit/s STS-1 line side interface.
•
Provides four-cell deep FIFO buffers in both the transmit and receive paths.
•
Provides a generic 8-bit microprocessor bus interface for configuration,
control, and status monitoring.
•
Provides a generic parallel output port and a generic parallel input port to
control and monitor front end line devices.
•
Provides a standard 5-signal P1149.1 JTAG test port for boundary scan
board test purposes.
•
Low-power, +5 Volt, CMOS technology.
•
208-pin high-performance plastic quad flat pack (PQFP) package.
1.1 The receiver section:
•
Frames to and descrambles the received STS-12c/3c/1 (STM-4c/1, AU-3)
stream.
•
Filters and captures the automatic protection switch channel (APS) bytes in
readable registers and detects APS byte failure.
•
Interprets the received payload pointer (H1, H2) and extracts the
STS-12c/3c/1 (STM-4c/1, AU-3) synchronous payload envelope and path
overhead.
•
Extracts ATM cells from the received STS-12c/3c/1 (STM-4c/1, AU-3)
synchronous payload envelope using ATM cell delineation and provides
optional ATM cell payload descrambling, header check sequence (HCS) error
detection and correction, and idle/unassigned cell filtering.
•
Provides a generic 16-bit wide datapath interface to read extracted cells from
an internal four-cell FIFO buffer.
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PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb)
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2
•
Extracts all transport overhead bytes and serializes them in four 5.184 Mbit/s
streams for optional external processing.
•
Extracts the section user channel (F1) and the order wire channels (E1, E2)
and serializes them into three independent 64 kbit/s streams for optional
external processing.
•
Extracts the data communication channels (D1-D3, D4-D12) and serializes
them at 192 kbit/s (D1-D3) and 576 kbit/s (D4-D12) for optional external
processing.
•
Extracts all path overhead bytes and serializes them at 576 kbit/s for optional
external processing.
•
Extracts the 16- or 64-byte section trace (C1) sequence and the 16- or 64byte path trace (J1) sequence into internal register banks.
•
Detects loss of signal (LOS), out of frame (OOF), loss of frame (LOF), line
alarm indication signal (AIS), line remote defect indication (LRDI), loss of
pointer (LOP), path alarm indication signal (AIS), path remote defect
indication signal (RDI-P) and loss of cell delineation (LCD).
•
Counts received section BIP-8 (B1) errors, received line BIP-96/24/8 (B2)
errors, line far end block errors (line FEBEs), received path BIP-8 (B3) errors
and path far end block errors (path FEBEs) for performance monitoring
purposes.
•
Counts received cells written into the receive FIFO, received HCS errored
cells that are discarded, and received HCS errored cells that are corrected
and passed on.
•
Extracts and serializes the GFC field from all received cells (including
idle/unassigned cells) for external processing.
1.2 The transmitter section:
•
Provides an internal four-cell FIFO into which cells are written using a generic
16-bit wide datapath interface.
•
Inserts the gener ic flow control (GFC) bits via a simple serial interface.
•
Counts transmit cells read from the transmit FIFO.
PM5355 S/UNI-622
DATA SHEET
PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
3
•
Provides idle/unassigned cell insertion, HCS generation/insertion, and ATM
cell payload scrambling.
•
Inserts ATM cells into the transmitted STS-12c/3c/1 (STM-4c/1, AU-3)
synchronous payload envelope.
•
Inserts a register programmable path signal label.
•
Generates the transmit payload pointer (H1, H2) and inserts the path
overhead.
•
Optionally inserts the 16- or 64-byte section trace (C1) sequence and the 16or 64-byte path trace (J1) sequence from internal register banks.
•
Optionally inserts externally generated path overhead bytes received via a
576 kbit/s serial interface.
•
Optionally inserts externally generated data communication channels (D1-D3,
D4-D12) via a 192 kbit/s (D1-D3) serial stream and a 576 kbit/s (D4-D12)
serial stream.
•
Optionally inserts externally generated section user channel (F1) and
externally generated order wire channels (E1, E2) via three 64 kbit/s serial
interfaces.
•
Optionally inserts externally generated transport overhead bytes received via
four 5.184 Mbit/s serial interfaces.
•
Scrambles the transmitted STS-12c/3c/1 (STM-4c/1, AU-3) stream and
inserts the framing bytes (A1, A2) and the identity byte (C1).
•
Optionally inserts path alarm indication signal (AIS), path remote defect
indication (RDI-P), line alarm indication signal (AIS) and line remote defect
indication (LRDI) indication.
•
Optionally inserts register programmable APS bytes.
•
Inserts path BIP-8 codes (B3), path far end block error (FEBE) indications,
line BIP-96/24/8 codes (B2), line far end block error (FEBE) indications, and
section BIP-8 codes (B1) to allow performance monitoring at the far end.
•
Allows forced insertion of all-zeros data (after scrambling), the corruption of
the framing bytes or the corruption of the section, line, or path BIP-8 codes for
diagnostic purposes.
PM5355 S/UNI-622
DATA SHEET
PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
4
2
APPLICATIONS
•
Workstations
•
LAN Switches and Hubs
•
Routers
•
Video Servers
•
Backbones
•
Broadband Switching Systems
PM5355 S/UNI-622
DATA SHEET
PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
5
3
REFERENCES
1. ITU-T Recommendation G.709 - "Synchronous Multiplexing Structure,"
Helsinki, March 1993.
2. ITU-T Recommendation I.432 - "B-ISDN User-Network Interface-Physical
Interface Specification," Helsinki, March 1993.
3. Bell Communications Research - "SONET Transport Systems Common
Generic Criteria", GR-253-CORE, Issue 1, December 1994.
4. Bell Communications Research - "Generic Requirements for Operations of
Broadband Switching Systems", TA-NWT-00001248, Issue 2, October 1993.
5. ATM Forum - "622 Mbps Physical Layer Specification", af-phy-0046.000,
January 1996.
6. ANSI T1.105-1991, Telecommunications - Digital Hierarchy - Optical Interface
Rates and Formats Specifications (SONET)
7. IEEE 1149.1 - "Standard Te st Access Port and Boundary Scan Architecture",
May 21, 1990.
8. PMC-940212, ATM_SCI_PHY, "SATURN Compliant Interfaces For ATM
Devices," October 1995, Issue 3.
PM5355 S/UNI-622
DATA SHEET
PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
6
4
APPLICATION EXAMPLES
The S/UNI-622 is typically used to implement the core of an ATM User Network
Interface by which an ATM terminal is linked to an ATM switching system using
SONET/SDH-compatible transport. The S/UNI-622 may find application at either
end of terminal-to-switch links or switch-to-switch links, both in private network
(LAN) and public network (WAN) situations. In a typical STS-3c (STM-1) or
STS-12c (STM-4c) application, the S/UNI-622 requires a clock and data
recovery/serial-to-parallel converter device in the receive direction and a serialto-parallel converter/clock synthesis device in the transmit direction on the line
side. The clock synthesis function is not required if the transmit side is looptimed
to the receive clock. The initial configuration and ongoing control and monitoring
of the S/UNI-622 are normally provided via a generic microprocessor interface.
The S/UNI-622 supports a "hardware-only" operating mode fo r STS-12c
(STM-4c) where an external microprocessor is not required. This application is
shown in Figure 1.
Figure 1 - Typical STS-12c/3c ATM Interface
PIN[7:0]
FPIN
MICRO BUS
FOR CONFIG, STATUS
AND CONTROL
RECEIVE
ALARM DETECT
SIGNALS
RECEIVE
OVERHEAD
EXTRACT
TRANSMIT
ALARM INSERT
SIGNALS
TRANSMIT
OVERHEAD
INSERT
TWRENB
RDAT[15:0]
RSOC
RRDENB
TDAT[15:0]
TSOC
TSD+/-
RSD+/-
O/E
E/O
Clock & Data
Recovery
PM5355 S/UNI-622
SATURN
USER NETWORK INTERFACE
RCA
TCA
PICLK
OOF
Parallel-to-
Serial &
Serial to
Parallel
Converter
POUT[7:0]
TCLK
Ref.
Clock
TFCLK
RFCLK
RXPRTY[1:0]
TXPRTY[1:0]
Clock
Synthesis
TRANSMIT CELL
INTERFACE
RECEIVE CELL
INTERFACE
In a typical STS-1 application, the S/UNI-622 requires a clock and data recovery
device in the receive direction and a clock source in the transmit direction on the
line side. The initial configuration and ongoing control and monitoring of the
S/UNI-622 are normally provided via a generic microprocessor interface. A
typical STS-1 ATM Interface is shown in Figure 2. On the receive side, an
PM5355 S/UNI-622
DATA SHEET
PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
7
external clock and data recovery device is used. On the transmit side, the
S/UNI-622 is configured for looptime operation where the receive clock, RSICLK,
is used as the transmit clock source.
Figure 2 - Typical STS-1 ATM Interface
RSIN
MICRO BUS
FOR CONFIG, STATUS
AND CONTROL
RECEIVE
ALARM DETECT
SIGNALS
RECEIVE
OVERHEAD
EXTRACT
TRANSMIT
ALARM INSERT
SIGNALS
TRANSMIT
OVERHEAD
INSERT
TWRENB
RDAT[15:0]
RSOC
RRDENB
TDAT[15:0]
TSOC
RSD
O/E
E/O
PM5355 S/UNI-622
SATURN
USER NETWORK INTERFACE
RCA
TCA
RSICLK
TSOUT
TFCLK
RFCLK
RXPRTY[1:0]
TXPRTY[1:0]
TSICLK
Clock & Data
Recovery
TRANSMIT CELL
INTERFACE
RECEIVE CELL
INTERFACE
51.84 MHz
Reference
PM5355 S/UNI-622
DATA SHEET
PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
8
5
BLOCK DIAGRAM
Figure 3 - Normal Operating Mode
Tx ATM
4 Cell
FIFO
Rx ATM
4 Cell
FIFO
Drop
Side
I/F
TDAT[15:0]
TCA
TSOC
RDAT[15:0]
RSOC
D[7:0]
A[7:0]
ALE
CSB
RDB
WRB
RSTB
INTB
Microprocessor I/F
TWRENB
Tx
Line O/H
Processor
Rx
Line O/H
Processor
TLD,TLOW
RLDCLK
RLD,RLOW
Tx ATM Cell
Processor
Rx ATM Cell
Processor
RCA
RRDENB
TMS
TCK
TDI
TDO
TRSTB
JTAG Test
Access Port
POUT[7:0]
PIN[7:0]
PICLK
OOF
FPOUT
FPIN
FPOS
L ine
Side
I/F
LCD
RPOH
TPOH
TPOHCLKRPOHCLK
TPOHFP
TPOHEN
RPOHFP
TPAIS
TPRDI
LOP
PAIS
PRDI
Path
O/H
Insert
Path
O/H
Extract
Rx Path O/H
Processor
Rx ConCat
Processor
Tx Path O/H
Processor
Tx ConCat
Processor
TFCLK
RFCLK
GROCLK
Transport
O/H
Insert
TTOH[4:1]
TTOHCLK
TTOHFP
TTOHEN
Transport
O/H
Extract
RTOH[4:1]
RTOHCLK
RTOHFP
TCLK
TFP
Byte
Interleaved
Demux
Byte
Interleaved
Mux
GTOCLK
POP[5:0]
PIP[3:0]
Parallel
Input/Output Port
TXPRTY[1:0]
RXPRTY[1:0]
TLAIS
LOS
LOF
Tx
Section O/H
Processor
RSDCLK,ROWCLK
RSD,RSOW,RSUC
TSDCLK,TOWCL
K
TSD,TSOW,TSUC
TLDCLK
TLRDI
LAIS
LRDI
Path
Trace
Buffer
TSOUT
TSICLK
RSICLK
RSIN
OHFP
TSEN
RGFC
RCP
TCP
TGFC
XOFF
Section
Trace
Buffer
Rx
Section O/H
Processor
PM5355 S/UNI-622
DATA SHEET
PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
9
Figure 4 - Loopback Modes
Tx ATM
4 Cell
FIFO
Rx ATM
4 Cell
FIFO
Drop
Side
I/F
Microprocessor I/F
Tx
Line O/H
Processor
Rx
Line O/H
Processor
Tx ATM Cell
Processor
Rx ATM Cell
Processor
JTAG Test
Access Port
L ine
Side
I/F
Path
O/H
Insert
Path
O/H
Extract
Rx Path O/H
Processor
Rx ConCat
Processor
Tx Path O/H
Processor
Tx ConCat
Processor
Transport
O/H
Insert
Transport
O/H
Extract
Byte
Interleaved
Demux
Byte
Interleaved
Mux
Parallel
Input/Output Port
Tx
Section O/H
Processor
Rx
Section O/H
Processor
Path
Trace
Buffer
DIAGNOSTIC
PATH
LOOPBACK
Section
Trace
Buffer
STS-1
LINE
LOOPBACK
STS-1
DIAGNOSTIC
LOOPBACK
PM5355 S/UNI-622
DATA SHEET
PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
10
6
DESCRIPTION
The PM5355 S/UNI-622 SATURN User Network Interface is a monolithic
integrated circuit that implements the SONET/SDH processing and ATM mapping
functions of a 622-Mbit/s ATM User Network Interface.
The S/UNI-622 receives SONET/SDH frames via a byte-serial interface (or bitserial interface for STS-1), and processes section, line, and path overhead. It
performs framing (A1, A2), performs descrambling, detects alarm conditions, and
monitors section, line, and path bit interleaved parity (B1, B2, B3), accumulating
error counts at each level for performance monitoring purposes. Line and path
far end block error indications (Z2, G1) are also accumulated. The S/UNI-622
interprets the received payload pointers (H1, H2) and extracts the synchronous
payload envelope which carries the received ATM cell payload. In addition to
basic processing of the received SONET/SDH overhead, the S/UNI-622 provides
convenient access to all overhead bytes, which are extracted and serialized on
lower rate interfaces, allowing additional external processing of overhead, if
desired.
The S/UNI-622 frames to the ATM payload using cell delineation. HCS error
correction is provided. Idle/unassigned cells may be dropped according to a
programmable filter. Cells are also dropped upon detection of an uncorrectable
header check sequence error. The ATM cell payloads are descrambled. The
ATM cells that are passed are written to a four-cell FIFO buffer. The received
cells are read from the FIFO using a generic 16-bit wide datapath interface.
Counts of errored received ATM cell headers that are uncorrectable and those
that are correctable are accumulated independently for performance monitoring
purposes.
The S/UNI-622 transmits SONET/SDH frames via a byte-serial interface (or bitserial interface for STS-1) and formats section, line, and path overhead
appropriately. It performs framing pattern insertion (A1, A2), scrambling, alarm
signal insertion, and creates section, line, and path bit interleaved parity (B1, B2,
B3) as required to allow performance monitoring at the far end. Line and path far
end block error indications (Z2, G1) are also inserted. The S/UNI-622 generates
the payload pointer (H1, H2) and inserts the synchronous payload envelope
which carries the ATM cell payload. In addition to the basic formatting of the
transmitted SONET/SDH overhead, the S/UNI-622 provides convenient access
to all overhead bytes, which are optionally inserted from lower rate serial
interfaces, allowing external sourcing of overhead, if desired. The S/UNI-622
also supports the insertion of a large variety of errors into the transmit stream,
PM5355 S/UNI-622
DATA SHEET
PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
11
such as framing pattern errors, bit interleaved parity errors, and illegal pointers,
which are useful for system diagnostics and tester applications.
ATM cells are written to an internal four-cell FIFO using a generic 16-bit wide
datapath interface. Idle/unassigned cells are automatically inserted when the
internal FIFO contains less than one cell. Generic flow control (GFC) bits may be
inserted downstream of the FIFO via a serial link so that all FIFO latency may be
bypassed. The S/UNI-622 provides generation of the header check sequence
and scrambles the payload of the ATM cells. Each of these transmit ATM cell
processing functions can be enabled or bypassed.
No auxiliary clocks are required directly by the S/UNI-622 since it operates from
two line clocks. The S/UNI-622 is configured, controlled and monitored via a
generic 8-bit microprocessor bus interface. The S/UNI-622 also provides a
standard 5-signal P1149.1 JTAG test port for boundary scan board test
purposes.
The S/UNI-622 is implemented in low-power, +5 Volt, CMOS technology. It has
TTL compatible inputs and outputs and is packaged in a 208-pin PQFP package.
PM5355 S/UNI-622
DATA SHEET
PMC-941027 ISSUE 3 SATURN USER NETWORK INTERFACE (622-Mb)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
12
7
PIN DIAGRAM
The S/UNI-622 is packaged in a 208-pin slugged plastic QFP package having a
body size of 28 mm by 28 mm and a pin pitch of 0.5 mm.
Figure 5 -
PM 5355
S/UNI-622
RDAT[5]
RDAT[4]
RTOH[1]
RTOH[2]
RTOH[3]
RTOH[4]
VDD_AC
VSS_AC
FPOS
FPIN
PIN[0]
PIN[1]
PIN[2]
PIN[3]
PIN[4]
RDAT[7]
RDAT[8]
RDAT[9]
RDAT[10]
RDAT[11]
RDAT[12]
RDAT[13]
RDAT[14]
RDAT[15]
VDD_AC
VDD_DC
PIN[5]
PIN 1
PIN
2
08
PIN
1
57
PIN 156
PIN 52
PIN
53
PIN
1
04
Index
PIN 105
VSS_DC
VSS_AC
A[0]
A[1]
A[2]
A[3]
A[4]
A[5]
A[6]
A[7]
D[0]
D[1]
D[2]
D[3]
VDD_AC
VDD_DC
VSS_DC
VSS_AC
D[4]
D[5]
D[6]
D[7]
RSTB
CSB
WRB
RDB
INTB
VDD_DC
VSS_DC
TDA T[0]
TDA T[1]
TDA T[2]
TDA T[3]
TDA T[4]
TDA T[5]
TDA T[6]
TDA T[7]
TDA T[8]
TDA T[9]
TDAT[10]
ALE
PIN[6]
PIN[7]
RSIN
RSICLK
VDD_DC
PICLK
VSS_DC
POP[0]
POP[1]
POP[2]
POP[3]
POP[4]
POP[5]
VDD_DC
VSS_DC
TDI
TMS
TRSTB
TSOUT
FPOUT
POUT[0]
POUT[1]
VDD_AC
VDD_DC
VSS_DC
VSS_AC
POUT[2]
POUT[3]
POUT[4]
POUT[5]
POUT[6]
POUT[7]
VDD_DC
VSS_DC
PIP[0]
PIP[1]
PIP[2]
PIP[3]
GTOCLK
TLAIS
TLRDI
TLDCLK
TTOH[1]
VDD_AC
TPOH
TTOH[4]
TTOH[3]
TTOH[2]
VDD_DC
TPOHCLK
TPOHFP
TPOHEN
VSS_AC
VSS_DC
TFP
BUS8
TCK
TDO
TPRDI
TPAIS
TCP
XOF
F
VDD_DC
TFCLK
VSS_DC
TCA
TGFC
TSOC
TW
RE
NB
TDAT[15
]
TXPRTY[0]
TXPRTY[1]
TDAT[11
]
TDAT[12
]
TDAT[13
]
TDAT[14
]
RDAT[3]
RDAT[1]
RDAT[0]
RXPRTY[1]
RXPRTY[0]
RSOC
RDAT[2]
RCA
TSEN
VSS_DC
RFCLK
VDD_DC
LCD
RGFC
RCP
PRDI
VSS_AC
VDD_AC
PAIS
RPOH
RRDENB
VSS_DC
LOP
RPOHFP
RPOHCLK
OHFP
GROCLK
VDD_DC
RLDCLK
LAIS
LRDI
LOS
ROW
CLK
RLOW
RLD
VSS_DC
OOF
LOF
RSOW
RSUC
RSD
VDD_DC
RSDCLK
RTOHCLK
RTOHFP
VSS_AC
VDD_DC
VDD_AC
VSS_DC
RDAT[6]
TTOHCLK
TTOHEN
T
LO
W
TTO
HFP
TSDCLK
TSD
TSICLK
T
SO
W
TOW
CLK
VSS_DC
TCLK
VDD_DC
TSUC
TLD
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