PMC PM5352-BI Datasheet

PM5352 S/UNI STAR

DATA SHEET PMC-1990421 ISSUE 2 SATURN USER NETWORK INTERFACE 155 (STAR)

PM5352

S/UNI-STAR

SATURN

USER NETWORK INTERFACE

(STAR)

DATA SHEET

ISSUE 2: FEBRUARY 2000

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PM5352 S/UNI STAR

DATA SHEET PMC-1990421 ISSUE 2 SATURN USER NETWORK INTERFACE 155 (STAR)

PUBLIC REVISION HISTORY

Issue

Issue Date Details of Change

No.

2 February,

2000

1 December,

1999

Added additional bytes to software initialization (section 8.1) to further reduce power consumption. DC characteristics section was added. Released data sheet (replaces draft data sheet issue 2)

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DATA SHEET PMC-1990421 ISSUE 2 SATURN USER NETWORK INTERFACE 155 (STAR)

1 FEATURES.............................................................................................. 1

1.1 GENERAL..................................................................................... 1

1.2 THE SONET RECEIVER .............................................................. 2

1.3 THE RECEIVE ATM PROCESSOR .............................................. 3

1.4 THE RECEIVE POS PROCESSOR.............................................. 3

1.5 THE SONET TRANSMITTER ....................................................... 4

1.6 THE TRANSMIT ATM PROCESSOR............................................ 4

1.7 THE TRANSMIT POS PROCESSOR ........................................... 5

2 APPLICATIONS....................................................................................... 6

3 REFERENCES......................................................................................... 7

4 DATASHEET OVERVIEW........................................................................ 9

5 PIN DIAGRAM ....................................................................................... 10

6 PIN DESCRIPTION.................................................................................11

6.1 LINE SIDE INTERFACE SIGNALS..............................................11

6.2 SECTION AND LINE STATUS DCC SIGNALS........................... 14

6.3 ATM (UTOPIA) AND PACKET OVER SONET (POS-PHY)

SYSTEM INTERFACE ................................................................ 15

6.4 MICROPROCESSOR INTERFACE SIGNALS............................ 34

6.5 JTAG TEST ACCESS PORT (TAP) SIGNALS............................ 36

6.6 ANALOG SIGNALS..................................................................... 37

6.7 POWER AND GROUND ............................................................. 37

7 MICROPROCESSOR INTERFACE....................................................... 45

8 OPERATIONS........................................................................................ 56

8.1 DEVICE INITIALIZATION............................................................ 56

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9 TEST FEATURES DESCRIPTION ........................................................ 57

9.1 MASTER TEST REGISTER........................................................ 57

9.2 JT AG TEST POR T...................................................................... 59

10 DC CHARACTERISTICS....................................................................... 69

1 1 ORDERING AND THERMAL INFORMA TION........................................ 70

12 MECHANICAL INFORMATION.............................................................. 71

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DATA SHEET PMC-1990421 ISSUE 2 SATURN USER NETWORK INTERFACE 155 (STAR)

1 FEATURES

1.1 General

• Single chip ATM User-Network Interface operating at 155.52 Mbit/s.

• Implements the ATM Forum User Network Interface Specification and

the ATM physical layer for Broadband ISDN according to CCITT Recommendation I.432.

• Implements the Point-to-Point Protocol (PPP) over SONET/SDH

specification according to RFC 1619/1662 of the PPP Working Group of the Internet Engineering Task Force (IETF).

• Processes duplex 155.52 Mbit/s STS-3c (STM-1) data streams with

on-chip clock and data recovery and clock synthesis.

• Exceeds Bellcore GR-253-CORE jitter tolerance and intrinsic jitter

criteria.

• Exceeds Bellcore GR-253-CORE jitter transfer and phase variation

criteria.

• Provides control circuitry required to exceed Bellcore GR-253-CORE

WAN clocking requirements related to wander transfer, holdover and long term stability when using an external VCXO.

• Compatible with ATM Forum’s Utopia Level 2 Specification with Multi-

PHY addressing and parity support.

• Implements the POS-PHY 16-bit System Interface for Packet over

SONET/SDH (POS) applicat ions. This system interface is similar to Utopia Level 2, but adapted to packet transfer. Both byte-level and packet-level transfer modes are supported.

• Provides a standard 5 signal IEEE 1149.1 JTAG test port for boundary

scan board test purposes.

• Provides a generic 8-bit microprocessor bus interface for configuration,

control, and status monitoring.

• Low power 3.3V CMOS with PECL and TTL compatible inputs and

CMOS/TTL outputs, with 5V tolerance inputs (system side interface is

3.3V only).

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DATA SHEET PMC-1990421 ISSUE 2 SATURN USER NETWORK INTERFACE 155 (STAR)

• Industrial temperature range (-40°C to +85°C).

• 304 pin Super BGA package.

1.2 The SONET Receiver

• Provides a serial interface at 155.52 Mbit/s.

• Recovers the clock and data.

• Frames to and de-scrambles the recovered stream.

• Detects signal degrade (SD) and signal fail (SF) threshold crossing

alarms based on received B2 errors.

• Captures and debounces the synchronization status (S1) byte in a

readable register.

• Filters and captures the automatic protection switch channel (K1, K2)

bytes in readable registers and detects APS byte failure.

• Counts received section BIP-8 (B1) errors, received line BIP-24 (B2)

errors, line far end block errors (FEBE), and received path BIP-8 (B3) errors and path far end block errors (FEBE).

• Detects loss of signal (LOS), out of frame (OOF), loss of frame (LOF),

line alarm indication signal (LAIS), line remote defect indication (LRDI), loss of pointer (LOP), path alarm indication signal (PAIS), path remote defect indication (PRDI) and path extended remote defect indicator (PERDI).

• Extracts the section and line data communication channels (D1-D3

and D4-12) as selected in internal register banks and serializes them at 192 Kbit/s (D1-D3) and 576 Kbit/s (D4-D12) for optional external processing.

• Extracts the 16 or 64 byte section trace (J0) sequence and the 16 or

64 byte path trace (J1) sequence into internal register banks.

• Interprets the received payload pointer (H1, H2) and extracts the STS-

3c (STM-1) synchronous payload envelope and path overhead.

• Provides a divide by 8 recovered clock (19.44 MHz).

• Provides a 8KHz receive frame pulse.

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1.3 The Receive ATM Processor

• Extracts ATM cells from the received STS-3c (STM-1) synchronous

payload envelope using ATM cell delineation.

• Provides ATM cell payload de-scrambling.

• Performs header check sequence (HCS) error detection and

correction, and idle/unassigned cell filtering.

• Detects Out of Cell Delineation (OCD) and Loss of Cell Delineation

(LCD).

• Counts number of received cells, idle cells, errored cells and dropped

cells.

• Provides a synchronous 8-bit wide, four-cell FIFO buffer.

1.4 The Receive POS Processor

• Generic design that supports packet based link layer protocols, like

PPP, HDLC and Frame Relay.

• Performs self synchronous POS data de-scrambling on SPE payload

(x43+1 polynomial).

• Performs flag sequence detection and terminates the received POS

frames.

• Performs frame check sequence (FCS) validation. The POS

processor supports the validation of both CRC-CCITT and CRC-32 frame check sequences.

• Performs Control Escape de-stuffing.

• Checks for packet abort sequence.

• Checks for octet aligned packet lengths and for minimum and

maximum packet lengths. Automatically deletes short packets (software configurable), and marks those exceeding the maximum length as errored.

• Provides a synchronous 256 byte FIFO buffer accessed through a 16-

bit data bus on the POS-PHY System Interface.

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1.5 The SONET Transmitter

• Synthesizes the 155.52 MHz transmit clock from a 19.44 MHz

reference.

• Provides a differential TTL serial interface (can be adapted to PECL

levels) at 155.52 Mbit/s with both line rate data (TXD+/-) and clock (TXC+/-).

• Provides a transmit frame pulse input to align the transport frames to a

system reference.

• Provides a transmit byte clock (divide by eight of the synthesized line

rate clock) to provide a timing reference for the transmit outputs.

• Optionally inserts register programmable APS (K1, K2) and

synchronization status (S1) bytes.

• Optionally inserts path alarm indication signal (PAIS), path remote

defect indication (PRDI), line alarm indication signal (LAIS) and line remote defect indication (LRDI).

• Inserts path BIP-8 codes (B3), path far end block error (G1)

indications, line BIP-24 codes (B2), line far end block error (M1) indications, and section BIP-8 codes (B1) to allow performance monitoring at the far end.

• Optionally inserts the section and line data communication channels

(D1-D3 or D4-12) via a 192 kbit/s (D1-D3) and 576 kbit/s (D4-D12) serial stream.

• Optionally inserts the 16 or 64 byte section trace (J0) sequence and

the 16 or 64 byte path trace (J1) sequence from internal register banks.

• Scrambles the transmitted STS-3c (STM-1) stream and inserts the

framing bytes (A1,A2).

• Inserts ATM cells or POS frames into the transmitted STS-3c (STM-1)

synchronous payload envelope.

1.6 The Transmit ATM Processor

• Provides idle/unassigned cell insertion.

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• Provides HCS generation/insertion, and ATM cell payload scrambling.

• Counts number of transmitted and idle cells.

• Provides a synchronous 8-bit wide, four cell FIFO buffer.

1.7 The Transmit POS Processor

• Generic design that supports any packet based link layer protocol, like

PPP, HDLC and Frame Relay.

• Performs self synchronous POS data scrambling (X43 + 1 polynomial).

• Encapsulates packets within a POS frame.

• Performs flag sequence insertion.

• Performs byte stuffing for transparency processing.

• Performs frame check sequence generation. The POS processor

supports the generation of both CRC-CCITT and CRC-32 frame check sequences.

• Aborts packets under the direction of the host or when the FIFO

underflows.

• Provides a synchronous 256 byte FIFO buffer accessed through

the16-bit data bus on the POS-PHY System Interface.

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2 APPLICATIONS

• DSLAM uplinks

• Access Concentrators

• WAN and edge ATM switches.

• LAN switches and hubs.

• Layer 3 switches.

• Multiservice switches (FR, ATM, IP, etc..).

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3 REFERENCES

• Bell Communications Research - GR-253-CORE “SONET Transport

Systems: Common Generic Criteria”, Issue 2, December 1995.

• Bell Communications Research - GR-436-CORE “Digital Network

Synchronization Plan”, Issue 1 Revision 1, June 1996..

• ITU-T Recommendation G.703 - "Physical/Electrical Characteristics of

Hierarchical Digital Interfaces", 1991.

• ITU-T Recommendation G.704 - "General Aspects of Digital

Transmission Systems; Terminal Equipment - Synchronous Frame Structures Used At 1544, 6312, 2048, 8488 and 44 736 kbit/s Hierarchical Levels", July, 1995.

• ITU, Recommendation G.707 - "Network Node Interface For The

Synchronous Digital Hierarchy", 1996.

• ITU Recommendation G781, “Structure of Recommendations on

Equipment for the Synchronous Design Hierarchy (SDH)”, January

1994.

• ITU, Recommendation G.783 - "Characteristics of Synchronous Digital

Hierarchy (SDH) Equipment Functional Blocks", 1996.

• ITU Recommendation I.432, “ISDN User Network Interfaces”, March

93.

• ATM Forum - ATM User-Network Interface Specification, V3.1,

October, 1995.

• ATM Forum - “UTOPIA, An ATM PHY Interface Specification, Level 2,

Version 1”, June, 1995.

• IETF Network Working Group – RFC-1619 “Point to Point Protocol

(PPP) over SONET/SDH Specification”, May 1994.

• IETF Network Working Group - RFC-1661 “The Point to Point Protocol

(PPP)”, July 1994.

• IETF Network Working Group - RFC-1662 “PPP in HDLC like framing”,

July 1994.

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• PMC-971147 “Saturn Compliant Interface for Packet over SONET

Physical Layer and Link Layer Devices, Level 2”, Issue 3, February

1998.

• PMC-950820 “SONET/SDH Bit Error Threshold Monitoring Application

Note”, Issue 2, September 1998.

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4 DATASHEET OVERVIEW

The PM5352 S/UNI-STAR is functionally equivalent to a single channel PM5351 S/UNI-TETRA (TETRA channel #4). The devices are software compatible and pin compatible. This datasheet provides a complete pinout description for the S/UNI-STAR, as well as any differences between these devices (including boundary scan register, test mode 0 register). For a complete functional and register description, please refer to the PMC-

971240.

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5 PIN DIAGRAM

The S/UNI-STAR is available in a 304 pin SBGA package having a body size of 31 mm by 31 mm and a ball pitch of 1.27 mm.

2322212019181716151413121110987654321

VDD VSS TDAT[12] TDAT[15] PHY_OEN VSS D[2] VSS A[0] A[3] A[7] VSS A[10] WRB TDO VSS N/C VSS N/C RAVD1_B RAVS1_B VSS VDD

B VSS VDD VSS TDAT[13] STPA N/C D[1] D[4] D[6] A[2] A[6] A[9] CSB RSTB TMS TCK N/C N/C QAVS_2 N/C VSS VDD VSS

C TDAT[7] VSS VDD TDAT[10] TDAT[14] TEOP BIAS D[3] D[5] A[1] A[5] A[8] ALE INTB TRSTB N/C N/C QAVD_2 N/C RAVD1_C VDD VSS N/C

D TDAT[4] TDAT[6] TDAT[9] VDD TDAT[11] VDD TERR D[0] VDD D[7] A[4] VDD RDB TDI VDD N/C N/C VDD RAVS1_C VDD N/C N/C VSS

E TDAT[0] TDAT[3] TDAT[5] TDAT[8] N/C VSS VSS N/C

F VSS TMOD TDAT[2] VDD VDD RAVS1_A N/C VSS

G VDD TADR[0] TADR[2] T DAT[1] RAVD1_A N/C VSS VSS

H VSS TPRTY V DD T ADR[1] N/C RAVS2_A RAVD2_A VSS

TCA / PTPA TENB

K N/C

L REOP RERR N/C N/C RAVD2_B TAVD1_A T AVS1_A TAVD1_B

M VSS RVAL

N/C N/C N/C

RSOC /

RSOP

RADR[2] RADR[0] VDD VDD VDD N/C N/C ATB3

T VSS VDD RPRTY RDAT[13] RAVS3_A N/C N/C VSS

RDAT[15] RDAT[14] RDAT[ 12] RDAT[9] TXCP VSS RAVD3_A N/C

VSS RDAT[11] RDAT[8] VDD VDD TXCN VSS VSS

W RDAT[10] RDAT[7] RDAT[5] RDAT[2] RAVS4_A SD T XDP VSS

RDAT[6] RDAT[4] RDAT[1] VDD RMOD VDD N/C N/C VDD N/C N/C VDD N/C N/C VDD VS S TFPI VDD RAVS4_C VDD RAVD4_A RX- TXDN

AA RDAT[3] VSS VDD RDAT[0] N/C N/C N/C RLD N/C N/C N/C N/C TLDCLK TSDCLK TLD VSS VSS QAVD_1 C- RAVD4_C VDD VSS R X+

TSOC /

VDD VDD VSS N/C RAVD2_C

TSOP

DTCA /

BIAS TFCLK

DTPA

DRCA /

VDD VDD TAVS1_B RAVD3_B VSS

DRPA

RCA / PRPA

RENB RFCLK RADR[1] ATB2 ATB1 ATB0 RAVS3_C

BOTTOM VIEW

RAVS2_C RAVS2_B N/C N/C

RAVD3_C RAVS3_B N/C N/C

AB VSS VDD VSS N/C RLDCLK RSD N/C N/C RALRM RCLK RFPO N/C TFPO N/C N/C VSS TSD VSS QAVS_1 C+ VSS VDD VSS

VDD VSS RSDCLK N/C N/C VSS N/C VSS N/C N/C N/C VSS TCLK N/C N/C VSS VSS VSS REFCLK RAVD4_B RAVS4_B VSS VDD

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6 PIN DESCRIPTION

6.1 Line Side Interface Signals Pin Name Type Pin

Function

No.

REFCLK Input AC5 The reference clock input (REFCLK) must provide a

jitter-free 19.44 MHz reference clock. It is used as the reference clock by both clock recovery and clock synthesis circuits.

When the WAN Synchronization controller is used, REFCLK is supplied using a VCXO. In this application, the transmit direction can be looped timed to any of the line receivers in order to meet wander transfer and holdover requirements.

RXD+ RXD-

Differential

PECL inputs

AA1 Y2

The receive differential data inputs (RXD+, RXD-) contain the NRZ bit serial receive stream. The receive clock is recovered from the RXD+/- bit stream. Please refer to the Operation section for a discussion of PECL interfacing issues.

SD Single-

Ended

PECL

Input

W3 The Signal Detect pin (SD) indicates the presence

of valid receive signal power from the Optical Physical Medium Dependent Device. A PECL high indicates the presence of valid data and a PECL low indicates a loss of signal. It is mandatory that SD be terminated into the equivalent network that RXD+/- is terminated into.

RCLK Output AB14 The receive byte clock (RCLK) provides a timing

reference for the S/UNI-STAR receive outputs. RCLK is a divide by eight of the recovered line rate clock (19.44 MHz).

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Pin Name Type Pin

Function

No.

RFPO Output AB13 The Receive Frame Pulse Output (RFPO), when

the framing alignment is found (the OOF register bit is logic zero), is an 8 kHz signal derived from the receive line clock. RFPO pulses high for one RCLK cycle every 2430 RCLK cycles (STS-3c (STM-1)). RFPO is updated on the rising edge of RCLK.

RALRM Output AB15 The Receive Alarm (RALRM) output indicates the

state of the receive framing. RALRM is low if no receive alarms are active. RALRM is high if line AIS (LAIS), path AIS (PAIS), line RDI (LRDI), path RDI (PRDI), enhanced path RDI (PERDI), loss of signal (LOS), loss of frame (LOF), out of frame (OOF), loss of pointer (LOP), loss of cell delineation (LCD), signal fail BER (SFBER), signal degrade BER (SDBER), path trace identification mismatch (TIM), path signal la bel mismatch (PSLM) is detected in the channel. Each alarm can be individually enabled using bits in the S/UNI-STAR Channel Alarm Control registers #1 and #2.

TXD+ TXD-

TXC+ TXC-

Differential TTL outpu

(externally

converted

to PECL)

Differential TTL outpu

(externally

converted

to PECL)

W2 Y1

U4 V3

RALRM is updated on the rising edge of RCLK. . The transmit differential data outputs (TXD+, TXD-)

contain the 155.52 Mbit/s transmit stream. .

The transmit differential clock outputs (TXC+, TXC-) contain the 155.52 Mbit/s transmit clock.

TXC+/- must be enabled by setting the TXC_OE register bit to logic one.

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Pin Name Type Pin

Function

No.

TFPI Input Y7 The active high framing position (TFPI) signal is an

8 kHz timing marker for the transmitter. TFPI is used to align the SONET/SDH transport frame generated by the S/UNI-STAR device to a system reference. TFPI is internally used to align a master frame pulse counter. When TFPI is not used, this counter is free-running.

TFPI should be brought high for a single TCLK period every 2430 (STS-3c (STM-1)) TCLK cycles, or a multiple thereof. TFPI shall be tied low if such synchronization is not required. TFPI cannot be used as an input to a loop-timed channel. For TFPI to operate correctly it is required that the TCLK/TFPO output be configured to output the CSU byte clock.

The TFPI_EN register bits allow use of the global framing pulse counter and TFPI for framing alignment.

TFPI is sampled on the rising edge of TCLK, but only when the TTSEL register bit is set to logic zero. When TTSEL is set to logic one, TFPI is unused.

TFPO Output AB11 The Transmit Frame Pulse Output (TFPO) pulses

high for one TCLK cycle every 2430 TCLK cycles and provides an 8 KHz timing reference. TFPO can be enabled using TFPO_CH[1:0] configuration register bits, with the restriction that the device must be self-timed (not in loop-timed or line-loopback modes). TFPO is updated on the rising edge of TCLK.

TCLK Output AC11 The transmit byte clock (TCLK) output provides a

timing reference for the S/UNI-STAR self-timed channel. TCLK always provide a divide by eight of the synthesized line rate clock and thus has a nominal frequency of 19.44 MHz. TFPI is sampled on the rising edge of TCLK. TCLK does not apply to internally loop-timed channels, in which case RCLK provides transmit timing information.

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6.2 Section and Line Status DCC Signals Pin Name Type Pin

Function

No.

RSD Output AB18 The receive se ction DCC (RSD) signal contains the

section data communications channel (D1-D3)

RSDCLK Output AC21 The receive section DCC clock (RSDCLK) is used

to clock out the section DCC. RSDCLK is a 192 kHz clock used to update the

RSD output. RSDCLK is generated by gapping a 216 kHz clock.

TSD Input AB7 The transmit section DCC (TSD) signal contains the

section data communications channel (D1-D3). TSD is sampled on the rising edge of TSDCLK.

TSDCLK Output AA10 The transmit section DCC clock (TSDCLK) is used

to clock in the section DCC. TSDCLK is a 192 kHz clock used to sample the

TSD input. TSDCLK is generated by gapping a 216 kHz clock.

RLD Output AA16 The re ceive line DCC (RLD) signal contains the line

data communications channel (D4-D12).

RLDCLK Output AB19 The receive line DCC clock (RLDCLK) is use d to

clock out the line DCC. RLDCLK is a 576 kHz clock used to update the

RLD output. RLDCLK is generated by gapping a

2.16 MHz clock.

TLD Input AA9 The transmit line DCC (TLD) signal contains the

line data communications channel (D4-D12). TLD is sampled on the rising edge of TLDCLK.

TLDCLK Output AA11 The transmit line DCC clock (TLDCLK) is used to

clock in the line DCC. TLDCLK is a 576 kHz clock used to sample the

TLD input. TLDCLK is generated by gapping a 2.16 MHz clock.

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6.3 ATM (UTOPIA) and Packet over SONET (POS-PHY) System Interface Pin Name Type Pin

No.

TDAT[15] TDAT[14] TDAT[13] TDAT[12] TDAT[11] TDAT[10] TDAT[9] TDAT[8] TDAT[7] TDAT[6] TDAT[5] TDAT[4] TDAT[3] TDAT[2] TDAT[1] TDAT[0]

Input

(ATM)

Input

(POS)

A20 C19 B20 A21 D19 C20 D21 E20 C23 D22 E21 D23 E22 F21 G20 E23

Function

UTOPIA Transmit Cell Data Bus (TDAT[15:0 ] ). This data bus carries the ATM cell octets that are

written to the selected transmit FIFO. TDAT[15:0] is considered valid only when TENB is simultaneously asserted and the S/UNI-STAR is selected via TADR[2:0].

TDAT[15:0] is sampled on the rising edge of TFCLK.

POS-PHY Transmit Packet Data Bus (TDAT[15:0]). This data bus carries the POS packet octets that

are written to the selected transmit FIFO. TDAT[15:0] is considered valid only when TENB is simultaneously asserted and the S/UNI-STAR is selected via TADR[2:0].

TDAT[15:0] is sampled on the rising edge of TFCLK.

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Pin Name Type Pin

No.

TPRTY Input

H22 UTOPIA Transmit bus parity (TPRTY) signal.

(ATM)

TPRTY Input

H22 POS-PHY Transmit bus parity (TPRTY) signal.

(POS)

Function

The transmit parity (TPRTY) signal indicates the parity of the TDAT[15:0] bus. A parity error is indicated by a status bit and a maskable interrupt. Cells with parity errors are inserted in the transmit stream, so the TPRTY input may be unused. Odd or even parity selection is made using the RXPTYP register bit.

TPRTY is considered valid only when TENB is simultaneously asserted and the S/UNI-STAR is selected via TADR[2:0].

TPRTY is sampled on the rising edge of TFCLK.

The transmit parity (TPRTY) signal indicates the parity of the TDAT[15:0] bus. A parity error is indicated by a status bit and a maskable interrupt. Packets with parity errors are inserted in the transmit stream, so the TPRTY input may be unused. Odd or even parity selection is made using the RXPTYP register bit. TPRTY is considered valid only when TENB is simultaneously asserted and the S/UNI-STAR is selected via TADR[2: 0].

TPRTY is sampled on the rising edge of TFCLK

TSOC Input

(ATM)

J21 UTOPIA Transmit Start of Cell (TSOC) signal.

The transmit start of cell (TSOC) signal marks the start of cell on the TDAT bus. When TSOC is high, the first word of the cell structure is present on the TDAT bus. It is not necessary for TSOC to be present for each cell. An interrupt may be generated if TSOC is high during any word other than the first word of the cell structure.

TSOC is considered valid only when TENB is simultaneously asserted and the S/UNI-STAR is selected via TADR[2:0].

TSOC is sampled on the rising edge of TFCLK.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 16

PM5352 S/UNI STAR

DATA SHEET PMC-1990421 ISSUE 2 SATURN USER NETWORK INTERFACE 155 (STAR)

Pin Name Type Pin

No.

TSOP Input

J21 POS-PHY Transmit Start of Packet (TSOP) signals.

(POS)

TENB Input

J22 UTOPIA Transmit Multi-PHY Write Enable (TENB)

(ATM)

Function

TSOP indicates the first word of a packet. TSOP is required to be present at the beginning of every packet for proper operation.

TSOP is considered valid only when TENB is simultaneously asserted and the S/UNI-STAR is selected via TADR[2:0].

TSOP is sampled on the rising edge of TFCLK.

signal. The TENB signal is an active low input which is

used along with the TADR[2:0] inputs to initiate writes to the transmit FIFO’s.

TENB works as follows. When sampled high, no write is performed, but the TADR[2:0] address is latched to identify the transmit FIFO to be accessed. When TENB is sampled low, the word on the TDAT bus is written into the transmit FIFO that is selected by the TADR[2:0} address bus. A complete 53 octet cell must be written to the transmit FIFO before it is inserted into the transmit stream. Idle cells are inserted when a complete cell is not available. While TENB is deasserted, TADR[2:0] can be used for polling TCA.

TENB is sampled on the rising edge of TFCLK.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 17

PM5352 S/UNI STAR

DATA SHEET PMC-1990421 ISSUE 2 SATURN USER NETWORK INTERFACE 155 (STAR)

Pin Name Type Pin

No.

TENB Input

J22 POS-PHY Transmit Multi-PHY Write Enable (TENB)

(POS)

TADR[2] TADR[1] TADR[0]

Input

(ATM)

G21 H20 G22

Function

signal. The S/UNI-STAR supports both byte-level and

packet-level transfer. Packet-level transfer operates in a similar fashion to Utopia, with a selection phase when TENB is deasserted and a transfer phase when TENB is asserted. While TENB is asserted, TADR[2:0] is used for polling PTPA and the currently selected PHY status is provided on STPA. Byte level transfer works on a cycle basis. When TENB is asserted, data is transferred to the selected PHY. Nothing happens when TENB is deasserted. Polling is not available and packet availability is indicated by DTPA.

TENB is sampled on the rising edge of TFCLK. Transmit Address (T ADR[2:0]) . The TADR[2:0] bus

is used for device selection and device polling in accordance with the Utopia Level 2 standard. When TADR[2:0] is set to the same value as the PHY_ADR[2:0] inputs than the transmit interface of this S/UNI-STAR is either being selected or polled. Note that the null-phy address 0x7 is an invalid Address and cannot be used to select the S/UNISTAR.

TADR[2:0] is sampled on the rising edge of TFCLK.

TADR[2] TADR[1] TADR[0]

Input

(POS)

G21 H20 G22

POS-PHY Transmit Write Address (TADR[2:0]) signals.

The TADR[2:0] bus is used to select the FIFO (and hence port) that is written to using the TENB signal. In packet level transfer mode, TADR[2:0] is also used for polling on PTPA.

Note that address 0x7 is the null-PHY address and cannot be used to select theS/UNI-STAR.

TADR[2:0] is sampled on the rising edge of TFCLK.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 18

PM5352 S/UNI STAR

DATA SHEET PMC-1990421 ISSUE 2 SATURN USER NETWORK INTERFACE 155 (STAR)

Pin Name Type Pin

No.

TCA Output

J23 UTOPIA Transmit multi-PHY Cell Available (TCA)

(ATM)

Function

The TCA signal indicates when a cell is available in the transmit FIFO for the port polled by TADR[2:0] when TENB is asserted. When high, TCA indicates that the transmit FIFO is not full and a complete cell may be written. When TCA goes low, it can be configured to indicate either that the transmit FIFO is near full or that the transmit FIFO is full. TCA will transition low on the rising edge of TFCLK after the Payload word 19 (TCALEVEL0=0) or 23 (TCALEVEL0=1) is sampled if the PHY being polled is the same as the PHY in use. To reduce FIFO latency, the FIFO depth at which TCA indicates "full" can be set to one, two, three or four cells. Note that regardless of what fill level TCA is set to indicate "full" at, the transmit cell processor can store 4 complete cells.

TCA is tri-stated when either the null-PHY address (0x7) or an address not matching the address set by PHY_ADR[2:0] is latched from the TADR[2:0] inputs when TENB is high.

TCA is updated on the rising edge of TFCLK.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 19

PM5352 S/UNI STAR

DATA SHEET PMC-1990421 ISSUE 2 SATURN USER NETWORK INTERFACE 155 (STAR)

Pin Name Type Pin

Function

No.

PTPA J23 POS-PHY Polled Transmit multi-PHY Packet

Available (PTPA). PTPA transitions high when a programmable

minimum number of bytes is available in the polled transmit FIFO (TPAHW M[7:0] register bits). Once high, PTPA indicates that the transmit FIFO is not full. When PTPA transitions low, it optionally indicates that the transmit FIFO is full or near full (TPALWM[7:0] register bits). PTPA allows to poll the PHY address selected by TADR[2:0] when TENB is asserted.

PTPA is tri-stated when either the null-PHY address (0x7) or an address not matching the address set by PHY_ADR[2:0] is latched from the TADR[2:0] inputs when TENB is high.

PTPA is only available in POS-PHY packet-level transfer mode, as selected by the POS_PLVL register bit. PTPA is tristated in byte-level transfer mode. PTPA is updated on the rising edge of TFCLK.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 20

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PMC PM5352-BI Datasheet

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