PMC PM5351-BI Datasheet

S/UNI-TETRA

SATURN USER NETWORK INTERFACE (155-TETRA)

DATASHEET PMC-1971240 ISSUE 7

PMC-Sierra, Inc.

PM5351

PM5351 S/UNI-TETRA

S/U NI-

155- TETRA

®

S/UNI-TETRA

SATURN

USER NETWORK INTERFACE

(155-TETRA)

PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000

DATA SHEET

ISSUE 7: FEBRUARY 2000

S/UNI-TETRA

SATURN USER NETWORK INTERFACE (155-TETRA)

DATASHEET PMC-1971240 ISSUE 7

REVISION HISTORY

PMC-Sierra, Inc.

PM5351 S/UNI-TETRA

Issue

Issue Date Details of Change

No.

7 February 2000

• Converted Bit 0 of register 0x0E to “Reserved"

• Added PERFCTRL register bit to register 0x0F

• Changed AVGPER bit description in register 0xDD.

PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000

S/UNI-TETRA

SATURN USER NETWORK INTERFACE (155-TETRA)

DATASHEET PMC-1971240 ISSUE 7

PMC-Sierra, Inc.

PM5351 S/UNI-TETRA

Issue

Issue Date Details of Change

No.

6 December,

1999

General update including:

• Page 17 – Signal Detect connection information

• Page 18 – Power info when using 155.52 transmit clocks

• Page 24,32 – Clarification on use of TENB and RENB

• Page 37 – PHY_OEN operation when the TETRA is

shared with other PHY devices on the same bus

• Page 38 – Device initialization information

• Page 40 – 220nf X7R 10% ceramatic capacitor used to

meet jitter transfer specifications

• Page 42 – Pull-up resistor on QAVD signals needed to avoid latchup during power-up

• Page 60, 214, 234 – Maximum packet length should be set no greater than 0xFFFE

• Page 66 – Packets are not aborted in overrun conditions

• Page 72 – RPA assertion information

• Page 86 – Revision ID bits incremented

• Page 105 – LANB_WAN bit added to select between jitter

transfer and non jitter transfer mode of operations

• Page 152 – Path far end receiver failure alarm persistence bit info updated

• Page 161 – Info on setting Path Signal Label for POS mode

• Page 176 – FIFO reset should be performed after FIFO overrrun

• Page 210 – Register bit added to select between abort sequence or flag insertion under a drop path AIS condition

• Page 216 – Maximum Receive Packet Available High Water Mark is 0xF0

PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000

S/UNI-TETRA

SATURN USER NETWORK INTERFACE (155-TETRA)

DATASHEET PMC-1971240 ISSUE 7

PMC-Sierra, Inc.

PM5351 S/UNI-TETRA

Issue

Issue Date Details of Change

No.

6 December

1999

• Page 229 – Info on setting Transmit Initiation Levels

• Page 232 – Setting of Transmit Packet Available High

Water Mark to avoid FIFO overrruns

• Page 250 – S1 debouncing information

• Page 268 – Updated boundary scan info

• Page 296 – Analog Power Supply Filtering info

• Page 298 – Updated Power Supply Sequencing info

• Page 303 – Setting the TETRA for SDH or SONET mode

• Page 308 – Updated POS Receive Synchronous FIFO

Timing Diagram

• Page 313 – Updated DC characteristic

• Page 336 – Updated air flow info

PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000

S/UNI-TETRA

SATURN USER NETWORK INTERFACE (155-TETRA)

DATASHEET PMC-1971240 ISSUE 7

LIST OF REGISTERS

REGISTER 0X00: S/UNI-TETRA MASTER RESET AND IDENTITY......................................109

REGISTER 0X01: S/UNI-TETRA MASTER CONFIGURATION............................................. 110

REGISTER 0X02: S/UNI-TETRA MASTER SYSTEM INTERFACE CONTROL ......................112

REGISTER 0X03: S/UNI-TETRA MASTER CLOCK MONITOR............................................. 114

REGISTER 0X04: S/UNI-TETRA MASTER INTERRUPT STATUS ........................................ 116

REGISTER 0X05: S/UNI-TETRA CHANNEL RESET AND MONITORING UPDATE ............... 118

REGISTER 0X06: S/UNI-TETRA CHANNEL CONFIGURATION ...........................................119

REGISTER 0X07: S/UNI-TETRA CHANNEL CONTROL.......................................................121

REGISTER 0X08: S/UNI-TETRA CHANNEL CONTROL EXTENSION..................................123

REGISTER 0X0A: S/UNI-TETRA CHANNEL INTERRUPT STATUS #1 .................................124

PMC-Sierra, Inc.

PM5351 S/UNI-TETRA

REGISTER 0X0B: S/UNI-TETRA CHANNEL INTERRUPT STATUS #2 .................................126

REGISTER 0X0C: CSPI (CLOCK SYNTHESIS) CONTROL AND STATUS............................128

REGISTER 0X0D: CSPI (CLOCK SYNTHESIS) RESERVED...............................................130

REGISTER 0X0E: CRSI (CLOCK RECOVERY) CONTROL AND STATUS ............................131

REGISTER 0X0F: CRSI (CLOCK RECOVERY) PLL MODE SELECT ...................................133

REGISTER 0X10: RSOP CONTROL/INTERRUPT ENABLE .................................................135

REGISTER 0X11: RSOP STATUS/INTERRUPT STATUS.....................................................137

REGISTER 0X12: RSOP SECTION BIP-8 LSB....................................................................139

REGISTER 0X13: RSOP SECTION BIP-8 MSB...................................................................139

REGISTER 0X14: TSOP CONTROL...................................................................................140

REGISTER 0X15: TSOP DIAGNOSTIC...............................................................................143

REGISTER 0X18: RLOP CONTROL/STATUS .....................................................................144

REGISTER 0X19: RLOP INTERRUPT ENABLE/INTERRUPT STATUS .................................147

REGISTER 0X1A: RLOP LINE BIP-24 LSB.........................................................................149

REGISTER 0X1B: RLOP LINE BIP-24................................................................................149

REGISTER 0X1C: RLOP LINE BIP-24 MSB ........................................................................150

REGISTER 0X1D: RLOP LINE FEBE LSB ..........................................................................151

REGISTER 0X1E: RLOP LINE FEBE ..................................................................................151

REGISTER 0X1F: RLOP LINE FEBE MSB..........................................................................152

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE vii

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SATURN USER NETWORK INTERFACE (155-TETRA)

DATASHEET PMC-1971240 ISSUE 7

REGISTER 0X20: TLOP CONTROL...................................................................................153

REGISTER 0X21: TLOP DIAGNOSTIC...............................................................................156

REGISTER 0X22: TLOP TRANSMIT K1..............................................................................157

REGISTER 0X23: TLOP TRANSMIT K2..............................................................................158

REGISTER 0X24: S/UNI-TETRA CHANNEL TRANSMIT SYNC. MESSAGE (S1)..................159

REGISTER 0X25: S/UNI-TETRA CHANNEL TRANSMIT J0/Z0.............................................160

REGISTER 0X28: SSTB CONTROL ...................................................................................161

REGISTER 0X29: SSTB SECTION TRACE IDENTIFIER STATUS .......................................163

REGISTER 0X2A: SSTB INDIRECT ADDRESS REGISTER.................................................165

REGISTER 0X2B: SSTB INDIRECT DATA REGISTER ........................................................166

REGISTER 0X30 (EXTD=0): RPOP STATUS/CONTROL .....................................................170

REGISTER 0X30 (EXTD=1): RPOP STATUS/CONTROL .....................................................172

PMC-Sierra, Inc.

PM5351 S/UNI-TETRA

REGISTER 0X31 (EXTD=0): RPOP INTERRUPT STATUS ..................................................174

REGISTER 0X31 (EXTD=1): RPOP INTERRUPT STATUS ..................................................176

REGISTER 0X32: RPOP POINTER INTERRUPT STATUS ...................................................177

REGISTER 0X33 (EXTD=0): RPOP INTERRUPT ENABLE..................................................179

REGISTER 0X33 (EXTD=1): RPOP INTERRUPT ENABLE .................................................181

REGISTER 0X34: RPOP POINTER INTERRUPT ENABLE ..................................................183

REGISTER 0X35: RPOP POINTER LSB .............................................................................185

REGISTER 0X36: RPOP POINTER MSB AND RDI FILTER CONTROL................................186

REGISTER 0X37: RPOP PATH SIGNAL LABEL ..................................................................188

REGISTER 0X38: RPOP PATH BIP-8 LSB ..........................................................................189

REGISTER 0X39: RPOP PATH BIP-8 MSB.........................................................................189

REGISTER 0X3A: RPOP PATH FEBE LSB.........................................................................190

REGISTER 0X3B: RPOP PATH FEBE MSB........................................................................190

REGISTER 0X3C: RPOP AUXILIARY RDI...........................................................................191

REGISTER 0X3D: RPOP ERROR EVENT CONTROL.........................................................193

REGISTER 0X40: TPOP CONTROL/DIAGNOSTIC.............................................................196

REGISTER 0X41: TPOP POINTER CONTROL ...................................................................199

REGISTER 0X43: TPOP CURRENT POINTER LSB............................................................203

REGISTER 0X44: TPOP CURRENT POINTER MSB...........................................................204

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SATURN USER NETWORK INTERFACE (155-TETRA)

DATASHEET PMC-1971240 ISSUE 7

REGISTER 0X45: TPOP ARBITRARY POINTER LSB..........................................................205

REGISTER 0X46: TPOP ARBITRARY POINTER MSB.........................................................206

REGISTER 0X47: TPOP PATH TRACE...............................................................................207

REGISTER 0X48: TPOP PATH SIGNAL LABEL...................................................................208

REGISTER 0X49: TPOP PATH STATUS .............................................................................209

REGISTER 0X50: SPTB CONTROL ...................................................................................217

REGISTER 0X51: SPTB PATH TRACE IDENTIFIER STATUS..............................................219

REGISTER 0X52: SPTB INDIRECT ADDRESS REGISTER .................................................221

REGISTER 0X53: SPTB INDIRECT DATA REGISTER.........................................................222

REGISTER 0X54: SPTB EXPECTED PATH SIGNAL LABEL................................................223

REGISTER 0X55: SPTB PATH SIGNAL LABEL STATUS .....................................................224

REGISTER 0X60: RXCP_50 CONFIGURATION 1 ..............................................................226

PMC-Sierra, Inc.

PM5351 S/UNI-TETRA

REGISTER 0X61: RXCP_50 CONFIGURATION 2 ..............................................................228

REGISTER 0X62: RXCP_50 FIFO/UTOPIA CONTROL & CONFIG......................................231

REGISTER 0X63: RXCP_50 INTERRUPT ENABLES AND COUNTER STATUS ..................233

REGISTER 0X64: RXCP_50 STATUS/INTERRUPT STATUS ..............................................235

REGISTER 0X65: RXCP_50 LCD COUNT THRESHOLD (MSB).........................................237

REGISTER 0X66: RXCP_50 LCD COUNT THRESHOLD (LSB)..........................................237

REGISTER 0X67: RXCP_50 IDLE CELL HEADER PATTERN .............................................239

REGISTER 0X68: RXCP_50 IDLE CELL HEADER MASK...................................................240

REGISTER 0X69: RXCP_50 CORRECTED HCS ERROR COUNT......................................241

REGISTER 0X6A: RXCP_50 UNCORRECTED HCS ERROR COUNT.................................242

REGISTER 0X6B: RXCP_50 RECEIVE CELL COUNTER (LSB)..........................................243

REGISTER 0X6C: RXCP_50 RECEIVE CELL COUNTER...................................................243

REGISTER 0X6D: RXCP_50 RECEIVE CELL COUNTER (MSB) ........................................243

REGISTER 0X6E: RXCP_50 IDLE CELL COUNTER (LSB).................................................245

REGISTER 0X6F: RXCP_50 IDLE CELL COUNTER ..........................................................245

REGISTER 0X70: RXCP_50 IDLE CELL COUNTER (MSB)................................................246

REGISTER 0X80: TXCP_50 CONFIGURATION 1 ..............................................................247

REGISTER 0X81: TXCP_50 CONFIGURATION 2 ..............................................................249

REGISTER 0X82: TXCP_50 CELL COUNT STATUS/CONFIGURATION OPTIONS..............251

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ix

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SATURN USER NETWORK INTERFACE (155-TETRA)

DATASHEET PMC-1971240 ISSUE 7

REGISTER 0X83: TXCP_50 INTERRUPT ENABLE/STATUS ..............................................252

REGISTER 0X84: TXCP_50 IDLE CELL HEADER CONTROL ............................................254

REGISTER 0X85: TXCP_50 IDLE CELL PAYLOAD CONTROL...........................................255

REGISTER 0X86: TXCP_50 TRANSMIT CELL COUNT (LSB).............................................256

REGISTER 0X87: TXCP_50 TRANSMIT CELL COUNT......................................................256

REGISTER 0X88: TXCP_50 TRANSMIT CELL COUNT (MSB)............................................256

REGISTER 0X90: S/UNI-TETRA CHANNEL AUTO LINE RDI CONTROL.............................258

REGISTER 0X91: S/UNI-TETRA CHANNEL AUTO PATH RDI CONTROL............................260

REGISTER 0X92: S/UNI-TETRA CHANNEL AUTO ENHANCED PATH RDI CONTROL.........262

REGISTER 0X93: S/UNI-TETRA CHANNEL RECEIVE RDI AND ENHANCED RDI CONTROL

EXTENSIONS .......................................................................................................265

REGISTER 0X94: S/UNI-TETRA CHANNEL RECEIVE LINE AIS CONTROL.........................267

REGISTER 0X95: S/UNI-TETRA CHANNEL RECEIVE PATH AIS CONTROL........................269

PMC-Sierra, Inc.

PM5351 S/UNI-TETRA

REGISTER 0X96: S/UNI-TETRA CHANNEL RECEIVE ALARM CONTROL #1......................271

REGISTER 0X97: S/UNI-TETRA CHANNEL RECEIVE ALARM CONTROL #2......................271

REGISTER 0XA0: RXFP CONFIGURATION.......................................................................273

REGISTER 0XA1: RXFP CONFIGURATION/INTERRUPT ENABLES...................................275

REGISTER 0XA2: RXFP INTERRUPT STATUS ..................................................................276

REGISTER 0XA3: RXFP MINIMUM PACKET LENGTH........................................................277

REGISTER 0XA4: RXFP MAXIMUM PACKET LENGTH (LSB) .............................................278

REGISTER 0XA5: RXFP MAXIMUM PACKET LENGTH (MSB)............................................278

REGISTER 0XA6: RXFP RECEIVE INITIATION LEVEL .......................................................279

REGISTER 0XA7: RXFP RECEIVE PACKET AVAILABLE HIGH WATER MARK....................281

REGISTER 0XA8: RXFP RECEIVE BYTE COUNTER (LSB)................................................282

REGISTER 0XA9: RXFP RECEIVE BYTE COUNTER .........................................................282

REGISTER 0XAA: RXFP RECEIVE BYTE COUNTER .........................................................282

REGISTER 0XAB: RXFP RECEIVE BYTE COUNTER (MSB)...............................................283

REGISTER 0XAC: RXFP RECEIVE FRAME COUNTER (LSB) ............................................284

REGISTER 0XAD: RXFP RECEIVE FRAME COUNTER......................................................284

REGISTER 0XAE: RXFP RECEIVE FRAME COUNTER (MSB)............................................284

REGISTER 0XAF: RXFP RECEIVE ABORTED FRAME COUNTER (LSB) ............................286

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE x

S/UNI-TETRA

SATURN USER NETWORK INTERFACE (155-TETRA)

DATASHEET PMC-1971240 ISSUE 7

REGISTER 0XB0: RXFP RECEIVE ABORTED FRAME COUNTER (MSB)...........................286

REGISTER 0XB1: RXFP RECEIVE FCS ERROR FRAME COUNTER (LSB) ........................287

REGISTER 0XB2: RXFP RECEIVE FCS ERROR FRAME COUNTER (MSB)........................287

REGISTER 0XB3: RXFP RECEIVE MINIMUM LENGTH ERROR FRAME COUNTER (LSB)..288 REGISTER 0XB4: RXFP RECEIVE MINIMUM LENGTH ERROR FRAME COUNTER (MSB).288 REGISTER 0XB5: RXFP RECEIVE MAXIMUM LENGTH ERROR FRAME COUNTER (LSB).289 REGISTER 0XB6: RXFP RECEIVE MAXIMUM LENGTH ERROR FRAME COUNTER (MSB)289

REGISTER 0XC0: TXFP INTERRUPT ENABLE/STATUS .....................................................290

REGISTER 0XC1: TXFP CONFIGURATION........................................................................292

REGISTER 0XC2: TXFP CONTROL...................................................................................294

REGISTER 0XC3: TXFP TRANSMIT PACKET AVAILABLE LOW WATER MARK ...................296

REGISTER 0XC4: TXFP TRANSMIT PACKET AVAILABLE HIGH WATER MARK..................297

PMC-Sierra, Inc.

PM5351 S/UNI-TETRA

REGISTER 0XC5: TXFP TRANSMIT BYTE COUNTER (LSB)..............................................298

REGISTER 0XC6: TXFP TRANSMIT BYTE COUNTER .......................................................298

REGISTER 0XC7: TXFP TRANSMIT BYTE COUNTER .......................................................298

REGISTER 0XC8: TXFP TRANSMIT BYTE COUNTER (MSB) .............................................299

REGISTER 0XC9: TXFP TRANSMIT FRAME COUNTER (LSB)...........................................300

REGISTER 0XCA: TXFP TRANSMIT FRAME COUNTER ....................................................300

REGISTER 0XCB: TXFP TRANSMIT FRAME COUNTER (MSB)..........................................301

REGISTER 0XCC: TXFP TRANSMIT USER ABORTED FRAME COUNTER (LSB)...............302

REGISTER 0XCD: TXFP TRANSMIT USER ABORTED FRAME COUNTER (MSB)...............302

REGISTER 0XCE: TXFP TRANSMIT FIFO ERROR ABORTED FRAME COUNTER (LSB)....303

REGISTER 0XCF: TXFP TRANSMIT FIFO ERROR ABORTED FRAME COUNTER (MSB)....303

REGISTER 0XD0: WANS CONFIGURATION ......................................................................305

REGISTER 0XD1: WANS INTERRUPT & STATUS .............................................................306

REGISTER 0XD2: WANS PHASE WORD [7:0] ...................................................................307

REGISTER 0XD3: WANS PHASE WORD [15:8].................................................................307

REGISTER 0XD4: WANS PHASE WORD [23:16]...............................................................307

REGISTER 0XD5: WANS PHASE WORD [30:24]...............................................................308

REGISTER 0XD9: WANS REFERENCE PERIOD [7:0] .......................................................309

REGISTER 0XDA: WANS REFERENCE PERIOD [15:8].....................................................309

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE xi

S/UNI-TETRA

SATURN USER NETWORK INTERFACE (155-TETRA)

DATASHEET PMC-1971240 ISSUE 7

REGISTER 0XDB: WANS PHASE COUNTER PERIOD[7:0] ................................................310

REGISTER 0XDC: WANS PHASE COUNTER PERIOD[15:8] ..............................................310

REGISTER 0XDD: WANS PHASE AVERAGE PERIOD [3:0] ............................................... 311

REGISTER 0XE0: RASE INTERRUPT ENABLE ..................................................................312

REGISTER 0XE1: RASE INTERRUPT STATUS ..................................................................313

REGISTER 0XE2: RASE CONFIGURATION/CONTROL......................................................315

REGISTER 0XE3: RASE SF ACCUMULATION PERIOD......................................................318

REGISTER 0XE4: RASE SF ACCUMULATION PERIOD......................................................318

REGISTER 0XE5: RASE SF ACCUMULATION PERIOD......................................................319

REGISTER 0XE6: RASE SF SATURATION THRESHOLD ...................................................320

REGISTER 0XE7: RASE SF SATURATION THRESHOLD ...................................................320

REGISTER 0XE8: RASE SF DECLARING THRESHOLD .....................................................321

PMC-Sierra, Inc.

PM5351 S/UNI-TETRA

REGISTER 0XE9: RASE SF DECLARING THRESHOLD .....................................................321

REGISTER 0XEA: RASE SF CLEARING THRESHOLD .......................................................322

REGISTER 0XEB: RASE SF CLEARING THRESHOLD .......................................................322

REGISTER 0XEC: RASE SD ACCUMULATION PERIOD .....................................................323

REGISTER 0XED: RASE SD ACCUMULATION PERIOD .....................................................323

REGISTER 0XEE: RASE SD ACCUMULATION PERIOD.....................................................324

REGISTER 0XEF: RASE SD SATURATION THRESHOLD...................................................325

REGISTER 0XF0: RASE SD SATURATION THRESHOLD...................................................325

REGISTER 0XF1: RASE SD DECLARING THRESHOLD.....................................................326

REGISTER 0XF2: RASE SD DECLARING THRESHOLD.....................................................326

REGISTER 0XF3: RASE SD CLEARING THRESHOLD.......................................................327

REGISTER 0XF4: RASE SD CLEARING THRESHOLD.......................................................327

REGISTER 0XF5: RASE RECEIVE K1...............................................................................328

REGISTER 0XF6: RASE RECEIVE K2...............................................................................329

REGISTER 0XF7: RASE RECEIVE Z1/S1...........................................................................330

REGISTER 0X400: MASTER TEST....................................................................................332

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DATASHEET PMC-1971240 ISSUE 7

LIST OF FIGURES

FIGURE 1: TYPICAL STS-3C (STM-1) ATM SWITCH PORT APPLICATION .......................... 13

FIGURE 2: TYPICAL STS-3C (STM-1) PACKER OVER SONET/SDH (PPP) APPLICATION... 15

FIGURE 3: TYPICAL STS-3C (STM-1) JITTER TOLERANCE ............................................... 62

FIGURE 4: POINTER INTERPRETATION STATE DIAGRAM................................................ 69

FIGURE 5: CELL DELINEATION STATE DIAGRAM ............................................................. 74

FIGURE 6: HCS VERIFICATION STATE DIAGRAM ............................................................. 76

FIGURE 7: PACKET OVER SONET/SDH FRAME FORMAT................................................. 78

FIGURE 8: CRC DECODER............................................................................................... 79

FIGURE 9: PACKET OVER SONET/SDH FRAME FORMAT................................................. 87

FIGURE 10: CRC GENERATOR......................................................................................... 88

PMC-Sierra, Inc.

PM5351 S/UNI-TETRA

FIGURE 11 : PRE-MATURE RPA ASSERTION TIMING........................................................ 94

FIGURE 12. PHASE COMPARATOR BLOCK DIAGRAM ...................................................... 97

FIGURE 13. PHASE AVERAGER BLOCK DIAGRAM............................................................ 98

FIGURE 14: INPUT OBSERVATION CELL (IN_CELL).........................................................342

FIGURE 15: OUTPUT CELL (OUT_CELL)..........................................................................342

FIGURE 16: BIDIRECTIONAL CELL (IO_CELL).................................................................343

FIGURE 17: LAYOUT OF OUTPUT ENABLE AND BIDIRECTIONAL CELLS........................343

FIGURE 18: ATM MAPPING INTO THE STS-3C (STM-1) SPE .............................................344

FIGURE 19: POS MAPPING INTO THE STS-3C (STM-1) SPE ............................................346

FIGURE 20: STS-3C (STM-1) OVERHEAD........................................................................348

FIGURE 21: 16-BIT WIDE, 27 WORD ATM CELL STRUCTURE...........................................357

FIGURE 22: PACKET DATA STRUCTURE .........................................................................358

FIGURE 23: CONCEPTUAL CLOCKING STRUCTURE ......................................................360

FIGURE 24: LINE LOOPBACK MODE ...............................................................................363

FIGURE 25: SERIAL DIAGNOSTIC LOOPBACK MODE .....................................................365

FIGURE 26: PARALLEL DIAGNOSTIC LOOPBACK MODE ................................................367

FIGURE 27: BOUNDARY SCAN ARCHITECTURE.............................................................369

FIGURE 28: TAP CONTROLLER FINITE STATE MACHINE ................................................371

FIGURE 29: WAN MODE ANALOG POWER PIN PASSIVE-FILTERING WITH 3.3V SUPPLY 376

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FIGURE 30: WAN MODE ANALOG POWER FILTERS WITH 3.3V SUPPLY (1).....................379

FIGURE 31: LAN MODE ANALOG POWER FILTERS WITH 3.3V SUPPLY (2) ......................380

FIGURE 32: POWER SEQUENCING CIRCUIT..................................................................382

FIGURE 33: INTERFACING TO ECL OR PECL...................................................................383

FIGURE 34: CLOCK RECOVERY EXTERNAL COMPONENTS ............................................385

FIGURE 35: MULTI-PHY POLLING AND ADDRESSING TRANSMIT CELL INTERFACE .......388

FIGURE 36: MULTI-PHY POLLING AND ADDRESSING RECEIVE CELL INTERFACE.........389

FIGURE 37: TRANSMIT POS SYSTEM INTERFACE TIMING.............................................391

FIGURE 38: RECEIVE POS SYSTEM INTERFACE.............................................................393

FIGURE 39: TRANSPORT OVERHEAD DATA LINK CLOCK AND DATA EXTRACTION........394

FIGURE 40: TRANSPORT OVERHEAD DATA LINK CLOCK AND DATA INSERTION...........395

FIGURE 41: MICROPROCESSOR INTERFACE READ TIMING..........................................401

PMC-Sierra, Inc.

PM5351 S/UNI-TETRA

FIGURE 42: MICROPROCESSOR INTERFACE WRITE TIMING.........................................403

FIGURE 43: RSTB TIMING DIAGRAM ...............................................................................404

FIGURE 44: TRANSMIT ATM SYSTEM INTERFACE TIMING DIAGRAM.............................406

FIGURE 45: RECEIVE ATM SYSTEM INTERFACE TIMING DIAGRAM ...............................408

FIGURE 46: TRANSMIT POS SYSTEM INTERFACE TIMING.............................................410

FIGURE 47: RECEIVE POS SYSTEM INTERFACE TIMING...............................................413

FIGURE 48: SECTION DCC TIMING DIAGRAM .................................................................414

FIGURE 49: LINE DCC TIMING DIAGRAM ........................................................................415

FIGURE 50: TRANSMIT AND RECEIVE FRAME PULSES ..................................................416

FIGURE 51: LINE SIDE TRANSMIT TIMING DIAGRAM (TXC_OE=1)..................................417

FIGURE 52: JTAG PORT INTERFACE TIMING ..................................................................418

FIGURE 53:- MECHANICAL DRAWING 304 PIN SUPER BALL GRID ARRAY (SBGA) ..........422

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DATASHEET PMC-1971240 ISSUE 7

LIST OF TABLES

TABLE 1: POINTER INTERPRETER EVENT (INDICATIONS) DESCRIPTION........................ 69

TABLE 2: POINTER INTERPRETER TRANSITION DESCRIPTION...................................... 71

TABLE 3: BYTE DESTUFFING........................................................................................... 78

TABLE 4: BYTE STUFFING................................................................................................ 88

TABLE 5: OBR MISMATCH MECHANISM ........................................................................... 91

TABLE 6: REGISTER MEMORY MAP.................................................................................. 99

TABLE 8: TFPO CHANNEL SELECTION.............................................................................111

TABLE 9: RECEIVE INITIATION LEVEL VALUES................................................................279

TABLE 10: TRANSMIT INITIATION LEVEL VALUES ............................................................294

TABLE 11: INTER PACKET GAPING VALUES.....................................................................295

PMC-Sierra, Inc.

PM5351 S/UNI-TETRA

TABLE 12: TEST MODE REGISTER MEMORY MAP...........................................................331

TABLE 13: INSTRUCTION REGISTER (LENGTH - 3 BITS) .................................................334

TABLE 14: IDENTIFICATION REGISTER (LENGTH – 32 BITS) ..........................................334

TABLE 15: S/UNI-TETRA BOUNDARY SCAN REGISTER (LENGTH – 155 BITS)................334

TABLE 16: S/UNI-QUAD BOUNDARY SCAN REGISTER (LENGTH – 114 BITS)...................338

TABLE 17: RECOMMENDED BERM SETTINGS................................................................359

TABLE 18 – SETTINGS FOR SONET OR SDH APPLICATIONS ...........................................387

TABLE 19: ABSOLUTE MAXIMUM RATINGS .....................................................................396

TABLE 20: D.C CHARACTERISTICS.................................................................................397

TABLE 21: MICROPROCESSOR INTERFACE READ ACCESS (FIGURE 41)......................400

TABLE 22: MICROPROCESSOR INTERFACE WRITE ACCESS (FIGURE 42).....................402

TABLE 23: RSTB TIMING (FIGURE 43) .............................................................................404

TABLE 24: TRANSMIT ATM SYSTEM INTERFACE TIMING (FIGURE 44)...........................405

TABLE 25: RECEIVE ATM SYSTEM INTERFACE TIMING (FIGURE 45) ..............................407

TABLE 26: TRANSMIT POS SYSTEM INTERFACE TIMING (FIGURE 46)...........................409

TABLE 27: RECEIVE POS SYSTEM INTERFACE TIMING (FIGURE 47) ............................. 411

TABLE 28: SECTION DCC TIMING (FIGURE 48) ...............................................................414

TABLE 29: LINE DCC TIMING (FIGURE 49).......................................................................415

TABLE 30: TRANSMIT AND RECEIVE FRAME PULSE TIMING (FIGURE 50).....................416

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TABLE 31: LINE SIDE TRANSMIT TIMIGN (TXC_OE=1 ONLY) (FIGURE 51) .....................417

TABLE 32: JTAG PORT INTERFACE (FIGURE 52) .............................................................417

TABLE 33: ORDERING INFORMATION .............................................................................420

TABLE 34: THERMAL INFORMATION ................................................................................420

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1 FEATURES

1.1 General

• Single chip QUAD ATM User-Network Interface operating at 155.52 Mbit/s.

• Implements the ATM Forum User Network Interface Specification and the

ATM physical layer for Broadband ISDN according to CCITT Recommendation I.432.

• Implements the Point-to-Point Protocol (PPP) over SONET/SDH specification

according to RFC 1619/1662 of the PPP Working Group of the Internet Engineering Task Force (IETF).

• Processes duplex 155.52 Mbit/s STS-3c (STM-1) data streams with on-chip

clock and data recovery and clock synthesis.

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• Exceeds Bellcore GR-253-CORE jitter tolerance and intrinsic jitter criteria.

• Exceeds Bellcore GR-253-CORE (1995 Issue) jitter transfer and phase

variation criteria.

• Provides control circuitry required to exceed Bellcore GR-253-CORE WAN

clocking requirements related to wander transfer, holdover and long term stability when using an external VCXO.

• Fully implements the ATM Forum’s Utopia Level 2 Specification with Multi-

PHY addressing and parity support.

• Implements the POS-PHY 16-bit System Interface for Packet over

SONET/SDH (POS) applications. This system interface is similar to Utopia Level 2, but adapted to packet transfer. Both byte-level and packet-level transfer modes are supported.

• Provides a standard 5 signal IEEE 1149.1 JTAG test port for boundary scan

board test purposes.

• Provides a generic 8-bit microprocessor bus interface for configuration,

control, and status monitoring.

• Low power 3.3V CMOS with PECL and TTL compatible inputs and

CMOS/TTL outputs, with 5V tolerance inputs (system side interface is 3.3V only).

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• Industrial temperature range (-40°C to +85°C).

• 304 pin Super BGA package.

1.2 The SONET Receiver

• Provides a serial interface at 155.52 Mbit/s.

• Recovers the clock and data.

• Frames to and de-scrambles the recovered stream.

• Detects signal degrade (SD) and signal fail (SF) threshold crossing alarms

based on received B2 errors.

• Captures and debounces the synchronization status (S1) byte in a readable

register.

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• Filters and captures the automatic protection switch channel (K1, K2) bytes in

readable registers and detects APS byte failure.

• Counts received section BIP-8 (B1) errors, received line BIP-24 (B2) errors,

line far end block errors (FEBE), received path BIP-8 (B3) errors and path far end block errors (FEBE).

• Detects loss of signal (LOS), out of frame (OOF), loss of frame (LOF), line

alarm indication signal (AIS), line remote defect indication (LRDI), loss of pointer (LOP), path alarm indication signal (AIS), path remote defect indication (PRDI) and path extended remote defect indicator (PERDI).

• Extracts the section and line data communication channels (D1-D3 and D4-

12) as selected in internal register banks and serializes them at 192 Kbit/s (D1-D3) and 576 Kbit/s (D4-D12) for optional external processing.

• Extracts the 16 or 64 byte section trace (J0) sequence and the 16 or 64 byte

path trace (J1) sequence into internal register banks.

• Interprets the received payload pointer (H1, H2) and extracts the STS-3c

(STM-1) synchronous payload envelope and path overhead.

• Provides individual divide by 8 recovered clocks (19.44 MHz) for each

channel.

• Provides individual 8KHz receive frame pulses for each channel.

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1.3 The Receive ATM Processor

• Extracts ATM cells from the received STS-3c (STM-1) synchronous payload

envelope using ATM cell delineation.

• Provides ATM cell payload de-scrambling.

• Performs header check sequence (HCS) error detection and correction, and

idle/unassigned cell filtering.

• Detects Out of Cell Delineation (OCD) and Loss of Cell Delineation (LCD).

• Counts number of received cells, idle cells, errored cells and dropped cells.

• Provides a synchronous 8-bit wide, four cell FIFO buffer.

1.4 The Receive POS Processor

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• Generic design that supports packet based link layer protocols, like PPP,

HDLC and Frame Relay.

• Performs self synchronous POS data de-scrambling on SPE payload (x43+1

polynomial).

• Performs flag sequence detection and terminates the received POS frames.

• Performs frame check sequence (FCS) validation. The POS processor

supports the validation of both CRC-CCITT and CRC-32 frame check sequences.

• Performs Control Escape de-stuffing.

• Checks for packet abort sequence.

• Checks for octet aligned packet lengths and for minimum and maximum

packet lengths. Automatically deletes short packets (software configurable), and marks those exceeding the maximum length as errored.

• Provides a synchronous 256 byte FIFO buffer accessed through a 16-bit data

bus on the POS-PHY System Interface.

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1.5 The SONET Transmitter

• Synthesizes the 155.52 MHz transmit clock from a 19.44 MHz reference.

• Provides a differential TTL serial interface (can be adapted to PECL levels) at

155.52 Mbit/s with both line rate data (TXD+/-) and clock (TXC+/-).

• Provides a single transmit frame pulse input across the four channels to align

the transport frames to a system reference.

• Provides a single transmit byte clock (divide by eight of the synthesized line

rate clock) to provide a timing reference for the transmit outputs.

• Optionally inserts register programmable APS (K1, K2) and synchronization

status (S1) bytes.

• Optionally inserts path alarm indication signal (PAIS), path remote defect

indication (PRDI), line alarm indication signal (LAIS) and line remote defect indication (LRDI).

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• Inserts path BIP-8 codes (B3), path far end block error (G1) indications, line

BIP-24 codes (B2), line far end block error ( M1) indications, and section BIP-8 codes (B1) to allow performance monitoring at the far end.

• Optionally inserts the section and line data communication channels (D1-D3

or D4-12) via a 192 kbit/s (D1-D3) and 576 kbit/s (D4-D12) serial stream.

• Optionally inserts the 16 or 64 byte section trace (J0) sequence and the 16 or

64 byte path trace (J1) sequence from internal register banks.

• Scrambles the transmitted STS-3c (STM-1) stream and inserts the framing

bytes (A1,A2).

• Inserts ATM cells or POS frames into the transmitted STS-3c (STM-1)

synchronous payload envelope.

1.6 The Transmit ATM Processor

• Provides idle/unassigned cell insertion.

• Provides HCS generation/insertion, and ATM cell payload scrambling.

• Counts number of transmitted and idle cells.

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• Provides a synchronous 8-bit wide, four cell FIFO buffer.

1.7 The Transmit POS Processor

• Generic design that supports any packet based link layer protocol, like PPP,

HDLC and Frame Relay.

• Performs self synchronous POS data scrambling (X43 + 1 polynomial).

• Encapsulates packets within a POS frame.

• Performs flag sequence insertion.

• Performs byte stuffing for transparency processing.

• Performs frame check sequence generation. The POS processor supports

the generation of both CRC-CCITT and CRC-32 frame check sequences.

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• Aborts packets under the direction of the host or when the FIFO underflows.

• Provides a synchronous 256 byte FIFO buffer accessed through the16-bit

data bus on the POS-PHY System Interface.

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2 APPLICATIONS

• WAN and edge ATM switches.

• LAN switches and hubs.

• Packet switches and hubs.

• Layer 3 switches.

• Multiservice switches (FR, ATM, IP, etc..).

• Gigabit and Terabit routers.

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3 REFERENCES

• Bell Communications Research - GR-253-CORE “SONET Transport Systems:

Common Generic Criteria”, Issue 2, December 1995.

• Bell Communications Research - GR-436-CORE “Digital Network

Synchronization Plan”, Issue 1 Revision 1, June 1996..

• ITU-T Recommendation G.703 - "Physical/Electrical Characteristics of

Hierarchical Digital Interfaces", 1991.

• ITU-T Recommendation G.704 - "General Aspects of Digital Transmission

Systems; Terminal Equipment - Synchronous Frame Structures Used At 1544, 6312, 2048, 8488 and 44 736 kbit/s Hierarchical Levels", July, 1995.

• ITU, Recommendation G.707 - "Network Node Interface For The

Synchronous Digital Hierarchy", 1996.

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• ITU Recommendation G781, “Structure of Recommendations on Equipment

for the Synchronous Design Hierarchy (SDH)”, January 1994.

• ITU, Recommendation G.783 - "Characteristics of Synchronous Digital

Hierarchy (SDH) Equipment Functional Blocks", 1996.

• ITU Recommendation I.432, “ISDN User Network Interfaces”, March 93.

• ATM Forum - ATM User-Network Interface Specification, V3.1, October, 1995.

• ATM Forum - “UTOPIA, An ATM PHY Interface Specification, Level 2, Version

1”, June, 1995.

• IETF Network Working Group – RFC-1619 “Point to Point Protocol (PPP) over

SONET/SDH Specification”, May 1994.

• IETF Network Working Group - RFC-1661 “The Point to Point Protocol

(PPP)”, July 1994.

• IETF Network Working Group - RFC-1662 “PPP in HDLC like framing”, July

1994.

• PMC-971147 “Saturn Compliant Interface for Packet over SONET Physical

Layer and Link Layer Devices, Level 2”, Issue 3, February 1998.

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• PMC-950820 “SONET/SDH Bit Error Threshold Monitoring Application Note”,

Issue 2, September 1998.

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4 DEFINITIONS

The following table defines the abbreviations for the S/UNI-TETRA.

AIS Alarm Indication Signal APS Automatic Protection Switching ASSP Application Specific Standard Product ATM Asynchronous Transfer Mode BER Bit Error Rate BIP Byte Interleaved Parity CBI Common Bus Interface

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CMOS Complementary Metal Oxide Semiconductor CRC Cyclic Redundancy Check CRSI CRU and Serial-In Parallel-Out CRU Clock Recovery Unit CSPI CSU and Parallel-In Serial-Out CSU Clock Synthesis Unit DCC Data Communication Channel ECL Emitter Controlled Logic ERDI Enhanced Remote Defect Indication ESD Electrostatic Discharge FCS Frame Check Sequence FEBE Far-End Block Error FIFO First-In First-Out GFC Generic Flow Control HCS Header Check Sequence HDLC High-level Data Link Layer LAN Local Area Network LCD Loss of Cell Delineation

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LOF Loss of Frame LOH Line Overhead LOP Loss of Pointer LOS Loss of Signal NC No Connect, indicates an unused pin NDF New Data Flag NNI Network-Network Interface ODL Optical Data Link OOF Out of Frame PECL Pseudo-ECL PLL Phase-Locked Loop

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POS Packet Over SONET PPP Point-to-Point Protocol PSL Path Signal Label PSLM Path Signal Label Mismatch RASE Receive APS, Synchronization Extractor and Bit

Error Monitor RDI Remote Defect Indication RLOP Receive Line Overhead Processor RPOP Receive Path Overhead Processor RSOP Receive Section Overhead Processor RXCP Receive ATM Cell Processor RXFP Receive POS Frame Processor SBGA Super Ball Grid Array SD Signal Degrade SDH Synchronous Digital Hierarchy SF Signal Fail SOH Section Overhead SONET Synchronous Optical Network SPE Synchronous Payload Envelope

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PMC PM5351-BI Datasheet

REVISION HISTORY

CONTENTS

LIST OF REGISTERS

LIST OF FIGURES

LIST OF TABLES

1 FEATURES

2 APPLICATIONS

3 REFERENCES

4 DEFINITIONS