Datasheet PM5351-BI Datasheet (PMC)

S/UNI-TETRA

SATURN USER NETWORK INTERFACE (155-TETRA)

DATASHEET PMC-1971240 ISSUE 7

PMC-Sierra, Inc.

PM5351

PM5351 S/UNI-TETRA

S/U NI-

155- TETRA

®

S/UNI-TETRA

SATURN

USER NETWORK INTERFACE

(155-TETRA)

PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000

DATA SHEET

ISSUE 7: FEBRUARY 2000

S/UNI-TETRA

SATURN USER NETWORK INTERFACE (155-TETRA)

DATASHEET PMC-1971240 ISSUE 7

REVISION HISTORY

PMC-Sierra, Inc.

PM5351 S/UNI-TETRA

Issue

Issue Date Details of Change

No.

7 February 2000

• Converted Bit 0 of register 0x0E to “Reserved"

• Added PERFCTRL register bit to register 0x0F

• Changed AVGPER bit description in register 0xDD.

PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000

S/UNI-TETRA

SATURN USER NETWORK INTERFACE (155-TETRA)

DATASHEET PMC-1971240 ISSUE 7

PMC-Sierra, Inc.

PM5351 S/UNI-TETRA

Issue

Issue Date Details of Change

No.

6 December,

1999

General update including:

• Page 17 – Signal Detect connection information

• Page 18 – Power info when using 155.52 transmit clocks

• Page 24,32 – Clarification on use of TENB and RENB

• Page 37 – PHY_OEN operation when the TETRA is

shared with other PHY devices on the same bus

• Page 38 – Device initialization information

• Page 40 – 220nf X7R 10% ceramatic capacitor used to

meet jitter transfer specifications

• Page 42 – Pull-up resistor on QAVD signals needed to avoid latchup during power-up

• Page 60, 214, 234 – Maximum packet length should be set no greater than 0xFFFE

• Page 66 – Packets are not aborted in overrun conditions

• Page 72 – RPA assertion information

• Page 86 – Revision ID bits incremented

• Page 105 – LANB_WAN bit added to select between jitter

transfer and non jitter transfer mode of operations

• Page 152 – Path far end receiver failure alarm persistence bit info updated

• Page 161 – Info on setting Path Signal Label for POS mode

• Page 176 – FIFO reset should be performed after FIFO overrrun

• Page 210 – Register bit added to select between abort sequence or flag insertion under a drop path AIS condition

• Page 216 – Maximum Receive Packet Available High Water Mark is 0xF0

PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000

S/UNI-TETRA

SATURN USER NETWORK INTERFACE (155-TETRA)

DATASHEET PMC-1971240 ISSUE 7

PMC-Sierra, Inc.

PM5351 S/UNI-TETRA

Issue

Issue Date Details of Change

No.

6 December

1999

• Page 229 – Info on setting Transmit Initiation Levels

• Page 232 – Setting of Transmit Packet Available High

Water Mark to avoid FIFO overrruns

• Page 250 – S1 debouncing information

• Page 268 – Updated boundary scan info

• Page 296 – Analog Power Supply Filtering info

• Page 298 – Updated Power Supply Sequencing info

• Page 303 – Setting the TETRA for SDH or SONET mode

• Page 308 – Updated POS Receive Synchronous FIFO

Timing Diagram

• Page 313 – Updated DC characteristic

• Page 336 – Updated air flow info

PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000

S/UNI-TETRA

SATURN USER NETWORK INTERFACE (155-TETRA)

DATASHEET PMC-1971240 ISSUE 7

LIST OF REGISTERS

REGISTER 0X00: S/UNI-TETRA MASTER RESET AND IDENTITY......................................109

REGISTER 0X01: S/UNI-TETRA MASTER CONFIGURATION............................................. 110

REGISTER 0X02: S/UNI-TETRA MASTER SYSTEM INTERFACE CONTROL ......................112

REGISTER 0X03: S/UNI-TETRA MASTER CLOCK MONITOR............................................. 114

REGISTER 0X04: S/UNI-TETRA MASTER INTERRUPT STATUS ........................................ 116

REGISTER 0X05: S/UNI-TETRA CHANNEL RESET AND MONITORING UPDATE ............... 118

REGISTER 0X06: S/UNI-TETRA CHANNEL CONFIGURATION ...........................................119

REGISTER 0X07: S/UNI-TETRA CHANNEL CONTROL.......................................................121

REGISTER 0X08: S/UNI-TETRA CHANNEL CONTROL EXTENSION..................................123

REGISTER 0X0A: S/UNI-TETRA CHANNEL INTERRUPT STATUS #1 .................................124

PMC-Sierra, Inc.

PM5351 S/UNI-TETRA

REGISTER 0X0B: S/UNI-TETRA CHANNEL INTERRUPT STATUS #2 .................................126

REGISTER 0X0C: CSPI (CLOCK SYNTHESIS) CONTROL AND STATUS............................128

REGISTER 0X0D: CSPI (CLOCK SYNTHESIS) RESERVED...............................................130

REGISTER 0X0E: CRSI (CLOCK RECOVERY) CONTROL AND STATUS ............................131

REGISTER 0X0F: CRSI (CLOCK RECOVERY) PLL MODE SELECT ...................................133

REGISTER 0X10: RSOP CONTROL/INTERRUPT ENABLE .................................................135

REGISTER 0X11: RSOP STATUS/INTERRUPT STATUS.....................................................137

REGISTER 0X12: RSOP SECTION BIP-8 LSB....................................................................139

REGISTER 0X13: RSOP SECTION BIP-8 MSB...................................................................139

REGISTER 0X14: TSOP CONTROL...................................................................................140

REGISTER 0X15: TSOP DIAGNOSTIC...............................................................................143

REGISTER 0X18: RLOP CONTROL/STATUS .....................................................................144

REGISTER 0X19: RLOP INTERRUPT ENABLE/INTERRUPT STATUS .................................147

REGISTER 0X1A: RLOP LINE BIP-24 LSB.........................................................................149

REGISTER 0X1B: RLOP LINE BIP-24................................................................................149

REGISTER 0X1C: RLOP LINE BIP-24 MSB ........................................................................150

REGISTER 0X1D: RLOP LINE FEBE LSB ..........................................................................151

REGISTER 0X1E: RLOP LINE FEBE ..................................................................................151

REGISTER 0X1F: RLOP LINE FEBE MSB..........................................................................152

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE vii

S/UNI-TETRA

SATURN USER NETWORK INTERFACE (155-TETRA)

DATASHEET PMC-1971240 ISSUE 7

REGISTER 0X20: TLOP CONTROL...................................................................................153

REGISTER 0X21: TLOP DIAGNOSTIC...............................................................................156

REGISTER 0X22: TLOP TRANSMIT K1..............................................................................157

REGISTER 0X23: TLOP TRANSMIT K2..............................................................................158

REGISTER 0X24: S/UNI-TETRA CHANNEL TRANSMIT SYNC. MESSAGE (S1)..................159

REGISTER 0X25: S/UNI-TETRA CHANNEL TRANSMIT J0/Z0.............................................160

REGISTER 0X28: SSTB CONTROL ...................................................................................161

REGISTER 0X29: SSTB SECTION TRACE IDENTIFIER STATUS .......................................163

REGISTER 0X2A: SSTB INDIRECT ADDRESS REGISTER.................................................165

REGISTER 0X2B: SSTB INDIRECT DATA REGISTER ........................................................166

REGISTER 0X30 (EXTD=0): RPOP STATUS/CONTROL .....................................................170

REGISTER 0X30 (EXTD=1): RPOP STATUS/CONTROL .....................................................172

PMC-Sierra, Inc.

PM5351 S/UNI-TETRA

REGISTER 0X31 (EXTD=0): RPOP INTERRUPT STATUS ..................................................174

REGISTER 0X31 (EXTD=1): RPOP INTERRUPT STATUS ..................................................176

REGISTER 0X32: RPOP POINTER INTERRUPT STATUS ...................................................177

REGISTER 0X33 (EXTD=0): RPOP INTERRUPT ENABLE..................................................179

REGISTER 0X33 (EXTD=1): RPOP INTERRUPT ENABLE .................................................181

REGISTER 0X34: RPOP POINTER INTERRUPT ENABLE ..................................................183

REGISTER 0X35: RPOP POINTER LSB .............................................................................185

REGISTER 0X36: RPOP POINTER MSB AND RDI FILTER CONTROL................................186

REGISTER 0X37: RPOP PATH SIGNAL LABEL ..................................................................188

REGISTER 0X38: RPOP PATH BIP-8 LSB ..........................................................................189

REGISTER 0X39: RPOP PATH BIP-8 MSB.........................................................................189

REGISTER 0X3A: RPOP PATH FEBE LSB.........................................................................190

REGISTER 0X3B: RPOP PATH FEBE MSB........................................................................190

REGISTER 0X3C: RPOP AUXILIARY RDI...........................................................................191

REGISTER 0X3D: RPOP ERROR EVENT CONTROL.........................................................193

REGISTER 0X40: TPOP CONTROL/DIAGNOSTIC.............................................................196

REGISTER 0X41: TPOP POINTER CONTROL ...................................................................199

REGISTER 0X43: TPOP CURRENT POINTER LSB............................................................203

REGISTER 0X44: TPOP CURRENT POINTER MSB...........................................................204

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE viii

S/UNI-TETRA

SATURN USER NETWORK INTERFACE (155-TETRA)

DATASHEET PMC-1971240 ISSUE 7

REGISTER 0X45: TPOP ARBITRARY POINTER LSB..........................................................205

REGISTER 0X46: TPOP ARBITRARY POINTER MSB.........................................................206

REGISTER 0X47: TPOP PATH TRACE...............................................................................207

REGISTER 0X48: TPOP PATH SIGNAL LABEL...................................................................208

REGISTER 0X49: TPOP PATH STATUS .............................................................................209

REGISTER 0X50: SPTB CONTROL ...................................................................................217

REGISTER 0X51: SPTB PATH TRACE IDENTIFIER STATUS..............................................219

REGISTER 0X52: SPTB INDIRECT ADDRESS REGISTER .................................................221

REGISTER 0X53: SPTB INDIRECT DATA REGISTER.........................................................222

REGISTER 0X54: SPTB EXPECTED PATH SIGNAL LABEL................................................223

REGISTER 0X55: SPTB PATH SIGNAL LABEL STATUS .....................................................224

REGISTER 0X60: RXCP_50 CONFIGURATION 1 ..............................................................226

PMC-Sierra, Inc.

PM5351 S/UNI-TETRA

REGISTER 0X61: RXCP_50 CONFIGURATION 2 ..............................................................228

REGISTER 0X62: RXCP_50 FIFO/UTOPIA CONTROL & CONFIG......................................231

REGISTER 0X63: RXCP_50 INTERRUPT ENABLES AND COUNTER STATUS ..................233

REGISTER 0X64: RXCP_50 STATUS/INTERRUPT STATUS ..............................................235

REGISTER 0X65: RXCP_50 LCD COUNT THRESHOLD (MSB).........................................237

REGISTER 0X66: RXCP_50 LCD COUNT THRESHOLD (LSB)..........................................237

REGISTER 0X67: RXCP_50 IDLE CELL HEADER PATTERN .............................................239

REGISTER 0X68: RXCP_50 IDLE CELL HEADER MASK...................................................240

REGISTER 0X69: RXCP_50 CORRECTED HCS ERROR COUNT......................................241

REGISTER 0X6A: RXCP_50 UNCORRECTED HCS ERROR COUNT.................................242

REGISTER 0X6B: RXCP_50 RECEIVE CELL COUNTER (LSB)..........................................243

REGISTER 0X6C: RXCP_50 RECEIVE CELL COUNTER...................................................243

REGISTER 0X6D: RXCP_50 RECEIVE CELL COUNTER (MSB) ........................................243

REGISTER 0X6E: RXCP_50 IDLE CELL COUNTER (LSB).................................................245

REGISTER 0X6F: RXCP_50 IDLE CELL COUNTER ..........................................................245

REGISTER 0X70: RXCP_50 IDLE CELL COUNTER (MSB)................................................246

REGISTER 0X80: TXCP_50 CONFIGURATION 1 ..............................................................247

REGISTER 0X81: TXCP_50 CONFIGURATION 2 ..............................................................249

REGISTER 0X82: TXCP_50 CELL COUNT STATUS/CONFIGURATION OPTIONS..............251

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ix

S/UNI-TETRA

SATURN USER NETWORK INTERFACE (155-TETRA)

DATASHEET PMC-1971240 ISSUE 7

REGISTER 0X83: TXCP_50 INTERRUPT ENABLE/STATUS ..............................................252

REGISTER 0X84: TXCP_50 IDLE CELL HEADER CONTROL ............................................254

REGISTER 0X85: TXCP_50 IDLE CELL PAYLOAD CONTROL...........................................255

REGISTER 0X86: TXCP_50 TRANSMIT CELL COUNT (LSB).............................................256

REGISTER 0X87: TXCP_50 TRANSMIT CELL COUNT......................................................256

REGISTER 0X88: TXCP_50 TRANSMIT CELL COUNT (MSB)............................................256

REGISTER 0X90: S/UNI-TETRA CHANNEL AUTO LINE RDI CONTROL.............................258

REGISTER 0X91: S/UNI-TETRA CHANNEL AUTO PATH RDI CONTROL............................260

REGISTER 0X92: S/UNI-TETRA CHANNEL AUTO ENHANCED PATH RDI CONTROL.........262

REGISTER 0X93: S/UNI-TETRA CHANNEL RECEIVE RDI AND ENHANCED RDI CONTROL

EXTENSIONS .......................................................................................................265

REGISTER 0X94: S/UNI-TETRA CHANNEL RECEIVE LINE AIS CONTROL.........................267

REGISTER 0X95: S/UNI-TETRA CHANNEL RECEIVE PATH AIS CONTROL........................269

PMC-Sierra, Inc.

PM5351 S/UNI-TETRA

REGISTER 0X96: S/UNI-TETRA CHANNEL RECEIVE ALARM CONTROL #1......................271

REGISTER 0X97: S/UNI-TETRA CHANNEL RECEIVE ALARM CONTROL #2......................271

REGISTER 0XA0: RXFP CONFIGURATION.......................................................................273

REGISTER 0XA1: RXFP CONFIGURATION/INTERRUPT ENABLES...................................275

REGISTER 0XA2: RXFP INTERRUPT STATUS ..................................................................276

REGISTER 0XA3: RXFP MINIMUM PACKET LENGTH........................................................277

REGISTER 0XA4: RXFP MAXIMUM PACKET LENGTH (LSB) .............................................278

REGISTER 0XA5: RXFP MAXIMUM PACKET LENGTH (MSB)............................................278

REGISTER 0XA6: RXFP RECEIVE INITIATION LEVEL .......................................................279

REGISTER 0XA7: RXFP RECEIVE PACKET AVAILABLE HIGH WATER MARK....................281

REGISTER 0XA8: RXFP RECEIVE BYTE COUNTER (LSB)................................................282

REGISTER 0XA9: RXFP RECEIVE BYTE COUNTER .........................................................282

REGISTER 0XAA: RXFP RECEIVE BYTE COUNTER .........................................................282

REGISTER 0XAB: RXFP RECEIVE BYTE COUNTER (MSB)...............................................283

REGISTER 0XAC: RXFP RECEIVE FRAME COUNTER (LSB) ............................................284

REGISTER 0XAD: RXFP RECEIVE FRAME COUNTER......................................................284

REGISTER 0XAE: RXFP RECEIVE FRAME COUNTER (MSB)............................................284

REGISTER 0XAF: RXFP RECEIVE ABORTED FRAME COUNTER (LSB) ............................286

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE x

S/UNI-TETRA

SATURN USER NETWORK INTERFACE (155-TETRA)

DATASHEET PMC-1971240 ISSUE 7

REGISTER 0XB0: RXFP RECEIVE ABORTED FRAME COUNTER (MSB)...........................286

REGISTER 0XB1: RXFP RECEIVE FCS ERROR FRAME COUNTER (LSB) ........................287

REGISTER 0XB2: RXFP RECEIVE FCS ERROR FRAME COUNTER (MSB)........................287

REGISTER 0XB3: RXFP RECEIVE MINIMUM LENGTH ERROR FRAME COUNTER (LSB)..288 REGISTER 0XB4: RXFP RECEIVE MINIMUM LENGTH ERROR FRAME COUNTER (MSB).288 REGISTER 0XB5: RXFP RECEIVE MAXIMUM LENGTH ERROR FRAME COUNTER (LSB).289 REGISTER 0XB6: RXFP RECEIVE MAXIMUM LENGTH ERROR FRAME COUNTER (MSB)289

REGISTER 0XC0: TXFP INTERRUPT ENABLE/STATUS .....................................................290

REGISTER 0XC1: TXFP CONFIGURATION........................................................................292

REGISTER 0XC2: TXFP CONTROL...................................................................................294

REGISTER 0XC3: TXFP TRANSMIT PACKET AVAILABLE LOW WATER MARK ...................296

REGISTER 0XC4: TXFP TRANSMIT PACKET AVAILABLE HIGH WATER MARK..................297

PMC-Sierra, Inc.

PM5351 S/UNI-TETRA

REGISTER 0XC5: TXFP TRANSMIT BYTE COUNTER (LSB)..............................................298

REGISTER 0XC6: TXFP TRANSMIT BYTE COUNTER .......................................................298

REGISTER 0XC7: TXFP TRANSMIT BYTE COUNTER .......................................................298

REGISTER 0XC8: TXFP TRANSMIT BYTE COUNTER (MSB) .............................................299

REGISTER 0XC9: TXFP TRANSMIT FRAME COUNTER (LSB)...........................................300

REGISTER 0XCA: TXFP TRANSMIT FRAME COUNTER ....................................................300

REGISTER 0XCB: TXFP TRANSMIT FRAME COUNTER (MSB)..........................................301

REGISTER 0XCC: TXFP TRANSMIT USER ABORTED FRAME COUNTER (LSB)...............302

REGISTER 0XCD: TXFP TRANSMIT USER ABORTED FRAME COUNTER (MSB)...............302

REGISTER 0XCE: TXFP TRANSMIT FIFO ERROR ABORTED FRAME COUNTER (LSB)....303

REGISTER 0XCF: TXFP TRANSMIT FIFO ERROR ABORTED FRAME COUNTER (MSB)....303

REGISTER 0XD0: WANS CONFIGURATION ......................................................................305

REGISTER 0XD1: WANS INTERRUPT & STATUS .............................................................306

REGISTER 0XD2: WANS PHASE WORD [7:0] ...................................................................307

REGISTER 0XD3: WANS PHASE WORD [15:8].................................................................307

REGISTER 0XD4: WANS PHASE WORD [23:16]...............................................................307

REGISTER 0XD5: WANS PHASE WORD [30:24]...............................................................308

REGISTER 0XD9: WANS REFERENCE PERIOD [7:0] .......................................................309

REGISTER 0XDA: WANS REFERENCE PERIOD [15:8].....................................................309

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE xi

S/UNI-TETRA

SATURN USER NETWORK INTERFACE (155-TETRA)

DATASHEET PMC-1971240 ISSUE 7

REGISTER 0XDB: WANS PHASE COUNTER PERIOD[7:0] ................................................310

REGISTER 0XDC: WANS PHASE COUNTER PERIOD[15:8] ..............................................310

REGISTER 0XDD: WANS PHASE AVERAGE PERIOD [3:0] ............................................... 311

REGISTER 0XE0: RASE INTERRUPT ENABLE ..................................................................312

REGISTER 0XE1: RASE INTERRUPT STATUS ..................................................................313

REGISTER 0XE2: RASE CONFIGURATION/CONTROL......................................................315

REGISTER 0XE3: RASE SF ACCUMULATION PERIOD......................................................318

REGISTER 0XE4: RASE SF ACCUMULATION PERIOD......................................................318

REGISTER 0XE5: RASE SF ACCUMULATION PERIOD......................................................319

REGISTER 0XE6: RASE SF SATURATION THRESHOLD ...................................................320

REGISTER 0XE7: RASE SF SATURATION THRESHOLD ...................................................320

REGISTER 0XE8: RASE SF DECLARING THRESHOLD .....................................................321

PMC-Sierra, Inc.

PM5351 S/UNI-TETRA

REGISTER 0XE9: RASE SF DECLARING THRESHOLD .....................................................321

REGISTER 0XEA: RASE SF CLEARING THRESHOLD .......................................................322

REGISTER 0XEB: RASE SF CLEARING THRESHOLD .......................................................322

REGISTER 0XEC: RASE SD ACCUMULATION PERIOD .....................................................323

REGISTER 0XED: RASE SD ACCUMULATION PERIOD .....................................................323

REGISTER 0XEE: RASE SD ACCUMULATION PERIOD.....................................................324

REGISTER 0XEF: RASE SD SATURATION THRESHOLD...................................................325

REGISTER 0XF0: RASE SD SATURATION THRESHOLD...................................................325

REGISTER 0XF1: RASE SD DECLARING THRESHOLD.....................................................326

REGISTER 0XF2: RASE SD DECLARING THRESHOLD.....................................................326

REGISTER 0XF3: RASE SD CLEARING THRESHOLD.......................................................327

REGISTER 0XF4: RASE SD CLEARING THRESHOLD.......................................................327

REGISTER 0XF5: RASE RECEIVE K1...............................................................................328

REGISTER 0XF6: RASE RECEIVE K2...............................................................................329

REGISTER 0XF7: RASE RECEIVE Z1/S1...........................................................................330

REGISTER 0X400: MASTER TEST....................................................................................332

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DATASHEET PMC-1971240 ISSUE 7

LIST OF FIGURES

FIGURE 1: TYPICAL STS-3C (STM-1) ATM SWITCH PORT APPLICATION .......................... 13

FIGURE 2: TYPICAL STS-3C (STM-1) PACKER OVER SONET/SDH (PPP) APPLICATION... 15

FIGURE 3: TYPICAL STS-3C (STM-1) JITTER TOLERANCE ............................................... 62

FIGURE 4: POINTER INTERPRETATION STATE DIAGRAM................................................ 69

FIGURE 5: CELL DELINEATION STATE DIAGRAM ............................................................. 74

FIGURE 6: HCS VERIFICATION STATE DIAGRAM ............................................................. 76

FIGURE 7: PACKET OVER SONET/SDH FRAME FORMAT................................................. 78

FIGURE 8: CRC DECODER............................................................................................... 79

FIGURE 9: PACKET OVER SONET/SDH FRAME FORMAT................................................. 87

FIGURE 10: CRC GENERATOR......................................................................................... 88

PMC-Sierra, Inc.

PM5351 S/UNI-TETRA

FIGURE 11 : PRE-MATURE RPA ASSERTION TIMING........................................................ 94

FIGURE 12. PHASE COMPARATOR BLOCK DIAGRAM ...................................................... 97

FIGURE 13. PHASE AVERAGER BLOCK DIAGRAM............................................................ 98

FIGURE 14: INPUT OBSERVATION CELL (IN_CELL).........................................................342

FIGURE 15: OUTPUT CELL (OUT_CELL)..........................................................................342

FIGURE 16: BIDIRECTIONAL CELL (IO_CELL).................................................................343

FIGURE 17: LAYOUT OF OUTPUT ENABLE AND BIDIRECTIONAL CELLS........................343

FIGURE 18: ATM MAPPING INTO THE STS-3C (STM-1) SPE .............................................344

FIGURE 19: POS MAPPING INTO THE STS-3C (STM-1) SPE ............................................346

FIGURE 20: STS-3C (STM-1) OVERHEAD........................................................................348

FIGURE 21: 16-BIT WIDE, 27 WORD ATM CELL STRUCTURE...........................................357

FIGURE 22: PACKET DATA STRUCTURE .........................................................................358

FIGURE 23: CONCEPTUAL CLOCKING STRUCTURE ......................................................360

FIGURE 24: LINE LOOPBACK MODE ...............................................................................363

FIGURE 25: SERIAL DIAGNOSTIC LOOPBACK MODE .....................................................365

FIGURE 26: PARALLEL DIAGNOSTIC LOOPBACK MODE ................................................367

FIGURE 27: BOUNDARY SCAN ARCHITECTURE.............................................................369

FIGURE 28: TAP CONTROLLER FINITE STATE MACHINE ................................................371

FIGURE 29: WAN MODE ANALOG POWER PIN PASSIVE-FILTERING WITH 3.3V SUPPLY 376

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FIGURE 30: WAN MODE ANALOG POWER FILTERS WITH 3.3V SUPPLY (1).....................379

FIGURE 31: LAN MODE ANALOG POWER FILTERS WITH 3.3V SUPPLY (2) ......................380

FIGURE 32: POWER SEQUENCING CIRCUIT..................................................................382

FIGURE 33: INTERFACING TO ECL OR PECL...................................................................383

FIGURE 34: CLOCK RECOVERY EXTERNAL COMPONENTS ............................................385

FIGURE 35: MULTI-PHY POLLING AND ADDRESSING TRANSMIT CELL INTERFACE .......388

FIGURE 36: MULTI-PHY POLLING AND ADDRESSING RECEIVE CELL INTERFACE.........389

FIGURE 37: TRANSMIT POS SYSTEM INTERFACE TIMING.............................................391

FIGURE 38: RECEIVE POS SYSTEM INTERFACE.............................................................393

FIGURE 39: TRANSPORT OVERHEAD DATA LINK CLOCK AND DATA EXTRACTION........394

FIGURE 40: TRANSPORT OVERHEAD DATA LINK CLOCK AND DATA INSERTION...........395

FIGURE 41: MICROPROCESSOR INTERFACE READ TIMING..........................................401

PMC-Sierra, Inc.

PM5351 S/UNI-TETRA

FIGURE 42: MICROPROCESSOR INTERFACE WRITE TIMING.........................................403

FIGURE 43: RSTB TIMING DIAGRAM ...............................................................................404

FIGURE 44: TRANSMIT ATM SYSTEM INTERFACE TIMING DIAGRAM.............................406

FIGURE 45: RECEIVE ATM SYSTEM INTERFACE TIMING DIAGRAM ...............................408

FIGURE 46: TRANSMIT POS SYSTEM INTERFACE TIMING.............................................410

FIGURE 47: RECEIVE POS SYSTEM INTERFACE TIMING...............................................413

FIGURE 48: SECTION DCC TIMING DIAGRAM .................................................................414

FIGURE 49: LINE DCC TIMING DIAGRAM ........................................................................415

FIGURE 50: TRANSMIT AND RECEIVE FRAME PULSES ..................................................416

FIGURE 51: LINE SIDE TRANSMIT TIMING DIAGRAM (TXC_OE=1)..................................417

FIGURE 52: JTAG PORT INTERFACE TIMING ..................................................................418

FIGURE 53:- MECHANICAL DRAWING 304 PIN SUPER BALL GRID ARRAY (SBGA) ..........422

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DATASHEET PMC-1971240 ISSUE 7

LIST OF TABLES

TABLE 1: POINTER INTERPRETER EVENT (INDICATIONS) DESCRIPTION........................ 69

TABLE 2: POINTER INTERPRETER TRANSITION DESCRIPTION...................................... 71

TABLE 3: BYTE DESTUFFING........................................................................................... 78

TABLE 4: BYTE STUFFING................................................................................................ 88

TABLE 5: OBR MISMATCH MECHANISM ........................................................................... 91

TABLE 6: REGISTER MEMORY MAP.................................................................................. 99

TABLE 8: TFPO CHANNEL SELECTION.............................................................................111

TABLE 9: RECEIVE INITIATION LEVEL VALUES................................................................279

TABLE 10: TRANSMIT INITIATION LEVEL VALUES ............................................................294

TABLE 11: INTER PACKET GAPING VALUES.....................................................................295

PMC-Sierra, Inc.

PM5351 S/UNI-TETRA

TABLE 12: TEST MODE REGISTER MEMORY MAP...........................................................331

TABLE 13: INSTRUCTION REGISTER (LENGTH - 3 BITS) .................................................334

TABLE 14: IDENTIFICATION REGISTER (LENGTH – 32 BITS) ..........................................334

TABLE 15: S/UNI-TETRA BOUNDARY SCAN REGISTER (LENGTH – 155 BITS)................334

TABLE 16: S/UNI-QUAD BOUNDARY SCAN REGISTER (LENGTH – 114 BITS)...................338

TABLE 17: RECOMMENDED BERM SETTINGS................................................................359

TABLE 18 – SETTINGS FOR SONET OR SDH APPLICATIONS ...........................................387

TABLE 19: ABSOLUTE MAXIMUM RATINGS .....................................................................396

TABLE 20: D.C CHARACTERISTICS.................................................................................397

TABLE 21: MICROPROCESSOR INTERFACE READ ACCESS (FIGURE 41)......................400

TABLE 22: MICROPROCESSOR INTERFACE WRITE ACCESS (FIGURE 42).....................402

TABLE 23: RSTB TIMING (FIGURE 43) .............................................................................404

TABLE 24: TRANSMIT ATM SYSTEM INTERFACE TIMING (FIGURE 44)...........................405

TABLE 25: RECEIVE ATM SYSTEM INTERFACE TIMING (FIGURE 45) ..............................407

TABLE 26: TRANSMIT POS SYSTEM INTERFACE TIMING (FIGURE 46)...........................409

TABLE 27: RECEIVE POS SYSTEM INTERFACE TIMING (FIGURE 47) ............................. 411

TABLE 28: SECTION DCC TIMING (FIGURE 48) ...............................................................414

TABLE 29: LINE DCC TIMING (FIGURE 49).......................................................................415

TABLE 30: TRANSMIT AND RECEIVE FRAME PULSE TIMING (FIGURE 50).....................416

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DATASHEET PMC-1971240 ISSUE 7

TABLE 31: LINE SIDE TRANSMIT TIMIGN (TXC_OE=1 ONLY) (FIGURE 51) .....................417

TABLE 32: JTAG PORT INTERFACE (FIGURE 52) .............................................................417

TABLE 33: ORDERING INFORMATION .............................................................................420

TABLE 34: THERMAL INFORMATION ................................................................................420

PMC-Sierra, Inc.

PM5351 S/UNI-TETRA

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE xvi

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DATASHEET PMC-1971240 ISSUE 7

1 FEATURES

1.1 General

• Single chip QUAD ATM User-Network Interface operating at 155.52 Mbit/s.

• Implements the ATM Forum User Network Interface Specification and the

ATM physical layer for Broadband ISDN according to CCITT Recommendation I.432.

• Implements the Point-to-Point Protocol (PPP) over SONET/SDH specification

according to RFC 1619/1662 of the PPP Working Group of the Internet Engineering Task Force (IETF).

• Processes duplex 155.52 Mbit/s STS-3c (STM-1) data streams with on-chip

clock and data recovery and clock synthesis.

PMC-Sierra, Inc.

PM5351 S/UNI-TETRA

• Exceeds Bellcore GR-253-CORE jitter tolerance and intrinsic jitter criteria.

• Exceeds Bellcore GR-253-CORE (1995 Issue) jitter transfer and phase

variation criteria.

• Provides control circuitry required to exceed Bellcore GR-253-CORE WAN

clocking requirements related to wander transfer, holdover and long term stability when using an external VCXO.

• Fully implements the ATM Forum’s Utopia Level 2 Specification with Multi-

PHY addressing and parity support.

• Implements the POS-PHY 16-bit System Interface for Packet over

SONET/SDH (POS) applications. This system interface is similar to Utopia Level 2, but adapted to packet transfer. Both byte-level and packet-level transfer modes are supported.

• Provides a standard 5 signal IEEE 1149.1 JTAG test port for boundary scan

board test purposes.

• Provides a generic 8-bit microprocessor bus interface for configuration,

control, and status monitoring.

• Low power 3.3V CMOS with PECL and TTL compatible inputs and

CMOS/TTL outputs, with 5V tolerance inputs (system side interface is 3.3V only).

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 1

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DATASHEET PMC-1971240 ISSUE 7

• Industrial temperature range (-40°C to +85°C).

• 304 pin Super BGA package.

1.2 The SONET Receiver

• Provides a serial interface at 155.52 Mbit/s.

• Recovers the clock and data.

• Frames to and de-scrambles the recovered stream.

• Detects signal degrade (SD) and signal fail (SF) threshold crossing alarms

based on received B2 errors.

• Captures and debounces the synchronization status (S1) byte in a readable

register.

PMC-Sierra, Inc.

PM5351 S/UNI-TETRA

• Filters and captures the automatic protection switch channel (K1, K2) bytes in

readable registers and detects APS byte failure.

• Counts received section BIP-8 (B1) errors, received line BIP-24 (B2) errors,

line far end block errors (FEBE), received path BIP-8 (B3) errors and path far end block errors (FEBE).

• Detects loss of signal (LOS), out of frame (OOF), loss of frame (LOF), line

alarm indication signal (AIS), line remote defect indication (LRDI), loss of pointer (LOP), path alarm indication signal (AIS), path remote defect indication (PRDI) and path extended remote defect indicator (PERDI).

• Extracts the section and line data communication channels (D1-D3 and D4-

12) as selected in internal register banks and serializes them at 192 Kbit/s (D1-D3) and 576 Kbit/s (D4-D12) for optional external processing.

• Extracts the 16 or 64 byte section trace (J0) sequence and the 16 or 64 byte

path trace (J1) sequence into internal register banks.

• Interprets the received payload pointer (H1, H2) and extracts the STS-3c

(STM-1) synchronous payload envelope and path overhead.

• Provides individual divide by 8 recovered clocks (19.44 MHz) for each

channel.

• Provides individual 8KHz receive frame pulses for each channel.

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1.3 The Receive ATM Processor

• Extracts ATM cells from the received STS-3c (STM-1) synchronous payload

envelope using ATM cell delineation.

• Provides ATM cell payload de-scrambling.

• Performs header check sequence (HCS) error detection and correction, and

idle/unassigned cell filtering.

• Detects Out of Cell Delineation (OCD) and Loss of Cell Delineation (LCD).

• Counts number of received cells, idle cells, errored cells and dropped cells.

• Provides a synchronous 8-bit wide, four cell FIFO buffer.

1.4 The Receive POS Processor

PMC-Sierra, Inc.

PM5351 S/UNI-TETRA

• Generic design that supports packet based link layer protocols, like PPP,

HDLC and Frame Relay.

• Performs self synchronous POS data de-scrambling on SPE payload (x43+1

polynomial).

• Performs flag sequence detection and terminates the received POS frames.

• Performs frame check sequence (FCS) validation. The POS processor

supports the validation of both CRC-CCITT and CRC-32 frame check sequences.

• Performs Control Escape de-stuffing.

• Checks for packet abort sequence.

• Checks for octet aligned packet lengths and for minimum and maximum

packet lengths. Automatically deletes short packets (software configurable), and marks those exceeding the maximum length as errored.

• Provides a synchronous 256 byte FIFO buffer accessed through a 16-bit data

bus on the POS-PHY System Interface.

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1.5 The SONET Transmitter

• Synthesizes the 155.52 MHz transmit clock from a 19.44 MHz reference.

• Provides a differential TTL serial interface (can be adapted to PECL levels) at

155.52 Mbit/s with both line rate data (TXD+/-) and clock (TXC+/-).

• Provides a single transmit frame pulse input across the four channels to align

the transport frames to a system reference.

• Provides a single transmit byte clock (divide by eight of the synthesized line

rate clock) to provide a timing reference for the transmit outputs.

• Optionally inserts register programmable APS (K1, K2) and synchronization

status (S1) bytes.

• Optionally inserts path alarm indication signal (PAIS), path remote defect

indication (PRDI), line alarm indication signal (LAIS) and line remote defect indication (LRDI).

PMC-Sierra, Inc.

PM5351 S/UNI-TETRA

• Inserts path BIP-8 codes (B3), path far end block error (G1) indications, line

BIP-24 codes (B2), line far end block error ( M1) indications, and section BIP-8 codes (B1) to allow performance monitoring at the far end.

• Optionally inserts the section and line data communication channels (D1-D3

or D4-12) via a 192 kbit/s (D1-D3) and 576 kbit/s (D4-D12) serial stream.

• Optionally inserts the 16 or 64 byte section trace (J0) sequence and the 16 or

64 byte path trace (J1) sequence from internal register banks.

• Scrambles the transmitted STS-3c (STM-1) stream and inserts the framing

bytes (A1,A2).

• Inserts ATM cells or POS frames into the transmitted STS-3c (STM-1)

synchronous payload envelope.

1.6 The Transmit ATM Processor

• Provides idle/unassigned cell insertion.

• Provides HCS generation/insertion, and ATM cell payload scrambling.

• Counts number of transmitted and idle cells.

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• Provides a synchronous 8-bit wide, four cell FIFO buffer.

1.7 The Transmit POS Processor

• Generic design that supports any packet based link layer protocol, like PPP,

HDLC and Frame Relay.

• Performs self synchronous POS data scrambling (X43 + 1 polynomial).

• Encapsulates packets within a POS frame.

• Performs flag sequence insertion.

• Performs byte stuffing for transparency processing.

• Performs frame check sequence generation. The POS processor supports

the generation of both CRC-CCITT and CRC-32 frame check sequences.

PMC-Sierra, Inc.

PM5351 S/UNI-TETRA

• Aborts packets under the direction of the host or when the FIFO underflows.

• Provides a synchronous 256 byte FIFO buffer accessed through the16-bit

data bus on the POS-PHY System Interface.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 5

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2 APPLICATIONS

• WAN and edge ATM switches.

• LAN switches and hubs.

• Packet switches and hubs.

• Layer 3 switches.

• Multiservice switches (FR, ATM, IP, etc..).

• Gigabit and Terabit routers.

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PM5351 S/UNI-TETRA

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3 REFERENCES

• Bell Communications Research - GR-253-CORE “SONET Transport Systems:

Common Generic Criteria”, Issue 2, December 1995.

• Bell Communications Research - GR-436-CORE “Digital Network

Synchronization Plan”, Issue 1 Revision 1, June 1996..

• ITU-T Recommendation G.703 - "Physical/Electrical Characteristics of

Hierarchical Digital Interfaces", 1991.

• ITU-T Recommendation G.704 - "General Aspects of Digital Transmission

Systems; Terminal Equipment - Synchronous Frame Structures Used At 1544, 6312, 2048, 8488 and 44 736 kbit/s Hierarchical Levels", July, 1995.

• ITU, Recommendation G.707 - "Network Node Interface For The

Synchronous Digital Hierarchy", 1996.

PMC-Sierra, Inc.

PM5351 S/UNI-TETRA

• ITU Recommendation G781, “Structure of Recommendations on Equipment

for the Synchronous Design Hierarchy (SDH)”, January 1994.

• ITU, Recommendation G.783 - "Characteristics of Synchronous Digital

Hierarchy (SDH) Equipment Functional Blocks", 1996.

• ITU Recommendation I.432, “ISDN User Network Interfaces”, March 93.

• ATM Forum - ATM User-Network Interface Specification, V3.1, October, 1995.

• ATM Forum - “UTOPIA, An ATM PHY Interface Specification, Level 2, Version

1”, June, 1995.

• IETF Network Working Group – RFC-1619 “Point to Point Protocol (PPP) over

SONET/SDH Specification”, May 1994.

• IETF Network Working Group - RFC-1661 “The Point to Point Protocol

(PPP)”, July 1994.

• IETF Network Working Group - RFC-1662 “PPP in HDLC like framing”, July

1994.

• PMC-971147 “Saturn Compliant Interface for Packet over SONET Physical

Layer and Link Layer Devices, Level 2”, Issue 3, February 1998.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 7

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DATASHEET PMC-1971240 ISSUE 7

• PMC-950820 “SONET/SDH Bit Error Threshold Monitoring Application Note”,

Issue 2, September 1998.

PMC-Sierra, Inc.

PM5351 S/UNI-TETRA

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 8

S/UNI-TETRA

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DATASHEET PMC-1971240 ISSUE 7

4 DEFINITIONS

The following table defines the abbreviations for the S/UNI-TETRA.

AIS Alarm Indication Signal APS Automatic Protection Switching ASSP Application Specific Standard Product ATM Asynchronous Transfer Mode BER Bit Error Rate BIP Byte Interleaved Parity CBI Common Bus Interface

PMC-Sierra, Inc.

PM5351 S/UNI-TETRA

CMOS Complementary Metal Oxide Semiconductor CRC Cyclic Redundancy Check CRSI CRU and Serial-In Parallel-Out CRU Clock Recovery Unit CSPI CSU and Parallel-In Serial-Out CSU Clock Synthesis Unit DCC Data Communication Channel ECL Emitter Controlled Logic ERDI Enhanced Remote Defect Indication ESD Electrostatic Discharge FCS Frame Check Sequence FEBE Far-End Block Error FIFO First-In First-Out GFC Generic Flow Control HCS Header Check Sequence HDLC High-level Data Link Layer LAN Local Area Network LCD Loss of Cell Delineation

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DATASHEET PMC-1971240 ISSUE 7

LOF Loss of Frame LOH Line Overhead LOP Loss of Pointer LOS Loss of Signal NC No Connect, indicates an unused pin NDF New Data Flag NNI Network-Network Interface ODL Optical Data Link OOF Out of Frame PECL Pseudo-ECL PLL Phase-Locked Loop

PMC-Sierra, Inc.

PM5351 S/UNI-TETRA

POS Packet Over SONET PPP Point-to-Point Protocol PSL Path Signal Label PSLM Path Signal Label Mismatch RASE Receive APS, Synchronization Extractor and Bit

Error Monitor RDI Remote Defect Indication RLOP Receive Line Overhead Processor RPOP Receive Path Overhead Processor RSOP Receive Section Overhead Processor RXCP Receive ATM Cell Processor RXFP Receive POS Frame Processor SBGA Super Ball Grid Array SD Signal Degrade SDH Synchronous Digital Hierarchy SF Signal Fail SOH Section Overhead SONET Synchronous Optical Network SPE Synchronous Payload Envelope

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DATASHEET PMC-1971240 ISSUE 7

SPTB SONET/SDH Path Trace Buffer SSTB SONET/SDH Section Trace Buffer TIM Trace Identifier Mismatch TIU Trace Identifier Unstable TLOP Transmit Line Overhead Processor TOH Transport Overhead TPOP Transmit Path Overhead Processor TSB Telecom System Block TSOP Transmit Section Overhead Processor TXCP Transmit ATM Cell Processor TXFP Transmit POS Frame Processor

PMC-Sierra, Inc.

PM5351 S/UNI-TETRA

UI Unit Interval UNI User-Network Interface VCI Virtual Connection Indicator VCXO Voltage Controlled Oscillator VPI Virtual Path Indicator WAN Wide Area Network XOR Exclusive OR logic operator

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 11

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SATURN USER NETWORK INTERFACE (155-TETRA)

DATASHEET PMC-1971240 ISSUE 7

5 APPLICATION EXAMPLES

The PM5351 S/UNI-TETRA is intended for use in equipment implementing Asynchronous Transfer Mode (ATM) User-Network Interfaces (UNI), ATM Network-Network Interfaces (NNI), as well as Packet over SONET/SDH (POS) interfaces. The POS interface can be used to support several packet based protocols, including the Point-to-Point Protocol (PPP). The S/UNI-TETRA may find application at either end of switch-to-switch links or switch-to-terminal links, both in public network (WAN) and private network (LAN) situations. The S/UNITETRA provides a comprehensive feature set as well as provides circuitry to enable full compliance to WAN synchronization requirements. The S/UNI-TETRA performs the mapping of either ATM cells or POS frames into the SONET/SDH STS-3c (STM-1) synchronous payload envelope (SPE) and processes applicable SONET/SDH section, line and path overhead.

In a typical STS-3c (STM-1) ATM application, the S/UNI-TETRA performs clock and data recovery for the receive direction and clock synthesis for the transmit direction of the line interface. On the system side, the S/UNI-TETRA interfaces directly with ATM layer processors and switching or adaptation functions using a Utopia Level 2 compliant synchronous FIFO style interface. The initial configuration and ongoing control and monitoring of the S/UNI-TETRA are normally provided via a generic microprocessor interface. This application is shown in Figure 1.

PMC-Sierra, Inc.

PM5351 S/UNI-TETRA

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DATASHEET PMC-1971240 ISSUE 7

Figure 1: Typical STS-3c (STM-1) ATM Switch Port Application

Utopia Level 2

ATM Layer Device

Tx Clk

TxEnb

TxAddr<4 :0>

TxCla v

TxSOC

TxPrty

TxD ata<15:0>

RxClk

RxEnb

RxAddr<4:0>

RxClav

R xSOC

RxPrty

RxData<15:0>

Interface

PMC-Sierra, Inc.

PM5351

S/UNI-155-TETRA

TFCL K TENB

TAD R[4:0] TCA

TSOC TPRTY TD AT[15:0]

RFCLK RENB

RADR[4:0] RC A

RSOC RPR TY

RDAT[15:0]

RXD1+/SD1

TXD1 +/-

RXD2+/SD2

TXD2 +/-

RXD3+/SD3

TXD3 +/-

RXD4+/SD4

TXD4 +/-

PM5351 S/UNI-TETRA

Optical

Transceiver

Optical

Transceiver

Optical

Transceiver

Optical

Transceiver

In a typical Packet over SONET/SDH application, using the PPP protocol, the S/UNI-TETRA performs clock and data recovery for the receive direction and clock synthesis for the transmit direction of the line interface. On the system side, the S/UNI-TETRA interfaces directly with a PPP link layer processors using a 256 byte synchronous FIFO interface over which packets are transferred. The initial configuration and ongoing control and monitoring of the S/UNI-TETRA are normally provided via a generic microprocessor interface. This application is shown in Figure 2.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 13

S/UNI-TETRA

SATURN USER NETWORK INTERFACE (155-TETRA)

DATASHEET PMC-1971240 ISSUE 7

Figure 2: Typical STS-3c (STM-1) Packer over SONET/SDH (PPP)

PMC-Sierra, Inc.

Application

PM5351 S/UNI-TETRA

Link Laye r Device

TFCLK

TENB

TA DR[4:0]

S TPA

DTPA[ 4:1]

TS OP TSOP

TP RTY

TDAT[ 15:0]

TMOD TMOD

TE OP TEOP TE RR TERR

RFCLK

RENB

RA DR[4:0] DRPA[4:1]

RV AL RV AL

RS OP

RPRTY

RDAT[ 15:0]

RMOD RMOD

RE OP REOP RE RR

PM5351

S/UNI-155-TETRA

TFCLK TENB

TA DR[4:0]

S TPA DTP A[4:1]

TP RTY

TDAT[ 15:0]

RFCLK

RENB RADR[4:0]

DRPA[ 4:1]

RSOP RP RTY

RDA T[15:0]

RERR

RXD1+/SD1

TX D1+/-

RXD2+/SD2

TX D2+/-

RXD3+/SD3

TX D3+/-

RXD4+/SD4

TX D4+/-

Optical

Transceiver

Optical

Transceiver

Optical

Transceiver

Optical

Transceiver

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S/UNI-TETRA

SATURN USER NETWORK INTERFACE (155-TETRA)

TXD1-4 -

SD1-4

RXD1-4

TXD1-4 +

REFCLK

CP1-4

CN1-4

TXC1-4 -

TXC1-4 +

DATASHEET PMC-1971240 ISSUE 7

6 BLOCK DIAGRAM

PMC-Sierra, Inc.

PM5351 S/UNI-TETRA

]

RENB

Rx

Buffer

]

RDAT[15:0

RSOC/RSOP

RPRTY

RCA/PRPA

rame

Processor

POS F

Rx

Path O/H

Rx

Line O/H

Rx

Section O/H

I/F

Rx Line

REOP

RMOD

RERR

RVAL

DRCA[4:1]/DRP[4:1

or ess

F I/

proc cro

Mi

Rx

ATM Cell

processor

Processor

Rx

APS,

Sync,

BERM

Processor

Line

DCC

Extract

DCC

Extract

Section

Processor

INTB

RSTB RDB WRB CSB ALE A[10:0] D[7:0]

RLDCLK1-4 RLD1-4

RSD1-4

RCLK1-4

RFPO1-4

RALRM1-4

DTPA[4:1]

OP

:0]

STPA

TRSTB

TCK

TMS

TDI

TDO

TLDCLK1-4

TLD1-4

TSDCLK1-4 RSDCLK1-4

TSD1-4

TCLK

TFPO

TFPI

st

JTAG Te

Access Port

TERR

TMOD

Line

DCC

Section

TDAT[15

DTCA[4:1]/

TEOP

Tx

ATM Cell

Insert

TSOC/TS

TPRTY

Utopia / POS-PHY

Processor

Tx

OEN

/PTPA

RFCLK RADR[4:0]

PHY_

TCA

TFCLKTENB

TADR[4:0]

System Interface

rame

Tx

Processor

POS F

Path

Processor

I/F

Trace

Section

WAN

Synchro-

nization

Path O/H

Line O/H

Section O/H

Tx Line

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 15

ATB0-3

+

-

S/UNI-TETRA

SATURN USER NETWORK INTERFACE (155-TETRA)

DATASHEET PMC-1971240 ISSUE 7

7 DESCRIPTION

The PM5351 S/UNI-TETRA SATURN User Network Interface is a monolithic integrated circuit that implements four channel SONET/SDH processing, ATM mapping and Packet over SONET/SDH mapping functions at the STS-3c (STM-

1) 155.52 Mbit/s rate. The S/UNI-TETRA receives SONET/SDH streams using a bit serial interface,

recovers the clock and data and processes section, line, and path overhead. It performs framing (A1, A2), de-scrambling, detects alarm conditions, and monitors section, line, and path bit interleaved parity (B1, B2, B3), accumulating error counts at each level for performance monitoring purposes. Line and path far end block error indications (M1, G1) are also accumulated. The S/UNI-TETRA interprets the received payload pointers (H1, H2) and extracts the synchronous payload envelope which carries the received ATM cell or POS packet payload.

PMC-Sierra, Inc.

PM5351 S/UNI-TETRA

When used to implement an ATM UNI or NNI, the S/UNI-TETRA frames to the ATM payload using cell delineation. HCS error correction is provided. Idle/unassigned cells may be dropped according to a programmable filter. Cells are also dropped upon detection of an uncorrectable header check sequence error. The ATM cell payloads are descrambled. The ATM cells that are passed are written to a four cell FIFO buffer. The received cells are read from the FIFO using a 16-bit wide Utopia level 2 compliant datapath interface. Counts of received ATM cell headers that are errored and uncorrectable and also those that are errored and correctable are accumulated independently for performance monitoring purposes.

When used to implement packet transmission over a SONET/SDH link, the S/UNI-TETRA extracts Packet over SONET/SDH (POS) frames from the SONET/SDH synchronous payload envelope. Frames are verified for correct construction and size. The Control Escape characters are removed. The error check sequence is optionally verified for correctness and the extracted packets are placed in a receive FIFO. The received packets are read from the FIFO through the system side interface. Valid and errored packet counts are provided for performance monitoring. The S/UNI-TETRA Packet over SONET/SDH implementation is flexible enough to support several link layer protocols, including HDLC, PPP and Frame Relay.

The S/UNI-TETRA transmits SONET/SDH streams using a bit serial interface and formats section, line, and path overhead appropriately. It synthesizes the transmit clock from a lower frequency reference and performs framing pattern insertion (A1, A2), scrambling, alarm signal insertion, and creates section, line, and path bit interleaved parity (B1, B2, B3) as required to allow performance

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DATASHEET PMC-1971240 ISSUE 7

monitoring at the far end. Line and path far end block error indications ( M1, G1) are also inserted. The S/UNI-TETRA generates the payload pointer (H1, H2) and inserts the synchronous payload envelope which carries the ATM cell or POS frame payload. Line and Section DCC ports are available for direct insertion and extraction of DCC data. The S/UNI-TETRA also supports the insertion of a large variety of errors into the transmit stream, such as framing pattern errors, bit interleaved parity errors, and illegal pointers, which are useful for system diagnostics and tester applications.

When used to implement an ATM UNI or NNI, ATM cells are written to an internal four cell FIFO using a 16-bit wide Utopia Level 2 datapath interface. Idle/unassigned cells are automatically inserted when the internal FIFO contains less than one cell. The S/UNI-TETRA provides generation of the header check sequence and scrambles the payload of the ATM cells. Each of these transmit ATM cell processing functions can be enabled or bypassed.

When used to implement a Packet over SONET/SDH link, the S/UNI-TETRA inserts POS frames into the SONET/SDH synchronous payload envelope. Packets to be transmitted are written into a 256-byte FIFO through the POS-PHY System Interface. POS Frames are built by inserting the flags, Control Escape characters and the FCS fields. Either the CRC-CCITT or CRC-32 can be computed and added to the frame. Several counters are provided for performance monitoring.

PMC-Sierra, Inc.

PM5351 S/UNI-TETRA

No line rate clocks are required directly by the S/UNI-TETRA as it synthesizes the transmit clock and recovers the receive clock using a 19.44 MHz reference clock. The S/UNI-TETRA outputs a differential TTL (externally coverted to PECL) line data (TXD+/-). Optionally, the S/UNI-TETRA can also output a differential TTL (externally converted to PECL) transmit line rate clock (TXC+/-). The S/UNITETRA also provides a WAN Synchronization controller that can be used to control an external VCXO in order to fully meet Bellcore GR-253-CORE jitter, wander, holdover and stability requirements.

The S/UNI-TETRA is configured, controlled and monitored via a generic 8-bit microprocessor bus interface. The S/UNI-TETRA also provides a standard 5 signal IEEE 1149.1 JTAG test port for boundary scan board test purposes.

The S/UNI-TETRA is implemented in low power, +3.3 Volt, CMOS technology. It has TTL and pseudo-ECL (PECL) compatible inputs and TTL/CMOS compatible outputs and is packaged in a 304 pin SBGA package.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 17

PMC-Sierra, Inc.

SATURN USER NETWORK INTERFACE (155-TETRA)

DTCA[4] /

DTCA[1] /

DRCA[4] /

DRCA[1] /

PM5351 S/UNI-TETRA

S/UNI-TETRA DATASHEET

PMC-1971240 ISSUE 7

8 PIN DIAGRAM

The S/UNI-TETRA is available in a 304 pin SBGA package having a body size of 31 mm by 31 mm and a ball pitch of 1.27 mm.

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

A VDD VSS TDAT[12] TDAT[15] PHY_OEN VSS D[2] VSS A[0] A[3] A[7] VSS A[10] WRB TDO VSS N/C VSS N/C RAVD1_B RAVS1_B VSS VDD

B VSS VDD VSS TDAT[13] STPA N/C D[1] D[4] D[6] A[2] A[6] A[9] CSB RSTB TMS TCK N/C N/C QAVS_5 C1+ VSS VDD VSS

C TDAT[7] VSS VDD TDAT[10] TDAT[14] TEOP BIAS D[3] D[5] A[1] A[5] A[8] ALE INTB TRSTB N/C N/C QAVD_5 C1- RAVD1_C VDD VSS TXD1P

D TDAT[4] TDAT[6] TDAT[9] VDD TDAT[11] VDD TERR D[0] VDD D[7] A[4] VDD RDB TDI VDD N/C N/C VDD RAVS1_C VDD TXC1P TXD1N RX1-

E TDAT[0] TDAT[3] TDAT[5] TDAT[8] TXC1N SD1 RX1+ TXD2P

F VSS TMOD TDAT[2] VDD VDD RAVS1_A TXD2N VSS

G TADR[0] TADR[2] TADR[4] TDAT[1] RAVD1_A TXC2P RX2- RX2+

H VSS TPRTY TADR[1] TADR[3] TXC2N RAVS2_A RAVD2_A VSS

TCA /

J

PTPA

DTCA[3] /

K

DTPA[3]

L REOP RERR

M VSS RVAL

DRCA[3] /

N

DRPA[3]

RSOC /

P

RSOP

R RADR[4] RADR[2] RADR[1] VDD VDD TXC3N TXC3P ATB3

T VSS RADR[0] RPRTY RDAT[13] RAVS3_A N/C TXD3P VSS

U

RDAT[15] RDAT[14] RDAT[12] RDAT[9] TXC4P SD3 RAVD3_A TXD3N

V VSS RDAT[11] RDAT[8] VDD VDD TXC4N RX3- VSS

W RDAT[10] RDAT[7] RDAT[5] RDAT[2] RAVS4_A SD4 TXD4P RX3+

Y

RDAT[6] RDAT[4] RDAT[1] VDD RMOD VDD RLDCLK2 RSD2 VDD RALRM3 RCLK2 VDD TLDCLK3 TSDCLK2 VDD TSD3 TFPI VDD RAVS4_C VDD RAVD4_A RX4- TXD4N

AA RDAT[3] VSS VDD RDAT[0] RSDCLK2 RLDCLK3 RSD3 RLD4 RLD1 RALRM1 RCLK1 RFPO1 TLDCLK4 TSDCLK4 TLD4 TLD2 TSD2 QAVD_1 C4- RAVD4_C VDD VSS RX4+

AB VSS VDD VSS RSDCLK3 RLDCLK4 RSD4 RSD1 RLD2 RALRM4 RCLK4 RFPO4 RFPO2 TFPO TLDCLK1 TSDCLK1 TLD3 TSD4 TSD1 QAVS_1 C4+ VSS VDD VSS

AC VDD VSS RSDCLK4 RSDCLK1 RLDCLK1 VSS RLD3 VSS RALRM2 RCLK3 RFPO3 VSS TCLK TLDCLK2 TSDCLK3 VSS TLD1 VSS REFCLK RAVD4_B RAVS4_B VSS VDD

TSOC /

TENB

DTPA[4]

DRCA[2] /

DRPA[2]

RENB RFCLK RADR[3] ATB2 ATB1 ATB0 RAVS3_C

VDD VDD SD2 N/C RAVD2_C

TSOP

BIAS TFCLK RAVS2_C RAVS2_B C2+ C2-

DTCA[2] /

DTPA[1]

DTPA[2]

VDD VDD TAVS1_B RAVD3_B VSS

DRPA[4]

RCA /

DRPA[1]

PRPA

RAVD2_B TAVD1_A TAVS1_A TAVD1_B

RAVD3_C RAVS3_B C3+ C3-

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 18

BOTTOM VIEW

S/UNI-TETRA

SATURN USER NETWORK INTERFACE (155-TETRA)

DATASHEET PMC-1971240 ISSUE 7

9 PIN DESCRIPTION

9.1 Line Side Interface Signals

PMC-Sierra, Inc.

PM5351 S/UNI-TETRA

Pin Name Type Pin

Function

No.

REFCLK Input AC5 The reference clock input (REFCLK) must provide a

jitter-free 19.44 MHz reference clock. It is used as the reference clock by both clock recovery and clock synthesis circuits.

When the WAN Synchronization controller is used, REFCLK is supplied using a VCXO. In this application, the transmit direction can be looped timed to any of the line receivers in order to meet wander transfer and holdover requirements.

This pin is shared by all channels.

RXD1+ RXD1RXD2+ RXD2RXD3+ RXD3RXD4+ RXD4-

Differential

PECL inputs

E2 D1 G1 G2 W1 V2 AA1 Y2

The receive differential data inputs (RXD+, RXD-) contain the NRZ bit serial receive stream. The receive clock is recovered from the RXD+/- bit stream. Please refer to the Operation section for a discussion of PECL interfacing issues and for the PECL voltage level selection through PECLV for 5V ODL interface.

This pin is available independently for each channel.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 19

S/UNI-TETRA

SATURN USER NETWORK INTERFACE (155-TETRA)

DATASHEET PMC-1971240 ISSUE 7

PMC-Sierra, Inc.

PM5351 S/UNI-TETRA

Pin Name Type Pin

No.

SD1 SD2 SD3 SD4

RCLK1 RCLK2 RCLK3 RCLK4

Single-

Ended

PECL

Input

E3 J3 U3 W3

Output AA13

Y13 AC14 AB14

Function

The Signal Detect pin (SD) indicates the presence of valid receive signal power from the Optical Physical Medium Dependent Device. A PECL high indicates the presence of valid data and a PECL low indicates a loss of signal. It is mandatory that SD be terminated into the equivalent network that RXD+/is terminated into.

SD input is compared to the common mode of the receive data line (RXD+/-). It is also assumed SD will be driven by a low impedance PECL voltage source coming from the same source as the RXD+/signals

This pin is available independently for each channel.

The receive byte clock (RCLK) provides a timing reference for the S/UNI-TETRA receive outputs. RCLK is a divide by eight of the recovered line rate clock (19.44 MHz).

RFPO1 RFPO2 RFPO3 RFPO4

Output AA12

AB12 AC13 AB13

This pin is available independently for each channel.

The Receive Frame Pulse Output (RFPO), when the framing alignment is found (the OOF register bit is logic zero), is an 8 kHz signal derived from the receive line clock. RFPO pulses high for one RCLK cycle every 2430 RCLK cycles (STS-3c (STM-1)). RFPO is updated on the rising edge of RCLK.

This pin is available independently for each channel.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 20

S/UNI-TETRA

SATURN USER NETWORK INTERFACE (155-TETRA)

DATASHEET PMC-1971240 ISSUE 7

PMC-Sierra, Inc.

PM5351 S/UNI-TETRA

Pin Name Type Pin

No.

RALRM1 RALRM2 RALRM3 RALRM4

TXD1+ TXD1TXD2+ TXD2TXD3+ TXD3TXD4+ TXD4-

Output AA14

AC15 Y14 AB15

Differential TTL output

C1 D2 E1

(externally

converted

to PECL)

F2 T2 U1 W2 Y1

Function

The Receive Alarm (RALRM) output indicates the state of the receive framing. RALRM is low if no receive alarms are active. RALRM is high if line AIS (LAIS), path AIS (PAIS), line RDI (LRDI), path RDI (PRDI), enhanced path RDI (PERDI), loss of signal (LOS), loss of frame (LOF), out of frame (OOF), loss of pointer (LOP), loss of cell delineation (LCD), signal fail BER (SFBER), signal degrade BER (SDBER), path trace identification mismatch (TIM), path signal label mismatch (PSLM) is detected in the associated channel. Each alarm can be individually enabled using bits in the S/UNI-TETRA Channel Alarm Control registers #1 and #2.

RALRM is updated on the rising edge of RCLK. This pin is available independently for each

channel. The transmit differential data outputs (TXD+, TXD-)

contain the 155.52 Mbit/s transmit stream. This pin is available independently for each

channel.

TXC1+ TXC1-

Differential

TTL output TXC2+ TXC2TXC3+ TXC3-

(externally

converted

to PECL) TXC4+ TXC4-

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 21

D3 E4 G3 H4 R2 R3 U4 V3

The transmit differential clock outputs (TXC+, TXC-) contain the 155.52 Mbit/s transmit clock.

TXC+/- must be enabled by setting the TXC_OE register bit to logic one. Enabling the transmit line clocks significantly increases the device power consumption and will likely require airflow. Most optic modules don’t require TXC+/-.

TXD+/- is updated on the falling edge of TXC+/-. This pin is available independently for each

channel.

S/UNI-TETRA

SATURN USER NETWORK INTERFACE (155-TETRA)

DATASHEET PMC-1971240 ISSUE 7

PMC-Sierra, Inc.

PM5351 S/UNI-TETRA

Pin Name Type Pin

Function

No.

TFPI Input Y7 The active high framing position (TFPI) signal is an

8 kHz timing marker for the transmitter. TFPI is used to align the SONET/SDH transport frame generated by the S/UNI-TETRA device to a system reference. TFPI is internally used to aligh a master frame pulse counter. When TFPI is not used, this counter is freerunning.

TFPI should be brought high for a single TCLK period every 2430 (STS-3c (STM-1)) TCLK cycles, or a multiple thereof. TFPI shall be tied low if such synchronization is not required. TFPI cannot be used as an input to a loop-timed channel. For TFPI to operate correctly it is required that the TCLK/TFPO output be configured to output the CSU byte clock.

The TFPI_EN register bits allow to individually configure each channel to use the global framing pulse counter and TFPI for framing alignment.

TFPI is sampled on the rising edge of TCLK, but only when the TTSEL register bit is set to logic zero. When TTSEL is set to logic one, TFPI is unused.

This pin is shared by all channels.

TCLK Output AC11 The transmit byte clock (TCLK) output provides a

timing reference for the S/UNI-TETRA self-timed channels. TCLK always provide a divide by eight of the synthesized line rate clock and thus has a nominal frequency of 19.44 MHz. TFPI is sampled on the rising edge of TCLK. TCLK does not apply to internally loop-timed channels, in which case the channel’s RCLK provides transmit timing information.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 22

S/UNI-TETRA

SATURN USER NETWORK INTERFACE (155-TETRA)

DATASHEET PMC-1971240 ISSUE 7

PMC-Sierra, Inc.

PM5351 S/UNI-TETRA

Pin Name Type Pin

Function

No.

TFPO Output AB11 The Transmit Frame Pulse Output (TFPO) pulses

high for one TCLK cycle every 2430 TCLK cycles and provides an 8 KHz timing reference. TFPO can be assigned to any of the four channels using TFPO_CH[1:0] configuration register bits, with the restriction that the selected channel must be selftimed (not in loop-timed or line-loopback modes). TFPO is updated on the rising edge of TCLK.

9.2 Section and Line Status DCC Signals Pin Name Type Pin

Function

No.

RSD1 RSD2 RSD3 RSD4

Output

AB17 Y16 AA17 AB18

The receive section DCC (RSD) signal contains the section data communications channel (D1-D3)

This pin is available independently for each channel.

RSDCLK1 RSDCLK2 RSDCLK3 RSDCLK4

TSD1 TSD2 TSD3 TSD4

AC20

Output

AA19 AB20 AC21

Input AB6

AA7 Y8 AB7

The receive section DCC clock (RSDCLK) is used to clock out the section DCC.

RSDCLK is a 192 kHz clock used to update the RSD output. RSDCLK is generated by gapping a 216 kHz clock.

This pin is available independently for each channel.

The transmit section DCC (TSD) signal contains the section data communications channel (D1-D3).

TSD is sampled on the rising edge of TSDCLK. This pin is available independently for each

channel.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 23

S/UNI-TETRA

SATURN USER NETWORK INTERFACE (155-TETRA)

DATASHEET PMC-1971240 ISSUE 7

PMC-Sierra, Inc.

PM5351 S/UNI-TETRA

Pin Name Type Pin

No.

TSDCLK1 TSDCLK2 TSDCLK3 TSDCLK4

RLD1 RLD2 RLD3 RLD4

RLDCLK1 RLDCLK2 RLDCLK3 RLDCLK4

Output

AB9 Y10 AC9 AA10

AA15 AB16 AC17 AA16

AC19 Y17 AA18 AB19

Function

The transmit section DCC clock (TSDCLK) is used to clock in the section DCC.

TSDCLK is a 192 kHz clock used to sample the TSD input. TSDCLK is generated by gapping a 216 kHz clock.

This pin is available independently for each channel.

The receive line DCC (RLD) signal contains the line data communications channel (D4-D12).

This pin is available independently for each channel.

The receive line DCC clock (RLDCLK) is used to clock out the line DCC.

RLDCLK is a 576 kHz clock used to update the RLD output. RLDCLK is generated by gapping a

2.16 MHz clock.

TLD1 TLD2 TLD3 TLD4

TLDCLK1 TLDCLK2 TLDCLK3 TLDCLK4

Input AC7

AA8 AB8 AA9

AB10

Output

AC10 Y11 AA11

This pin is available independently for each channel.

The transmit line DCC (TLD) signal contains the line data communications channel (D4-D12).

TLD is sampled on the rising edge of TLDCLK. This pin is available independently for each

channel. The transmit line DCC clock (TLDCLK) is used to

clock in the line DCC. TLDCLK is a 576 kHz clock used to sample the TLD

input. TLDCLK is generated by gapping a 2.16 MHz clock.

This pin is available independently for each channel.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 24

PMC-Sierra, Inc.

SATURN USER NETWORK INTERFACE (155-TETRA)

S/UNI-TETRA DATASHEET

PMC-1971240 ISSUE 7

PM5351 S/UNI-TETRA

9.3 ATM (UTOPIA) and Packet over SONET (POS-PHY) System Interface Pin Name Type Pin

No.

TDAT[15] TDAT[14] TDAT[13] TDAT[12] TDAT[11] TDAT[10] TDAT[9] TDAT[8] TDAT[7] TDAT[6] TDAT[5] TDAT[4] TDAT[3] TDAT[2] TDAT[1] TDAT[0]

Input

(ATM)

Input

(POS)

A20 C19 B20 A21 D19 C20 D21 E20 C23 D22 E21 D23 E22 F21 G20 E23

Function

UTOPIA Transmit Cell Data Bus (TDAT[15:0]). This data bus carries the ATM cell octets that are

written to the selected transmit FIFO. TDAT[15:0] is considered valid only when TENB is simultaneously asserted and the S/UNI-TETRA is selected via TADR[4:0].

TDAT[15:0] is sampled on the rising edge of TFCLK.

POS-PHY Transmit Packet Data Bus (TDAT[15:0]). This data bus carries the POS packet octets that

are written to the selected transmit FIFO. TDAT[15:0] is considered valid only when TENB is simultaneously asserted and the S/UNI-TETRA is selected via TADR[4:0].

TDAT[15:0] is sampled on the rising edge of TFCLK.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 25

S/UNI-TETRA

SATURN USER NETWORK INTERFACE (155-TETRA)

DATASHEET PMC-1971240 ISSUE 7

PMC-Sierra, Inc.

PM5351 S/UNI-TETRA

Pin Name Type Pin

No.

TPRTY Input

H22 UTOPIA Transmit bus parity (TPRTY) signal.

(ATM)

TPRTY Input

H22 POS-PHY Transmit bus parity (TPRTY) signal.

(POS)

Function

The transmit parity (TPRTY) signal indicates the parity of the TDAT[15:0] bus. A parity error is indicated by a status bit and a maskable interrupt. Cells with parity errors are inserted in the transmit stream, so the TPRTY input may be unused. Odd or even parity selection is made independently for each channel using the RXPTYP register bit.

TPRTY is considered valid only when TENB is simultaneously asserted and the S/UNI-TETRA is selected via TADR[4:0].

TPRTY is sampled on the rising edge of TFCLK.

The transmit parity (TPRTY) signal indicates the parity of the TDAT[15:0] bus. A parity error is indicated by a status bit and a maskable interrupt. Packets with parity errors are inserted in the transmit stream, so the TPRTY input may be unused. Odd or even parity selection is made independently for each channel using the RXPTYP register bit. TPRTY is considered valid only when TENB is simultaneously asserted and the S/UNI-TETRA is selected via TADR[4:0].

TSOC Input

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 26

(ATM)

TPRTY is sampled on the rising edge of TFCLK

J21 UTOPIA Transmit Start of Cell (TSOC) signal.

The transmit start of cell (TSOC) signal marks the start of cell on the TDAT bus. When TSOC is high, the first word of the cell structure is present on the TDAT bus. It is not necessary for TSOC to be present for each cell. An interrupt may be generated if TSOC is high during any word other than the first word of the cell structure.

TSOC is considered valid only when TENB is simultaneously asserted and the S/UNI-TETRA is selected via TADR[4:0].

TSOC is sampled on the rising edge of TFCLK.

S/UNI-TETRA

SATURN USER NETWORK INTERFACE (155-TETRA)

DATASHEET PMC-1971240 ISSUE 7

PMC-Sierra, Inc.

PM5351 S/UNI-TETRA

Pin Name Type Pin

No.

TSOP Input

J21 POS-PHY Transmit Start of Packet (TSOP) signals.

(POS)

TENB Input

J22 UTOPIA Transmit Multi-PHY Write Enable (TENB)

(ATM)

Function

TSOP indicates the first word of a packet. TSOP is required to be present at the beginning of every packet for proper operation.

TSOP is considered valid only when TENB is simultaneously asserted and the S/UNI-TETRA is selected via TADR[4:0].

TSOP is sampled on the rising edge of TFCLK.

signal. The TENB signal is an active low input which is

used along with the TADR[4:0] inputs to initiate writes to the transmit FIFO’s.

TENB works as follows. When sampled high, no write is performed, but the TADR[4:0] address is latched to identify the transmit FIFO to be accessed. When TENB is sampled low, the word on the TDAT bus is written into the transmit FIFO that is selected by the TADR[4:0] address bus. A complete 53 octet cell must be written to the transmit FIFO before it is inserted into the transmit stream. Idle cells are inserted when a complete cell is not available. While TENB is deasserted, TADR[4:0] can be used for polling TCA.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 27

TENB is sampled on the rising edge of TFCLK.

S/UNI-TETRA

SATURN USER NETWORK INTERFACE (155-TETRA)

DATASHEET PMC-1971240 ISSUE 7

PMC-Sierra, Inc.

PM5351 S/UNI-TETRA

Pin Name Type Pin

No.

TENB Input

J22 POS-PHY Transmit Multi-PHY Write Enable (TENB)

(POS)

Function

signal. The S/UNI-TETRA supports both byte-level and

packet-level transfer. Packet-level transfer operates in a similar fashion to Utopia, with a selection phase when TENB is deasserted and a transfer phase when TENB is asserted. While TENB is asserted, TADR[4:0] is exclusively used for polling PTPA and the currently selected PHY status is provided on STPA. While TENB is deasserted, TADR[4:0] can be used for polling PTPA as well as selecting the next PHY to transfer to. Byte level transfer works on a cycle basis. When TENB is asserted, data is transferred to the selected PHY. Nothing happens when TENB is deasserted. Polling is not available and packet availability is indicated by DTPA[4:1].

TENB is sampled on the rising edge of TFCLK.

TADR[4] TADR[3] TADR[2] TADR[1] TADR[0]

Input

(ATM)

G21 H20 G22 H21 G23

UTOPIA Transmit Write Address (TADR[4:0]) signals.

The TADR[4:0] bus is used to select the FIFO (and hence port) that is written to using the TENB signal and the FIFO's whose cell available signal is visible on the TCA polling output.

Note that address 0x1F is the null-PHY address and cannot be assigned to any port on the S/UNI-TETRA.

TADR[4:0] is sampled on the rising edge of TFCLK.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 28

S/UNI-TETRA

SATURN USER NETWORK INTERFACE (155-TETRA)

DATASHEET PMC-1971240 ISSUE 7

PMC-Sierra, Inc.

PM5351 S/UNI-TETRA

Pin Name Type Pin

No.

TADR[4] TADR[3] TADR[2] TADR[1] TADR[0]

TCA Output

Input

(POS)

G21 H20 G22 H21 G23

J23 UTOPIA Transmit multi-PHY Cell Available (TCA)

(ATM)

Function

POS-PHY Transmit Write Address (TADR[4:0]) signals.

The TADR[4:0] bus is used to select the FIFO (and hence port) that is written to using the TENB signal. In packet level transfer mode, TADR[4:0] is also used for polling on PTPA.

Note that address 0x1F is the null-PHY address and cannot be assigned to any port on the S/UNI-TETRA.

TADR[4:0] is sampled on the rising edge of TFCLK.

The TCA signal indicates when a cell is available in the transmit FIFO for the port polled by TADR[4:0] when TENB is asserted. When high, TCA indicates that the corresponding transmit FIFO is not full and a complete cell may be written. When TCA goes low, it can be configured to indicate either that the corresponding transmit FIFO is near full or that the corresponding transmit FIFO is full. TCA will transition low on the rising edge of TFCLK after the Payload word 19 (TCALEVEL0=0) or 23 (TCALEVEL0=1) is sampled if the PHY being polled is the same as the PHY in use. To reduce FIFO latency, the FIFO depth at which TCA indicates "full" can be set to one, two, three or four cells. Note that regardless of what fill level TCA is set to indicate "full" at, the transmit cell processor can store 4 complete cells.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 29

TCA is tri-stated when either the null-PHY address (0x1F) or an address not matching the address space set by PHY_ADR[2:0] is latched from the TADR[4:0] inputs when TENB is high.

TCA is updated on the rising edge of TFCLK.

S/UNI-TETRA

SATURN USER NETWORK INTERFACE (155-TETRA)

DATASHEET PMC-1971240 ISSUE 7

PMC-Sierra, Inc.

PM5351 S/UNI-TETRA

Pin Name Type Pin

Function

No.

PTPA J23 POS-PHY Polled Transmit multi-PHY Packet

Available (PTPA). PTPA transitions high when a programmable

minimum number of bytes is available in the polled transmit FIFO (TPAHWM[7:0] register bits). Once high, PTPA indicates that the transmit FIFO is not full. When PTPA transitions low, it optionally indicates that the transmit FIFO is full or near full (TPALWM[7:0] register bits). PTPA allows to poll the PHY address selected by TADR[4:0] when TENB is asserted.

PTPA is tri-stated when either the null-PHY address (0x1F) or an address not matching the address space set by PHY_ADR[2:0] is latched from the TADR[4:0] inputs when TENB is high.

PTPA is only available in POS-PHY packet-level transfer mode, as selected by the POS_PLVL register bit. PTPA is tristated in byte-level transfer mode. PTPA is updated on the rising edge of TFCLK.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 30

S/UNI-TETRA

SATURN USER NETWORK INTERFACE (155-TETRA)

DATASHEET PMC-1971240 ISSUE 7

PMC-Sierra, Inc.

PM5351 S/UNI-TETRA

Pin Name Type Pin

No.

STPA Output

B19 POS-PHY Selected multi-PHY Transmit Packet

(POS)

Function

Available (STPA) signal. STPA transitions high when a predefined

(TPAHWM[7:0] register bits) minimum number of bytes is available in the selected transmit FIFO (the FIFO that data is written into). Once high, STPA indicates that the transmit FIFO is not full. When STPA transitions low, it optionally indicates that the transmit FIFO is full or near full (TPALWM[7:0] register bits). STPA always provide status indication for the selected PHY in order to avoid FIFO overflows while polling is performed.

The PHY Layer device shall tristate STPA when TENB is deasserted. STPA shall also be tristated when either the null-PHY address (0x1F) or an address not matching the address space set by PHY_ADR[2:0] is presented on the TADR[4:0] signals when TENB is sampled high (deasserted during the previous clock cycle).

TFCLK Input

(ATM)

TFCLK Input

(POS)

STPA is only available in POS-PHY packet-level transfer mode, as selected by the POS_PLVL register bit. STPA is tristated in byte-level transfer mode. STPA is updated on the rising edge of TFCLK.

K20 UTOPIA Transmit FIFO Write Clock (TFCLK).

This signal is used to write ATM cells to the four cell transmit FIFOs.

TFCLK cycles at a 50 MHz or lower instantaneous rate.

K20 POS-PHY Transmit FIFO Write Clock (TFCLK).

This signal is used to write packet octets into the 256 bytes packet FIFO’s.

TFCLK cycles at a 50 MHz or lower instantaneous rate.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 31

S/UNI-TETRA

SATURN USER NETWORK INTERFACE (155-TETRA)

DATASHEET PMC-1971240 ISSUE 7

PMC-Sierra, Inc.

PM5351 S/UNI-TETRA

Pin Name Type Pin

No.

DTCA[4] DTCA[3] DTCA[2] DTCA[1]

Output

(ATM)

K22 K23 L20 L21

Function

UTOPIA Direct Transmit Cell Available (DTCA[4:1]). These output signals provide direct status indication

of when a cell is available in the transmit FIFO for the corresponding port. When high, DTCA indicates that the corresponding transmit FIFO is not full and a complete cell may be written. When DTCA goes low, it can be configured to indicate either that the corresponding transmit FIFO is near full or that the corresponding transmit FIFO is full. DTCA will transition low on the rising edge of TFCLK after the Payload word 19 (TCALEVEL0=0) or 23 (TCALEVEL0=1) is sampled if the PHY being polled is the same as the PHY in use. To reduce FIFO latency, the FIFO depth at which DTCA indicates "full" can be set to one, two, three or four cells. Note that regardless of what fill level DTCA is set to indicate "full" at, the transmit cell processor can store 4 complete cells

DTCA[4:1] are updated on the rising edge of TFCLK.

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Pin Name Type Pin

No.

DTPA[4] DTPA[3] DTPA[2] DTPA[1]

Output

(POS)

K22 K23

L20 L21

Function

POS-PHY Direct Transmit Packet Available (DTPA[4:1]).

These output signals provide direct status indication of when some programmable number of bytes is available in the transmit FIFO, for the corresponding port. When transitioning high, DTPA indicates that the transmit FIFO has enough room to store data. The transition level is selected by the TXFP Transmit Packet Available Low Water-mark (TPALWM[7:0]) register. When DTPA transitions low, it indicates that the transmit FIFO is either full or near full as selected by the TXFP Transmit Packet Available High Water-mark (TPAHWM[7:0]) register. This last option provides the Link Layer system with some look ahead capability in order to avoid FIFO overruns and smoothly transition between PHY’s.

DTPA[4:1] are updated on the rising edge of TFCLK.

TMOD Input

(POS)

F22 POS-PHY Transmit Word Modulo (TMOD) signal.

TMOD indicates the size of the current word. TMOD is only used during the last word transfer of a packet, at the same time TEOP is asserted. During a packet transfer every word must be complete except the last word, which can be composed of 1 or 2 bytes. TMOD set high indicates a 1-byte word (present on MSB’s, LSB’s are discarded) while TMOD set low indicates a 2-byte word.

TMOD is considered valid only when TENB is simultaneously asserted and the S/UNI-TETRA is selected via TADR[4:0].

TMOD is sampled on the rising edge of TFCLK.

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Pin Name Type Pin

No.

TEOP Input

C18 POS-PHY Transmit End of Packet (TEOP).

(POS)

TERR Input

D17 POS-PHY Transmit Error (TERR).

(POS)

Function

The active high TEOP signal marks the end of a packet on the TDAT[15:0] bus. When TEOP is high, the last word of the packet is present on the TDAT[15:0] data bus and TMOD indicates how many bytes this last word is composed of. It is legal to set TSOP high at the same time TEOP is high. This provides support for one or two byte packets, as indicated by the value of TMOD.

TEOP is considered valid only when TENB is simultaneously asserted and the S/UNI-TETRA is selected via TADR[4:0].

TEOP is sampled on the rising edge of TFCLK.

The transmit error indicator (TERR) is used to indicate that the current packet must be aborted. TERR should only be asserted during the last word transfer of a packet. Packets marked with TERR will be appended with the abort sequence (0x7D-0x7E) when transmission.

TERR is considered valid only when TENB is simultaneously asserted and the S/UNI-TETRA is selected via TADR[4:0].

TERR is sampled on the rising edge of TFCLK.

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Pin Name Type Pin

No.

RDAT[15] RDAT[14] RDAT[13] RDAT[12] RDAT[11] RDAT[10] RDAT[9] RDAT[8] RDAT[7] RDAT[6] RDAT[5] RDAT[4] RDAT[3] RDAT[2] RDAT[1] RDAT[0]

Output

(ATM)

Output

(POS)

U23 U22

T20 U21 V22

W23

U20 V21

W22

Y23

W21

Y22

AA23

W20

Y21

AA20

U23 U22

T20 U21 V22

W23

U20 V21

W22

Y23

W21

Y22

AA23

W20

Y21

AA20

Function

UTOPIA Receive Cell Data Bus (RDAT[15:0]). This data bus carries the ATM cells that are read

from the receive FIFO selected by RADR[4:0]. RDAT[15:0] is tri-stated when RENB is high.

RDAT[15:0] is tristated when RENB is high. RDAT[15:0] is also tristated when either the nullPHY address (0x1F) or an address not matching the address space is latched from the RADR[4:0] inputs when RENB is high.

RDAT[15:0] is updated on the rising edge of RFCLK.

POS-PHY Receive Packet Data Bus (RDAT[15:0]). This data bus carries the POS packet octets that

are read from the selected receive FIFO. RDAT[15:0] is considered valid only when RVAL is asserted.

RDAT[15:0] is tristated when RENB is high. RDAT[15:0] is also tristated when either the nullPHY address (0x1F) or an address not matching the address space is latched from the RADR[4:0] inputs.

RDAT[15:0] is updated on the rising edge of RFCLK.

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Pin Name Type Pin

No.

RPRTY Output

T21 UTOPIA Receive Parity (RPRTY).

(ATM)

RPRTY Output

T21 POS-PHY Receive Parity (RPRTY).

(POS)

Function

The receive parity (RPRTY) signal indicates the parity of the RDAT bus. RPRTY reflects the parity of RDAT[15:0]. Odd or even parity selection is made independently for every channel by using the RXPTYP register bit (in ATM cell processors, the four RXCP shall be programmed with the same parity setting).RPRTY is tristated when RENB is high. RPRTY is also tristated when either the nullPHY address (0x1F) or an address not matching the address space is latched from the RADR[4:0] inputs when RENB is high.

RPRTY is updated on the rising edge of RFCLK.

The receive parity (RPRTY) signal indicates the parity of the RDAT bus. Odd or even parity selection is made independently for every channel by using the RXPTYP register bit (in POS Frame Processors; the four RXFP shall be programmed with the same parity setting). RPRTY is tristated when RENB is high. RPRTY is also tristated when either the null-PHY address (0x1F) or an address not matching the address space is latched from the RADR[4:0] inputs.

RSOC Output

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(ATM)

RPRTY is updated on the rising edge of RFCLK.

P23 UTOPIA Receive Start of Cell (RSOC).

RSOC marks the start of cell on the RDAT bus. RSOC is tristated when RENB is deasserted.

RSOC is also tristated when either the null-PHY address (0x1F) or an address not matching the address space is latched from the RADR[4:0] inputs when RENB is high.

RSOC is sampled on the rising edge of RFCLK.

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Pin Name Type Pin

No.

RSOP Output

P23 POS-PHY Receive Start of Packet (RSOP).

(POS)

RENB Input

P22 UTOPIA Receive multi-PHY Read Enable (RENB).

(ATM)

Function

RSOP marks the first word of a packet transfer. RSOP is tristated when RENB is deasserted. RSOP

is also tristated when either the null-PHY address (0x1F) or an address not matching the address space is latched from the RADR[4:0] inputs.

RSOP/RSOP is sampled on the rising edge of RFCLK

The RENB signal is used to initiate reads from the receive FIFO’s. RENB works as follows. When RENB is sampled high, no read is performed and RDAT[15:0], RPRTY and RSOC are tristated, and the address on RADR[4:0] is latched to select the device or port for the next FIFO access. When RENB is sampled low, the word on the RDAT bus is read from the selected receive FIFO.

RENB must operate in conjunction with RFCLK to access the FIFO’s at a high enough rate to prevent FIFO overflows. The system may de-assert RENB at anytime it is unable to accept another byte.

RENB is sampled on the rising edge of RFCLK.

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Pin Name Type Pin

No.

RENB Input

P22 POS-PHY Receive multi-PHY Read Enable

(POS)

Function

(RENB). The S/UNI-TETRA supports both byte-level and

packet-level transfer. Packet-level transfer operates as described above, with a selection phase when RENB is deasserted and a transfer phase when RENB is asserted. While RENB is asserted, RADR[4:0] is exclusively used for polling RPA. While RENB is deasserted, RADR[4:0] can be used for polling RPA as well as selecting the next PHY to transfer from. Byte level transfer works on a cycle basis. When RENB is asserted data is transferred from the selected PHY and RADR[4:0] is used to select the PHY. Nothing happens when RENB is deasserted. Polling is not possible; packet availability is directly indicated by DRPA[4:1].

During a data transfer, RVAL shall be monitored since it will indicate if the data is valid. Once RVAL is deasserted, RENB or RADR[4:0] must be used to select a new PHY for data transfer.

RADR[4] RADR[3] RADR[2] RADR[1] RADR[0]

Input

(ATM)

R23 P20 R22 R21 T22

RENB must operate in conjunction with RFCLK to access the FIFO’s at a high enough rate to prevent FIFO overflows. The system may de-assert RENB at anytime it is unable to accept another byte.

RENB is sampled on the rising edge of RFCLK. UTOPIA Receive Read Address (RADR[4:0]). The RADR[4:] signal is used to select the FIFO (and

hence port) that is read from using the RENB signal and the FIFO whose cell available signal is visible on the RCA output.

Note that address 0x1F is the null-PHY address and will not be identified to any port on the S/UNI-TETRA.

RADR[4:0] is sampled on the rising edge of RFCLK.

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Pin Name Type Pin

No.

RADR[4] RADR[3] RADR[2] RADR[1] RADR[0]

RCA Output

Input

(POS)

R23 P20 R22 R21 T22

N20 UTOPIA Receive multi-PHY Cell Available (RCA).

(ATM)

Function

POS-PHY Receive Read Address (RADR[4:0]). The RADR[4:0] signal is used to select the FIFO

(and hence port) that is read from using the RENB signal.

The RADR[4:0] bus is used to select the FIFO (and hence port) that is written to using the TENB signal and the FIFO's whose packet available signal is visible on the PRPA polling output.

Note that address 0x1F is the null-PHY address and will not be identified to any port on the S/UNI-TETRA.

RADR[4:0] is sampled on the rising edge of RFCLK.

RCA indicates when a cell is available in the receive FIFO for the port selected by RADR[4:0]. RCA can be configured to be de-asserted when either zero or four bytes remain in the selected/addressed FIFO. RCA will thus transition low on the rising edge of RFCLK after Payload word 24 (RCALEVEL0=1) or 19 (RCALEVEL0=0) is output if the PHY being polled is the same as the PHY in use.

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RCA is tristated when either the null-PHY address (0x1F) or an address not matching the address space is latched from the RADR[4:0] inputs when RENB is high.

RCA is updated on the rising edge of RFCLK.

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Pin Name Type Pin

No.

PRPA Output

N20 POS-PHY Polled multi-PHY Receive Packet

(POS)

Function

Available (PRPA) signal. PRPA indicates when data is available in the polled

receive FIFO. When PRPA is high, the receive FIFO has at least one end of packet or a predefined number of bytes to be read (the number of bytes might be user programmable). PRPA is low when the receive FIFO fill level is below the assertion threshold and the FIFO contains no end of packet.

PRPA allows to poll every PHY while transferring data from the selected PHY.

PRPA is driven by a PHY layer device when its address is polled on RADR[4:0]. A PHY layer device shall tristate PRPA when either the null-PHY address (0x1F) or an address not matching the address range set by the PHY_ADR[2:0] register bits is provided on RADR[4:0].

PRPA is only available in POS-PHY packet-level transfer mode, as selected by the POS_PLVL register bit. PRPA is tristated in byte-level transfer mode. PRPA is updated on the rising edge of RFCLK.

Note: In some conditions RPA can assert prematurely. Refer to section 10.15.2.1.

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Pin Name Type Pin

No.

RVAL Output

M22 POS-PHY Receive Data Valid (RVAL).

(POS)

Function

RVAL indicates the validity of the receive data signals. When RVAL is high, the Receive signals (RDAT, RSOP, REOP, RMOD, RPRTY and RERR) are valid. When RVAL is low, all Receive signals are invalid and must be disregarded. RVAL will transition low on a FIFO empty condition or on an end of packet. . No data will be removed from the receive FIFO while RVAL is deasserted. Once deasserted, RVAL will remain deasserted until the current PHY is deselected.

RVAL allows to monitor the selected PHY during a data transfer, while monitoring other PHY’s is done using DRPA[4:1].

RVAL is tristated when RENB is deasserted. RVAL is also tristated when either the null-PHY address (0x1F) or an address not matching the PHY layer device address is presented on the RADR[4:0] signals.

RFCLK Input

(ATM)

RFCLK Input

(ATM)

RVAL is updated on the rising edge of RFCLK.

P21 UTOPIA Receive FIFO Read Clock (RFCLK).

RFCLK is used to read ATM cells from the receive FIFO’s. RFCLK must cycle at a 50 MHz or lower instantaneous rate, but at a high enough rate to avoid FIFO overflows.

P21 POS-PHY Receive FIFO Read Clock (RFCLK).

This signal is used to read packets from the receive FIFO’s. RFCLK must cycle at a 50 MHz or lower instantaneous rate, but at a high enough rate to avoid FIFO overflows.

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Pin Name Type Pin

No.

DRCA[4] DRCA[3] DRCA[2] DRCA[1]

DRPA[4] DRPA[3] DRPA[2] DRPA[1]

Output

(ATM)

Output

(POS)

M21 N23 N22 N21

Function

UTOPIA Direct Receive Cell Available (DRCA[4:1]). These output signals provides direct status

indication of when a cell is available in the receive FIFO for the corresponding port. DRCA can be configured to be de-asserted when either zero or four bytes remain in the selected/addressed FIFO. DRCA will thus transition low on the rising edge of RFCLK after Payload word 24 (RCALEVEL0=1) or 19 (RCALEVEL0=0) is output if the PHY being polled is the same as the PHY in use.

DRCA[x] is updated on the rising edge of RFCLK. POS-PHY Direct Receive Packet Available

(DRPA[4:1]). DRPA[x] provides a direct status indication. DRPA

indicates when data is available in the receive FIFO. When DRPA is high, the receive FIFO has at least one end of packet or a programmable minimum number of bytes to be read. DRPA is otherwise low. The polarity of DRPA can be inverted with the RPAINV register bit.

DRPA[x] is updated on the rising edge of RFCLK. Note: In some conditions RPA can assert

prematurely. Refer to section 10.15.2.1.

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Pin Name Type Pin

No.

RMOD Output

Y19 POS-PHY Receive Modulo (RMOD).

(POS)

REOP Output

L23 POS-PHY Receive End Of Packet (REOP).

(POS)

Function

The RMOD signal indicates the number of bytes carried by the RDAT[15:0] bus during the last word of a packet transfer. During a packet transfer every word must be complete except the last word which can be composed of 1 or 2 bytes. RMOD set high indicate a single byte word (present on MSB’s, LSB’s are discarded) while RMOD set low indicates a two byte word. RMOD is only used in POS mode.

RMOD is tristated when RENB is deasserted. RMOD is also tristated when either the null-PHY address (0x1F) or an address not matching the address space set by PHY_ADR[2:0] is latched from the RADR[4:0] inputs when RENB is high.

RMOD is updated on the rising edge of RFCLK.

The REOP signal marks the end of packet on the RDAT[15:0] bus. When the RXFP-50 is selected, REOP is set high to mark the last word of the packet presented on the RDAT[15:0] bus. During this same cycle RMOD is used to indicate if the last word has 1 or 2 bytes. It is legal to set RSOP high at the same time REOP is high. This provides support for one or two bytes packets, as indicated by the value of RMOD. REOP is only used in POS mode.

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REOP is tristated when RENB is deasserted. REOP is also tristated when either the null-PHY address (0x1F) or an address not matching the address space is latched from the RADR[4:0] inputs when RENB is high.

REOP is updated on the rising edge of RFCLK.

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Pin Name Type Pin

No.

RERR Output

L22 POS-PHY Receive Error (RERR).

(POS)

PHY_OEN Input

A19 The PHY Output Enable (PHY_OEN) signal

(ATM/

POS)

Function

The RERR signal indicates that the current packet is aborted. RERR can only be asserted during the last word transfer, at the same time REOP is asserted. RERR is only used in POS mode.

RERR is tristated when RENB is deasserted. RERR is also tristated when either the null-PHY address (0x1F) or an address not matching the address space is latched from the RADR[4:0] inputs when RENB is high.

RERR is updated on the rising edge of RFCLK.

controls the operation of the system interface. When set to logic zero, all System Interface outputs are held tristate. When PHY_OEN is set to logic one, the interface is enabled. PHY_OEN can be overwritten by the PHY_EN Master System Interface Configuration register bit. PHY_OEN and PHY_EN are OR’ed together to enable the interface.

When the S/UNI-TETRA is the only PHY layer device on the bus, PHY_OEN can safely be tied to logic one. When the S/UNI-TETRA shares the bus with other devices, then PHY_OEN must be tied to logic zero, and the PHY_EN register bit used to enable the bus once its PHY_ADR[2:0] is programmed in order to avoid conflicts.

The PHY Output Enable does not tristate the DTCA, DTPA, DRCA, DRPA pins.

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9.4 Microprocessor Interface Signals

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PM5351 S/UNI-TETRA

Pin Name Type Pin

Function

No.

CSB Input B11 The active-low chip select (CSB) signal is low

during S/UNI-TETRA register accesses. If CSB is used, it must be held high while RSTB is

low to properly initialize the device. If CSB is not required (i.e. register accesses are controlled using the RDB and WRB signals only), CSB must be connected to an inverted version of the RSTB input to ensure proper device initialization.

RDB Input D11 The active-low read enable (RDB) signal is low

during S/UNI-TETRA register read accesses. The S/UNI-TETRA drives the D[7:0] bus with the contents of the addressed register while RDB and CSB are low.

WRB Input A10 The active-low write strobe (WRB) signal is low

during a S/UNI-TETRA register write accesses. The D[7:0] bus contents are clocked into the addressed register on the rising WRB edge while CSB is low.

D[0] D[1] D[2] D[3] D[4] D[5] D[6] D[7]

A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7] A[8] A[9]

I/O D16

B17 A17 C16 B16 C15 B15 D14

Input A15

C14 B14 A14 D13 C13 B13 A13 C12 B12

The bi-directional data bus D[7:0] is used during S/UNI-TETRA register read and write accesses.

The address bus A[9:0] selects specific registers during S/UNI-TETRA register accesses.

Except for S/UNI-TETRA global registers, the A[9:8] bits allow to select which channel is being accessed. The A[7:0] bits allow to select which register is being access within a given channel address space.

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Pin Name Type Pin

Function

No.

A[10]/TRS Input A11 The test register select (TRS) signal selects

between normal and test mode register accesses. TRS is high during test mode register accesses, and is low during normal mode register accesses.

RSTB Input

pull-up

B10 The active-low reset (RSTB) signal provides an

asynchronous S/UNI-TETRA reset. RSTB is a Schmitt triggered input with an integral pull-up resistor.

ALE Input

pull-up

C11 The address latch enable (ALE) is active-high and

latches the address bus A[7:0] when low. When ALE is high, the internal address latches are transparent. It allows the S/UNI-TETRA to interface to a multiplexed address/data bus. ALE has an integral pull-up resistor.

INTB Output

Open-

drain

C10 The active-low interrupt (INTB) signal goes low

when a S/UNI-TETRA interrupt source is active and that source is unmasked. The S/UNI-TETRA may be enabled to report many alarms or events via interrupts.

Examples of interrupt sources are loss of signal (LOS), loss of frame (LOF), line AIS, line remote defect indication (LRDI) detect, loss of pointer (LOP), path AIS, path remote defect indication detect and others.

INTB is tristated when the interrupt is acknowledged via an appropriate register access. INTB is an open drain output.

9.5 JTAG Test Access Port (TAP) Signals Pin Name Type Pin

Function

No.

TCK Input B8 The test clock (TCK) signal provides timing for test

operations that are carried out using the IEEE P1149.1 test access port.

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Pin Name Type Pin

Function

No.

TMS Input

pull-up

B9 The test mode select (TMS) signal controls the test

operations that are carried out using the IEEE P1149.1 test access port. TMS is sampled on the rising edge of TCK. TMS has an integral pull-up resistor.

TDI Input

pull-up

D10 The test data input (TDI) signal carries test data into

the S/UNI-TETRA via the IEEE P1149.1 test access port. TDI is sampled on the rising edge of TCK. TDI has an integral pull-up resistor.

TDO Tristate A9 The test data output (TDO) signal carries test data

out of the S/UNI-TETRA via the IEEE P1149.1 test access port. TDO is updated on the falling edge of TCK. TDO is a tristate output which is inactive except when scanning of data is in progress.

TRSTB Input

pull-up

C9 The active-low test reset (TRSTB) signal provides

an asynchronous S/UNI-TETRA test access port reset via the IEEE P1149.1 test access port. TRSTB is a Schmitt triggered input with an integral pull-up resistor.

9.6 Analog Signals Pin Name Type Pin

CP1

Analog B4 CN1 CP2 CN2 CP3 CN3 CP4 CN4

No.

C5 K2 K1 N2 N1 AB4 AA5

Note that when not being used, TRSTB must be connected to the RSTB input.

Function

The analog CP and CN pins are provided for applications that must meet SONET/SDH jitter transfer specifications. A 220 nF X7R 10% ceramic capacitor can be attached across CP and CN.

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Pin Name Type Pin

ATB0

Analog I/O P2 ATB1 ATB2 ATB3

9.7 Power and Ground Pin Name Type Pin

BIAS Bias

Voltage

No.

P3 P4 R1

No.

K21 C17

Function

The Analog Test Bus (ATB). These pins are used for manufacturing testing only and should be connected ground.

Function

I/O Bias (BIAS). When tied to +5V via a 1 KΩ resistor, the BIAS input is used to bias the wells in the input and I/O pads so that the pads can tolerate 5V on their inputs without forward biasing internal ESD protection devices. When BIAS is tied to +3.3V, the inputs and bi-directional inputs will only tolerate 3.3V level inputs.

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Pin Name Type Pin

No.

VDD Power A1

A23 B2 B22 C3 C21 D4 D6 D9 D12 D15 D18 D20 F4 F20 J4 J20 M4 M20 R4 R20 V4 V20 Y4 Y6 Y9 Y12 Y15 Y18 Y20 AA3 AA21 AB2 AB22 AC1 AC23

Function

The digital power (VDD) pins should be connected to a well-decoupled +3.3 V DC supply.

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Pin Name Type Pin

No.

VSS Ground A2

A6 A8 A12 A16 A18 A22 B1 B3 B21 B23 C2 C22 F1 F23 H1 H23 M1 M23 T1 T23 V1 V23 AA2 AA22 AB1 AB3 AB21 AB23 AC2 AC6 AC8 AC12 AC16 AC18 AC22

Function

The digital ground (VSS) pins should be connected to ground.

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Pin Name Type Pin

No.

QAVD Analog

Power

QAVS Analog

Ground

AA6 C6

AB5 B5

AVD Analog

PowerG4A4

C4 H2 L4 J1 U2 M2 N4 Y3 AC4 AA4 L3 L1

Function

QAVD1 QAVD2

The quiet analog power (QAVD) pins for the analog core. QAVD should be connected to analog +3.3V through a 100Ω resistor to avoid latchup during power-up.

QAVS1 QAVS2

The quiet analog ground (QAVS) pins for the analog core. QAVS should be connected to analog GND.

RAVD1_A - Channel #1 PECL Input Buffer RAVD1_B - Channel #1 CRU RAVD1_C - Channel #1 CRU RAVD2_A - Channel #2 PECL Input Buffer RAVD2_B - Channel #2 CRU RAVD2_C - Channel #2 CRU RAVD3_A - Channel #3 PECL Input Buffer RAVD3_B - Channel #3 CRU RAVD3_C - Channel #3 CRU RAVD4_A - Channel #4 PECL Input Buffer RAVD4_B - Channel #4 CRU RAVD4_C - Channel #4 CRU TAVD1_A - CSU TAVD1_B - CSU

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The analog power (AVD) pins for the analog core. AVD should be connected to analog +3.3V.

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Pin Name Type Pin

No.

AVS Analog

GroundF3A3

D5 H3 K3 K4 T4 N3 P1 W4 AC3 Y5 L2 M3

Notes on Pin Description:

Function

RAVS1_A - Channel #1 PECL Input Buffer RAVS1_B - Channel #1 CRU RAVS1_C - Channel #1 CRU RAVS2_A - Channel #2 PECL Input Buffer RAVS2_B - Channel #2 CRU RAVS2_C - Channel #2 CRU RAVS3_A - Channel #3 PECL Input Buffer RAVS3_B - Channel #3 CRU RAVS3_C - Channel #3 CRU RAVS4_A - Channel #4 PECL Input Buffer RAVS4_B - Channel #4 CRU RAVS4_C - Channel #4 CRU TAVS1_A - CSU TAVS1_B - CSU

The analog ground (AVS) pins for the analog core. AVS should be connected to analog GND.

1. All S/UNI-TETRA inputs and bi-directionals present minimum capacitive loading and operate at TTL logic levels except: the SD, RXD+ and RXDinputs which operate at pseudo-ECL (PECL) logic levels

2. The RDAT[15:0], RPRTY, RSOC, REOP, RMOD, RERR, RVAL, DRCA4-1, RCA/PRPA, DTCA4-1, TCA/PRPA, STPA, TCLK and RCLK1-4 outputs have a 4 mA DC drive capability. The TDO and INTB outputs have a 1 mA drive capability. All the other outputs have a 2 mA DC drive capability. The TXD+ and TXD- outputs should be terminated in a passive network and interface at PECL levels.

3. It is mandatory that every ground pin (VSS) be connected to the printed circuit board ground plane to ensure a reliable device operation.

4. It is mandatory that every power pin (VDD) be connected to the printed circuit board power plane to ensure a reliable device operation.

5. All analog power and ground can be sensitive to noise. They must be isolated from the digital power and ground. Care must be taken to decouple these pins from each other and all other analog power and ground pins.

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Power supply filtering recommendations are provided in the OPERATION section of this document .

6. Due to ESD protection structures in the pads it is necessary to exercise caution when powering a device up or down. ESD protection devices behave as diodes between power supply pins and from I/O pins to power supply pins. Under extreme conditions it is possible to blow these ESD protection devices or trigger latch up. Please adhere to the recommended power supply sequencing as described in the OPERATION section of this document .

7. If it is intended to substitute a S/UNI-TETRA in a S/UNI-QUAD socket, special attention must be given to the NC pins. The requirement is that no S/UNI-TETRA input pin is left floating when used in a S/UNI-QUAD socket. Please refer to the relevant PMC-Sierra, Inc. application note.

8. Some device pins can be made 5V tolerant by connecting the BIAS pins to a 5V power supply, while some other pins are 3.3V only. In summary, the system interface (ATM or POS) is 3.3V only while the microprocessor interface, SONET and line interfaces are 5V tolerant.

3.3V only I/O’s:

RDAT[15:0], RSOC/RSOP, RPRTY, RENB, REOP, RMOD, RERR, RVAL, TDAT[15:0], TSOC/TSOP, TPRTY, TENB, TEOP, TMOD, TERR, RCA/RPA, DRCA4-1/DRPA4-1, TCA/PTPA, STPA, DTCA4-1/DTPA4-1, RADR[5:0], TADR[5:0], PHY_OEN

5V tolerant I/O’s:

REFCLK, RXD RCLK4-1, RFPO4-1, RALRM4-1, TCLK, TFPO, TFPI, RSD, RSDCLK, TSD, TSDCLK. RLD, RLDCLK, TLD, TLDCLK., D[7:0], A[10:0], WRB, RDB, CSB, RSTB, INTB, ALE, TRSTB, TCK, TMS, TDI, TDO,

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10 FUNCTIONAL DESCRIPTION

10.1 Receive Line Interface (CRSI)

The Receive Line Interface allows to directly interface the S/UNI-TETRA with optical modules (ODLs) or other medium interfaces. This block performs clock and data recovery and performs serial to parallel conversion on the incoming

155.52 Mbit/s data stream.

10.1.1 Clock Recovery

The clock recovery unit recovers the clock from the incoming bit serial data stream. The clock recovery unit is fully compliant with SONET and SDH jitter tolerance requirements. The clock recovery unit utilizes a low frequency reference clock to train and monitor its clock recovery PLL. Under loss of signal conditions, the clock recovery unit continues to output a line rate clock that is locked to this reference for keep alive purposes. The clock recovery unit utilizes a reference clocks at 19.44 MHz. The clock recovery unit provides status bits that indicate whether it is locked to data or the reference. The clock recovery unit also supports diagnostic loopback and a loss of signal input that squelches normal input data.

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Initially, the PLL locks to the reference clock, REFCLK. When the frequency of the recovered clock is within 488 ppm of the reference clock, the PLL attempts to lock to the data. Once in data lock, the PLL reverts to the reference clock if no data transitions occur in 80 bit periods or if the recovered clock drifts beyond 488 ppm of the reference clock.

When the transmit clock is derived from the recovered clock (loop timing), the accuracy of the transmit clock is directly related to the REFCLK reference accuracy in the case of a loss of signal condition. To meet the Bellcore GR-253CORE SONET Network Element free-run accuracy specification, the reference must be within +/-20ppm. When used in LAN applications, the REFCLK accuracy may be relaxed to +/-50ppm.

The loop filter transfer function is optimized to enable the PLL to track the jitter, yet tolerate the minimum transition density expected in a received SONET/SDH data signal. The total loop dynamics of the clock recovery PLL yield a jitter tolerance that exceeds the minimum tolerance proposed for SONET equipment by GR-253-CORE (Figure 3).

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Figure 3: Typical STS-3c (STM-1) Jitter Tolerance

100

10

GR-253-CORE

1

0.1 100 1000 10000 100000 1000000 10000000

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PM5351 S/UNI-TETRA

Note that for frequencies below 300 Hz, the jitter tolerance is greater than 15 UIpp; 15 UIpp is the maximum jitter tolerance of the test equipment. Also note that the dip in the tolerance curve between 300 Hz and 10 kHz is due to the S/UNI-TETRA's internal clock difference detector: if the recovered clock drifts beyond 488 ppm of the reference, the PLL locks to the reference clock.

10.1.2 Serial to Parallel Converter

The Serial to Parallel Converter (SIPO) converts the received bit serial stream to a byte serial stream. The SIPO searches for the SONET/SDH framing pattern (A1, A2) in the receive stream, and performs serial to parallel conversion on octet boundaries.

10.2 Receive Section Overhead Processor (RSOP)

The Receive Section Overhead Processor (RSOP) provides frame synchronization, de-scrambling, section level alarm and performance monitoring. In addition, it extracts the section data communication channel from the section overhead and, if selected, provides it serially on output RSD.

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10.2.1 Framer

The Framer Block determines the in-frame/out-of-frame status of the receive stream.

While in-frame, the framing bytes (A1, A2) in each frame are compared against the expected pattern. Out-of-frame is declared when four consecutive frames containing one or more framing pattern errors have been received.

While out-of-frame, the SIPO block monitors the receive stream for an occurrence of the framing pattern. When a framing pattern is recognized, the Framer block verifies that an error free framing pattern is present in the next frame before declaring in-frame.

10.2.2 Descramble

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The Descramble Block utilizes a frame synchronous descrambler to process the receive stream. The generating polynomial is x7 + x6 + 1 and the sequence

length is 127. Details of the de-scrambling operation are provided in the references. Note that the framing bytes (A1 and A2) and the trace/growth bytes (J0/Z0) are not descrambled. A register bit is provided to disable the descrambling operation.

10.2.3 Data Link Extract

The Data Link Extract Block extracts the section data communication channel (bytes D1, D2, and D3) from the STS-3c (STM-1) stream. The extracted bytes are serialized and output on signal RSD at a nominal 192 kbit/s rate. Timing for downstream processing of the data communication channel is provided by the RSDCLK signal that is also output by the Data Link Extract Block. RSDCLK is derived from a 216 kHz clock that is gapped to yield an average frequency of 192 kHz. RSD is updated with timing aligned to RSDCLK.

10.2.4 Error Monitor

The Error Monitor Block calculates the received section BIP-8 error detection code (B1) based on the scrambled data of the complete STS-3c (STM-1) frame. The section BIP-8 code is based on a bit interleaved parity calculation using even parity. Details are provided in the references. The calculated BIP-8 code is compared with the BIP-8 code extracted from the B1 byte of the following frame. Differences indicate that a section level bit error has occurred. Up to 64000 (8 x

8000) bit errors can be detected per second. The Error Monitor Block accumulates these section level bit errors in a 16-bit saturating counter that can

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be read via the microprocessor interface. Circuitry is provided to latch this counter so that its value can be read while simultaneously resetting the internal counter to 0 or 1, if appropriate, so that a new period of accumulation can begin without loss of any events. It is intended that this counter be polled at least once per second so as not to miss bit error events.

10.2.5 Loss of Signal

The Loss of Signal Block monitors the scrambled data of the receive stream for the absence of 1's. When 20 ± 3 µs of all zeros patterns is detected, a loss of signal (LOS) is declared. Loss of signal is cleared when two valid framing words are detected and during the intervening time, no loss of signal condition is detected. The LOS signal is optionally reported on the RALRM output pin when enabled by the LOSEN Receive Alarm Control Register bit.

10.2.6 Loss of Frame

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The Loss of Frame Block monitors the in-frame / out-of-frame status of the Framer Block. A loss of frame (LOF) is declared when an out-of-frame (OOF) condition persists for 3 ms. The LOF is cleared when an in-frame condition persists for a period of 3 ms. To provide for intermittent out-of-frame (or in-frame) conditions, the 3 ms timer is not reset to zero until an in-frame (or out-of-frame) condition persists for 3 ms. The LOF and OOF signals are optionally reported on the RALRM output pin when enabled by the LOFEB and OOFEN Receive Alarm Control Register bits.

10.3 Receive Line Overhead Processor (RLOP)

The Receive Line Overhead Processor (RLOP) provides line level alarm and performance monitoring. In addition, it extracts the line data communication channel from the line overhead and, if selected, provides it serially on output RLD.

10.3.1 Line RDI Detect

The Line RDI Detect Block detects the presence of Line Remote Defect Indication (LRDI) in the receive stream. Line RDI is declared when a 110 binary pattern is detected in bits 6, 7, and 8 of the K2 byte, for three or five consecutive frames. Line RDI is removed when any pattern other than 110 is detected in bits 6, 7, and 8 of the K2 byte for three or five consecutive frames. The LRDI signal is optionally reported on the RALRM output pin when enabled by the LRDIEN Receive Alarm Control Register bit.

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10.3.2 Line AIS Detect

The Line AIS Block detects the presence of a Line Alarm Indication Signal (LAIS) in the receive stream. Line AIS is declared when a 111 binary pattern is detected in bits 6, 7, and 8 of the K2 byte, for three or five consecutive frames. Line AIS is removed when any pattern other than 111 is detected in bits 6, 7, and 8 of the K2 byte for three or five consecutive frames. The LAIS signal is optionally reported on the RALRM output pin when enabled by the LAISEN Receive Alarm Control Register bit.

10.3.3 Data Link Extract Block

The Data Link Extract Block extracts the line data communication channel (bytes D4 to D12) from the STS-3c (STM-1) stream. The extracted bytes are serialized and output on the RLD output at a nominal 576 kbit/s rate. Timing for downstream processing of the data communication channel is provided by the RLDCLK output. RLDCLK is derived from a 2.16 MHz clock that is gapped to yield an average frequency of 576 kHz.

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10.3.4 Error Monitor Block

The Error Monitor Block calculates the received line BIP-8 error detection codes based on the Line Overhead bytes and synchronous payload envelopes of the STS-3c (STM-1) stream. The line BIP-8 code is a bit interleaved parity calculation using even parity. Details are provided in the references. The calculated BIP-8 codes are compared with the BIP-8 codes extracted from the following frame. Any differences indicate that a line layer bit error has occurred. Optionally the RLOP can be configured to count a maximum of only one BIP error per frame.

This block also extracts the line FEBE code from the M1 byte. The FEBE code is contained in bits 2 to 8 of the M1 byte, and represents the number of line BIP-8 errors that were detected in the last frame by the far end. The FEBE code value has 25 legal values (0 to 24) for an STS-3c (STM-1) stream. Illegal values are interpreted as zero errors.

The Error Monitor Block accumulates B2 error events and FEBE events in two 20 bit saturating counter that can be read via the microprocessor interface. The contents of these counters may be transferred to internal holding registers by writing to any one of the counter addresses, or by using the TIP register bit feature. During a transfer, the counter value is latched and the counter is reset to 0 (or 1, if there is an outstanding event). Note, these counters should be polled at least once per second to avoid saturation.

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The B2 error events counters optionally can be configured to accumulate only "word" errors. A B2 word error is defined as the occurrence of one or more B2 bit error events during a frame. The B2 error counter is incremented by one for each frame in which a B2 word error occurs.

In addition the FEBE events counters optionally can be configured to accumulate only "word" events. In STS-3c (STM-1) framing a FEBE word event is defined as the occurrence of one or more FEBE bit events during a frame. The FEBE event counter is incremented by one for each frame in which a FEBE event occurs.

10.4 The Receive APS, Synchronization Extractor and Bit Error Monitor (RASE)

10.4.1 Automatic Protection Switch Control

The Automatic Protection Switch (APS) control block filters and captures the receive automatic protection switch channel bytes (K1 and K2) allowing them to be read via the RASE APS K1 Register and the RASE APS K2 Register. The bytes are filtered for three frames before being written to these registers. A protection switching byte failure alarm is declared when twelve successive frames have been received, where no three consecutive frames contain identical K1 bytes. The protection switching byte failure alarm is removed upon detection of three consecutive frames containing identical K1 bytes. The detection of invalid APS codes is done in software by polling the RASE APS K1 Register and the RASE APS K2 Register.

10.4.2 Bit Error Rate Monitor

The Bit Error Monitor Block (BERM) calculates the received line BIP-24 error detection code (B2) based on the line overhead and synchronous payload envelope of the receive data stream. The line BIP-24 code is a bit interleaved parity calculation using even parity. Details are provided in the references. The calculated BIP code is compared with the BIP-24 code extracted from the B2 byte(s) of the following frame. Any differences indicate that a line layer bit error has occurred. Up to 192000 (24 BIP/frame x 8000 frames/second) bit errors can be detected per second for STS-3c (STM-1) rate.

The BERM accumulates these line layer bit errors in a 20 bit saturating counter that can be read via the microprocessor interface. During a read, the counter value is latched and the counter is reset to 0 (or 1, if there is an outstanding event). Note, this counter should be polled at least once per second to avoid saturation which in turn may result in missed bit error events.

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The BERM block is able to simultaneously monitor for signal fail (SF) or signal degrade (SD) threshold crossing and provide alarms through software interrupts. The bit error rates associated with the SF or SD alarms are programmable over a range of 10-3 to 10-9. Details are provided in the Operations section.

In both declaring and clearing detection states, the accumulated BIP count is continuously compared against the threshold. This allows to rapidly declare in the presence of error bursts or error rates that significantly exceed the monitored BER. This behavior allows meeting the ITU -T G.783 detection requirements at various error rates (where the detection time is a function of the actual BER, for a given monitored BER.

10.4.3 Synchronization Status Extraction

The Synchronization Status Extraction (SSE) Block extracts the synchronization status (S1) byte from the line overhead. The SSE block can be configured to capture the S1 nibble after three or after eight frames with the same value (filtering turned on) or after any change in the value (filtering turned off). The S1 nibble can be read via the microprocessor interface. Optionally, the SSE can be configured to perform filtering based on the whole S1 byte. Although this mode of operation is not standard, it might become useful in the future.

PM5351 S/UNI-TETRA

10.5 Receive Path Overhead Processor (RPOP)

The Receive Path Overhead Processor (RPOP) provides pointer interpretation, extraction of path overhead, extraction of the synchronous payload envelope, and path level alarm indication and performance monitoring.

10.5.1 Pointer Interpreter

The Pointer Interpreter interprets the incoming pointer (H1, H2) as specified in the references. The pointer value is used to determine the location of the path overhead (the J1 byte) in the incoming STS-3c (STM-1) stream. The algorithm can be modeled by a finite state machine. Within the pointer interpretation algorithm three states are defined as shown below:

NORM_state (NORM) AIS_state (AIS) LOP_state (LOP)

The transition between states will be consecutive events (indications), e.g., three consecutive AIS indications to go from the NORM_state to the AIS_state. The kind and number of consecutive indications activating a transition is chosen such

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3 x eq_new_poin

t

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that the behavior is stable and insensitive to low BER. The only transition on a single event is the one from the AIS_state to the NORM_state after receiving a NDF enabled with a valid pointer value. It should be noted that, since the algorithm only contains transitions based on consecutive indications, this implies that, for example, non-consecutively received invalid indications do not activate the transitions to the LOP_state.

Figure 4: Pointer Interpretation State Diagram

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8 x

inv_point

LOP

inc_ind / dec_ind

8 x

NDF_enable

NORM

3 x

eq_new_point

3 x AI S_ind

8 x inv_point

NDF_enable

3 x

eq_new_point

3 x

AIS_ind

NDF_enable

AIS

The following table defines the events (indications) shown in the state diagram.

Table 1: Pointer Interpreter Event (Indications) Description

Event (Indication) Description

norm_point disabled NDF + ss + offset value equal to active offset NDF_enable enabled NDF + ss + offset value in range of 0 to 782 or

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enabled NDF + ss, if NDFPOR bit is set (Note that the current pointer is not updated by an enabled NDF if the pointer is out of range).

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AIS_ind H1 = 'hFF, H2 = 'hFF inc_ind disabled NDF + ss + majority of I bits inverted + no

majority of D bits inverted + previous NDF_enable, inc_ind or dec_ind more than 3 frames ago

dec_ind disabled NDF + ss + majority of D bits inverted + no

majority of I bits inverted + previous NDF_enable, inc_ind or dec_ind more than 3 frames ago

inv_point not any of above (i.e., not norm_point, and not

NDF_enable, and not AIS_ind, and not inc_ind and not dec_ind)

new_point disabled_NDF + ss + offset value in range of 0 to 782 but

not equal to active offset inc_req majority of I bits inverted + no majority of D bits inverted dec_req majority of D bits inverted + no majority of I bits inverted

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Note 1.- active offset is defined as the accepted current phase of the SPE

(VC) in the NORM_state and is undefined in the other states.

Note 2 - enabled NDF is defined as the following bit patterns: 1001, 0001,

1101, 1011, 1000.

Note 3 - disabled NDF is defined as the following bit patterns: 0110, 1110,

0010, 0100, 0111.

Note 4 - the remaining six NDF codes (0000, 0011, 0101, 1010, 1100, 1111)

result in an inv_point indication. Note 5 - ss bits are unspecified in SONET and has bit pattern 10 in SDH Note 6 - the use of ss bits in definition of indications may be optionally

disabled. Note 7 - the requirement for previous NDF_enable, inc_ind or dec_ind be

more than 3 frames ago may be optionally disabled. Note 8 - new_point is also an inv_point. Note 9 - LOP is not declared if all the following conditions exist:

• the received pointer is out of range (>782),

• the received pointer is static,

• the received pointer can be interpreted, according

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to majority voting on the I and D bits, as a positive or negative justification indication,

• after making the requested justification, the received pointer continues to be interpretable as a pointer justification.

When the received pointer returns to an in-range value, the S/UNI/TETRA will interpret it correctly.

Note 10 - LOP will exit at the third frame of a three frame sequence consisting

of one frame with NDF enabled followed by two frames with NDF disabled, if all three pointers have the same legal value.

The transitions indicated in the state diagram are defined in the following table.

Table 2: Pointer Interpreter Transition Description

Transition Description

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inc_ind/dec_ind offset adjustment (increment or decrement indication) 3 x eq_new_point three consecutive equal new_point indications NDF_enable single NDF_enable indication 3 x AIS_ind three consecutive AIS indications 8 x inv_point eight consecutive inv_point indications 8 x NDF_enable eight consecutive NDF_enable indications

Note 1 - the transitions from NORM_state to NORM_state do not represent

state changes but imply offset changes.

Note 2 - 3 x new_point takes precedence over other events and if the

IINVCNT bit is set resets the inv_point count.

Note 3 - all three offset values received in 3 x eq_new_point must be

identical.

Note 4 - "consecutive event counters" are reset to zero on a change of state

except for consecutive NDF count.

The Pointer Interpreter detects loss of pointer (LOP) in the incoming STS-3c (STM-1) stream. LOP is declared on entry to the LOP_state as a result of eight consecutive invalid pointers or eight consecutive NDF enabled indications. The alarm condition is reported in the receive alarm port and is optionally returned to

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the source node by signaling the corresponding Transmit Path Overhead Processor in the local S/UNI-TETRA to insert a path RDI indication.

The Pointer Interpreter detects path AIS in the incoming STS-3c (STM-1) stream. PAIS is declared on entry to the AIS_state after three consecutive AIS indications. The alarm condition reported in the receive alarm port and is optionally returned to the source node by signaling the corresponding Transmit Path Overhead Processor in the local SONET/SDH equipment to insert a path RDI indication.

Invalid pointer indications (inv_point), invalid NDF codes, new pointer indications (new_point), discontinuous change of pointer alignment, and illegal pointer changes are also detected and reported by the Pointer Interpreter block via register bits. An invalid NDF code is any NDF code that does not match the NDF enabled or NDF disabled definitions. The third occurrence of equal new_point indications (3 x eq_new_point) is reported as a discontinuous change of pointer alignment event (DISCOPA) instead of a new pointer event and the active offset is updated with the receive pointer value. An illegal pointer change is defined as a inc_ind or dec_ind indication that occurs within three frames of the previous inc_ind, dec_ind or NDF_enable indications. Illegal pointer changes may be optionally disabled via register bits.

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The active offset value is used to extract the path overhead from the incoming stream and can be read from an internal register.

10.5.2 SPE Timing

The SPE Timing Block provides SPE timing information to the Error Monitor and the Extract blocks. The block contains a free running timeslot counter that is initialized by a J1 byte identifier (which identifies the first byte of the SPE). Control signals are provided to the Error Monitor and the Extract blocks to identify the Path Overhead bytes and to downstream circuitry to extract the ATM cell or POS payload.

10.5.3 Error Monitor

The Error Monitor Block contains two 16-bit counters that are used to accumulate path BIP-8 errors (B3), and far end block errors (FEBEs). The contents of the two counters may be transferred to holding registers, and the counters reset under microprocessor control.

Path BIP-8 errors are detected by comparing the path BIP-8 byte (B3) extracted from the current frame, to the path BIP-8 computed for the previous frame.

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FEBEs are detected by extracting the 4-bit FEBE field from the path status byte (G1). The legal range for the 4-bit field is between 0000 and 1000, representing zero to eight errors. Any other value is interpreted as zero errors.

Path RDI alarm is detected by extracting bit 5 of the path status byte. The PRDI signal is set high when bit 5 is set high for five/ten consecutive frames. PRDI is set low when bit 5 is low for five/ten consecutive frames. Auxiliary RDI alarm is detected by extracting bit 6 of the path status byte. The Auxiliary RDI alarm is indicated when bit 6 is set high for five/ten consecutive frames. The Auxiliary RDI alarm is removed when bit 6 is low for five/ten consecutive frames. The Enhanced RDI alarm is detected when the enhanced RDI code in bits 5,6,7 of the path status byte indicates the same error codepoint for five/ten consecutive frames. The Enhanced RDI alarm is removed when the enhanced RDI code in bits 5,6,7 of the path status byte indicates the same non error codepoint for five/ten consecutive frames. The ERDII maskable interrupt is set high when bits 5, 6 & 7 of the path status byte (G1) byte are set to a new codepoint for five or ten consecutive frames. The ERDIV[2:0] signal reflects the state of the filtered ERDI value (G1 byte bits 5, 6, & 7).

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10.6 Receive ATM Cell Processor (RXCP)

The Receive ATM Cell Processor (RXCP) performs ATM cell delineation, provides cell filtering based on idle/unassigned cell detection and HCS error detection, and performs ATM cell payload de-scrambling. The RXCP also provides a four cell deep receive FIFO. This FIFO is used to separate the STS-3c (STM-1) line timing from the higher layer ATM system timing.

10.6.1 Cell Delineation

Cell Delineation is the process of framing to ATM cell boundaries using the header check sequence (HCS) field found in the cell header. The HCS is a CRC-8 calculation over the first 4 octets of the ATM cell header. When performing delineation, correct HCS calculations are assumed to indicate cell boundaries. Cells are assumed to be byte-aligned to the synchronous payload envelope. The cell delineation algorithm searches the 53 possible cell boundary candidates individually to determine the valid cell boundary location. While searching for the cell boundary location, the cell delineation circuit is in the HUNT state. When a correct HCS is found, the cell delineation state machine locks on the particular cell boundary, corresponding to the correct HCS, and enters the PRESYNC state. The PRESYNC state validates the cell boundary location. If the cell boundary is invalid, an incorrect HCS will be received within the next DELTA cells, at which time a transition back to the HUNT state is executed. If no HCS errors are detected in this PRESYNC period, the SYNC state is entered.

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While in the SYNC state, synchronization is maintained until ALPHA consecutive incorrect HCS patterns are detected. In such an event a transition is made back to the HUNT state. The state diagram of the delineation process is shown in Figure 5.

Figure 5: Cell Delineation State Diagram

HUNT

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correct HCS (byte by byte)

Incorrect HCS (cell by cell)

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PRESYNC

ALPHA consecutive incorrect HCS's (cell by cell)

The values of ALPHA and DELTA determine the robustness of the delineation process. ALPHA determines the robustness against false misalignments due to bit errors. DELTA determines the robustness against false delineation in the synchronization process. ALPHA is chosen to be 7 and DELTA is chosen to be 6. These values result in an average time to delineation of 33.66 µs for the STS-3c (STM-1) rate.

10.6.2 Descrambler

The self synchronous descrambler operates on the 48 byte cell payload only. The circuitry descrambles the information field using the x43 + 1 polynomial. The descrambler is disabled for the duration of the header and HCS fields and may optionally be disabled for the payload.

SYNC

DELTA consecutive correct HCS's (cell by cell)

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10.6.3 Cell Filter and HCS Verification

Cells are filtered (or dropped) based on HCS errors and/or a cell header pattern. Cell filtering is optional and is enabled through the RXCP registers. Cells are passed to the receive FIFO while the cell delineation state machine is in the SYNC state as described above. When both filtering and HCS checking are enabled, cells are dropped if uncorrectable HCS errors are detected, or if the corrected header contents match the pattern contained in the RXCP Match Header Pattern and RXCP Match Header Mask registers. Idle or unassigned cell filtering is accomplished by writing the appropriate cell header pattern into the RXCP Match Header Pattern and RXCP Match Header Mask registers. Idle/Unassigned cells are assumed to contain the all zeros pattern in the VCI and VPI fields. The RXCP Match Header Pattern and RXCP Match Header Mask registers allow filtering control over the contents of the GFC, PTI, and CLP fields of the header.

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The HCS is a CRC-8 calculation over the first 4 octets of the ATM cell header. The RXCP block verifies the received HCS using the polynomial, x8 + x2 + x + 1. The coset polynomial, x6 + x4 + x2 + 1, is added (modulo 2) to the received HCS octet before comparison with the calculated result. While the cell delineation state machine (described above) is in the SYNC state, the HCS verification circuit implements the state machine shown in Figure 6.

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Figure 6: HCS Verification State Diagram

ATM DELINEATION

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SYNC STATE

Apparent Multi-Bit Error

(Drop Cell)

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ALPHA consecutive incorrect HCS's (To HUNT state)

No Errors

Detected

(Pass Cell)

DELTA consecutive correct HCS's (From PRESYNC state)

CORRECTION

MODE

No Errors Detected

In M Cells

(Pass M Cell)

Single-Bit Error

(Correct Error

and Pass Cell)

th

Errors

Detected

(Drop Cell)

DETECTION

MODE

No Errors Detected

(Pass Cell)

In normal operation, the HCS verification state machine remains in the 'Correction Mode' state. Incoming cells containing no HCS errors are passed to the receive FIFO. Incoming single-bit errors are corrected, and the resulting cell is passed to the FIFO. Upon detection of a single-bit error or a multi-bit error, the state machine transitions to the 'Detection Mode' state. In this state, programmable HCS error filtering is provided. The detection of any HCS error causes the corresponding cell to be dropped. The state machine transitions back to the 'Correction Mode' state when M (where M = 1, 2, 4, 8) cells are received with correct HCSs. The Mth cell is not discarded.

10.6.4 Performance Monitor

The Performance Monitor consists of two 8-bit saturating HCS error event counters and a 19-bit saturating receive cell counter. One of the counters accumulates correctable HCS errors which are HCS single-bit errors detected and corrected while the HCS Verification state machine is in the 'Correction Mode' state. The second counter accumulates uncorrectable HCS errors which are HCS bit errors detected while the HCS Verification state machine is in the

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'Detection Mode' state or HCS bit errors detected but not corrected while the state machine is in the 'Correction Mode' state. The 19-bit receive cell counter counts all cells written into the receive FIFO. Filtered cells are not counted.

Each counter may be read through the microprocessor interface. Circuitry is provided to latch these counters so that their values can be read while simultaneously resetting the internal counters to 0 or 1, if appropriate, so that a new period of accumulation can begin without loss of any events. It is intended that the counter be polled at least once per second so as not to miss HCS error events.

10.7 Receive POS Frame Processor (RXFP)

The Receive POS Frame Processor (RXFP) performs packet extraction, provides FCS error correction, performs packet payload de-scrambling, and provides performance monitoring functions. The RXFP also provides a 256 byte deep receive FIFO. This FIFO is used to separate the STS-3c (STM-1) line timing from the link layer system timing, and to handle timing differences caused by the removal of escape characters.

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10.7.1 Overhead Removal

The overhead removal consist of striping SONET/SDH overhead bytes from the data stream. Once overhead bytes are removed, the data stream consists of POS frame octets which can be fed directly to the descrambler or the POS Frame Delineation block.

10.7.2 Descrambler

When enabled, the self-synchronous descrambler operates on the POS Frame data, de-scrambling the data with the polynomial x43 + 1. De-scrambling is performed on the raw data stream, before any POS frame delineation or byte destuffing is performed. Data scrambling can provide for a more robust system preventing the injection of hostile patterns into the data stream.

10.7.3 POS Frame Delineation

This block accepts data one byte at a time and arranges it as POS framed octets. Frame boundaries are found by searching for the Flag Character (0x7E). Flags are also used to fill inter-packet spacing. This block removes the Flag Sequence and passes the data onto the Byte Destuffing block.

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The POS Frame Delineation is performed on the descrambled data and consists of arranging the POS framed octets. Frame boundaries are found by searching for the Flag Character (0x7E). Flags are also used to fill inter-packet spacing. This block removes the Flag Sequence and passes the data onto the Byte Destuffing block. The POS Frame format is shown on Figure 7.

Figure 7: Packet Over SONET/SDH Frame Format

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Flag Information FCS Flag

In the event of a FIFO overflow caused by the FIFO being full while a packet is being received, the packet is marked with an error so it can be discarded by the system. Following bytes associated with this now aborted frame are discarded. Reception of POS data resumes when a Start of Packet is encountered and the FIFO level is below the programmable Reception Initialization Level (RIL[7:0]).

10.7.4 Byte Destuffing

The byte destuffing algorithm searches for the Control Escape character (0x7D). These characters are added for transparency in the transmit direction, as shown in Table 3, and must be removed to recover the user data. When the Control Escape character is encountered, it is removed and the following data byte is XORed with 0x20. Only the Flag Sequence (0x7E) and the Control Escape character itself are expected to have been escaped in the transmit direction, but this implementation does not preclude escaping other values as well.

Flag

Packet

(PPP or other)

POS Frame

10.7.5 FCS Check

The FCS Generator performs a CRC-CCITT or CRC-32 calculation on the whole POS frame, after byte destuffing and data de-scrambling. A parallel implementation of the CRC polynomial is used. The CRC algorithm for the frame

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Table 3: Byte Destuffing

Original Escaped

7E (Flag Sequence) 7D-5E 7D (Control Escape) 7D-5D Aborted Packet 7D-7E

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checking sequence (FCS) field is either a CRC-CCITT or CRC-32 function. The CRC-CCITT is two bytes in size and has a generating polynomial g(X) = 1 + X5 + X12 + X16. The CRC-32 is four bytes in size and has a generating polynomial g(X) = 1 + X + X2 + X4 + X5 + X7 + X8 + X10 + X11 + X12 + X16 + X22 + X23 + X + X32. The first FCS bit transmitted is the coefficient of the highest term. The RXFP-50 implements a CRC decoder that uses a CRC encoder. The coder registers are preset to ones. Then the packet data and CRC are feed in. The result should be a constant number provided in the HDLC documentation. A different value indicates an error. Packets with FCS errors are marked as such and should be discarded by the system.

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Figure 8: CRC Decoder

g

1

2

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g

n-1

26

Message

+

D

10.7.6 Performance Monitor

The Performance Monitor consists of four 16-bit saturating error event counters and one 24-bit saturating received good packet counter. One of the error event counters accumulates FCS errors. The second error event counter accumulates minimum length violation packets. The third error event counter accumulates maximum length violation packets. The fourth error event counter accumulates aborted packets. The 24-bit receive good packet counter counts all error free packets.

Each counter may be read through the microprocessor interface. Circuitry is provided to latch these counters so that their values can be read while simultaneously resetting the internal counters to 0 or 1, whichever is appropriate, so that a new period of accumulation can begin without loss of any events. The counters are intended to be polled at least once per second so error events will not be missed.

The RXFP-50 monitors the packets for both minimum and maximum length errors. When a packet size is smaller than MINPL[7:0], the packet is marked with an error but still written into the FIFO. Misformed packets, that is packets that do not at least contain the FCS field plus one byte, are treated differently. If a

0

+

D

1

. . .

+ +

D

n-1

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misformed packet is received and FCS stripping is enabled, the packet is discarded, not written in the FIFO, and counted as a minimum packet size violation. If a misformed packet is received and FCS stripping is disabled, it is written into the FIFO since in this case the misformed packet criteria is reduced to one byte, but will still count as a minimum packet size violation. When the packet size exceeds MAXPL[15:0] the packet is marked with an error and the exceeding bytes are discarded.

Packet greater than 64k bytes are not supported. When the MAXPL is set to 0xFFFF, a packet of length greater than 0xFFFF will generate an MINLI instead of a MAXLI. When the MAXPL value is less than 0xFFFF, the behaviour will be normal for any packet length less than, equal or greater than 0xFFFF. It is recommended to only set MAXPL to a value smaller or equal to 0xFFFE.

10.7.7 Receive FIFO

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The Receive FIFO block contains storage for 256 octets, along with management circuitry for reading and writing the FIFO. The receive FIFO provides for the separation of the physical layer timing from the system timing.

Receive FIFO management functions include filling the receive FIFO, indicating when packets or bytes are available to be read from the receive FIFO, maintaining the receive FIFO read and write pointers, and detecting FIFO overrun and underrun conditions. Upon detection of an overrun, the FIFO aborts the current packet and discards the current incoming bytes until there is room in the FIFO. Once enough room is available, as defined by the RIL[7:0] register, the RXFP-50 will wait for the next start of packet before writing any data into the FIFO. FIFO overruns are indicated through a maskable interrupt and register bit and are considered a system error. A FIFO underrun is caused when the System Interface tries to read more data words while the FIFO is empty. This action will be detected and reported through the FUDRI interrupt, but it is not considered a system error. The system will continue to operate normally. In that situation, RVAL can be used by the Link Layer device to find out if valid or invalid data is provided on the System Interface.

10.8 Transmit Line Interface (CSPI)

The Transmit Line Interface allows to directly interface the S/UNI-TETRA with optical modules (ODLs) or other medium interfaces. This block performs clock synthesis and performs parallel to serial conversion of the incoming outgoing

155.52 Mbit/s data stream.

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10.8.1 Clock Synthesis

The transmit clock is synthesized from a 19.44 MHz reference. The transfer function yields a typical low pass corner of 2.0 MHz above which reference jitter is attenuated at 12 dB per octave. The design of the loop filter and PLL is optimized for minimum intrinsic jitter. With a jitter free 19.44 MHz reference, the intrinsic jitter is typically less than 0.01 UI RMS when measured using a high pass filter with a 12 kHz cutoff frequency.

The REFCLK reference should be within ±20 ppm to meet the SONET free-run accuracy requirements specified in GR-253-CORE.

10.8.2 Parallel to Serial Converter

The Parallel to Serial Converter (PISO) converts the transmit byte serial stream to a bit serial stream. Every self-timed channel (a self-timed channel is one that uses the CSU output clock) share a common line rate clock and byte clock, which can be output as TCLK. Only self-timed channels can be synchronized using the TFPI input. When a channel is loop-timed, TCLK, TFPI and TFPI are no more available and the receive signals shall be used instead to extract timing information.

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10.9 Transmit Section Overhead Processor (TSOP)

The Transmit Section Overhead Processor (TSOP) provides frame pattern insertion (A1, A2), scrambling, section level alarm signal insertion, and section BIP-8 (B1) insertion.

10.9.1 Line AIS Insert

Line AIS insertion results in all bits of the SONET/SDH frame being set to 1 before scrambling except for the section overhead. The Line AIS Insert Block substitutes all ones as described when enabled through an internal register (Register 0x14 TSOP) accessed through the microprocessor interface. Activation or deactivation of line AIS insertion is synchronized to frame boundaries.

10.9.2 Data Link Insert

The Data Link Insert Block inserts the section data communication channel (bytes D1, D2, and D3) into the STS-3c (STM-1) stream when enabled by an internal register accessed via the common bus interface. The bytes to be inserted are serially input on signal TSD at a nominal 192 kbit/s rate. Timing for upstream processing of the data communication channel is provided by the

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TSDCLK signal that is output by the Data Link Insert Block. TSDCLK is derived from a 216 kHz clock that is gapped to yield an average frequency of 192 kHz. TSD is sampled with timing aligned to TSDCLK

10.9.3 BIP-8 Insert

The BIP-8 Insert Block calculates and inserts the BIP-8 error detection code (B1) into the transmit stream.

The BIP-8 calculation is based on the scrambled data of the complete STS-3c (STM-1) frame. The section BIP-8 code is based on a bit interleaved parity calculation using even parity. Details are provided in the references. The calculated BIP-8 code is then inserted into the B1 byte of the following frame before scrambling. BIP-8 errors may be continuously inserted under register control for diagnostic purposes.

10.9.4 Framing and Identity Insert

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The Framing and Identity Insert Block inserts the framing bytes (A1, A2) and trace/growth bytes (J0/Z0) into the STS-3c (STM-1) frame. Framing bit errors may be continuously inserted under register control for diagnostic purposes.

10.9.5 Scrambler

The Scrambler Block utilizes a frame synchronous scrambler to process the transmit stream when enabled through an internal register accessed via the microprocessor interface. The generating polynomial is x7 + x6 + 1. Precise

details of the scrambling operation are provided in the references. Note that the framing bytes and the identity bytes are not scrambled. All zeros may be continuously inserted (after scrambling) under register control for diagnostic purposes.

10.10 Transmit Line Overhead Processor (TLOP)

The Transmit Line Overhead Processor (TLOP) provides line level alarm signal insertion, and line BIP-24 insertion (B2).

10.10.1 APS Insert

The APS Insert Block inserts the two automatic protection switch (APS) channel bytes in the Line Overhead (K1 and K2) into the transmit stream when enabled by an internal register.

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10.10.2 Data Link Insert

The Data Link Insert Block inserts the line data communication channel (DCC) (bytes D4 to D12) into the STS-3c (STM-1) stream when enabled by an internal register. The D4 to D12 bytes are input serially using the TLD signal at a nominal 576 kbit/s rate. Timing for processing of the line DCC is provided by the TLDCLK output. TLDCLK is derived from a 2.16 MHz clock that is gapped to yield an average frequency of 576 kHz.

10.10.3 Line BIP Calculate

The Line BIP Calculate Block calculates the line BIP-24 error detection code (B2) based on the line overhead and synchronous payload envelope of the transmit stream. The line BIP-24 code is a bit interleaved parity calculation using even parity. Details are provided in the references. The calculated BIP-24 code is inserted into the B2 byte positions of the following frame. BIP-24 errors may be continuously inserted under register control for diagnostic purposes.

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10.10.4 Line RDI Insert

The Line RDI Insert Block controls the insertion of line remote defect indication. Line RDI insertion is enabled using the TLRDI input, or register control. Line RDI is inserted by transmitting the code 110 (binary) in bit positions 6, 7, and 8 of the K2 byte contained in the transmit stream.

10.10.5 Line FEBE Insert

The Line FEBE Insert Block accumulates line BIP-24 errors (B2) detected by the Receive Line Overhead Processor and encodes far end block error indications in the transmit M1 byte.

10.11 Transmit Path Overhead Processor (TPOP)

The Transmit Path Overhead Processor (TPOP) provides transport frame alignment generation, pointer generation (H1, H2), path overhead insertion and the insertion of path level alarm signals.

10.11.1 Pointer Generator

The Pointer Generator Block generates the outgoing payload pointer (H1, H2) as specified in the references. The concatenation indication (the NDF field set to

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1001, I-bits and D-bits set to all ones, and unused bits set to all zeros) is inserted in the second and third pointer byte locations in the transmit stream.

• (1) A "normal pointer value" locates the start of the SPE. Note: 0 ≤ "normal pointer value" ≤ 782, and the new data flag (NDF) field is set to 0110. Note that values greater than 782 may be inserted, using internal registers, to generate a loss of pointer alarm in downstream circuitry.

• (2) Arbitrary "pointer values" may be generated using internal registers. These new values may optionally be accompanied by a programmable new data flag. New data flags may also be generated independently using internal registers.

• (3) Positive pointer movements may be generated using a bit in an internal register. A positive pointer movement is generated by inverting the five I-bits of the pointer word. The SPE is not inserted during the positive stuff opportunity byte position, and the pointer value is incremented by one. Positive pointer movements may be inserted once per frame for diagnostic purposes.

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• (4) Negative pointer movements may be generated using a bit in an internal register. A negative pointer movement is generated by inverting the five Dbits of the pointer word. The SPE is inserted during the negative stuff opportunity byte position, the H3 byte, and the pointer value is decremented by one. Negative pointer movements may be inserted once per frame for diagnostic purposes.

The pointer value is used to insert the path overhead into the transmit stream. The current pointer value may be read via internal registers.

10.11.2 BIP-8 Calculate

The BIP-8 Calculate Block performs a path bit interleaved parity calculation on the SPE of the transmit stream. Details are provided in the references. The resulting parity byte is inserted in the path BIP-8 (B3) byte position of the subsequent frame. BIP-8 errors may be continuously inserted under register control for diagnostic purposes.

10.11.3 FEBE Calculate

The FEBE Calculate Block accumulates far end block errors on a per frame basis, and inserts the accumulated value (up to maximum value of eight) in the FEBE bit positions of the path status (G1) byte. The FEBE information is derived

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from path BIP-8 errors detected by the receive path overhead processor, RPOP. Far end block errors may be inserted under register control for diagnostic purposes.

10.12 Transmit ATM Cell Processor (TXCP)

The Transmit ATM Cell Processor (TXCP) provides rate adaptation via idle/unassigned cell insertion, provides HCS generation and insertion, and performs ATM cell scrambling. The TXCP contains a four cell transmit FIFO. An idle or unassigned cell is transmitted if a complete ATM cell has not been written into the FIFO.

10.12.1 Idle/Unassigned Cell Generator

The Idle/Unassigned Cell Generator inserts idle or unassigned cells into the cell stream when enabled. Registers are provided to program the GFC, PTI, and CLP fields of the idle cell header and the idle cell payload. The idle cell HCS is automatically calculated and inserted.

PM5351 S/UNI-TETRA

10.12.2 Scrambler

The Scrambler scrambles the 48 octet information field. Scrambling is performed using a parallel implementation of the self synchronous scrambler (x43 + 1 polynomial) described in the references. The cell headers are transmitted unscrambled, and the scrambler may optionally be disabled.

10.12.3 HCS Generator

The HCS Generator performs a CRC-8 calculation over the first four header octets. A parallel implementation of the polynomial, x8+x2+x+1, is used. The coset polynomial, x6+x4+x2+1, is added (modulo 2) to the residue. The HCS

Generator optionally inserts the result into the fifth octet of the header.

10.13 Transmit POS Frame Processor (TXFP)

The Transmit POS Frame Processor (TXFP) provides rate adaptation by transmitting flag sequences (0x7E) between packets, provides FCS generation and insertion, performs packet data scrambling, and provides performance monitoring functions. The TXFP contains a 256 byte transmit FIFO. This FIFO is used to separate the STS-3c (STM-1) line timing from the link layer system timing, and to handle timing differences caused by insertion of escape characters.

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10.13.1 Transmit FIFO

The Transmit FIFO is responsible for holding packets provided through the Input Interface until they are transmitted. The transmit FIFO can accommodate a maximum of 256 bytes. There is no limit on the number of packets that can be stored, other than the FIFO depth limitation. Octets are written in with a single 16 bit data bus running off TFCLK and are read out with a single 8-bit data bus running off the SONET/SDH clock. Separate read and write clock domains provide for separation of the physical layer line timing (PICLK) from the System Link layer timing (TFCLK).

Internal read and write pointers track the insertion and removal of octets, and indicate the fill status of the Transmit FIFO. These status indications are used to detect underrun and overrun conditions, abort packets as appropriate on both System and Line sides, control flag insertion and to generate the TPA outputs.

The TXFP does not abort packets under an overrun condition. The packet will be sent and will appear as a good packet with a good FCS. Overruns should never occur in normal system operating conditions, thus this limitation should not affect the system performance. Overruns can be avoided by setting the high and low watermarks. The optimal setup depends on the system design.

PMC-Sierra, Inc.

PM5351 S/UNI-TETRA

10.13.2 POS Frame Generator

The POS Frame Generator runs off of the SONET/SDH sequencer to create the POS frames to be transmitted, whose format is shown in Figure 7. Flags are inserted whenever the Transmit FIFO is empty and there is no data to transmit. When there is enough data to be transmitted, the block operates normally; it removes the packets from the Transmit FIFO and transmits them. In addition, FCS generation, error insertion, byte stuffing, and scrambling can be optionally enabled.

Figure 9: Packet Over SONET/SDH Frame Format

Flag Information FCS Flag

Packet

(PPP or other)

In the event of a FIFO underflow caused by the FIFO being empty while a packet is being transmitted, the packet is aborted by transmitting the Abort Sequence.

Flag

POS Frame

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The Abort Sequence consists of an Escape Control character (0x7D) followed by the Flag Sequence (0x7E). Bytes associated with this aborted frame are still read from the FIFO but are discarded and replaced with the Flag Sequence in the outgoing data stream. Transmission of data resumes when a Start of Packet is encountered in the FIFO data stream.

The POS Frame Generator also performs Inter Packet Gaping. This operation consists of inserting a programmable number of Flag Sequence characters between each POS Frame transmission. This feature allows to control the system effective data transmission rate if required.

10.13.3 FCS Generator

The FCS Generator performs a CRC-CCITT or CRC-32 calculation on the whole POS frame, before byte stuffing and data scrambling. A parallel implementation of the CRC polynomial is used. The CRC algorithm for the frame checking sequence (FCS) field is either a CRC-CCITT or CRC-32 function. The CRCCCITT is two bytes in size and has a generating polynomial g(X) = 1 + X5 + X12 + X16. The CRC-32 is four bytes in size and has a generating polynomial g(X) = 1 + X + X2 + X4 + X5 + X7 + X8 + X10 + X11 + X12 + X16 + X22 + X23 + X26 + X32. The first FCS bit transmitted is the coefficient of the highest term. When transmitting a packet from the Transmit FIFO, the FCS Generator appends the result after the last data byte, before the closing flag. Note that the Frame Check Sequence is the one's complement of the CRC register after calculation ends. FCS calculation and insertion can be disabled.

PMC-Sierra, Inc.

PM5351 S/UNI-TETRA

Figure 10: CRC Generator

g

1

D

0

LSB MSB

D

1

g

2

D

2

Parity Che ck Digits

g

n-1

D

n -1

An error insertion mechanism is provided for system diagnosis purposes. Error insertion is performed by inverting the resulting FCS value, before transmission. This should cause an FCS Error at the far end.

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10.13.4 Byte Stuffing

The POS Frame generator provides transparency by performing byte stuffing. This operation is done after the FCS calculation. Two characters need to be escaped, the Flag Sequence (0x7E) and the Escape Character itself (0x7D). When a character is being escaped, it is XORed with 0x20 before transmission and preceded by the Control Escape (0x7D) character.

Original Escaped

7E (Flag Sequence) 7D-5E 7D (Control Escape) 7D-5D Abort Sequence 7D-7E

10.13.5 Data Scrambling

PMC-Sierra, Inc.

Table 4: Byte Stuffing

PM5351 S/UNI-TETRA

The Scrambler will optionally scramble the whole packet data, including the FCS and the flags. Scrambling is performed after the POS frame is formed using a

parallel implementation of the self synchronous scrambler polynomial, x43+1. On reset, the scrambler is set to all ones to ensure scrambling on start-up. The scrambler may optionally be completely disabled. Data scrambling can provide for a more robust system preventing the injection of hostile patterns into the data stream.

10.13.6 SONET/SDH Framer

The SONET/SDH Framer gaps the POS frames in order to insert the SONET/SDH framing and overhead bytes (Section/Line Overhead and Path Overhead). The framer uses framing alignment information provided by the RPOP to perform its function. The TXFP does not set any SONET/SDH overhead byte.

10.14 SONET/SDH Section and Path Trace Buffers (SSTB and SPTB)

The SONET/SDH Section Trace Buffer (SSTB) block and the SONET/SDH Path Trace Buffer (SPTB) block are identical. The blocks can handle both 64-byte CLLI messages in SONET and 16-byte E.164 messages in SDH. The generic SONET/SDH Trace Buffer (STB) block is described below.

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Datasheet PM5351-BI Datasheet (PMC)

Specifications and Main Features

Frequently Asked Questions

User Manual

REVISION HISTORY

CONTENTS

LIST OF REGISTERS

LIST OF FIGURES

LIST OF TABLES

1 FEATURES

2 APPLICATIONS

3 REFERENCES

4 DEFINITIONS

5 APPLICATION EXAMPLES

6 BLOCK DIAGRAM

7 DESCRIPTION

8 PIN DIAGRAM

9 PIN DESCRIPTION

10.10.1 APS Insert

10.10.2 Data Link Insert

10.10.4 Line RDI Insert

10.10.5 Line FEBE Insert

10.11.1 Pointer Generator

10.11.2 BIP-8 Calculate

10.11.3 FEBE Calculate

10.12.1 Idle/Unassigned Cell Generator

10.12.2 Scrambler

10.12.3 HCS Generator

10.13.1 Transmit FIFO

10.13.2 POS Frame Generator

10.13.3 FCS Generator

10.13.4 Byte Stuffing

10.13.5 Data Scrambling

10.13.6 SONET/SDH Framer