18.3ATM SYSTEM INTERFACE TIMING................................................................234
18.4TRANSMIT AND RECEIVE FRAME PULSES.................................................238
18.5JTAG TEST PORT TIMING...............................................................................239
19ORDERING AND THERMAL INFORMATION...............................................................242
20MECHANICAL INFORMATION .....................................................................................244
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1 FEATURES
1.1 General
Single chip QUAD ATM User-Network Interface operating at 155.52 Mbit/s.
•
Implements the ATM Forum User Network Interface Specification and the
•
ATM physical layer for Broadband ISDN according to CCITT
Recommendation I.432.
Processes duplex 155.52 Mbit/s STS-3c (STM-1) data streams with on-chip
•
clock and data recovery and clock synthesis.
Exceeds Bellcore GR-253-CORE jitter tolerance and intrinsic jitter criteria.
•
Fully implements the ATM Forum’s Utopia Level 2 Specification with Multi-
•
PHY addressing and parity support.
Provides a standard 5 signal IEEE 1149.1 JTAG test port for boundary scan
•
board test purposes.
Provides a generic 8-bit microprocessor bus interface for configuration,
•
control, and status monitoring.
Low power 3.3V CMOS with PECL and TTL compatible inputs and
•
CMOS/TTL outputs, with 5V tolerance inputs (system side interface is 3.3V
only).
Industrial temperature range (-40°C to +85°C).
•
304 pin Super BGA package.
•
1.2 The SONET Receiver
Provides a serial interface at 155.52 Mbit/s.
•
Recovers the clock and data.
•
Frames to and de-scrambles the recovered stream.
•
Detects signal degrade (SD) and signal fail (SF) threshold crossing alarms
•
based on received B2 errors.
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Captures and debounces the synchronization status (S1) byte in a readable
•
PM5349 S/UNI-QUAD
register.
Filters and captures the automatic protection switch channel (K1, K2) bytes in
•
readable registers and detects APS byte failur e.
Counts received section BIP-8 (B1) errors, received line BIP-24 (B2) errors,
•
line far end block errors (FEBE), received path BIP-8 (B3) errors and path far
end block errors (FEBE).
Detects loss of signal (LOS), out of frame (OOF), loss of frame (LOF), line
•
alarm indication signal (LAIS), line remote defect indication (LRDI), loss of
pointer (LOP), path alarm indication signal (PAIS), path remote defect
indication (PRDI) and path extended remote defect indicator (PERDI).
Interprets the received payload pointer (H1, H2) and extracts the STS-3c
•
(STM-1) synchronous payload envelope and path overhead.
Provides individual divide by 8 recovered clocks (19.44 MHz) for each
•
channel.
Provides individual 8KHz receive frame pulses for each channel.
•
1.3 The Receive ATM Processor
Extracts ATM cells from the received STS-3c (STM-1) synchronous payload
•
envelope using ATM cell delineation.
Provides ATM cell payload de-scrambling.
•
Performs header check sequence (HCS) error detection and correction, and
•
idle/unassigned cell filtering.
Detects Out of Cell Delineation (OCD) and Loss of Cell Delineation (LCD).
•
Counts number of received cells, idle cells, errored cells and dropped cells.
•
Provides a synchronous 8-bit wide, four-cell FIFO buffer.
•
1.4 The SONET Transmitter
Synthesizes the 155.52 MHz transmit clock from a 19.44 MHz reference.
•
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Provides a differential TTL serial interface (can be adapted to PECL levels) at
•
PM5349 S/UNI-QUAD
155.52 Mbit/s.
Provides a single transmit frame pulse input across the four channels to align
•
the transport frames to a system reference.
Provides a single transmit byte clock (divide by eight of the synthesized line
•
rate clock) to provide a timing reference for the transmit outputs.
Optionally inserts register programmable APS (K1, K2) and synchronization
•
status (S1) bytes.
Optionally inserts path alarm indication signal (PAIS), path remote defect
•
indication (PRDI), line alarm indication signal (LAIS) and line remote defect
indication (LRDI).
Inserts path BIP-8 codes (B3), path far end block error (G1) indications, line
•
BIP-24 codes (B2), line far end block error (M1) indications, and section BIP-8
codes (B1) to allow performance monitoring at the far end.
Scrambles the transmitted STS-3c (STM-1) stream and inserts the framing
•
bytes (A1, A2).
Inserts ATM cells into the transmitted STS-3c (STM-1) synchronous payload
•
envelope.
1.5 The Transmit ATM Processor
Provides idle/unassigned cell insertion.
•
Provides HCS generation/insertion, and ATM cell payload scrambling.
•
Counts number of transmitted and idle cells.
•
Provides a synchronous 8-bit wide, four cell FIFO buffer.
•
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2 APPLICATIONS
LAN switches and hubs.
•
Layer 3 switches.
•
Multiservice switches (FR, ATM, IP, etc..).
•
Gibabit and terabit routers.
•
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3 REFERENCES
Bell Communications Research - GR-253-CORE “SONET Transport Systems:
•
Common Generic Criteria”, Issue 2, December 1995.
Bell Communications Research - GR-436-CORE “Digital Network
•
Synchronization Plan”, Issue 1 Revision 1, June 1996..
ITU-T Recommendation G.703 - "Physical/Electrical Characteristics of
•
Hierarchical Digital Interfaces", 1991.
ITU-T Recommendation G.704 - "General Aspects of Digital Transmission
•
Systems; Terminal Equipment - Synchronous Frame Structures Used At 1544,
6312, 2048, 8488 and 44 736 kbit/s Hierarchical Levels", July, 1995.
ITU, Recommendation G.707 - "Network Node Interface For The Synchronous
•
Digital Hierarchy", 1996.
ITU Recommendation G781, “Structure of Recommendations on Equipment
•
for the Synchronous Design Hierarchy (SDH)”, January 1994.
ITU, Recommendation G.783 - "Characteristics of Synchronous Digital
•
Hierarchy (SDH) Equipment Functional Blocks", 1996.
ITU Recommendation I.432, “ISDN User Network Interfaces”, March 93.
•
ATM Forum - ATM User-Network Interface Specification, V3.1, October, 1995.
•
ATM Forum - “UTOPIA, An ATM P HY Interface Specification, Level 2, Version
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y
y
[
]
]
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p
S/UNI-QUAD
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PM5349 S/UNI-QUAD
5 APPLICATION EXAMPLES
The PM5349 S/UNI-QUAD is intended for use in equipment implementing
Asynchronous Transfer Mode (ATM) User-Network Interfaces (UNI). The S/UNIQUAD may find application at either end of switch-to-switch links or switch-toterminal links. The S/UNI-QUAD performs the ma pping of ATM cells into the
SONET/SDH STS-3c (STM-1) synchronous payload envelope (SPE) and
processes applicable SONET/SDH section, line and path overhead.
In a typical STS-3c (STM-1) ATM application, the S/UNI-QUAD performs clock
and data recovery for the receive direction and clock synthesis for the transmit
direction of the line interface. On the system side, the S/UNI-QUAD interfaces
directly with ATM layer processors and switching or adaptation functions using a
Utopia Level 2 compliant synchronous FIFO style interface. The initial
configuration and ongoing control and monitoring of the S/UNI-QUAD are
normally provided via a generic microprocessor interface. This application is
shown in Figure 1.
Figure 1: Typical STS-3c (STM-1) ATM Switch Port Application
ATM Layer Device
TxClk
TxEnb
TxAddr<4:0>
TxClav
TxSOC
TxPrt
TxData<15:0>
RxClk
RxEnb
RxAddr<4:0>
RxCla v
RxSOC
RxPrt
RxData<15:0>
Uto
Interface
ia Level 2
PM5349
S/UNI-155-QUAD
TFCLK
TENB
4:0
TADR
TCA
TSOC
TPRTY
TDAT[15:0
RFCLK
RENB
4:0
RADR
RCA
RSOC
RPRTY
RDAT
15:0
RXD1+/SD1
TXD1+/-
RXD2+/SD2
TXD2+/-
RXD3+/SD3
TXD3+/-
RXD4+/SD4
TXD4+/-
Optical
Transceiver
Optical
Transceiver
Optical
Transceiver
Optical
Transceiver
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6 BLOCK DIAGRAM
TRSTB
TCK
TMS
TDI
TDO
:0]
TSOC
TDAT[15
TPRTY
TCA
DTCA[4:1]
st
JTAG T e
Access Port
Tx
Tx
Tx
OEN
PHY_
TFCLKTENB
TADR[4:0]
Utopia
System Interface
ATM Cell
Processor
Path O/H
Processor
Line O/H
Processor
RFCLK RADR[4:0]
RENB
RCA
]
RPRTY
RSOC
RDAT[15:0
DRCA[4:1]
INTB
or
ess
F
I/
proc
cro
Mi
Rx
ATM Cell
processor
Rx
Path O/H
Processor
Rx
APS,
Sync,
Rx
Line O/H
Processor
BERM
RSTB
RDB
WRB
CSB
ALE
A[10:0]
D[7:0]
TCLK
TFPO
TFPI
Tx
Processor
Section O/H
I/F
Tx Line
ATB0-3
TXD1-4 -
TXD1-4 +
TXC1-4 -
TXC1-4 +
REFCLK
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Rx
Processor
Section O/H
I/F
Rx Line
-
+
SD1-4
RXD1-4
RXD1-4
RCLK1-4
RFPO1-4
RALRM1-4
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7 DESCRIPTION
The PM5349 S/UNI-QUAD SATURN User Network Interface is a monolithic
integrated circuit that implements four channel SONET/SDH processing and ATM
mapping functions at the STS-3c (STM-1) 155.52 Mbit/s rate.
The S/UNI-QUAD receives SONET/SDH streams using a bit serial interface,
recovers the clock and data and processes section, line, and path overhead. It
performs framing (A1, A2), de-scrambling, detects alarm conditions, and monitors
section, line, and path bit interleaved parity (B1, B2, B3), accumulating error
counts at each level for performance monitoring purposes. Line and path far end
block error indications (M1, G1) are also accumulated. The S/UNI-QUAD
interprets the received payload pointers (H1, H2) and extracts the synchronous
payload envelope which carries the received ATM cell payload.
The S/UNI-QUAD frames to the ATM payload using cell delineation. HCS error
correction is provided. Idle/unassigned cells may be dropped according to a
programmable filter. Cells are also dropped upon detection of an uncorrectable
header check sequence error. The ATM cell payloads are descrambled. The ATM
cells that are passed are written to a four cell FIFO buffer. The received cells are
read from the FIFO using a 16-bit wide Utopia level 2 compliant datapath
interface. Counts of received ATM cell headers that are errored and uncorrectable
and also those that are errored and correctable are accumulated independently
for performance monitoring purposes.
The S/UNI-QUAD transmits SONET/SDH streams using a bit serial interface and
formats section, line, and path overhead appropriately. It synthesizes the transmit
clock from a lower frequency reference and performs framing pattern insertion
(A1, A2), scrambling, alarm signal insertion, and creates section, line, and path
bit interleaved parity (B1, B2, B3) as required to allow performance monitoring at
the far end. Line and path far end block error indications (M1, G1) are also
inserted. The S/UNI-QUAD generates the payload pointer (H1, H2) and inserts
the synchronous payload envelope which carries the ATM cell payload. The
S/UNI-QUAD also supports the insertion of a large variety of errors into the
transmit stream, such as framing pattern errors, bit interleaved parity errors, and
illegal pointers, which are useful for system diagnostics and tester applications.
ATM cells are written to an internal four cell FIFO using a 16-bit wide Utopia Level
2 datapath interface. Idle/unassigned cells are automatically inserted when the
internal FIFO contains less than one cell. The S/UNI-QUAD provides generation
of the header check sequence and scrambles the payload of the ATM cells. Each
of these transmit ATM cell processing functions can be enabled or bypassed.
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PM5349 S/UNI-QUAD
No line rate clocks are required directly by the S/UNI-QUAD as it synthesizes the
transmit clock and recovers the receive clock using a 19.44 MHz reference clock.
The S/UNI-QUAD outputs a differential TTL (externally coverted to PECL) line
data (TXD+/-).
The S/UNI-QUAD is configured, controlled and monitored via a generic 8-bit
microprocessor bus interface. The S/UNI-QUAD also provides a standard 5
signal IEEE 1149.1 JTAG test port for boundary scan board test purposes.
The S/UNI-QUAD is implemented in low power, +3.3 Volt, CMOS technology. It
has TTL and pseudo-ECL (PECL) compatible inputs and TTL/CMOS compatible
outputs and is packaged in a 304 pin SBGA package.
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8 PIN DIAGRAM
The S/UNI-QUAD is available in a 304 pin SBGA package having a body size of
31 mm by 31 mm and a ball pitch of 1.27 mm.
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9 PIN DESCRIPTION
9.1 Line Side Interface Signals
Pin NameTypePin
Function
No.
REFCLKInputAC5The reference clock input (REFCLK) must provide a
jitter-free 19.44 MHz reference clock. It is used as
the reference clock by both clock recovery and clock
synthesis circuits.
This pin is shared by all channels.
RXD1+
RXD1RXD2+
RXD2RXD3+
RXD3RXD4+
RXD4-
SD1
SD2
SD3
SD4
Differential
PECL
inputs
Single-
Ended
PECL
Input
E2
D1
G1
G2
W1
V2
AA1
Y2
E3
J3
U3
W3
The receive differential data inputs (RXD+, RXD-)
contain the NRZ bit serial receive stream. The
receive clock is recovered from the RXD+/- bit
stream. Please refer to the Operation section for a
discussion of PECL interfacing issues.
This pin is available independently for each channel.
The Signal Detect pin (SD) indicates the presence
of valid receive signal power from the Optical
Physical Medium Dependent Device. A PECL high
indicates the presence of valid data and a PECL low
indicates a loss of signal. It is mandatory that SD be
terminated into the equivalent network that RXD+/is terminated into.
This pin is available independently for each channel.
RCLK1
RCLK2
RCLK3
RCLK4
OutputAA13
Y13
AC14
AB14
The receive byte clock (RCLK) provides a timing
reference for the S/UNI-QUAD receive outputs.
RCLK is a divide by eight of the recovered line rate
clock (19.44 MHz).
This pin is available independently for each channel.
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PM5349 S/UNI-QUAD
Pin NameTypePin
No.
RFPO1
RFPO2
RFPO3
RFPO4
RALRM1
RALRM2
RALRM3
RALRM4
OutputAA12
AB12
AC13
AB13
OutputAA14
AC15
Y14
AB15
Function
The Receive Frame Pulse Output (RFPO), when the
framing alignment is found (the OOF register bit is
logic zero), is an 8 kHz signal derived from the
receive line clock. RFPO pulses high for one RCLK
cycle every 2430 RCLK cycles (STS-3c (STM-1)).
RFPO is updated on the rising edge of RCLK.
This pin is available independently for each channel.
The Receive Alarm (RALRM) output indicates the
state of the receive framing. RALRM is low if no
receive alarms are active. RALRM is high if line AIS
(LAIS), path AIS (PAIS), line RDI (LRDI), path RDI
(PRDI), enhanced path RDI (PERDI), loss of signal
(LOS), loss of frame (LOF), out of frame (OOF),
loss of pointer (LOP), loss of cell delineation (LCD),
signal fail BER (SFBER), signal degrade BER
(SDBER), or path signal label mismatch (PSLM) is
detected in the associated channel. Each alarm can
be individually enabled using bits in the S/UNIQUAD Channel Alarm Control registers #1 and #2.
TXD1+
TXD1TXD2+
TXD2TXD3+
TXD3TXD4+
TXD4-
Differential
TTL output
(externally
converted
to PECL)
C1
D2
E1
F2
T2
U1
W2
Y1
RALRM is updated on the rising edge of RCLK.
This pin is available independently for each channel.
The transmit differential data outputs (TXD+, TXD-)
contain the 155.52 Mbit/s transmit stream.
This pin is available independently for each channel.
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Pin NameTypePin
Function
No.
TFPIInputY7The active high framing position (TFPI) signal is an
8 kHz timing marker for the transmitter. TFPI is used
to align the SONET/SDH transport frame generated
by the S/UNI-QUAD device to a system reference.
TFPI is internally used to align a master frame pulse
counter. When TFPI is not used, this counter is freerunning.
TFPI should be brought high for a single TCLK
period every 2430 (STS-3c (STM-1)) TCLK cycles,
or a multiple thereof. TFPI shall be tied low if such
synchronization is not required. TFPI cannot be
used as an input to a loop-timed channel. For TFPI
to operate correctly it is required that the
TCLK/TFPO output be configured to output the
CSU byte clock.
The TFPI_EN register bits allow to individually
configure each channel to use the global framing
pulse counter and TFPI for framing alignment.
TFPI is sampled on the rising edge of TCLK, but
only when the TTSEL register bit is set to logic zero.
When TTSEL is set to logic one, TFPI is unused.
This pin is shared by all channels.
TCLKOutputAC11The transmit byte clock (TCLK) output provides a
timing reference for the S/UNI-QUAD self-timed
channels. TCLK always provide a divide by eight of
the synthesized line rate clock and thus has a
nominal frequency of 19.44 MHz. TFPI is sampled
on the rising edge of TCLK. TCLK does not apply to
internally loop-timed channels, in which case the
channel’s RCLK provides transmit timing
information.
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high for one TCLK cycle every 2430 TCLK cycles
and provides an 8 KHz timing reference. TFPO can
be assigned to any of the four channels using
TFPO_CH[1:0] configuration register bits, with the
restriction that the selected channel must be selftimed (not in loop-timed or line-loopback modes).
TFPO is updated on the rising edge of TCLK.
9.2 UTOPIA Level 2 System Interface
Pin NameTypePin
UTOPIA Transmit Cell Data Bus (TDAT[15:0]).
This data bus carries the ATM cell octets that are
written to the selected transmit FIFO. TDAT[15:0] is
considered valid only when TENB is simultaneously
asserted and the S/UNI-QUAD is selected via
TADR[4:0].
TDAT[15:0] is sampled on the rising edge of TFCLK.
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PM5349 S/UNI-QUAD
Pin NameTypePin
Function
No.
TPRTYInputH22UTOPIA Transmit bus parity (TPRTY) signal.
The transmit parity (TPRTY) signal indicates the
parity of the TDAT[15:0] bus. A parity error is
indicated by a status bit and a maskable interrupt.
Cells with parity errors are inserted in the transmit
stream, so the TPRTY input may be unused. Odd or
even parity selection is made independently for
each channel using the RXPTYP register bit.
TPRTY is considered valid only when TENB is
simultaneously asserted and the S/UNI-QUAD is
selected via TADR[4:0].
TPRTY is sampled on the rising edge of TFCLK.
TSOCInputJ21UTOPIA Transmit Start of Cell (TSOC) signal.
The transmit start of cell (TSOC) signal marks the
start of cell on the TDAT bus. When TSOC is high,
the first word of the cell structure is present on the
TDAT bus. It is not necessary for TSOC to be
present for each cell. An interrupt may be
generated if TSOC is high during any word other
than the first word of the cell structure.
TSOC is considered valid only when TENB is
simultaneously asserted and the S/UNI-QUAD is
selected via TADR[4:0].
TSOC is sampled on the rising edge of TFCLK.
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signal.
The TENB signal is an active low input which is
used along with the TADR[4:0] inputs to initiate
writes to the transmit FIFO’s.
TENB works as follows. When sampled high, no
write is performed, but the TADR[4:0] address is
latched to identify the transmit FIFO to be
accessed. When TENB is sampled low, the word on
the TDAT bus is written into the transmit FIFO that is
selected by the TADR[4:0] address bus. A complete
53 octet cell must be written to the transmit FIFO
before it is inserted into the transmit stream. Idle
cells are inserted when a complete cell is not
available. While TENB is deasserted, TADR[4:0] can
be used for polling TCA.
The TADR[4:0] bus is used to select the FIFO (and
hence port) that is written to using the TENB signal
and the FIFO's whose cell available signal is visible
on the TC A poll ing output.
Note that address 0x1F is the null-PHY address and
cannot be assigned to any port on the S/UNI-QUAD.
TADR[4:0] is sampled on the rising edge of TFCLK.
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Pin NameTypePin
Function
No.
TCAOutputJ23UTOPIA Transmit multi-PHY Cell Available (TCA)
The TCA signal indicates when a cell is available in
the transmit FIFO for the port polled by TADR[4:0]
when TENB is asserted. When high, TCA indicates
that the corresponding transmit FIFO is not full and
a complete cell may be written. Wh en TCA goes
low, it can be configured to indicate either that the
corresponding transmit FIFO is near full or that the
corresponding transmit FIFO is full. TCA will
transition low on the rising edge of TFCLK after the
Payload word 19 (TCALEVEL0=0) or 23
(TCALEVEL0=1) is sampled if the PHY being polled
is the same as the PHY in use. To reduce FIFO
latency, the FIFO depth at which TCA indicates "full"
can be set to one, two, three or four cells. Note that
regardless of what fill level TCA is set to indicate
"full" at, the transmit cell processor can store 4
complete cells.
TCA is tri-stated when either the null-PHY address
(0x1F) or an address not matching the address
space set by PHY_ADR[2:0] is latched from the
TADR[4:0] inputs when TENB is high.
This signal is used to write ATM cells to the four cell
transmit FIFOs.
TFCLK cycles at a 50 MHz or lower instantaneous
rate.
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PM5349 S/UNI-QUAD
Pin NameTypePin
No.
DTCA[4]
DTCA[3]
DTCA[2]
DTCA[1]
OutputK22
K23
L20
L21
Function
UTOPIA Direct Transmit Cell Available (DTCA[4:1]).
These output signals provide di r ect status indi cation
of when a cell is available in the transmit FIFO for
the corresponding port. When high, DTCA indicates
that the corresponding transmit FIFO is not full and
a complete cell may be written. Wh en DTCA goes
low, it can be configured to indicate either that the
corresponding transmit FIFO is near full or that the
corresponding transmit FIFO is full. DTCA will
transition low on the rising edge of TFCLK after the
Payload word 19 (TCALEVEL0=0) or 23
(TCALEVEL0=1) is sampled if the PHY being polled
is the same as the PHY in use. To reduce FIFO
latency, the FIFO depth at which DTCA indicates
"full" can be set to one, two, three or four cells. Note
that regardless of what fill level DTCA is set to
indicate "full" at, the transmit cell processor can
store 4 complete cells
DTCA[4:1] are updated on the rising edge of
TFCLK.
UTOPIA Receive Cell Data Bus (RDAT[15:0]).
This data bus carries the ATM cells that are read
from the receive FIFO selected by RADR[4:0].
RDAT[15:0] is tri-stated when RENB is high.
RDAT[15:0] is tristated when RENB is high.
RDAT[15:0] is also tristated when either the nullPHY address (0x1F) or an address not matching
the address space is latched from the RADR[4:0]
inputs when RENB is high.
RDAT[15:0] is updated on the rising edge of
RFCLK.
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Pin NameTypePin
Function
No.
RPRTYOutputT21UTOPIA Receive Parity (RPRTY).
The receive parity (RPRTY) signal indicates the
parity of the RDAT bus. RPRTY reflects the parity of
RDAT[15:0]. Odd or even parity selection is made
independently for every channel by using the
RXPTYP register bit (in ATM cell processors, the
four RXCP shall be programmed with the same
parity setting).RPRTY is tristated when RENB is
high. RPRTY is also tristated when either the nullPHY address (0x1F) or an address not matching
the address space is latched from the RADR[4:0]
inputs when RENB is high.
RPRTY is updated on the rising edge of RFCLK.
RSOCOutputP23UTOPIA Receive Start of Cell (RSOC).
RSOC marks the start of cell on the RDAT bus.
RSOC is tristated when RENB is deasserted.
RSOC is also tristated when either the null-PHY
address (0x1F) or an address not matching the
address space is latched from the RADR[4:0] inputs
when RENB is high.
The RENB signal is used to initiate reads from the
receive FIFO’s. RENB works as follows. When
RENB is sampled high, no read is performed and
RDAT[15:0], RPRTY and RSOC are tristated, and
the address on RADR[4:0] is latched to select the
device or port for the next FIFO access. When
RENB is sampled low, the word on the RDAT bus is
read from the selected receive FIFO.
RENB must operate in conjunction with RFCLK to
access the FIFO’s at a high enough rate to prevent
FIFO overflows. The system may de-assert RENB
at anytime it is unable to accept another byte.
RENB is sampled on the rising edge of RFCLK.
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Pin NameTypePin
Function
No.
RADR[4]
RADR[3]
RADR[2]
RADR[1]
RADR[0]
Input
R23
P20
R22
R21
T22
UTOPIA Receive Read Address (RADR[4:0]).
The RADR[4:] signal is used to select the FIFO (and
hence port) that is read from using the RENB signal
and the FIFO whose cell available signal is visible
on the RCA output.
Note that address 0x1F is the null-PHY address and
will not be identified to any port on the
S/UNI-QUAD.
RADR[4:0] is sampled on the rising edge of RFCLK.
RCAOutputN20UTOPIA Receive multi-PHY Cell Available (RCA).
RCA indicates when a cell is available in the receive
FIFO for the port selected by RADR[4:0]. RCA can
be configured to be de-asser ted when either zero or
four bytes remain in the selected/addressed FIFO.
RCA will thus transition low on the rising edge of
RFCLK after Payload word 24 (RCALEVEL0=1) or
19 (RCALEVEL0=0) is output if the PHY being
polled is the same as the PHY in use.
RCA is tristated when either the null-PHY address
(0x1F) or an address not matching the address
space is latched from the RADR[4:0] inputs when
RENB is high.
RFCLK is used to read ATM cells from the receive
FIFO’s. RFCLK must cycle at a 50 MHz or lower
instantaneous rate, but at a high enough rate to
avoid FIFO overflows.
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Pin NameTypePin
Function
No.
DRCA[4]
DRCA[3]
DRCA[2]
DRCA[1]
OutputM21
N23
N22
N21
UTOPIA Direct Receive Cell Available (DRCA[4:1]).
These output signals provides di r ect status
indication of when a cell is available in the receive
FIFO for the corresponding port. DRCA can be
configured to be de-asserted when either zero or
four bytes remain in the selected/addressed FIFO.
DRCA will thus transition low on the rising edge of
RFCLK after Payload word 24 (RCALEVEL0=1) or
19 (RCALEVEL0=0) is output if the PHY being
polled is the same as the PHY in use.
DRCA[x] is updated on the rising edge of RFCLK.
PHY_OENInputA19The PHY Output Enable (PHY_OEN) signal controls
the operation of the system interface. When set to
logic zero, all System Interface outputs are held
tristate. When PHY_OEN is set to logic one, the
interface is enabled. PHY_OEN can be overwritten
by the PHY_EN Master System Interface
Configuration register bit. PHY_OEN and PHY_EN
are OR’ed together to enable the interface.
When the S/UNI-QUAD is the only PHY layer device
on the bus, PHY_O EN can safely be tied to logic
one. When the S/UNI-QUAD shares the bus with
other devices, then PHY_OEN must be tied to logic
zero, and the PHY_EN register bit used to enable
the bus once its PHY_ADR[2:0] is programmed in
order to avoid conflicts.
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CSBInputB11The active-low chip select (CSB) signal is low
during S/UNI-QUAD register accesses.
Note that when not being used, CSB must be tied
high. If CSB is not required (i.e., registers accesses
are controlled using the RDB and WRB signals
only), CSB must be connected to an inverted
version of the RSTB input.
RDBInputD11The active-low read enable (RDB) signal is low
during S/UNI-QUAD register read accesses. The
S/UNI-QUAD drives the D[7:0] bus with the contents
of the addressed register while RDB and CSB are
low.
WRBInputA10The active-low write strobe (WRB) signal is low
during a S/UNI-QUAD register write accesses. The
D[7:0] bus contents are clocked into the addressed
register on the rising WRB edge while CSB is low.
D[0]
D[1]
D[2]
D[3]
D[4]
D[5]
D[6]
D[7]
I/OD16
B17
A17
C16
B16
C15
B15
D14
The bi-directional data bus D[7:0] is used during
S/UNI-QUAD register read and write accesses.
A[0]
A[1]
A[2]
A[3]
A[4]
A[5]
A[6]
A[7]
A[8]
A[9]
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InputA15
C14
B14
A14
D13
C13
B13
A13
C12
B12
The address bus A[9:0] selects specific registers
during S/UNI-QUAD register accesses.
Except for S/UNI-QUAD global registers, the A[9:8]
bits allow to select which channel is being
accessed. The A[7:0] bits allow to select which
register is being access within a given channel
address space.
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Pin NameTypePin
Function
No.
A[10]/TRSInputA11The test register select (TRS) signal selects
between normal and test mode register accesses.
TRS is high during test mode register accesses,
and is low during normal mode register accesses.
RSTBInput
pull-up
B10The active-low reset (RSTB) signal provides an
asynchronous S/UNI-QUAD reset. RSTB is a
Schmitt triggered input with an integral pull-up
resistor.
ALEInput
pull-up
C11The address latch enable (ALE) is active-high and
latches the address bus A[7:0] when low. When
ALE is high, the internal address latches are
transparent. It allows the S/UNI-QUAD to interface
to a multiplexed address/data bus. ALE has an
integral pull-up resistor.
INTBOutput
Open-
drain
C10The active-low interrupt (INTB) signal goes low
when a S/UNI-QUAD interrupt source is active and
that source is unmasked. The S/UNI-QUAD may be
enabled to report many alarms or events via
interrupts.
Examples of interrupt sources are loss of signal
(LOS), loss of frame (LOF), line AIS, line remote
defect indication (LRDI) detect, loss of pointer
(LOP), path AIS, path remote defect indication
detect and others.
INTB is tristated when the interrupt is acknowledged
via an appropriate register access. INTB is an open
drain output.
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9.4 JTAG Test Access Port (TAP) Signals
Pin NameTypePin
Function
No.
TCKInputB8The test clock (TCK) signal provides timing for test
operations that are carried out using the IEEE
P1149.1 test access port.
TMSInput
pull-up
B9The test mode select (TMS) signal controls the test
operations that are carried out using the IEEE
P1149.1 test access port. TMS is sampled on the
rising edge of TCK. TMS has an integral pull-up
resistor.
TDIInput
pull-up
D10The test data input (TDI) signal carries test data into
the S/UNI-QUAD via the IEEE P1149.1 test access
port. TDI is sampled on the rising edge of TCK. TDI
has an integral pull-up resistor.
TDOTristateA9The test data output (TDO) signal carries test data
out of the S/UNI-QUAD via the IEEE P1149.1 test
access port. TDO is updated on the falling edge of
TCK. TDO is a tristate output which is inactive
except when scanning of data is in progress.
TRSTBInput
pull-up
C9The active-low test reset (TRSTB) signal provides
an asynchronous S/UNI-QUAD test access port
reset via the IEEE P1149.1 test access port.
TRSTB is a Schmitt triggered input with an integral
pull-up resistor.
Note that when not being used, TRSTB must be
connected to the RSTB input.
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9.5 Analog Signals
Pin NameTypePin
ATB0
Analog I/O P2
ATB1
ATB2
ATB3
9.6 Power and Ground
Pin NameTypePin
BIASBias
Voltage
No.
P3
P4
R1
No.
K21
C17
Function
The Analog Test Bus (ATB). These pins are used for
manufacturing testing only and should be connected
ground.
Function
I/O Bias (BIAS). When tied to +5V via a 1 KΩ
resistor, the BIAS input is used to bias the wells in
the input and I/O pads so that the pads can tolerate
5V on their inputs without forward biasing internal
ESD protection devices. When BIAS is tied to
+3.3V, the inputs and bi-direction al inputs will only
tolerate 3.3V level inputs.
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The analog ground (AVS) pins for the analog core.
AVS should be connected to analog GND.
1. All S/UNI-QUAD inputs and bi-directionals present minimum capacitive
loading and operate at TTL logic levels except: the SD, RXD+ and RXDinputs which operate at pseudo-ECL (PECL) logic levels
2. The RDAT[7:0], RPRTY, RSOC, DRCA4-1, RCA, DTCA4-1, TCA, TCLK and
RCLK1-4 outputs have a 4 mA DC drive capability. The TDO output has a 1
mA drive capability. All the other outputs have a 2 mA DC drive capability.
The TXD+ and TXD- outputs are met to be terminated in a passive network
and interface at PECL levels.
3. It is mandatory that every ground pin (VSS) be connected to the printed
circuit board ground plane to ensure a reliable device operation.
4. It is mandatory that every power pin (VDD) be connected to the printed circuit
board power plane to ensure a reliable device operation.
5. All analog power and ground can be sensitive to noise. They must be
isolated from the digital power and ground. Care must be taken to decouple
these pins from each other and all other analog power and ground pins.
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Power supply filtering recommendations are provided in the
OPERATION section of this document.
6. Due to ESD protection structures in the pads it is necessary to exercise
caution when powering a device up or down. ESD protection devices behave
as diodes between power supply pins and from I/O pins to power suppl y pins.
Under extreme conditions it is possible to blow these ESD protection devices
or trigger latch up. Please adhere to the recommended power supplysequencing as described in the OPERATION section of this document.
7. If it is intended to substitute a S/UNI-QUAD in a S/UNI-TETRA socket,
special attention must be given to the NC pins. The requirement is that no
S/UNI-QUAD input pin is left floating when used in a S/UNI-QUAD socket.
Please refer to the relevant PMC-Sierra, Inc. application note.
8. Some device pins can be made 5V tolerant by connecting the BIAS pins to a
5V power supply, while some other pins are 3.3V only. In summary, the
system interface is 3.3V only while the microprocessor interface, SONET and
line interfaces can be 5V tolerant.
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10 FUNCTIONAL DESCRIPTION
10.1 Receive Line Interface (CRSI)
The Receive Line Interface allows to directly interface the S/UNI-QUAD with
optical modules (ODLs) or other medium interfaces. This block performs clock
and data recovery and performs serial to parallel conversion on the incoming
155.52 Mbit/s data stream.
10.1.1 Clock Recovery
The clock recovery unit recovers the clock from the incoming bit serial data
stream. The clock recovery unit is fully compliant with SONET and SDH jitter
tolerance requirements. The clock recovery unit utilizes a low frequency
reference clock to train and monitor its clock recovery PLL. Under loss of signal
conditions, the clock recovery unit continues to output a line rate clock that is
locked to this reference for keep alive purposes. The clock recovery unit utilizes a
reference clocks at 19.44 MHz. The clock recovery unit provides status bits that
indicate whether it is locked to data or the reference. The clock recovery unit also
supports diagnostic loopback and a loss of signal input that squelches normal
input data.
Initially, the PLL locks to the reference clock, REFCLK. When the frequency of
the recovered clock is within 488 ppm of the reference clock, the PLL attempts to
lock to the data. Once in data lock, the PLL reverts to the reference clock if no
data transitions occur in 80 bit periods or if the recovered clock drifts beyond 488
ppm of the reference clock.
When the transmit clock is derived from the recovered clock (loop timing), the
accuracy of the transmit clock is directly related to the REFCLK reference
accuracy in the case of a loss of signal condition. To meet the Bellcore GR-253CORE SONET Network Element free-run accuracy specification, the refe rence
must be within +/-20ppm. When not loop timed, the REFCLK accuracy may be
relaxed to +/-50ppm.
The loop filter transfer function is optimized to enable the PLL to track the jitter,
yet tolerate the minimum transition density expected in a received SONET/SDH
data signal. The total loop dynamics of the clock recovery PLL yield a jitter
tolerance that exceeds the minimum tolerance proposed for SONET equipment
by GR-253-CORE (Figure 3).
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Figure 2: Typical STS-3c (STM-1) Jitter Tolerance
100
10
GR-253-CORE
1
0.1
100100010000100000100000010000000
Jitter Freq. (Hz)
Note that for frequencies below 300 Hz, the jitter tolerance is greater than 15
UIpp; 15 UIpp is the maximum jitter tolerance of the test equipment. Also note
that the dip in the tolerance curve between 300 Hz and 10 kHz is due to the
S/UNI-QUAD's internal clock difference detector: if the recovered clock drifts
beyond 488 ppm of the reference, the PLL locks to the reference clock.
10.1.2 Serial to Parallel Converter
The Serial to Parallel Converter (SIPO) converts the received bit serial stream to
a byte serial stream. The SIPO searches for the SONET/SDH framing pattern
(A1, A2) in the receive stream, and performs serial to parallel conversion on octet
boundaries.
10.2 Receive Section Overhead Processor (RSOP)
The Receive Section Overhead Processor (RSOP) provides frame
synchronization, de-scrambling, section level alarm and performance monitoring.
10.2.1 Framer
The Framer Block determines the in-frame/out-of-frame status of the receive
stream.
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While in-frame, the framing bytes (A1, A2) in each frame are compared against
the expected pattern. Out-of-frame is declared when four consecutive frames
containing one or more framing pattern errors have been received.
While out-of-frame, the SIPO block monitors the receive stream for an occurrence
of the framing pattern. When a framing pattern is recognized, the Framer block
verifies that an error free framing pattern is present in the next frame before
declaring in-frame.
10.2.2 Descramble
The Descramble Block utilizes a frame synchronous descrambler to process the
receive stream. The generating polynomial is x7 + x6 + 1 and the sequence
length is 127. Details of the de-scrambling operation are provided in the
references. Note that the framing bytes (A1 and A2) and the trace/growth bytes
(J0/Z0) are not descrambled. A register bit is provided to disable the descrambling operation.
10.2.3 Error Monitor
The Error Monitor Block calculates the received section BIP-8 error detection
code (B1) based on the scrambled data of the complete STS-3c (STM-1) frame.
The section BIP-8 code is based on a bit interleaved parity calculation using even
parity. Details are provided in the references. The calculated BIP-8 code is
compared with the BIP-8 code extracted from the B1 byte of the following frame.
Differences indicate that a section level bit error has occurred. Up to 64000 (8 x
8000) bit errors can be detected per second. The Error Monitor Block
accumulates these section level bit errors in a 16-bit saturating counter that can
be read via the microprocessor interface. Circuitry is provided to latch this
counter so that its value can be read while simultaneously resetting the internal
counter to 0 or 1, if appropriate, so that a new period of accumulation can begin
without loss of any events. It is intended that this counter be polled at least once
per second so as not to miss bit error events.
10.2.4 Loss of Signal
The Loss of Signal Block monitors the scrambled data of the receive stream for
the absence of 1's. When 20 ± 3 µs of all zeros patterns is detected, a loss of
signal (LOS) is declared. Loss of signal is cleared when two valid framing words
are detected and during the intervening time, no loss of signal condition is
detected. The LOS signal is optionally reported on the RALRM output pin when
enabled by the LOSEN Receive Alarm Control Register bit.
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10.2.5 Loss of Frame
The Loss of Frame Block monitors the in-frame / out-of-frame status of the
Framer Block. A loss of frame (LOF) is declared when an out-of-frame (OOF)
condition persists for 3 ms. The LOF is cleared when an in-frame condition
persists for a period of 3 ms. To provide for intermittent out-of-frame (or in-frame)
conditions, the 3 ms timer is not reset to zero until an in-frame (or out-of-frame)
condition persists for 3 ms. The LOF and OOF signals are optionally reported on
the RALRM output pin when enabled by the LOFEB and OOFEN Receive Alarm
Control Register bits.
10.3 Receive Line Overhead Processor (RLOP)
The Receive Line Overhead Processor (RLOP) provides line level alarm and
performance monitoring.
10.3.1 Line RDI Detect
The Line RDI Detect Block detects the presence of Line Remote Defect
Indication (LRDI) in the receive stream. Line RDI is declared when a 110 binary
pattern is detected in bits 6, 7, and 8 of the K2 byte, for three or five consecutive
frames. Line RDI is removed when any pattern other than 110 is detected in bits
6, 7, and 8 of the K2 byte for three or five consecutive frames. The LRDI signal is
optionally reported on the RALRM output pin when enabled by the LRDIEN
Receive Alarm Control Register bit.
10.3.2 Line AIS Detect
The Line AIS Block detects the presence of a Line Alarm Indication Signal (LAIS)
in the receive stream. Line AIS is declared when a 111 binary pattern is detected
in bits 6, 7, and 8 of the K2 byte, for three or five consecutive frames. Line AIS is
removed when any pattern other than 111 is detected in bits 6, 7, and 8 of the K2
byte for three or five consecutive frames. The LAIS signal is optionally repor ted
on the RALRM output pin when enabled by the LAISEN Receive Alarm Control
Register bit.
10.3.3 Error Monitor Block
The Error Monitor Block calculates the received line BIP-8 error detection codes
based on the Line Overhead bytes and synchronous payload envelopes of the
STS-3c (STM-1) stream. The line BIP-8 code is a bit interleaved parity calculation
using even parity. Details are provided in the references. The calculated BIP-8
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codes are compared with the BIP-8 codes extracted from the following frame. Any
differences indicate that a line layer bit error has occurred. Optionally the RLOP
can be configured to count a maximum of only one BIP error per frame.
This block also extracts the line FEBE code from the third Z2 byte. The FEBE
code is contained in bits 2 to 8 of the Z2 byte, and represents the number of line
BIP-8 errors that were detected in the last frame by the far end. The FEBE code
value has 25 legal values (0 to 24) for an STS-3c (STM-1) stream. Illegal values
are interpreted as zero errors.
The Error Monitor Block accumulates B2 error events and FEBE events in two 20
bit saturating counter that can be read via the microprocessor interface. The
contents of these counters may be transferred to internal holding registers by
writing to any one of the counter addresses, or by using the TIP register bit
feature. During a transfer, the counter value is latched and the counter is reset to
0 (or 1, if there is an outstanding event). Note, these counters should be polled at
least once per second to avoid saturation.
The B2 error events counters optionally can be configured to accumulate only
"word" errors. A B2 word error is defined as the occurrence of one or more B2 bit
error events during a frame. The B2 error counter is incremented by one for each
frame in which a B2 word error occurs.
In addition the FEBE events counters optionally can be configured to accumulate
only "word" events. In STS-3c (STM-1) framing a FEBE word event is defined as
the occurrence of one or more FEBE bit events during a frame. The FEBE event
counter is incremented by one for each frame in which a FEBE event occurs.
10.4 The Receive APS, Synchronization Extractor and Bit Error Monitor (RASE)
10.4.1 Automatic Protection Switch Control
The Automatic Protection Switch (APS) control block filters and captures the
receive automatic protection switch channel bytes (K1 and K2) allowing them to
be read via the RASE APS K1 Register and the RASE APS K2 Register. The
bytes are filtered for three frames before being written to these registers. A
protection switching byte failure alarm is declared when twelve successive
frames have been received, where no three consecutive frames contain identical
K1 bytes. The protection switching byte failure alarm is removed upon detection
of three consecutive frames containing identical K1 bytes. The detection of
invalid APS codes is done in software by polling the RASE APS K1 Reg ister and
the RASE APS K2 Register.
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10.4.2 Bit Error Rate Monitor
The Bit Error Monitor Block (BERM) calculates the received line BIP-24 error
detection code (B2) based on the line overhead and synchronous payload
envelope of the receive data stream. The line BIP-24 code is a bit interleaved
parity calculation using even parity. Details are provided in the references. The
calculated BIP code is compared with the BIP-24 code extracted from the B2
byte(s) of the following frame. Any differences indicate that a line layer bit error
has occurred. Up to 192000 (24 BIP/frame x 8000 frames/second) bit errors can
be detected per second for STS-3c (STM-1) rate.
The BERM accumulates these line layer bit errors in a 20 bit saturating counter
that can be read via the microprocessor interface. Dur ing a read, the counter
value is latched and the counter is reset to 0 (or 1, if there is an outstanding
event). Note, this counter should be polled at least once per second to avoid
saturation which in turn may result in missed bit error events.
The BERM block is able to simultaneously monitor for signal fail (SF) or signal
degrade (SD) threshold crossing and provide alarms through software interrupts.
The bit error rates associated with the SF or SD alarms are programmable over a
range of 10-3 to 10-9. Details are provided in the Operations section.
In both declaring and clearing detection states, the accumulated BIP count is
continuously compared against the threshold. This allows to rapidly declare in the
presence of error bursts or error rates that significantly exceed the monitored
BER. This behavior allows meeting the ITU-T G.783 detection requirements at
various error rates (where the detection time is a function of the actual BER, for a
given monitored BER.
10.4.3 Synchronization Status Extraction
The Synchronization Status Extraction (SSE) Block extracts the synchronization
status (S1) byte from the line overhead. The SSE block can be configured to
capture the S1 nibble after three or after eight frames with the same value
(filtering turned on) or after any change in the value (filtering turned off). The S1
nibble can be read via the microprocessor interface.
Optionally, the SSE can be configured to perform filtering based on the whole S1
byte. Although this mode of operation is not standard, it might become useful in
the future.
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10.5 Receive Path Overhead Processor (RPOP)
The Receive Path Overhead Processor (RPOP) provides pointer interpretation,
extraction of path overhead, extraction of the synchronous payload envelope, and
path level alarm indication and performance monitoring.
10.5.1 Pointer Interpreter
The Pointer Interpreter interprets the incoming pointer (H1, H2) as specified in
the references. The pointer value is used to determine the location of the path
overhead (the J1 byte) in the incoming STS-3c (STM-1) stream. The algorithm
can be modeled by a finite state machine. Within the pointer interpretation
algorithm three states are defined as shown below:
NORM_state (NORM)
AIS_state (AIS)
LOP_state (LOP)
The transition between states will be consecutive events (indications), e.g., three
consecutive AIS indications to go from the NORM_state to the AIS_state. The
kind and number of consecutive indications activating a transition is chosen such
that the behavior is stable and insensitive to low BER. The only transition on a
single event is the one from the AIS_state to the NORM_state after receiving a
NDF enabled with a valid pointer value. It should be noted that, since the
algorithm only contains transitions based on consecutive indications, this implies
that, for example, non-consecutively received invalid indications do not activate
the transitions to the LOP_state.
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Figure 3: Pointe r Interpretation State Diagram
3 x eq_new_poi nt
inc_ind /
dec_ind
NDF_enable
NORM
3 x
eq_new_poi nt
8 x
inv_point
LOP
8 x
NDF_enabl e
3 x
eq_new_poi nt
3 x AIS_i nd
8 x inv_po int
3 x
AIS_i nd
NDF_enable
AIS
The following table defines the events (indications) shown in the state diagram.
norm_pointdisabled NDF + ss + offset value equal to active offset
NDF_enableenabled NDF + ss + offset value in range of 0 to 782 or
enabled NDF + ss, if NDFPOR bit is set (Note that the
current pointer is not updated by an enabled NDF if the
pointer is out of range).
AIS_indH1 = 'hFF, H2 = 'hFF
inc_inddisabled NDF + ss + majority of I bits inverted + no
majority of D bits inverted + previous NDF_enable, inc_ind
or dec_ind more than 3 frames ago
dec_inddisabled NDF + ss + majority of D bits inverted + no
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majority of I bits inverted + previous NDF_enable, inc_ind
or dec_ind more than 3 frames ago
inv_pointnot any of above (i.e., not norm_point, and not
NDF_enable, and not AIS_ind, and not inc_ind and not
dec_ind)
new_pointdisabled_NDF + ss + offset value in range of 0 to 782 but
not equal to active offset
inc_reqmajority of I bits inverted + no majority of D bits inverted
dec_reqmajority of D bits inverted + no majority of I bits inverted
Note 1.-active offset is defined as the accepted current phase of the SPE
(VC) in the NORM_state and is undefined in the other states.
Note 2 -enabled NDF is defined as the following bit patterns: 1001, 0001,
1101, 1011, 1000.
Note 3 -disabled NDF is defined as the following bit patterns: 0110, 1110,
result in an inv_point indication.
Note 5 -ss bits are unspecified in SONET and has bit pattern 10 in SDH
Note 6 -the use of ss bits in definition of indications may be optionally
disabled.
Note 7 -the requirement for previous NDF_enable, inc_ind or dec_ind be
more than 3 frames ago may be optionally disabled.
Note 8 -new_point is also an inv_point.
Note 9 -LOP is not declared if all the following conditions exist:
• the received pointer is out of range (>782),
• the received pointer is static,
• the received pointer can be interpreted, according
to majority voting on the I and D bits, as a
positive or negative justification indication,
• after making the requested justification, the received
pointer continues to be interpretable as a
pointer justification.
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When the received pointer returns to an in-range value, the
S/UNI/QUAD will interpret it correctly.
Note 10 -LOP will exit at the third frame of a three frame sequence consisting
of one frame with NDF enabled followed by two frames with NDF
disabled, if all three pointers have the same legal value.
The transitions indicated in the state diagram are defined in the fo llowing table.
inc_ind/dec_indoffset adjustment (increment or decrement indication)
3 x eq_new_pointthree consecutive equal new_point indications
NDF_enablesingle NDF_enable indication
3 x AIS_indthree consecutive AIS indications
8 x inv_pointeight consecutive inv_point indications
8 x NDF_enableeight consecutive NDF_enable indications
Note 1 -the transitions from NORM_state to NORM_state do not represent
state changes but imply offset changes.
Note 2 -3 x new_point takes precedence over other events and if the
IINVCNT bit is set resets the inv_point count.
Note 3 -all three offset values received in 3 x eq_new_point must be
identical.
Note 4 -"consecutive event counters" are reset to zero on a change of state
except for consecutive NDF count.
The Pointer Interpreter detects loss of pointer (LOP) in the incoming STS-3c
(STM-1) stream. LOP is declared on entry to the LOP_state as a result of eight
consecutive invalid pointers or eight consecutive NDF enabled indications. The
alarm condition is reported in the receive alarm por t and is optionally returned to
the source node by signaling the corresponding Transmit Path Overhead
Processor in the local S/UNI-QUAD to insert a path RDI indication.
The Pointer Interpreter detects path AIS in the incoming STS-3c (STM-1)
stream. PAIS is declared on entry to the AIS_state after three consecutive AIS
indications. The alarm condition reported in the receive alarm port and is
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optionally returned to the source node by signaling the corresponding Transmit
Path Overhead Processor in the local SONET/SDH equipment to insert a path
RDI indication.
Invalid pointer indications (inv_point), invalid NDF codes, new pointer indications
(new_point), discontinuous change of pointer alig nment, and illegal pointer
changes are also detected and reported by the Pointer Interpreter block via
register bits. An invalid NDF code is any NDF code that does not match the NDF
enabled or NDF disabled definitions. The third occurrence of equal new_point
indications (3 x eq_new_point) is reported as a discontinuous change of pointer
alignment event (DISCOPA) instead of a new pointer event and the active offset
is updated with the receive pointer value. An illegal pointer change is defined as
a inc_ind or dec_ind indication that occurs within three frames of the previous
inc_ind, dec_ind or NDF_enable indications. Illegal pointer changes may be
optionally disabled via register bits.
The active offset value is used to extract the path overhead from the incoming
stream and can be read from an internal register.
10.5.2 SPE Timing
The SPE Timing Block provides SPE timing information to the Error Monitor and
the Extract blocks. The block contains a free running timeslot counter that is
initialized by a J1 byte identifier (which identifies the first byte of the SPE).
Control signals are provided to the Error Monitor and the Extract blocks to identify
the Path Overhead bytes and to downstream circuitry to extract the ATM cell
payload.
10.5.3 Error Monitor
The Error Monitor Block contains two 16-bit counters that are used to accumulate
path BIP-8 errors (B3), and far end block errors (FEBEs). The contents of the two
counters may be transferred to holding registers, and the counters reset under
microprocessor control.
Path BIP-8 errors are detected by comparing the path BIP-8 byte (B3) extracted
from the current frame, to the path BIP-8 computed for the previous frame.
FEBEs are detected by extracting the 4-bit FEBE field from the path status byte
(G1). The legal range for the 4-bit field is between 0000 and 1000, representing
zero to eight errors. Any other value is interpreted as zero errors.
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Path RDI alarm is detected by extracting bit 5 of the path status byte. The PRDI
signal is set high when bit 5 is set high for five/ten consecutive frames. PRDI is
set low when bit 5 is low for five/ten consecutive frames. Auxiliary RDI alarm is
detected by extracting bit 6 of the path status byte. The Auxiliary RDI alarm is
indicated when bit 6 is set high for five/ten consecutive frames. The Auxiliary RDI
alarm is removed when bit 6 is low for five/ten consecutive frames. The
Enhanced RDI alarm is detected when the enhanced RDI code in bits 5,6,7 of
the path status byte indicates the same error codepoint for five/ten consecutive
frames. The Enhanced RDI alarm is removed when the enhanced RDI code in
bits 5,6,7 of the path status byte indicates the same non error codepoint for
five/ten consecutive frames. The ERDII maskable interrupt is set high when bits
5, 6 & 7 of the path status byte (G1) byte are set to a new codepoint for five or ten
consecutive frames. The ERDIV[2:0] signal reflects the state of the filtered ERDI
value (G1 byte bits 5, 6, & 7).
10.6 Receive ATM Cell Processor (RXCP)
The Receive ATM Cell Processor (RXCP) performs ATM cell delineation,
provides cell filtering based on idle/unassigned cell detection and HCS error
detection, and performs ATM cell payload de-scrambling. The RXCP also
provides a four cell deep receive FIFO. This FIFO is used to separate the STS-3c
(STM-1) line timing from the higher layer ATM system timing.
10.6.1 Cell Delineation
Cell Delineation is the process of framing to ATM cell boundaries using the
header check sequence (HCS) field found in the cell header. The HCS is a
CRC-8 calculation over the first 4 octets of the ATM cell header. When
performing delineation, correct HCS calculations are assumed to indicate cell
boundaries. Cells are assumed to be byte-aligned to the synchronous payload
envelope. The cell delineation algorithm searches the 53 possible cell boundary
candidates individually to determine the valid cell boundary location. While
searching for the cell boundary location, the cell delineation circuit is in the HUNT
state. When a correct HCS is found, the cell delineation state machine locks on
the particular cell boundary, corresponding to the correct HCS, and enters the
PRESYNC state. The PRESYNC state validates the cell boundary location. If
the cell boundary is invalid, an incorrect HCS will be received within the next
DELTA cells, at which time a transition back to the HUNT state is executed. If no
HCS errors are detected in this PRESYNC period, the SYNC state is entered.
While in the SYNC state, synchronization is main tained until ALPHA consecutive
incorrect HCS patterns are detected. In such an event a transition is made back
to the HUNT state. The state diagram of the delineation process is shown in
Figure 4.
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Figure 4: Cell Delineation State Diagram
correct HCS
(byte by byte)
HUNT
Incorrect HCS
(cell by cell)
ALPHA
consecutive
incorrect HCS's
(cell by cell)
SYNC
PRESYNC
DELTA
consecutive
correct HCS's
(cell by cell)
The values of ALPHA and DELTA determine the robustness of the delineation
process. ALPHA determines the robustness against false misalignments due to
bit errors. DELTA determines the robustness against false delineation in the
synchronization process. ALPHA is chosen to be 7 and DELTA is chosen to be 6.
These values result in an average time to delineation of 33.66 µs for the STS-3c
(STM-1) rate.
10.6.2 Descrambler
The self synchronous descrambler operates on the 48 byte cell payload only. The
circuitry descrambles the information field using the x43 + 1 polynomial. The
descrambler is disabled for the duration of the header and HCS fields and may
optionally be disabled for the payload.
10.6.3 Cell Filter and HCS Verification
Cells are filtered (or dropped) based on HCS errors and/or a cell header pattern.
Cell filtering is optional and is enabled through the RXCP registers. Cells are
passed to the receive FIFO while the cell delineation state machine is in the
SYNC state as described above. When both filtering and HCS checking are
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enabled, cells are dropped if uncorrectable HCS errors are detected, or if the
corrected header contents match the pattern contained in the RXCP Match
Header Pattern and RXCP Match Header Mask registers. Idle or unassigned cell
filtering is accomplished by writing the appropriate cell header pattern into the
RXCP Match Header Pattern and RXCP Match Header Mask registers.
Idle/Unassigned cells are assumed to contain the all zeros pattern in the VCI and
VPI fields. The RXCP Match Header Pattern and RXCP Match Header Mask
registers allow filtering control over the contents of the GFC, PTI, and CLP fields
of the header.
The HCS is a CRC-8 calculation over the first 4 octets of the ATM cell header.
The RXCP block verifies the received HCS using the polynomial, x8 + x2 + x + 1.
The coset polynomial, x6 + x4 + x2 + 1, is added (modulo 2) to the received HCS
octet before comparison with the calculated result. While the cell delineation
state machine (described above) is in the SYNC state, the HCS verification circuit
implements the state machine shown in Figure 5.
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In normal operation, the HCS ver ification state machine remains in the
'Correction Mode' state. Incoming cells containing no HCS errors are passed to
the receive FIFO. Incoming single-bit errors are corrected, and the resulting cell
is passed to the FIFO. Upon detection of a single-bit error or a multi-bit error, the
state machine transitions to the 'Detection Mode' state. In this state,
programmable HCS error filtering is provided. The detection of any HCS error
causes the corresponding cell to be dropped. The state machine transitions back
to the 'Correction Mode' state when M (where M = 1, 2, 4, 8) cells are received
with correct HCSs. The Mth cell is not discarded.
10.6.4 Performance Monitor
The Performance Monitor consists of two 12-bit saturating HCS error event
counters and a 21-bit saturating receive cell counter. One of the counters
accumulates correctable HCS errors which are HCS single-bit errors detected
and corrected while the HCS Verification state machine is in the 'Correction
Mode' state. The second counter accumulates uncorrectable HCS errors which
are HCS bit errors detected while the HCS Verification state machine is in the
'Detection Mode' state or HCS bit errors detected but not corrected while the
state machine is in the 'Correction Mode' state. The 21-bit receive cell counter
counts all cells written into the receive FIFO. Filtered cells are not counted.
Each counter may be read through the microprocessor interface. Circuitry is
provided to latch these counters so that their values can be read while
simultaneously resetting the internal counters to 0 or 1, if appropriate, so that a
new period of accumulation can begin without loss of any events. It is intended
that the counter be polled at least once per second so as not to miss HCS error
events.
10.7 Transmit Line Interface (CSPI)
The Transmit Line Interface allows to directly interface the S/UNI-QUAD with
optical modules (ODLs) or other medium interfaces. This block performs clock
synthesis and performs parallel to serial conversion of the incoming outgoing
155.52 Mbit/s data stream.
10.7.1 Clock Synthesis
The transmit clock is synthesized from a 19.44 MHz reference. The transfer
function yields a typical low pass corner of 2.0 MHz above which reference jitter
is attenuated at 1 2 dB per octave. The design of the loop f ilter and PLL is
optimized for minimum intrinsic jitter. With a jitter free 19.44 MHz reference, the
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intrinsic jitter is typically less than 0.01 UI RMS when measured using a high
pass filter with a 12 kHz cutoff frequency.
The REFCLK reference should be within ±20 ppm to meet the SONET free-run
accuracy requirements specified in GR-253-CORE.
10.7.2 Parallel to Serial Converter
The Parallel to Serial Converter (PISO) converts the transmit byte serial stream
to a bit serial stream. Every self-timed channel (a self-timed channel is one that
uses the CSU output clock) share a common line rate clock and byte clock, which
can be output as TCLK. Only self-timed channels can be synchronized using the
TFPI input. When a channel is loop-timed, TCLK, TFPI and TFPI are no more
available and the receive signals shall be used instead to extract timing
information.
10.8 Transmit Section Overhead Processor (TSOP)
The Transmit Section Overhead Processor (TSOP) provides frame pattern
insertion (A1, A2), scrambling, section level alarm signal insertion, and section
BIP-8 (B1) insertion.
10.8.1 Line AIS Insert
Line AIS insertion results in all bits of the SONET/SDH frame being set to 1
before scrambling except for the section overhead. The Line AIS Insert Block
substitutes all ones as described when enabled through an internal register (Reg
0x14, TSOP) accessed through the microprocessor interface. Activation or
deactivation of line AIS insertion is synchronized to frame boundaries.
10.8.2 BIP-8 Insert
The BIP-8 Insert Block calculates and inserts the BIP-8 error detection code (B1)
into the transmit stream.
The BIP-8 calculation is based on the scrambled data of the complete STS-3c
(STM-1) frame. The section BIP-8 code is based on a bit interleaved parity
calculation using even parity. Details are provided in the references. The
calculated BIP-8 code is then inserted into the B1 byte of the following frame
before scrambling. BIP-8 errors may be continuously inserted under register
control for diagnostic purposes.
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10.8.3 Framing and Identity Insert
The Framing and Identity Insert Block inserts the framing bytes (A1, A2) into the
STS-3c (STM-1) frame. Framing bit errors may be continuously inserted under
register control for diagnostic purposes.
10.8.4 Scrambler
The Scrambler Block utilizes a frame synchronous scrambler to process the
transmit stream when enabled through an internal register accessed via the
microprocessor interface. The generating polynomial is x7 + x6 + 1. Precise
details of the scrambling operation are provided in the references. Note that the
framing bytes and the identity bytes are not scrambled. All zeros may be
continuously inserted (after scrambling) under register control for diagnostic
purposes.
10.9 Transmit Line Overhead Processor (TLOP)
The Transmit Line Overhead Processor (TLOP) provides line level alarm signal
insertion, and line BIP-24 insertion (B2).
10.9.1 APS Insert
The APS Insert Block inserts the two automatic protection switch (APS) channel
bytes in the Line Overhead (K1 and K2) into the transmit stream when enabled
by an internal register.
10.9.2 Line BIP Calculate
The Line BIP Calculate Block calculates the line BIP-24 error detection code (B2)
based on the line overhead and synchronous payload envelope of the transmit
stream. The line BIP-24 code is a bit interleaved parity calculation using even
parity. Details are provided in the references. The calculated BIP-24 code is
inserted into the B2 byte positions of the following frame. BIP-24 errors may be
continuously inserted under register control for diagnostic purposes.
10.9.3 Line RDI Insert
The Line RDI Insert Block controls the insertion of line remote defect indication.
Line RDI insertion is enabled using the TLRDI input, or register control. Line RDI
is inserted by transmitting the code 110 (binary) in bit positions 6, 7, and 8 of the
K2 byte contained in the transmit stream.
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10.9.4 Line FEBE Insert
The Line FEBE Insert Block accumulates line BIP-24 errors (B2) detected by the
Receive Line Overhead Processor and encodes far end block error indications in
the transmit M1 byte.
10.10 Transmit Path Overhead Processor (TPOP)
The Transmit Path Overhead Processor (TPOP) provides transport frame
alignment generation, pointer generation (H1, H2), path overhead insertion and
the insertion of path level alarm signals.
10.10.1
Pointer Generator
The Pointer Generator Block generates the outgoing payload pointer (H1, H2) as
specified in the references. The concatenation indication (the NDF field set to
1001, I-bits and D-bits set to all ones, and unused bits set to all zeros) is inserted
in the second and third pointer byte locations in the transmit stream.
• (1) A "normal pointer value" locates the start of the SPE. Note: 0 ≤ "normal
pointer value" ≤ 782, and the new data flag (NDF) field is set to 0110. Note
that values greater than 782 may be inserted, using internal registers, to
generate a loss of pointer alarm in downstream circuitry.
• (2) Arbitrary "pointer values" may be generated using internal registers.
These new values may optionally be accompanied by a programmable new
data flag. New data flags may also be generated independently using internal
registers.
• (3) Positive pointer movements may be generated using a bit in an internal
register. A positive pointer movement is generated by inverting the five I-bits
of the pointer word. The SPE is not inserted during the positive stuff
opportunity byte position, and the pointer value is incremented by one.
Positive pointer movements may be inserted once per frame for diagnostic
purposes.
• (4) Negative pointer movements may be generated using a bit in an internal
register. A negative pointer movement is generated by inverting the five D-bits
of the pointer word. The SPE is inserted during the negative stuff opportunity
byte position, the H3 byte, and the pointer value is decremented by one.
Negative pointer movements may be inserted once per frame for diagnostic
purposes.
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The pointer value is used to insert the path overhead into the transmit stream.
The current pointer value may be read via internal registers.
10.10.2
BIP-8 Calculate
The BIP-8 Calculate Block performs a path bit interleaved parity calculation on
the SPE of the transmit stream. Details are provided in the references. The
resulting parity byte is inserted in the path BIP-8 (B3) byte position of the
subsequent frame. BIP-8 errors may be continuously inserted under register
control for diagnostic purposes.
10.10.3
FEBE Calculate
The FEBE Calculate Block accumulates far end block errors on a per frame
basis, and inserts the accumulated value (up to maximum value of eight) in the
FEBE bit positions of the path status (G1) byte. The FEBE information is derived
from path BIP-8 errors detected by the receive path overhead processor, RPOP.
Far end block errors may be inserted under register control for diagnostic
purposes.
10.11 Transmit ATM Cell Processor (TXCP)
The Transmit ATM Cell Processor (TXCP) provides rate adaptation via
idle/unassigned cell insertion, provides HCS generation and insertion, and
performs ATM cell scrambling. The TXCP contains a four cell transmit FIFO. An
idle or unassigned cell is transmitted if a complete ATM cell has not been written
into the FIFO.
10.11.1
Idle/Unassigned Cell Generator
The Idle/Unassigned Cell Generator inserts idle or unassigned cells into the cell
stream when enabled. Registers are provided to program the GFC, PTI, and
CLP fields of the idle cell header and the idle cell payload. The idle cell HCS is
automatically calculated and inserted.
10.11.2
Scrambler
The Scrambler scrambles the 48 octet information field. Scrambling is performed
using a parallel implementation of the self synchronous scrambler (x43 + 1
polynomial) described in the references. The cell headers are transmitted
unscrambled, and the scrambler may optionally be disabled.
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10.11.3
HCS Generator
The HCS Generator performs a CRC-8 calculation over the first four header
octets. A parallel implementation of the polynomial, x8+x2+x+1, is used. The
coset polynomial, x6+x4+x2+1, is added (modulo 2) to the residue. The HCS
Generator optionally inserts the result into the fifth octet of the header.
10.12 UTOPIA Level 2 System Interface
The S/UNI-QUAD system interface provides a Utopia level 2 compliant bus to
transfer ATM cells between the ATM layer device and the S/UNI-QUAD.
10.12.1
Receive ATM Interface
The Receive ATM FIFO (RXCP) provides FIFO management at the S/UNI-QUAD
receive cell interface. The receive FIFO contains four cells. The FIFO provides
the cell rate decoupling function between the transmission system physical layer
and the ATM layer.
In general, the management functions include filling the receive FIFO, indicating
when the receive FIFO contains cells, maintaining the receive FIFO read and
write pointers, and detecting FIFO overrun and underrun conditions.
10.12.2
The FIFO interface is “UTOPIA Level 2" compliant and accepts a read clock
(RFCLK) and read enable signal (RENB). The receive FIFO output bus
(RDAT[15:0]) is tri-stated when RENB is logic one or if the PHY device address
(RADR[4:0]) selected does not match this device's address. The interface
indicates the start of a cell (RSOC) and the receive cell available status (RCA
and DRCA[4:1]) when data is read from the receive FIFO (using the rising edges
of RFCLK). The RCA (and DRCA[x]) status changes from available to
unavailable when the FIFO is either empty (RCALEVEL0=1) or near empty
(RCALEVEL0 is logic zero). This interface also indicates FIFO overruns via a
maskable interrupt and register bits. Read accesses while RCA (or DRCA[x]) is a
logic zero will output invalid data. The FIFO is reset on FIFO overrun, causing up
to 4 cells to be lost.
Transmit ATM Interface
The ATM Transmit FIFO (TXCP) provides FIFO management at the S/UNI-QUAD
transmit cell interface. The transmit FIFO contains four cells. The FIFO depth
may be programmed to four, three, two, or one cells. The FIFO provides the cell
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rate decoupling function between the transmission system physical layer and the
ATM layer.
In general, the management functions include emptying cells from the transmit
FIFO, indicating when the transmit FIFO is full, maintaining the transmit FIFO
read and write pointers, and detecting a FIFO overrun condition.
The FIFO interface is “UTOPIA Level 2” compliant and accepts a write clock
(TFCLK), a write enable signal (TENB), the start of a cell (TSOC) indication, the
parity bit (TPRTY), and the ATM device address (TADR[4:0]) when data is written
to the transmit FIFO (using the rising edges of TFCLK). The interface provides
the transmit cell available status (TCA and DTCA[4:1]) which can transition from
"available" to "unavailable" when the transmit FIFO is near full (when
TCALEVEL0 is logic zero) or when the FIFO is full (when TCALEVEL0 is logic
one) and can accept no more writes. To reduce FIFO latency, the FIFO depth at
which TCA and DTCA[x] indicates "full" can be set to one, two, three or four cells
by the FIFODP[1:0] bits of TXCP Configuration 2 register. If the programmed
depth is less than four, more than one cell may be written after TCA or DTCA[x] is
asserted as the TXCP still allows four cells to be stored in its FIFO. This interface
also indicates FIFO overruns via a maskable interrupt and register bit, but write
accesses while TCA or DTCA[x] is logic zero are not processed. The TXCP
automatically transmits idle cells until a full cell is available to be transmitted.
10.13 JTAG Test Access Port
The JTAG Test Access Port block provides JTAG support for boundary scan. The
standard JTAG EXTEST, SAMPLE, BYPASS, IDCODE and STCTEST
instructions are supported. The S/UNI-QUAD identification code is 053490CD
hexadecimal.
10.14 Microprocessor Interface
The microprocessor interface block provides normal and test mode registers, and
the logic required to connect to the microprocessor interface. The normal mode
registers are required for normal operation, and test mode registers are used to
enhance the testability of the S/UNI-QUAD. Th e register set is accessed as
shown in Table 3. In the following section every register is documented and
identified using the register number (REG #). The corresponding memory map
address for every channel (CH #1,2,3,4) is given in the table. Addresses that are
not shown are not used and must be treated as Reserved.
Table 3: Register Memory Map
Address A[10:0]Description
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REG#CH
#1
CH
#2
CH
#3
CH
#4
00000S/UNI-QUAD Master Reset and Identity
01001S/UNI-QUAD Master Configura tion
02002S/UNI-QUAD Master System Interface Config
03003S/UNI-QUAD Master Clock Monitor
04004S/UNI-QUAD Master Interrupt Status
05005105205305S/UNI-QUAD Channel Reset and Performance
Monitoring Update
06006106206206S/UNI-QUAD Channel Configuration
07007107207307S/UNI-QUAD Channel Control
08008108208308S/UNI-QUAD Channel Control Extensions
09009109209309Reserved
0A00A10A20A30AS/UNI-QUAD Channel Interrupt Status 1
0B00B10B20B30BReserved
0C00CCSPI Control and Status (Clock Synthesis)
0D00DReserved
0E00E10E20E30ECRSI Control and Status (Clock Recovery)
19019119219319RLOP Interrupt Enable/Status
1A01A11A21A31ARLOP Line BIP-24 LSB
1B01B11B21B31BRLOP Line BIP-24
1C01C11C21C31CRLOP Line BIP-24 MSB
1D01D11D21D31DRLOP Line FEBE LSB
1E01E11E21E31ERLOP Line FEBE
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Address A[10:0]
REG#CH
#1
CH
#2
CH
#3
CH
FE0FE1FE2FE3FE
FF0FF1FF2FF3FF
400S/UNI-QUAD Master Test Register
401
-
4FF
501
-
5FF
601
-
6FF
701
7FF
Notes on Register Memory Map:
For all register accesses, CSB must be low.
•
Addresses that are not shown must be treated as Reserved.
•
A[10] is the test resister select (TRS) and should be set to logic zero for
•
normal mode register access.
Description
#4
Reserved
Reserved
Reserved for Test
-
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11 NORMAL MODE REGISTER DESCRIPTION
Normal mode registers are used to configure and monitor the operation of the
S/UNI-QUAD. Normal mode registers (as opposed to test mode registers) are
selected when TRS (A[10]) is low.
Notes on Normal Mode Register Bits:
1. Writing values into unused register bits has no effect. However, to ensure
software compatibility with future, feature-enhanced versions of the product,
unused register bits must be written with logic zero. Reading back unused
bits can produce either a logic one or a logic zero; hence, unused register bits
should be masked off by software when read.
2. All configuration bits that can be written into can also be read back. This
allows the processor controlling the S/UNI-QUAD to determine the
programming state of the block.
3. Writable normal mode register bits are cleared to logic zero upon reset unless
otherwise noted.
4. Writing into read-only normal mode register bit locations does not affect
S/UNI-QUAD operation unless otherwise noted. Performance monitoring
counters registers are a common exception.
5. Certain register bits are reserved. These bits are associated with megacell
functions that are unused in this application. To ensure that the S/UNI-QUAD
operates as intended, reserved register bits must be written with their default
value as indicated by the register bit description.
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Register 0x00: S/UNI-QUAD Master Reset and Identity
Bit TypeFunctionDefault
Bit 7R/WRESET0
Bit 6RTYPE[3]1
Bit 5RTYPE[2]1
Bit 4RTYPE[1]1
Bit 3RTYPE[0]0
Bit 2RID[2]0
Bit 1RID[1]0
Bit 0RID[0]1
This register allows the revision of the S/UNI-QUAD to be read by software
permitting graceful migration to support newer feature enhanced versions of the
S/UNI-QUAD. It also provides software reset capability.
In addition, writing to this register simultaneously loads all the performance meter
registers in the RSOP, RLOP, RPOP, RXCP and TXCP blocks.
ID[2:0]:
The ID bits can be read to provide a binary S/UNI-QUAD revision number.
TYPE[3:0]:
The TYPE bits distinguish the S/UNI-QUAD from the other members of the
S/UNI family of devices.
RESET:
The RESET bit allows the S/UNI-QUAD to be reset under software control. If
the RESET bit is a logic one, the entire S/UNI-QUAD is held in reset. This bit
is not self-clearing. Therefore, a logic zero must be written to bring the
S/UNI-QUAD out of reset. Holding the S/UNI-QUAD in a reset state places it
into a low power, stand-by mode. A hardware reset clears the RESET bit,
thus negating the software reset. Otherwise, the effect of a software reset is
equivalent to that of a hardware reset.
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Register 0x01: S/UNI-QUAD Master Configuration
Bit TypeFunctionDefault
Bit 7R/WPECLV0
Bit 6R/WReserved0
Bit 5R/WTFPO_CH[1]0
Bit 4R/WTFPO_CH[0]0
Bit 3R/WReserved 0
Bit 2R/WReserved0
Bit 1R/WReserved1
Bit 0R/WReserved1
TFPO_CH[1:0]:
The transmit frame pulse channel select (TFPO_CH[1:0]) bits selects which
channel’s transmit frame pulse is available on the TFPO output pin. Since the
RFPO1-4 output pins are providing transmit timing information for loop-timed
channels, it is suggested (but not mandatory) that a self-timed channel be
selected. Self-timed channels all operate off the same clock synthesis unit
and thus have a common timing reference (their frequency will be identical
although their frame pulses might not be aligned).
The PECL reveiver input voltage (PECLV) bit configures the PECL receiver
level shifter. When PECLV is set to logic zero, the PECL receivers are
configured to operate with a 3.3V input voltage. When PECLV is set to logic
one, the PECL receivers are configured to operate with a 5.0V input voltage.
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Reserved:
The reserved bits must be programmed to their default value proper
operation.
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Register 0x02: S/UNI-QUAD Master System Interface Control
Bit TypeFunctionDefault
Bit 7R/WPHY_ADR[2]0
Bit 6R/WPHY_ADR[1]0
Bit 5R/WPHY_ADR[0]0
Bit 4R/WPHY_EN0
Bit 3UnusedX
Bit 2R/WReserved0
Bit 1R/WReserved 0
Bit 0R/WReserved0
PHY_EN:
The PHY_EN enables the System Interface (Utopia bus).
When set to logic zero, all the output signals of the System Interface are held
in high impedance. When set to logic one, the System Interface is driven. This
register bit must be set to logic one to start using the device. If the System
Interface is shared by several PHY layer devices, they should all be
configured with their own unique PHY_ADR[2:0] (see below) value before
enabling them, otherwise conflicts could occur on the bus resulting in
damages to the devices.
PHY_ADR[2:0]:
The PHY_ADR[2:0] is Device Identification Address (PHY_ADR[2:0]). The
PHY_ADR[2:0] register bits are the most-significant bits of the address space
which this S/UNI-QUAD occupies. When the PHY_ADR[2:0] inputs match the
TADR[4:2] or RADR[4:2] inputs, then one of the four quadrants (as
determined by the TADR[1:0] or RADR[1:0] inputs) in this S/UNI-QUAD is
selected for transmit or receive operations. Note that the null-PHY address
0x1F is the null-PHY address and cannot be assigned to any port on the
S/UNI-QUAD.
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Register 0x03: S/UNI-QUAD Master Clock Monitor
Bit TypeFunctionDefault
Bit 7RRCLK4AX
Bit 6RRCLK3AX
Bit 5RRCLK2AX
Bit 4RRCLK1AX
Bit 3RTCLKAX
Bit 2RRFCLKAX
Bit 1RTFCLKAX
Bit 0RREFCLKAX
This register provides activity monitoring on S/UNI-QUAD clocks. When a
monitored clock signal makes a low to high transition, the corresponding register
bit is set high. The bit will remain high until this register is read, at which point, all
the bits in this register are cleared. A lack of transitions is indicated by the
corresponding register bit reading low. This register should be read at periodic
intervals to detect clock failures.
REFCLKA:
The REFCLK active (REFCLKA) bit monitors for low to high transitions on the
REFCLK reference clock input. REFCLKA is set high on a rising edge of
REFCLK, and is set low when this register is read.
TFCLKA:
The TFCLK active (TFCLKA) bit monitors for low to high transitions on the
TFCLK transmit FIFO clock input. TFCLKA is set high on a rising edge of
TFCLK, and is set low when this register is read.
RFCLKA:
The RFCLK active (RFCLKA) bit monitors for low to high transitions on the
RFCLK receive FIFO clock input. RFCLKA is set high on a rising edge of
RFCLK, and is set low when this register is read.
TCLKA:
The TCLK active (TCLKA) bit monitors for low to high transitions on the TCLK
output. TCLKA is set high on a rising edge of TCLK, and is set low when this
register is read.
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RCLK1A:
The Channel #1 RCLK active (RCLK1A) bit monitors for low to high transitions
on the RCLK1 output. RCLK1A is set high on a rising edge of RCLK1, and is
set low when this register is read.
RCLK2A:
The Channel #2 RCLK active (RCLK2A) bit monitors for low to high transitions
on the RCLK2 output. RCLK2A is set high on a rising edge of RCLK2, and is
set low when this register is read.
RCLK3A:
The Channel #3 RCLK active (RCLK3A) bit monitors for low to high transitions
on the RCLK3 output. RCLK3A is set high on a rising edge of RCLK3, and is
set low when this register is read.
RCLK4A:
The Channel #4 RCLK active (RCLK4A) bit monitors for low to high transitions
on the RCLK4 output. RCLK4A is set high on a rising edge of RCLK4, and is
set low when this register is read.
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Register 0x04: S/UNI-QUAD Master Interrupt Status
Bit TypeFunctionDefault
Bit 7UnusedX
Bit 6UnusedX
Bit 5UnusedX
Bit 4RCSUIX
Bit 3RCHNL4IX
Bit 2RCHNL3IX
Bit 1RCHNL2IX
Bit 0RCHNL1IX
When the interrupt output INTB goes low, this register allows the source of an
active interrupt to be identified down to the channel level. Further register
accesses are required for the channel in question to determine the cause of an
active interrupt and to acknowledge the interrupt source.
CHNL1I:
The CHNL1I bit is high when an interrupt request is active from the channel
#1. The Channel #1 Interrupt Status register should be read to identify the
source of the interrupt.
CHNL2I:
The CHNL2I bit is high when an interrupt request is active from the channel
#2. The Channel #2 Interrupt Status register should be read to identify the
source of the interrupt.
CHNL3I:
The CHNL3I bit is high when an interrupt request is active from the channel
#3. The Channel #3 Interrupt Status register should be read to identify the
source of the interrupt.
CHNL4I:
The CHNL4I bit is high when an interrupt request is active from the channel
#4. The Channel #4 Interrupt Status register should be read to identify the
source of the interrupt.
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CSUI:
The CSUI bit is high when an interrupt request is active from the Clock
Synthesis and PISO block (CSPI, Clock Synthesis Unit). The CSUI interrupt
sources are enabled in the Clock Synthesis Interrupt Control/Status Register.
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Register 0x05: S/UNI-QUAD Channel Reset and Monitoring Update
Bit TypeFunctionDefault
Bit 7R/WCHRESET0
Bit 6UnusedX
Bit 5UnusedX
Bit 4UnusedX
Bit 3UnusedX
Bit 2UnusedX
Bit 1UnusedX
Bit 0RTIPX
This register provides software reset capability on a per channel basis. It also
loads, by writing this register (without setting the CHRESET bit), all the error
counters in the RSOP, RLOP, RPOP, RXCP and TXCP blocks.
TIP:
The TIP bit is set to a logic one when any value with the CHRESET bit set to
logic zero is written to this register. Such a write initiates an accumulation
interval transfer and loads all the performance meter registers in the RSOP,
RLOP, RPOP, RXCP and TXCP blocks for channel #1. TIP remains high while
the transfer is in progress, and is set to a logic zero when the transfer is
complete. TIP can be polled by a microprocessor to determine when the
accumulation interval transfer is complete.
CHRESET:
The CHRESET bit allows the Channel to be reset under software control. If
the CHRESET bit is a logic one, the entire channel is held in reset. This bit is
not self-clearing. Therefore, a logic zero must be written to bring the channel
out of reset. Holding a channel in a reset state places it into a low power,
stand-by mode. A hardware reset clears the CHRESET bit, thus negating the
software reset. Otherwise, the effect of a software reset is equivalent to that
of a hardware reset.
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Register 0x06: S/UNI-QUAD Channel Configuration
Bit TypeFunctionDefault
Bit 7R/WAUTOPFEBE1
Bit 6R/WAUTOLFEBE1
Bit 5R/WAUTOLRDI1
Bit 4R/WAUTOPRDI1
Bit 3R/WReserved0
Bit 2R/WReserved0
Bit 1R/WReserved0
Bit 0R/WReserved1
AUTOPRDI
The AUTOPRDI bit determines whether STS path remote defect indication
(RDI) is sent immediately upon detection of an incoming alarm. When
AUTOPRDI is set to logic one, STS path RDI is inserted immediately upon
declaration of several alarms. Each alarm can individually be enabled and
disabled using the S/UNI-QUAD Channel Path RDI Control Registers.
AUTOLRDI
The AUTOLRDI bit determines if line remote defect indication (RDI) is sent
immediately upon detection of an incoming alarm. When AUTOLRDI is set to
logic one, line RDI is inserted immediately upon declaration of several
alarms. Each alarm can individually be enabled and disabled using the S/UNIQUAD Channel Line RDI Control Registers.
AUTOPFEBE
The AUTOPFEBE bit determines if the path far end block errors are sent upon
detection of an incoming path BIP error events. When AUTOPFEBE is set to
logic one, one path FEBE is inserted for each path BIP error event,
respectively. When AUTOPFEBE is set to logic zero, incoming path BIP error
events do not generate FEBE events.
AUTOLFEBE
The AUTOLFEBE bit determines if line far end block errors are sent upon
detection of an incoming line BIP error events. When AUTOLFEBE is set to
logic one, one line FEBE is inserted for each line BIP error event, respectively.
When AUTOLFEBE is set to logic zero, incoming line BIP error events do not
generate FEBE events.
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Register 0x07: S/UNI-QUAD Channel Control
Bit TypeFunctionDefault
Bit 7R/WTFPI_EN0
Bit 6R/WReserved0
Bit 5R/WRXDINV0
Bit 4UnusedX
Bit 3R/WPDLE0
Bit 2R/WLLE0
Bit 1R/WSDLE0
Bit 0R/WLOOPT0
This register controls the timing and high speed loopback features of the
S/UNI-QUAD.
LOOPT:
The LOOPT bit selects the source of timing for the transmit section of the
channel. When LOOPT is a logic zero, the transmitter timing is derived from
input REFCLK (Clock Synthesis Unit) is used. When LOOPT is a logic one,
the transmitter timing is derived from the recovered clock. (Clock Recovery
Unit).
SDLE:
The SDLE bit enables the serial diagnostic loopback. When SDLE is a logic
one, the transmit serial stream is connected to the receive stream. The SDLE
and the LLE bits should not be set high simultaneously.
LLE:
The LLE bit enables the S/UNI-QUAD line loopback. When LLE is a logic
one, the value on RXD+/- differential inputs is synchronously mapped to the
TXD+/- differential outputs, after clock recovery. The SDLE and the LLE bits
should not be set high simultaneously.
PDLE:
The PDLE bit enables the parallel diagnostic loopback. When PDLE is a logic
one, the transmit parallel stream is connected to the receive stream. The
loopback point is between the TPOP and the RPOP blocks. Blocks upstream
of the loopback point continue to operate normally. For example line AIS may
be inserted in the transmit stream upstream of the loopback point using the
TSOP Control register.
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RXDINV:
The RXDINV bit selects the active polarity of the RXD+/- signals. The default
configuration selects RXD+ to be active high and RXD- to be active low.
When RXDINV is set to logic one, RXD+ to be active low and RXD- to be
active high.
TFPI_EN:
The TFPI_EN bit controls the framing alignment in the transmit direction.
When TFPI_EN is set to logic one the transmit SONET/SDH framing is
aligned to a master (available to all four channels) framing pulse counter,
which can also be aligned to the TFPI device input. When TFPI_EN is set to
logic zero the transmit framing alignment is arbitrary. External framing
(TFPI_EN set to logic one) shall only be used when the channel is in selftimed mode. TFPI_EN should always be set to logic zero when the channel is
loop-timed (LOOPT set to logic one) or in line loopback (LLE set to logic one).
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Register 0x08: S/UNI-QUAD Channel Control Extension
Bit TypeFunctionDefault
Bit 7UnusedX
Bit 6UnusedX
Bit 5UnusedX
Bit 4UnusedX
Bit 3UnusedX
Bit 2R/WReserved0
Bit 1R/WReserved0
Bit 0R/WReserved0
This register controls the timing and high speed loopback features of the
S/UNI-QUAD.
Reserved:
The reserved bits must be programmed to their default value proper
operation.
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Register 0x0A: S/UNI-QUAD Channel Interrupt Status #1
Bit TypeFunctionDefault
Bit 7UnusedX
Bit 6RRASEI X
Bit 5RCRUIX
Bit 4RTXCPIX
Bit 3RRXCPIX
Bit 2RRPOPIX
Bit 1RRLOPIX
Bit 0RRSOPIX
This register allows the source of an active interrupt to be identified down to the
block level within a given channel. Further register accesses are required for the
block in question to determine the cause of an active interrupt and to
acknowledge the interrupt source.
RSOPI:
The RSOPI bit is high when an interrupt request is active from the RSOP
block. The RSOP interrupt sources are enabled in the RSOP Control/Interrupt
Enable Register.
RLOPI:
The RLOPI bit is high when an interrupt request is active from the RLOP
block. The RLOP interrupt sources are enabled in the RLOP Interrupt
Enable/Status Register.
RPOPI:
The RPOPI bit is high when an interrupt request is active from the RPOP
block. The RPOP interrupt sources are enabled in the RPOP Interrupt Enable
Register.
RXCPI:
The RXCPI bit is high when an interrupt request is active from the RXCP
block. The RXCP interrupt sources are enabled in the RXCP Interrupt
Enable/Status Register.
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TXCPI:
The TXCPI bit is high when an interrupt request is active from the TXCP
block. The TXCP interrupt sources are enabled in the TXCP Interrupt
Control/Status Register.
CRUI:
The CRUI bit is high when an interrupt request is active from the Clock
Recovery and SIPO block (CRSI, Clock Recovery Unit). The CRUI interrupt
sources are enabled in the Clock Recovery Interrupt Control/Status Register.
RASEI:
The RASEI bit is high when an interrupt request is active from the RASE
block. The RASE interrupt sources are enabled in the RASE Interrupt Enable
Register.
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Register 0x0C: CSPI (Clock Synthesis) Control and Status
Bit TypeFunctionDefault
Bit 7R/WReserved0
Bit 6R/WReserved 0
Bit 5RTROOLIX
Bit 4UnusedX
Bit 3RTROOLVX
Bit 2UnusedX
Bit 1R/WTROOLE0
Bit 0R/WReserved0
This register controls the clock synthesis and reports the state of the transmit
phase locked loop.
TROOLE:
The TROOLE bit is an interrupt enable for the transmit reference out of lock
status. When TROOLE is set to logic one, an interrupt is generated when the
TROOLV bit changes state.
TROOLV:
The transmit reference out of lock status indicates the clock synthesis phase
locked loop is unable to lock to the reference on REFCLK. TROOLV is a logic
one if the divided down synthesized clock frequency is not within 488 ppm of
the REFCLK frequency.
TROOLI:
The TROOLI bit is the transmit reference out of lock interrupt status bit.
TROOLI is set high when the TROOLV bit of the S/UNI-QUAD Clock
Synthesis Control and Status register changes state. TROOLV indicates the
clock synthesis phase locked loop is unable to lock to the reference on
REFCLK and is a logic one if the divided down synthesized clock frequency is
not within 488 ppm of the REFCLK frequency. TROOLI is cleared when this
register is read.
Reserved:
The reserved bits must be programmed to logic zero for proper operation.
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Register 0x0D: CSPI (Clock Synthesis) Reserved
Bit TypeFunctionDefault
Bit 7UnusedX
Bit 6UnusedX
Bit 5UnusedX
Bit 4UnusedX
Bit 3R/WReserved0
Bit 2R/WReserved0
Bit 1R/WReserved0
Bit 0R/WReserved0
Reserved:
The reserved bits must be programmed to logic zero for proper operation.
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Register 0x0E: CRSI (Clock Recovery) Control and Status
Bit TypeFunctionDefault
Bit 7R/WReserved0
Bit 6RRROOLIX
Bit 5RRDOOLIX
Bit 4RRROOLVX
Bit 3RRDOOLVX
Bit 2R/WRROOLE0
Bit 1R/WRDOOLE0
Bit 0R/WReserved0
This register controls the clock recovery and reports the state of the receive
phase locked loop.
RDOOLE:
The RDOOLE bit is an interrupt enable for the receive data out of lock status.
When RDOOLE is set to logic one, an interrupt is generated when the
RDOOLV bit changes state.
RROOLE:
The RROOLE bit is an interrupt enable for the reference out of lock status.
When RROOLE is set to logic one, an interrupt is generated when the
RROOLV bit changes state.
RDOOLV:
The receive data out of lock status indicates the clock recovery phase locked
loop is unable to lock to the incoming data stream. RDOOLV is a logic one if
the divided down recovered clock frequency is not within 488 ppm of the
REFCLK frequency or if no transitions have occurred on the RXD+/- inputs for
more than 80 bit periods.
RROOLV:
The receive reference out of lock status indicates the clock recovery phase
locked loop is unable to lock to the receive reference (REFCLK). RROOLV
should be polled after a power up reset to determine when the CRU PLL is
operational. When RROOLV is a logic one, the CRU is unable to lock to the
receive reference. When RROOLV is a logic zero, the CRU is locked to the
receive reference. The RROOLV bit may remain set at logic one for several
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hundred milliseconds after the removal of the power on reset as the CRU PLL
locks to the receive reference clock.
RDOOLI:
The RDOOLI bit is the receive data out of lock interrupt status bit. RDOOLI is
set high when the RDOOLV bit of the S/UNI-QUAD Clock Recovery Control
and Status register changes state. RDOOLI is cleared when this register is
read.
RROOLI:
The RROOLI bit is the receive reference out of lock interrupt status bit.
RROOLI is set high when the RROOLV bit of the Clock Synthesis Control and
Status register changes state. RROOLI is cleared when this register is read.
Reserved:
The reserved bits must be programmed to logic zero for proper operation.
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Register 0x0F: CRSI (Clock Recovery) Reserved
Bit TypeFunctionDefault
Bit 7R/WReserved 0
Bit 6R/WReserved 0
Bit 5R/WReserved 0
Bit 4R/WReserved 0
Bit 3R/WReserved0
Bit 2R/WReserved0
Bit 1R/WReserved0
Bit 0R/WReserved0
Reserved:
The reserved bits must be programmed to logic zero for proper operation.
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Register 0x10: RSOP Control/Interrupt Enable
Bit TypeFunctionDefault
Bit 7R/WBIPWORD0
Bit 6R/WDDS0
Bit 5WFOOFX
Bit 4R/WALGO2 0
Bit 3R/WBIPEE0
Bit 2R/WLOSE0
Bit 1R/WLOFE0
Bit 0R/WOOFE0
OOFE:
The OOFE bit is an interrupt enable for the out of frame alarm. When OOFE
is set to logic one, an interrupt is generated when the out of frame alarm
changes state.
LOFE:
The LOFE bit is an interrupt enable for the loss of frame alarm. When LOFE
is set to logic one, an interrupt is generated when the loss of frame alarm
changes state.
LOSE:
The LOSE bit is an interrupt enable for the loss of signal alarm. When LOSE
is set to logic one, an interrupt is generated when the loss of signal alarm
changes state.
BIPEE:
The BIPEE bit is an interrupt enable for the section BIP-8 errors. When
BIPEE is set to logic one, an interrupt is generated when a section BIP-8 error
(B1) is detected.
ALGO2:
The ALGO2 bit position selects the framing algorithm used to confirm and
maintain the frame alignment. When a logic one is written to the ALGO2 bit
position, the framer is enabled to use the second of the framing algorithms
where only the first A1 framing byte and the first 4 bits of the last A2 framing
byte (12 bits total) are examined. This algorithm examines only 12 bits of the
framing pattern regardless of the STS mode; all other framing bits are
ignored. When a logic zero is written to the ALGO2 bit position, the framer is
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enabled to use the first of the framing algorithms where all the A1 framing
bytes and all the A2 framing bytes are examined. This algorithm examines all
48 bits of the STS-3c (STM-1/AU3/AU4) framing pattern.
FOOF:
The FOOF bit controls the framing of the RSOP. When a logic one is written
to FOOF, the RSOP is forced out of frame at the next frame boundary. The
FOOF bit is a write only bit, register reads may yield a logic one or a logic
zero.
DDS:
The DDS bit is set to logic one to disable the de-scrambling of the STS-3c
(STM-1) stream. When DDS is a logic zero, de-scrambling is enabled.
BIPWORD:
The BIPWORD bit position enables the accumulating of section block BIP
errors. When a logic one is written to the BIPWORD bit position, one or more
errors in the BIP-8 byte result in a single error accumulated in the B1 error
counter. When a logic zero is written to the BIPWORD bit position, all errors
in the B1 byte are accumulated in the B1 error counter.
Reserved:
The reserved bits must be programmed to logic zero for proper operation.
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Register 0x11: RSOP Status/Interrupt Status
Bit TypeFunctionDefault
Bit 7UnusedX
Bit 6RBIPEIX
Bit 5RLOSIX
Bit 4RLOFIX
Bit 3ROOFIX
Bit 2RLOSVX
Bit 1RLOFVX
Bit 0ROOFVX
OOFV:
The OOFV bit is read to determine the out-of-frame state of the RSOP. When
OOFV is high, the RSOP is out of frame. When OOFV is low, the RSOP is inframe.
LOFV:
The LOFV bit is read to determine the loss of frame state of the RSOP. When
LOFV is high, the RSOP has declared loss of frame.
LOSV:
The LOSV bit is read to determine the loss of signal state of the RSOP. When
LOSV is high, the RSOP has declared loss of signal.
OOFI:
The OOFI bit is the out of frame interrupt status bit. OOFI is set high when a
change in the out-of-frame state occurs. This bit is cleared when this register
is read.
LOFI:
The LOFI bit is the loss of frame interrupt status bit. LOFI is set high when a
change in the loss-of-frame state occurs. This bit is cleared when this register
is read.
LOSI:
The LOSI bit is the loss of signal interrupt status bit. LOSI is set high when a
change in the loss-of-signal state occurs. This bit is cleared when this register
is read.
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BIPEI:
The BIPEI bit is the section BIP-8 interrupt status bit. BIPEI is set high when
a section layer (B1) bit error is detected. This bit is cleared when this register
is read.
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Register 0x12: RSOP Section BIP-8 LSB
Bit TypeFunctionDefault
Bit 7RSBE[7]X
Bit 6RSBE[6]X
Bit 5RSBE[5]X
Bit 4RSBE[4]X
Bit 3RSBE[3]X
Bit 2RSBE[2]X
Bit 1RSBE[1]X
Bit 0RSBE[0]X
Register 0x13: RSOP Section BIP-8 MSB
Bit TypeFunctionDefault
Bit 7RSBE[15]X
Bit 6RSBE[14]X
Bit 5RSBE[13]X
Bit 4RSBE[12]X
Bit 3RSBE[11]X
Bit 2RSBE[10]X
Bit 1RSBE[9]X
Bit 0RSBE[8]X
SBE[15:0]:
Bits SBE[15:0] represent the number of section BIP-8 errors (individual or
block) that have been detected since the last time the error count was polled.
The error count is polled by writing to either of the RSOP Section BIP-8
Register addresses. Such a write transfers the internally accumulated error
count to the Section BIP-8 registers within approximately 7 µs and
simultaneously resets the internal counter to begin a new cycle of error
accumulation. This transfer and reset is carried out in a manner that ensures
that coincident events are not lost.
The count can also be polled by writing to the Master Reset and Identity /
Load Performance Meters register (0x05). Writing to register 0x05
simultaneously loads all the performance meter registers in the RSOP, RLOP,
RPOP, RXCP and TXCP blocks.
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Register 0x14: TSOP Control
Bit TypeFunctionDefault
Bit 7UnusedX
Bit 6R/WDS0
Bit 5R/WReserved0
Bit 4R/WReserved0
Bit 3R/WReserved0
Bit 2R/WReserved0
Bit 1R/WReserved0
Bit 0R/WLAIS0
LAIS:
The LAIS bit controls the insertion of line alarm indication signal (AIS). When
LAIS is set to logic one, the TSOP inserts AIS into the transmit SONET/SDH
stream. Activation or deactivation of line AIS insertion is synchronized to
frame boundaries. Line AIS insertion results in all bits of the SONET/SDH
frame being set to one prior to scrambling except for the section overhead.
DS:
The DS bit is set to logic one to disable the scrambling of the STS-3c (STM-1)
stream. When DS is a logic zero, scrambling is enabled.
Reserved:
The reserved bits must be programmed to logic zero for proper operation.
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Register 0x15: TSOP Diagnostic
Bit TypeFunctionDefault
Bit 7UnusedX
Bit 6UnusedX
Bit 5UnusedX
Bit 4UnusedX
Bit 3UnusedX
Bit 2R/WDLOS0
Bit 1R/WDBIP80
Bit 0R/WDFP0
DFP:
The DFP bit controls the insertion of a single bit error continuously in the most
significant bit (bit 1) of the A1 section overhead framing byte. When DFP is
set to logic one, the A1 bytes are set to 0x76 instead of 0xF6.
DBIP8:
The DBIP8 bit controls the insertion of bit errors continuously in the section
BIP-8 byte (B1). When DBIP8 is set to logic one, the B1 byte is inverted.
DLOS:
The DLOS bit controls the insertion of all zeros in the transmit stream. When
DLOS is set to logic one, the transmit stream is forced to 0x00.
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Register 0x18: RLOP Control/Status
Bit TypeFunctionDefault
Bit 7R/WBIPWORD0
Bit 6R/WALLONES0
Bit 5R/WAISDET0
Bit 4R/WLRDIDET0
Bit 3R/WBIPWORDO0
Bit 2R/WFEBEWORD0
Bit 1RLAISVX
Bit 0RLRDIVX
LRDIV:
The LRDIV bit is read to determine the remote defect indication state of the
RLOP. When LRDIV is high, the RLOP has declared line RDI.
LAISV:
The LAISV bit is read to determine the line AIS state of the RLOP. When
LAISV is high, the RLOP has declared line AIS.
FEBEWORD:
The FEBEWORD bit controls the accumulation of FEBEs. When
FEBEWORD is logic one, the FEBE event counter is incremented only once
per frame, whenever one or more FEBE bits occur during that frame. When
FEBEWORD is logic zero, the FEBE event counter is incremented for each
and every FEBE bit that occurs during that frame (the counter can be
incremented up to 24).
BIPWORDO:
The BIPWORDO bit controls the indication of B2 errors reported to the TLOP
block for insertion as FEBEs. When BIPWORDO is logic one, the BIP errors
are indicated once per frame whenever one or more B2 bit errors occur
during that frame. When BIPWORD0 is logic zero, BIP errors are indicated
once for every B2 bit error that occurs during that frame. The accumulation of
B2 error events functions independently and is controlled by the BIPWORD
register bit..
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LRDIDET:
The LRDIDET bit determines the Line LRDI detection algorithm. When
LRDIDET is set to logic one, Line LRDI is declared when a 110 binary pattern
is detected in bits 6,7 and 8 of the K2 byte for three consecutive frames.
When LRDIDET is set to logic zero, Line LRDI is declared when a 110 binary
pattern is detected in bits 6,7 and 8 of the K2 byte for five consecutive frames.
AISDET:
The AISDET bit determines the Line AIS detection algorithm. When AISDET
is set to logic one, Line AIS is declared when a 111 binary pattern is detected
in bits 6,7 and 8 of the K2 byte for three consecutive frames. When AISDET
is set to logic zero, Line AIS is declared when a 111 binary pattern is detected
in bits 6,7 and 8 of the K2 byte for five consecutive frames.
ALLONES:
The ALLONES bit controls automatically forcing the SONET frame passed to
downstream blocks to logical all-ones whenever LAIS is detected. When
ALLONES is set to logic one, the SONET frame is forced to logic one
immediately when the LAIS alarm is declared. When LAIS is removed, the
received byte is immediately returned to carrying data. When ALLONES is
set to logic zero, the received byte carries the data regardless of the state of
LAIS.
BIPWORD:
The BIPWORD bit controls the accumulation of B2 errors. When BIPWORD
is logic one, the B2 error event counter is incremented only once per frame
whenever one or more B2 bit errors occur during that frame. When
BIPWORD is logic zero, the B2 error event counter is incremented for each
B2 bit error that occurs during that frame (the counter can be incremented up
to 24 times per frame).
Reserved:
The reserved bits must be programmed to logic zero for proper operation.
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Register 0x19: RLOP Interrupt Enable/Interrupt Status
Bit TypeFunctionDefault
Bit 7R/WFEBEE0
Bit 6R/WBIPEE0
Bit 5R/WLAISE0
Bit 4R/WLRDIE0
Bit 3RFEBEIX
Bit 2RBIPEIX
Bit 1RLAISIX
Bit 0RLRDIIX
LRDII:
The LRDII bit is the line far end receive failure interrupt status bit. LRDII is set
high when a change in the line RDI state occurs. This bit is cleared when this
register is read.
LAISI:
The LAISI bit is the line AIS interrupt status bit. LAISI is set high when a
change in the line AIS state occurs. This bit is cleared when this register is
read.
BIPEI:
The BIPEI bit is the line BIP interrupt status bit. BIPEI is set high when a line
layer (B2) bit error is detected. This bit is cleared when this register is read.
FEBEI:
The FEBEI bit is the line far end block error interrupt status bit. FEBEI is set
high when a line layer FEBE (M1) is detected. This bit is cleared when this
register is read.
LRDIE:
The LRDIE bit is an interrupt enable for the line remote defect indication
alarm. When LRDIE is set to logic one, an interrupt is generated when line
RDI changes state.
LAISE:
The LAISE bit is an interrupt enable for line AIS. When LAISE is set to logic
one, an interrupt is generated when line AIS changes state.
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BIPEE:
The BIPEE bit is an interrupt enable for the line BIP-24 errors. When BIPEE
is set to logic one, an interrupt is generated when a line BIP-24 error (B2) is
detected.
FEBEE:
The FEBEE bit is an interrupt enable for the line far end block errors. When
FEBEE is set to logic one, an interrupt is generated when FEBE (M1) is
detected.
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Register 0x1A: RLOP Line BIP-24 LSB
Bit TypeFunctionDefault
Bit 7RLBE[7]X
Bit 6RLBE[6]X
Bit 5RLBE[5]X
Bit 4RLBE[4]X
Bit 3RLBE[3]X
Bit 2RLBE[2]X
Bit 1RLBE[1]X
Bit 0RLBE[0]X
Register 0x1B: RLOP Line BIP-24
Bit TypeFunctionDefault
Bit 7RLBE[15]X
Bit 6RLBE[14]X
Bit 5RLBE[13]X
Bit 4RLBE[12]X
Bit 3RLBE[11]X
Bit 2RLBE[10]X
Bit 1RLBE[9]X
Bit 0RLBE[8]X
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Register 0x1C: RLOP Line BIP-24 MSB
Bit TypeFunctionDefault
Bit 7UnusedX
Bit 6UnusedX
Bit 5UnusedX
Bit 4UnusedX
Bit 3RLBE[19]X
Bit 2RLBE[18]X
Bit 1RLBE[17]X
Bit 0RLBE[16]X
LBE[19:0]
Bits LBE[19:0] represent the number of line BIP-24 errors (individual or block)
that have been detected since the last time the error count was polled. The
error count is polled by writing to any of the RLOP Line BIP Registers or Line
FEBE Register addresses. Such a write transfers the internally accumulated
error count to the Line BIP Registers within approximately 7 µs and
simultaneously resets the internal counter to begin a new cycle of error
accumulation.
The count can also be polled by writing to the
and Monitoring Update register (0x05)
. Writing to register 0x05 simultaneously
S/UNI-QUAD Channel Reset
loads all the performance meter registers in the RSOP, RLOP, RPOP, RXCP
and TXCP blocks.
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Register 0x1D: RLOP Line FEBE LSB
Bit TypeFunctionDefault
Bit 7RLFE[7]X
Bit 6RLFE[6]X
Bit 5RLFE[5]X
Bit 4RLFE[4]X
Bit 3RLFE[3]X
Bit 2RLFE[2]X
Bit 1RLFE[1]X
Bit 0RLFE[0]X
Register 0x1E: RLOP Line FEBE
Bit TypeFunctionDefault
Bit 7RLFE[15]X
Bit 6RLFE[14]X
Bit 5RLFE[13]X
Bit 4RLFE[12]X
Bit 3RLFE[11]X
Bit 2RLFE[10]X
Bit 1RLFE[9]X
Bit 0RLFE[8]X
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Register 0x1F: RLOP Line FEBE MSB
Bit TypeFunctionDefault
Bit 7UnusedX
Bit 6UnusedX
Bit 5UnusedX
Bit 4UnusedX
Bit 3RLFE[19]X
Bit 2RLFE[18]X
Bit 1RLFE[17]X
Bit 0RLFE[16]X
LFE[19:0]
Bits LFE[19:0] represent the number of line FEBE errors (individual or block)
that have been detected since the last time the error count was polled. The
error count is polled by writing to any of the RLOP Line BIP Registers or Line
FEBE Register addresses. Such a write transfers the internally accumulated
error count to the Line FEBE Registers within approximately 7 µs and
simultaneously resets the internal counter to begin a new cycle of error
accumulation.
The count can also be polled by writing to the
and Monitoring Update register (0x05)
. Writing to register 0x05 simultaneously
S/UNI-QUAD Channel Reset
loads all the performance meter registers in the RSOP, RLOP, RPOP, RXCP
and TXCP blocks.
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