PMC PM5349-BI Datasheet
PMC-Sierra, Inc.
/
S/UNI-QUAD
DATASHEET
PMC-971239 ISSUE 6 SATURN USER NETWORK INTERFACE (155-QUAD)
PM5349 S/UNI-QUAD
PM5349
®
UNI-
S
QUAD
155-
S/UNI-QUAD
SATURN
USER NETWORK INTERFACE
(155-QUAD)
DATASHEET
ISSUE 6: JULY 1999
PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000
PMC-Sierra, Inc.
S/UNI-QUAD
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PM5349 S/UNI-QUAD
REVISION HISTORY
Issue
Issue Date Details of Change
No.
6 July, 1999 General Update:
•
Section 4: Augmented the DEFINITIONS table
•
Section 9.6: Changed TDO output drive from 2mA to 1mA, changed
other DC currents from 16mA to 4mA and 4mA to 2mA
•
Section 11: Added RPOP PAISCONV and LOPCONV status bits in
Register 0x30
•
Section 11: Clarified EPRDIEN register bit description in Register
0x40
•
Section 11: Added H4INSB register bit to Register 0x82
•
Section 11: Fixed logic level specification in Register 0x91
•
Section 11: Changed Z1/S1_CAP bit description in Register 0xE2
•
Section 13.8: Enhanced Power Supply Sequencing information
•
Section 13.9: Analog Power Supply Filtering new recommendations
•
Section 16: DC Characteristics updated into include IDDOP values
•
Section 19: Maximum temperature changed from TC = +85°C to TA
= +85°C. Added Airflow versus Theta JA chart.
5 January, 1999 General update
4 September, 1998 General Update
PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000
PMC-Sierra, Inc.
S/UNI-QUAD
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PM5349 S/UNI-QUAD
CONTENTS
1 FEATURES ........................................................................................................................1
1.1 GENERAL.............................................................................................................1
1.2 THE SONET RECEIVER......................................................................................1
1.3 THE RECEIVE ATM PROCESSOR......................................................................2
1.4 THE SONET TRANSMITTER...............................................................................2
1.5 THE TRANSMIT A TM PROCESSOR ...................................................................3
2 APPLICATIONS .................................................................................................................4
3 REFERENCES ..................................................................................................................5
4 DEFINITIONS....................................................................................................................6
5 APPLICATION EXAMPLES...............................................................................................7
6 BLOCK DIAGRAM.............................................................................................................8
7 DESCRIPTION ..................................................................................................................9
8 PIN DIAGRAM.................................................................................................................11
9 PIN DESCRIPTION .........................................................................................................12
9.1 LINE SIDE INTERFACE SIGNALS ....................................................................12
9.2 UTOPIA LEVEL 2 SYSTEM INTERFACE ..........................................................15
9.3 MICROPROCESSOR INTERFACE SIGNALS ...................................................23
9.4 JTAG TEST ACCESS PORT (TAP) SIGNALS....................................................25
9.5 ANALOG SIGNALS ............................................................................................26
9.6 POWER AND GROUND.....................................................................................26
10 FUNCTIONAL DESCRIPTION ........................................................................................32
10.1 RECEIVE LINE INTERFACE (CRSI)..................................................................32
10.1.1 CLOCK RECOVERY.......................................................................32
10.1.2 SERIAL TO P ARALLEL CONVERTER ...........................................33
10.2 RECEIVE SECTION OVERHEAD PROCESSOR (RSOP)................................33
10.2.1 FRAMER.........................................................................................33
10.2.2 DESCRAMBLE................................................................................34
10.2.3 ERROR MONITOR..........................................................................34
10.2.4 LOSS OF SIGNAL ..........................................................................34
10.2.5 LOSS OF FRAME...........................................................................35
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10.3 RECEIVE LINE OVERHEAD PROCESSOR (RLOP).........................................35
10.3.1 LINE RDI DETECT..........................................................................35
10.3.2 LINE AIS DETECT..........................................................................35
10.3.3 ERROR MONITOR BLOCK............................................................35
10.4 THE RECEIVE APS, SYNCHRONIZATION EXTRACTOR AND BIT ERROR
MONITOR (RASE)..............................................................................................36
10.4.1 AUTOM ATIC PROTECTION SWITCH CONTROL..........................36
10.4.2 BIT ERROR RATE MONITOR.........................................................37
10.4.3 SYNCHRONIZATION STATUS EXTR ACTION................................37
10.5 RECEIVE PATH OVERHEAD PROCESSOR (RPOP)........................................38
10.5.1 POINTER INTERPRETER..............................................................38
10.5.2 SPE TIMING....................................................................................42
10.5.3 ERROR MONITOR..........................................................................42
10.6 RECEIVE ATM CELL PROCESSO R (RXCP) .................................................... 43
10.6.1 CELL DELINEATION.......................................................................43
10.6.2 DESCRAMBLER.............................................................................44
10.6.3 CELL FILTER AND HCS VERIFICATION .......................................44
10.6.4 PERFORMANCE MONITOR ..........................................................46
10.7 TRANSMIT LINE INTERFACE (CSPI) ...............................................................46
10.7.1 CLOCK SYNTHESIS ...................................................................... 46
10.7.2 PARALLEL TO SERIAL CONVERTER ...........................................47
10.8 TRANSMIT SECTION OVERHEAD PROCESSOR (TSOP)..............................47
10.8.1 LINE AIS INSERT ...........................................................................47
10.8.2 BIP-8 INSERT.................................................................................47
10.8.3 FRAMING AND IDENTITY INSERT ...............................................48
10.8.4 SCRAMBLER..................................................................................48
10.9 TRANSMIT LINE OVERHEAD PROCESSOR (TLOP) ......................................48
10.9.1 APS INSERT...................................................................................48
10.9.2 LINE BIP CALCULATE....................................................................48
10.9.3 LINE RDI INSERT...........................................................................48
10.9.4 LINE FEBE INSERT........................................................................49
10.10 TRANSMIT PATH OVERHEAD PROCESSOR (TPOP) ..................................... 49
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10.10.1 POINTER GENERATOR.................................................................49
10.10.2 BIP-8 CALCULATE..........................................................................50
10.10.3 FEBE CALCULATE.........................................................................50
10.11 TRANSMIT ATM CELL PROCESSOR (TXCP) ..................................................50
10.11.1 IDLE/UNASSIGNED CELL GENERATOR......................................50
10.11.2 SCRAMBLER..................................................................................50
10.11.3 HCS GENERATOR..........................................................................51
10.12 UTOPIA LEVEL 2 SYSTEM INTERFACE ..........................................................51
10.12.1 RECEIVE ATM INTERFACE...........................................................51
10.12.2 TRANSMIT ATM INTERFACE.........................................................51
10.13 JTAG TEST ACCESS PORT...............................................................................52
10.14 MICROPROCESSOR INTERFACE....................................................................52
11 NORMAL MODE REGISTER DESCRIPTION ................................................................59
12 TEST FEATURES DESCRIPTION ................................................................................193
12.1 MASTER TEST REGISTER .............................................................................193
12.2 TEST MODE 0 DETAILS..................................................................................195
12.3 JTAG TEST PORT ............................................................................................196
12.3.1 BOUNDARY SCAN CELLS...........................................................198
13 OPERATION ..................................................................................................................201
13.1 SONET/SDH FRAME MAPPINGS AND OVERHEAD BYTE USAGE.............201
13.1.1 ATM MAPPING..............................................................................201
13.1.2 TRANSPORT AND PATH OVERHEAD BYTES............................202
13.2 ATM CELL DATA STRUCTURE........................................................................204
13.3 BIT ERROR RATE MONITOR ..........................................................................205
13.4 CLOCKING OPTIONS......................................................................................206
13.5 LOOPBACK OPERATION ................................................................................208
13.6 JTAG SUPPORT...............................................................................................212
13.6.1 TAP CONTROLLER ......................................................................213
13.6.1.1 STATES ............................................................................215
13.6.1.2 INSTRUCTIONS ..............................................................216
13.7 BOARD DESIGN RECOMMENDATIONS ........................................................217
13.8 POWER SUPPLY SEQUENCING ....................................................................218
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13.9 ANALOG POWER SUPPLY FILTERING ..........................................................219
13.10 INTERFACING TO ECL OR PECL DEVICES ..................................................220
13.11 INITIALIZING THE S/UNI-QUAD......................................................................222
13.12 USING THE S/UNI-QUAD WITH A 5 VOLT ODL..............................................222
14 FUNCTIONAL TIMING ..................................................................................................223
14.1 ATM UTOPIA LEVEL 2 SYSTEM INTERFACE................................................223
15 ABSOLUTE MAXIMUM RATINGS.................................................................................226
16 D.C. CHARACTERISTICS.............................................................................................227
17 MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS..............................229
18 A.C. TIMING CHARACTERISTICS................................................................................233
18.1 SYSTEM RESET TIMING.................................................................................233
18.2 REFERENCE TIMING ......................................................................................233
18.3 ATM SYSTEM INTERFACE TIMING................................................................234
18.4 TRANSMIT AND RECEIVE FRAME PULSES.................................................238
18.5 JTAG TEST PORT TIMING...............................................................................239
19 ORDERING AND THERMAL INFORMATION...............................................................242
20 MECHANICAL INFORMATION .....................................................................................244
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PMC-971239 ISSUE 6 SATURN USER NETWORK INTERFACE (155-QUAD)
PM5349 S/UNI-QUAD
1 FEATURES
1.1 General
Single chip QUAD ATM User-Network Interface operating at 155.52 Mbit/s.
•
Implements the ATM Forum User Network Interface Specification and the
•
ATM physical layer for Broadband ISDN according to CCITT
Recommendation I.432.
Processes duplex 155.52 Mbit/s STS-3c (STM-1) data streams with on-chip
•
clock and data recovery and clock synthesis.
Exceeds Bellcore GR-253-CORE jitter tolerance and intrinsic jitter criteria.
•
Fully implements the ATM Forum’s Utopia Level 2 Specification with Multi-
•
PHY addressing and parity support.
Provides a standard 5 signal IEEE 1149.1 JTAG test port for boundary scan
•
board test purposes.
Provides a generic 8-bit microprocessor bus interface for configuration,
•
control, and status monitoring.
Low power 3.3V CMOS with PECL and TTL compatible inputs and
•
CMOS/TTL outputs, with 5V tolerance inputs (system side interface is 3.3V
only).
Industrial temperature range (-40°C to +85°C).
•
304 pin Super BGA package.
•
1.2 The SONET Receiver
Provides a serial interface at 155.52 Mbit/s.
•
Recovers the clock and data.
•
Frames to and de-scrambles the recovered stream.
•
Detects signal degrade (SD) and signal fail (SF) threshold crossing alarms
•
based on received B2 errors.
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Captures and debounces the synchronization status (S1) byte in a readable
•
PM5349 S/UNI-QUAD
register.
Filters and captures the automatic protection switch channel (K1, K2) bytes in
•
readable registers and detects APS byte failur e.
Counts received section BIP-8 (B1) errors, received line BIP-24 (B2) errors,
•
line far end block errors (FEBE), received path BIP-8 (B3) errors and path far
end block errors (FEBE).
Detects loss of signal (LOS), out of frame (OOF), loss of frame (LOF), line
•
alarm indication signal (LAIS), line remote defect indication (LRDI), loss of
pointer (LOP), path alarm indication signal (PAIS), path remote defect
indication (PRDI) and path extended remote defect indicator (PERDI).
Interprets the received payload pointer (H1, H2) and extracts the STS-3c
•
(STM-1) synchronous payload envelope and path overhead.
Provides individual divide by 8 recovered clocks (19.44 MHz) for each
•
channel.
Provides individual 8KHz receive frame pulses for each channel.
•
1.3 The Receive ATM Processor
Extracts ATM cells from the received STS-3c (STM-1) synchronous payload
•
envelope using ATM cell delineation.
Provides ATM cell payload de-scrambling.
•
Performs header check sequence (HCS) error detection and correction, and
•
idle/unassigned cell filtering.
Detects Out of Cell Delineation (OCD) and Loss of Cell Delineation (LCD).
•
Counts number of received cells, idle cells, errored cells and dropped cells.
•
Provides a synchronous 8-bit wide, four-cell FIFO buffer.
•
1.4 The SONET Transmitter
Synthesizes the 155.52 MHz transmit clock from a 19.44 MHz reference.
•
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Provides a differential TTL serial interface (can be adapted to PECL levels) at
•
PM5349 S/UNI-QUAD
155.52 Mbit/s.
Provides a single transmit frame pulse input across the four channels to align
•
the transport frames to a system reference.
Provides a single transmit byte clock (divide by eight of the synthesized line
•
rate clock) to provide a timing reference for the transmit outputs.
Optionally inserts register programmable APS (K1, K2) and synchronization
•
status (S1) bytes.
Optionally inserts path alarm indication signal (PAIS), path remote defect
•
indication (PRDI), line alarm indication signal (LAIS) and line remote defect
indication (LRDI).
Inserts path BIP-8 codes (B3), path far end block error (G1) indications, line
•
BIP-24 codes (B2), line far end block error (M1) indications, and section BIP-8
codes (B1) to allow performance monitoring at the far end.
Scrambles the transmitted STS-3c (STM-1) stream and inserts the framing
•
bytes (A1, A2).
Inserts ATM cells into the transmitted STS-3c (STM-1) synchronous payload
•
envelope.
1.5 The Transmit ATM Processor
Provides idle/unassigned cell insertion.
•
Provides HCS generation/insertion, and ATM cell payload scrambling.
•
Counts number of transmitted and idle cells.
•
Provides a synchronous 8-bit wide, four cell FIFO buffer.
•
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2 APPLICATIONS
LAN switches and hubs.
•
Layer 3 switches.
•
Multiservice switches (FR, ATM, IP, etc..).
•
Gibabit and terabit routers.
•
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3 REFERENCES
Bell Communications Research - GR-253-CORE “SONET Transport Systems:
•
Common Generic Criteria”, Issue 2, December 1995.
Bell Communications Research - GR-436-CORE “Digital Network
•
Synchronization Plan”, Issue 1 Revision 1, June 1996..
ITU-T Recommendation G.703 - "Physical/Electrical Characteristics of
•
Hierarchical Digital Interfaces", 1991.
ITU-T Recommendation G.704 - "General Aspects of Digital Transmission
•
Systems; Terminal Equipment - Synchronous Frame Structures Used At 1544,
6312, 2048, 8488 and 44 736 kbit/s Hierarchical Levels", July, 1995.
ITU, Recommendation G.707 - "Network Node Interface For The Synchronous
•
Digital Hierarchy", 1996.
ITU Recommendation G781, “Structure of Recommendations on Equipment
•
for the Synchronous Design Hierarchy (SDH)”, January 1994.
ITU, Recommendation G.783 - "Characteristics of Synchronous Digital
•
Hierarchy (SDH) Equipment Functional Blocks", 1996.
ITU Recommendation I.432, “ISDN User Network Interfaces”, March 93.
•
ATM Forum - ATM User-Network Interface Specification, V3.1, October, 1995.
•
ATM Forum - “UTOPIA, An ATM P HY Interface Specification, Level 2, Version
•
1”, June, 1995.
PMC-950820 “SONET/SDH Bit Error Threshold Monitoring Application Note”,
•
Issue 2, September 1998.
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4 DEFINITIONS
The following table defines the abbreviations for the S/UNI-QUAD.
CRSI CRU and SIPO
CRU Clock Recovery Unit
CSPI CSU and PISO
CSU Clo ck Synthesis Unit
RASE Receive APS, Synchronization Extractor and
Bit Error Monitor
RLOP Receive Line Overhead Processor
RPOP Receive Path Overhead Processor
RSOP Receive Section Overhead Processor
RXCP Receive ATM Cell Processor
TLOP Transmit Line Overhead Processor
TPOP Transmit Path Overhead Processor
TSOP Transmit Section Overhead Processor
TXCP Transmit ATM Cell Processor
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y
y
[
]
]
[
]
[
]
p
S/UNI-QUAD
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5 APPLICATION EXAMPLES
The PM5349 S/UNI-QUAD is intended for use in equipment implementing
Asynchronous Transfer Mode (ATM) User-Network Interfaces (UNI). The S/UNIQUAD may find application at either end of switch-to-switch links or switch-toterminal links. The S/UNI-QUAD performs the ma pping of ATM cells into the
SONET/SDH STS-3c (STM-1) synchronous payload envelope (SPE) and
processes applicable SONET/SDH section, line and path overhead.
In a typical STS-3c (STM-1) ATM application, the S/UNI-QUAD performs clock
and data recovery for the receive direction and clock synthesis for the transmit
direction of the line interface. On the system side, the S/UNI-QUAD interfaces
directly with ATM layer processors and switching or adaptation functions using a
Utopia Level 2 compliant synchronous FIFO style interface. The initial
configuration and ongoing control and monitoring of the S/UNI-QUAD are
normally provided via a generic microprocessor interface. This application is
shown in Figure 1.
Figure 1: Typical STS-3c (STM-1) ATM Switch Port Application
ATM Layer Device
TxClk
TxEnb
TxAddr<4:0>
TxClav
TxSOC
TxPrt
TxData<15:0>
RxClk
RxEnb
RxAddr<4:0>
RxCla v
RxSOC
RxPrt
RxData<15:0>
Uto
Interface
ia Level 2
PM5349
S/UNI-155-QUAD
TFCLK
TENB
4:0
TADR
TCA
TSOC
TPRTY
TDAT[15:0
RFCLK
RENB
4:0
RADR
RCA
RSOC
RPRTY
RDAT
15:0
RXD1+/SD1
TXD1+/-
RXD2+/SD2
TXD2+/-
RXD3+/SD3
TXD3+/-
RXD4+/SD4
TXD4+/-
Optical
Transceiver
Optical
Transceiver
Optical
Transceiver
Optical
Transceiver
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6 BLOCK DIAGRAM
TRSTB
TCK
TMS
TDI
TDO
:0]
TSOC
TDAT[15
TPRTY
TCA
DTCA[4:1]
st
JTAG T e
Access Port
Tx
Tx
Tx
OEN
PHY_
TFCLKTENB
TADR[4:0]
Utopia
System Interface
ATM Cell
Processor
Path O/H
Processor
Line O/H
Processor
RFCLK RADR[4:0]
RENB
RCA
]
RPRTY
RSOC
RDAT[15:0
DRCA[4:1]
INTB
or
ess
F
I/
proc
cro
Mi
Rx
ATM Cell
processor
Rx
Path O/H
Processor
Rx
APS,
Sync,
Rx
Line O/H
Processor
BERM
RSTB
RDB
WRB
CSB
ALE
A[10:0]
D[7:0]
TCLK
TFPO
TFPI
Tx
Processor
Section O/H
I/F
Tx Line
ATB0-3
TXD1-4 -
TXD1-4 +
TXC1-4 -
TXC1-4 +
REFCLK
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Rx
Processor
Section O/H
I/F
Rx Line
-
+
SD1-4
RXD1-4
RXD1-4
RCLK1-4
RFPO1-4
RALRM1-4
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7 DESCRIPTION
The PM5349 S/UNI-QUAD SATURN User Network Interface is a monolithic
integrated circuit that implements four channel SONET/SDH processing and ATM
mapping functions at the STS-3c (STM-1) 155.52 Mbit/s rate.
The S/UNI-QUAD receives SONET/SDH streams using a bit serial interface,
recovers the clock and data and processes section, line, and path overhead. It
performs framing (A1, A2), de-scrambling, detects alarm conditions, and monitors
section, line, and path bit interleaved parity (B1, B2, B3), accumulating error
counts at each level for performance monitoring purposes. Line and path far end
block error indications (M1, G1) are also accumulated. The S/UNI-QUAD
interprets the received payload pointers (H1, H2) and extracts the synchronous
payload envelope which carries the received ATM cell payload.
The S/UNI-QUAD frames to the ATM payload using cell delineation. HCS error
correction is provided. Idle/unassigned cells may be dropped according to a
programmable filter. Cells are also dropped upon detection of an uncorrectable
header check sequence error. The ATM cell payloads are descrambled. The ATM
cells that are passed are written to a four cell FIFO buffer. The received cells are
read from the FIFO using a 16-bit wide Utopia level 2 compliant datapath
interface. Counts of received ATM cell headers that are errored and uncorrectable
and also those that are errored and correctable are accumulated independently
for performance monitoring purposes.
The S/UNI-QUAD transmits SONET/SDH streams using a bit serial interface and
formats section, line, and path overhead appropriately. It synthesizes the transmit
clock from a lower frequency reference and performs framing pattern insertion
(A1, A2), scrambling, alarm signal insertion, and creates section, line, and path
bit interleaved parity (B1, B2, B3) as required to allow performance monitoring at
the far end. Line and path far end block error indications (M1, G1) are also
inserted. The S/UNI-QUAD generates the payload pointer (H1, H2) and inserts
the synchronous payload envelope which carries the ATM cell payload. The
S/UNI-QUAD also supports the insertion of a large variety of errors into the
transmit stream, such as framing pattern errors, bit interleaved parity errors, and
illegal pointers, which are useful for system diagnostics and tester applications.
ATM cells are written to an internal four cell FIFO using a 16-bit wide Utopia Level
2 datapath interface. Idle/unassigned cells are automatically inserted when the
internal FIFO contains less than one cell. The S/UNI-QUAD provides generation
of the header check sequence and scrambles the payload of the ATM cells. Each
of these transmit ATM cell processing functions can be enabled or bypassed.
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No line rate clocks are required directly by the S/UNI-QUAD as it synthesizes the
transmit clock and recovers the receive clock using a 19.44 MHz reference clock.
The S/UNI-QUAD outputs a differential TTL (externally coverted to PECL) line
data (TXD+/-).
The S/UNI-QUAD is configured, controlled and monitored via a generic 8-bit
microprocessor bus interface. The S/UNI-QUAD also provides a standard 5
signal IEEE 1149.1 JTAG test port for boundary scan board test purposes.
The S/UNI-QUAD is implemented in low power, +3.3 Volt, CMOS technology. It
has TTL and pseudo-ECL (PECL) compatible inputs and TTL/CMOS compatible
outputs and is packaged in a 304 pin SBGA package.
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8 PIN DIAGRAM
The S/UNI-QUAD is available in a 304 pin SBGA package having a body size of
31 mm by 31 mm and a ball pitch of 1.27 mm.
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
VDD VSS TDAT[12] TDAT[15] PHY_OEN VSS D[2] VSS A[0] A[3] A[7] VSS A[10] WRB TDO VSS N/C VSS N/C RAVD1_B RAVS1_B VSS VDD
A
VSS VDD VSS TDAT[13] N/C N/C D[1] D[4] D[6] A[2] A[6] A[9] CSB RSTB TMS TCK N/C N/C QAVS_5 N/C VSS VDD VSS
B
TDAT[7] VSS VDD TDAT[10] TDAT[14] N/C BIAS D[3] D[5] A[1] A[5] A[8] ALE INTB TRSTB N/C N/C QAVD_5 N/C RAVD1_C VDD VSS TXD1P
C
TDAT[4] TDAT[6] TDAT[9] VDD TDAT[11] VDD N/C D[0] VDD D[7] A[4] VDD RDB TDI VDD N/C N/C VDD RAVS1_C VDD N/C TXD1N RX1-
D
TDAT[0] TDAT[3] TDAT[5] TDAT[8] N/C SD1 RX1+ TXD2P
E
VSS N/C TDAT[2] VDD VDD RAVS1_A TXD2N VSS
F
TADR[0] TADR[2] TADR[4] TDAT[1] RAVD1_A N/C RX2- RX2+
G
VSS TPRTY TADR[1] TADR[3] N/C RAVS2_A RAVD2_A VSS
H
TCA
J
DTCA[3] DTCA[4]
K
L
N/C N/C
M
VSS N/C
DRCA[3] DRCA[2] DRCA[1] RCA
N
RSOC
P
R
RADR[4] RADR[2] RADR[1] VDD VDD N/C N/C ATB3
VSS RADR[0] RPRTY RDAT[13] RAVS3_A N/C TXD3P VSS
T
RDAT[15] RDAT[14] RDAT[12] RDAT[9] N/C SD3 RAVD3_A TXD3N
U
VSS RDAT[11] RDAT[8] VDD VDD N/C RX3- VSS
V
RDAT[10] RDAT[7] RDAT[5] RDAT[2] RAVS4_A SD4 TXD4P RX3+
W
RDAT[6] RDAT[4] RDAT[1] VDD N/C VDD N/C N/C VDD RALRM3 RCLK2 VDD N/C N/C VDD N/C TFPI VDD RAVS4_C VDD RAVD4_A RX4- TXD4N
Y
RDAT[3] VSS VDD RDAT[0] N/C N/C N/C N/C N/C RALRM1 RCLK1 RFPO1 N/C N/C N/C N/C N/C QAVD_1 N/C RAVD4_C VDD VSS RX4+
AA
VSS VDD VSS N/C N/C N/C N/C N/C RALRM4 RCLK4 RFPO4 RFPO2 TFPO N/C N/C N/C N/C N/C QAVS_1 N/C VSS VDD VSS
AB
VDD VSS N/C N/C N/C VSS N/C VSS RALRM2 RCLK3 RFPO3 VSS TCLK N/C N/C VSS N/C VSS REFCLK RAVD4_B RAVS4_B VSS VDD
AC
TSOC
TENB
RENB RFCLK RADR[3] ATB2 ATB1 ATB0 RAVS3_C
VDD VDD SD2 N/C RAVD2_C
BIAS TFCLK RAVS2_C RAVS2_B N/C N/C
DTCA[1] DTCA[2]
DRCA[4]
VDD VDD TAVS1_B RAVD3_B VSS
RAVD2_B TAVD1_A TAVS1_A TAVD1_B
RAVD3_C RAVS3_B N/C N/C
BOTT OM VIEW
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9 PIN DESCRIPTION
9.1 Line Side Interface Signals
Pin Name Type Pin
Function
No.
REFCLK Input AC5 The reference clock input (REFCLK) must provide a
jitter-free 19.44 MHz reference clock. It is used as
the reference clock by both clock recovery and clock
synthesis circuits.
This pin is shared by all channels.
RXD1+
RXD1RXD2+
RXD2RXD3+
RXD3RXD4+
RXD4-
SD1
SD2
SD3
SD4
Differential
PECL
inputs
Single-
Ended
PECL
Input
E2
D1
G1
G2
W1
V2
AA1
Y2
E3
J3
U3
W3
The receive differential data inputs (RXD+, RXD-)
contain the NRZ bit serial receive stream. The
receive clock is recovered from the RXD+/- bit
stream. Please refer to the Operation section for a
discussion of PECL interfacing issues.
This pin is available independently for each channel.
The Signal Detect pin (SD) indicates the presence
of valid receive signal power from the Optical
Physical Medium Dependent Device. A PECL high
indicates the presence of valid data and a PECL low
indicates a loss of signal. It is mandatory that SD be
terminated into the equivalent network that RXD+/is terminated into.
This pin is available independently for each channel.
RCLK1
RCLK2
RCLK3
RCLK4
Output AA13
Y13
AC14
AB14
The receive byte clock (RCLK) provides a timing
reference for the S/UNI-QUAD receive outputs.
RCLK is a divide by eight of the recovered line rate
clock (19.44 MHz).
This pin is available independently for each channel.
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Pin Name Type Pin
No.
RFPO1
RFPO2
RFPO3
RFPO4
RALRM1
RALRM2
RALRM3
RALRM4
Output AA12
AB12
AC13
AB13
Output AA14
AC15
Y14
AB15
Function
The Receive Frame Pulse Output (RFPO), when the
framing alignment is found (the OOF register bit is
logic zero), is an 8 kHz signal derived from the
receive line clock. RFPO pulses high for one RCLK
cycle every 2430 RCLK cycles (STS-3c (STM-1)).
RFPO is updated on the rising edge of RCLK.
This pin is available independently for each channel.
The Receive Alarm (RALRM) output indicates the
state of the receive framing. RALRM is low if no
receive alarms are active. RALRM is high if line AIS
(LAIS), path AIS (PAIS), line RDI (LRDI), path RDI
(PRDI), enhanced path RDI (PERDI), loss of signal
(LOS), loss of frame (LOF), out of frame (OOF),
loss of pointer (LOP), loss of cell delineation (LCD),
signal fail BER (SFBER), signal degrade BER
(SDBER), or path signal label mismatch (PSLM) is
detected in the associated channel. Each alarm can
be individually enabled using bits in the S/UNIQUAD Channel Alarm Control registers #1 and #2.
TXD1+
TXD1TXD2+
TXD2TXD3+
TXD3TXD4+
TXD4-
Differential
TTL output
(externally
converted
to PECL)
C1
D2
E1
F2
T2
U1
W2
Y1
RALRM is updated on the rising edge of RCLK.
This pin is available independently for each channel.
The transmit differential data outputs (TXD+, TXD-)
contain the 155.52 Mbit/s transmit stream.
This pin is available independently for each channel.
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Pin Name Type Pin
Function
No.
TFPI Input Y7 The active high framing position (TFPI) signal is an
8 kHz timing marker for the transmitter. TFPI is used
to align the SONET/SDH transport frame generated
by the S/UNI-QUAD device to a system reference.
TFPI is internally used to align a master frame pulse
counter. When TFPI is not used, this counter is freerunning.
TFPI should be brought high for a single TCLK
period every 2430 (STS-3c (STM-1)) TCLK cycles,
or a multiple thereof. TFPI shall be tied low if such
synchronization is not required. TFPI cannot be
used as an input to a loop-timed channel. For TFPI
to operate correctly it is required that the
TCLK/TFPO output be configured to output the
CSU byte clock.
The TFPI_EN register bits allow to individually
configure each channel to use the global framing
pulse counter and TFPI for framing alignment.
TFPI is sampled on the rising edge of TCLK, but
only when the TTSEL register bit is set to logic zero.
When TTSEL is set to logic one, TFPI is unused.
This pin is shared by all channels.
TCLK Output AC11 The transmit byte clock (TCLK) output provides a
timing reference for the S/UNI-QUAD self-timed
channels. TCLK always provide a divide by eight of
the synthesized line rate clock and thus has a
nominal frequency of 19.44 MHz. TFPI is sampled
on the rising edge of TCLK. TCLK does not apply to
internally loop-timed channels, in which case the
channel’s RCLK provides transmit timing
information.
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Pin Name Type Pin
Function
No.
TFPO Output AB11 The Transmit Frame Pulse Output (TFPO) pulses
high for one TCLK cycle every 2430 TCLK cycles
and provides an 8 KHz timing reference. TFPO can
be assigned to any of the four channels using
TFPO_CH[1:0] configuration register bits, with the
restriction that the selected channel must be selftimed (not in loop-timed or line-loopback modes).
TFPO is updated on the rising edge of TCLK.
9.2 UTOPIA Level 2 System Interface
Pin Name Type Pin
Function
No.
TDAT[15]
TDAT[14]
TDAT[13]
TDAT[12]
TDAT[11]
TDAT[10]
TDAT[9]
TDAT[8]
TDAT[7]
TDAT[6]
TDAT[5]
TDAT[4]
TDAT[3]
TDAT[2]
TDAT[1]
TDAT[0]
Input A20
C19
B20
A21
D19
C20
D21
E20
C23
D22
E21
D23
E22
F21
G20
E23
UTOPIA Transmit Cell Data Bus (TDAT[15:0]).
This data bus carries the ATM cell octets that are
written to the selected transmit FIFO. TDAT[15:0] is
considered valid only when TENB is simultaneously
asserted and the S/UNI-QUAD is selected via
TADR[4:0].
TDAT[15:0] is sampled on the rising edge of TFCLK.
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Pin Name Type Pin
Function
No.
TPRTY Input H22 UTOPIA Transmit bus parity (TPRTY) signal.
The transmit parity (TPRTY) signal indicates the
parity of the TDAT[15:0] bus. A parity error is
indicated by a status bit and a maskable interrupt.
Cells with parity errors are inserted in the transmit
stream, so the TPRTY input may be unused. Odd or
even parity selection is made independently for
each channel using the RXPTYP register bit.
TPRTY is considered valid only when TENB is
simultaneously asserted and the S/UNI-QUAD is
selected via TADR[4:0].
TPRTY is sampled on the rising edge of TFCLK.
TSOC Input J21 UTOPIA Transmit Start of Cell (TSOC) signal.
The transmit start of cell (TSOC) signal marks the
start of cell on the TDAT bus. When TSOC is high,
the first word of the cell structure is present on the
TDAT bus. It is not necessary for TSOC to be
present for each cell. An interrupt may be
generated if TSOC is high during any word other
than the first word of the cell structure.
TSOC is considered valid only when TENB is
simultaneously asserted and the S/UNI-QUAD is
selected via TADR[4:0].
TSOC is sampled on the rising edge of TFCLK.
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Pin Name Type Pin
Function
No.
TENB Input J22 UTOPIA Transmit Multi-PHY Write Enable (TENB)
signal.
The TENB signal is an active low input which is
used along with the TADR[4:0] inputs to initiate
writes to the transmit FIFO’s.
TENB works as follows. When sampled high, no
write is performed, but the TADR[4:0] address is
latched to identify the transmit FIFO to be
accessed. When TENB is sampled low, the word on
the TDAT bus is written into the transmit FIFO that is
selected by the TADR[4:0] address bus. A complete
53 octet cell must be written to the transmit FIFO
before it is inserted into the transmit stream. Idle
cells are inserted when a complete cell is not
available. While TENB is deasserted, TADR[4:0] can
be used for polling TCA.
TENB is sampled on the rising edge of TFCLK.
TADR[4]
TADR[3]
TADR[2]
TADR[1]
TADR[0]
Input G21
H20
G22
H21
G23
UTOPIA Transmit Write Address (TADR[4:0])
signals.
The TADR[4:0] bus is used to select the FIFO (and
hence port) that is written to using the TENB signal
and the FIFO's whose cell available signal is visible
on the TC A poll ing output.
Note that address 0x1F is the null-PHY address and
cannot be assigned to any port on the S/UNI-QUAD.
TADR[4:0] is sampled on the rising edge of TFCLK.
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Pin Name Type Pin
Function
No.
TCA Output J23 UTOPIA Transmit multi-PHY Cell Available (TCA)
The TCA signal indicates when a cell is available in
the transmit FIFO for the port polled by TADR[4:0]
when TENB is asserted. When high, TCA indicates
that the corresponding transmit FIFO is not full and
a complete cell may be written. Wh en TCA goes
low, it can be configured to indicate either that the
corresponding transmit FIFO is near full or that the
corresponding transmit FIFO is full. TCA will
transition low on the rising edge of TFCLK after the
Payload word 19 (TCALEVEL0=0) or 23
(TCALEVEL0=1) is sampled if the PHY being polled
is the same as the PHY in use. To reduce FIFO
latency, the FIFO depth at which TCA indicates "full"
can be set to one, two, three or four cells. Note that
regardless of what fill level TCA is set to indicate
"full" at, the transmit cell processor can store 4
complete cells.
TCA is tri-stated when either the null-PHY address
(0x1F) or an address not matching the address
space set by PHY_ADR[2:0] is latched from the
TADR[4:0] inputs when TENB is high.
TCA is updated on the rising edge of TFCLK.
TFCLK Input K20 UTOPIA Transmit FIFO Write Clock (TFCLK).
This signal is used to write ATM cells to the four cell
transmit FIFOs.
TFCLK cycles at a 50 MHz or lower instantaneous
rate.
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Pin Name Type Pin
No.
DTCA[4]
DTCA[3]
DTCA[2]
DTCA[1]
Output K22
K23
L20
L21
Function
UTOPIA Direct Transmit Cell Available (DTCA[4:1]).
These output signals provide di r ect status indi cation
of when a cell is available in the transmit FIFO for
the corresponding port. When high, DTCA indicates
that the corresponding transmit FIFO is not full and
a complete cell may be written. Wh en DTCA goes
low, it can be configured to indicate either that the
corresponding transmit FIFO is near full or that the
corresponding transmit FIFO is full. DTCA will
transition low on the rising edge of TFCLK after the
Payload word 19 (TCALEVEL0=0) or 23
(TCALEVEL0=1) is sampled if the PHY being polled
is the same as the PHY in use. To reduce FIFO
latency, the FIFO depth at which DTCA indicates
"full" can be set to one, two, three or four cells. Note
that regardless of what fill level DTCA is set to
indicate "full" at, the transmit cell processor can
store 4 complete cells
RDAT[15]
RDAT[14]
RDAT[13]
RDAT[12]
RDAT[11]
RDAT[10]
RDAT[9]
RDAT[8]
RDAT[7]
RDAT[6]
RDAT[5]
RDAT[4]
RDAT[3]
RDAT[2]
RDAT[1]
RDAT[0]
Output U23
U22
T20
U21
V22
W23
U20
V21
W22
Y23
W21
Y22
AA23
W20
Y21
AA20
DTCA[4:1] are updated on the rising edge of
TFCLK.
UTOPIA Receive Cell Data Bus (RDAT[15:0]).
This data bus carries the ATM cells that are read
from the receive FIFO selected by RADR[4:0].
RDAT[15:0] is tri-stated when RENB is high.
RDAT[15:0] is tristated when RENB is high.
RDAT[15:0] is also tristated when either the nullPHY address (0x1F) or an address not matching
the address space is latched from the RADR[4:0]
inputs when RENB is high.
RDAT[15:0] is updated on the rising edge of
RFCLK.
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Pin Name Type Pin
Function
No.
RPRTY Output T21 UTOPIA Receive Parity (RPRTY).
The receive parity (RPRTY) signal indicates the
parity of the RDAT bus. RPRTY reflects the parity of
RDAT[15:0]. Odd or even parity selection is made
independently for every channel by using the
RXPTYP register bit (in ATM cell processors, the
four RXCP shall be programmed with the same
parity setting).RPRTY is tristated when RENB is
high. RPRTY is also tristated when either the nullPHY address (0x1F) or an address not matching
the address space is latched from the RADR[4:0]
inputs when RENB is high.
RPRTY is updated on the rising edge of RFCLK.
RSOC Output P23 UTOPIA Receive Start of Cell (RSOC).
RSOC marks the start of cell on the RDAT bus.
RSOC is tristated when RENB is deasserted.
RSOC is also tristated when either the null-PHY
address (0x1F) or an address not matching the
address space is latched from the RADR[4:0] inputs
when RENB is high.
RSOC is sampled on the rising edge of RFCLK.
RENB Input P22 UTOPIA Receive multi-PHY Read Enable (RENB).
The RENB signal is used to initiate reads from the
receive FIFO’s. RENB works as follows. When
RENB is sampled high, no read is performed and
RDAT[15:0], RPRTY and RSOC are tristated, and
the address on RADR[4:0] is latched to select the
device or port for the next FIFO access. When
RENB is sampled low, the word on the RDAT bus is
read from the selected receive FIFO.
RENB must operate in conjunction with RFCLK to
access the FIFO’s at a high enough rate to prevent
FIFO overflows. The system may de-assert RENB
at anytime it is unable to accept another byte.
RENB is sampled on the rising edge of RFCLK.
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Pin Name Type Pin
Function
No.
RADR[4]
RADR[3]
RADR[2]
RADR[1]
RADR[0]
Input
R23
P20
R22
R21
T22
UTOPIA Receive Read Address (RADR[4:0]).
The RADR[4:] signal is used to select the FIFO (and
hence port) that is read from using the RENB signal
and the FIFO whose cell available signal is visible
on the RCA output.
Note that address 0x1F is the null-PHY address and
will not be identified to any port on the
S/UNI-QUAD.
RADR[4:0] is sampled on the rising edge of RFCLK.
RCA Output N20 UTOPIA Receive multi-PHY Cell Available (RCA).
RCA indicates when a cell is available in the receive
FIFO for the port selected by RADR[4:0]. RCA can
be configured to be de-asser ted when either zero or
four bytes remain in the selected/addressed FIFO.
RCA will thus transition low on the rising edge of
RFCLK after Payload word 24 (RCALEVEL0=1) or
19 (RCALEVEL0=0) is output if the PHY being
polled is the same as the PHY in use.
RCA is tristated when either the null-PHY address
(0x1F) or an address not matching the address
space is latched from the RADR[4:0] inputs when
RENB is high.
RCA is updated on the rising edge of RFCLK.
RFCLK Input P21 UTOPIA Receive FIFO Read Clock (RFCLK).
RFCLK is used to read ATM cells from the receive
FIFO’s. RFCLK must cycle at a 50 MHz or lower
instantaneous rate, but at a high enough rate to
avoid FIFO overflows.
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Pin Name Type Pin
Function
No.
DRCA[4]
DRCA[3]
DRCA[2]
DRCA[1]
Output M21
N23
N22
N21
UTOPIA Direct Receive Cell Available (DRCA[4:1]).
These output signals provides di r ect status
indication of when a cell is available in the receive
FIFO for the corresponding port. DRCA can be
configured to be de-asserted when either zero or
four bytes remain in the selected/addressed FIFO.
DRCA will thus transition low on the rising edge of
RFCLK after Payload word 24 (RCALEVEL0=1) or
19 (RCALEVEL0=0) is output if the PHY being
polled is the same as the PHY in use.
DRCA[x] is updated on the rising edge of RFCLK.
PHY_OEN Input A19 The PHY Output Enable (PHY_OEN) signal controls
the operation of the system interface. When set to
logic zero, all System Interface outputs are held
tristate. When PHY_OEN is set to logic one, the
interface is enabled. PHY_OEN can be overwritten
by the PHY_EN Master System Interface
Configuration register bit. PHY_OEN and PHY_EN
are OR’ed together to enable the interface.
When the S/UNI-QUAD is the only PHY layer device
on the bus, PHY_O EN can safely be tied to logic
one. When the S/UNI-QUAD shares the bus with
other devices, then PHY_OEN must be tied to logic
zero, and the PHY_EN register bit used to enable
the bus once its PHY_ADR[2:0] is programmed in
order to avoid conflicts.
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9.3 Microprocessor Interface Signals
Pin Name Type Pin
Function
No.
CSB Input B11 The active-low chip select (CSB) signal is low
during S/UNI-QUAD register accesses.
Note that when not being used, CSB must be tied
high. If CSB is not required (i.e., registers accesses
are controlled using the RDB and WRB signals
only), CSB must be connected to an inverted
version of the RSTB input.
RDB Input D11 The active-low read enable (RDB) signal is low
during S/UNI-QUAD register read accesses. The
S/UNI-QUAD drives the D[7:0] bus with the contents
of the addressed register while RDB and CSB are
low.
WRB Input A10 The active-low write strobe (WRB) signal is low
during a S/UNI-QUAD register write accesses. The
D[7:0] bus contents are clocked into the addressed
register on the rising WRB edge while CSB is low.
D[0]
D[1]
D[2]
D[3]
D[4]
D[5]
D[6]
D[7]
I/O D16
B17
A17
C16
B16
C15
B15
D14
The bi-directional data bus D[7:0] is used during
S/UNI-QUAD register read and write accesses.
A[0]
A[1]
A[2]
A[3]
A[4]
A[5]
A[6]
A[7]
A[8]
A[9]
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Input A15
C14
B14
A14
D13
C13
B13
A13
C12
B12
The address bus A[9:0] selects specific registers
during S/UNI-QUAD register accesses.
Except for S/UNI-QUAD global registers, the A[9:8]
bits allow to select which channel is being
accessed. The A[7:0] bits allow to select which
register is being access within a given channel
address space.
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Pin Name Type Pin
Function
No.
A[10]/TRS Input A11 The test register select (TRS) signal selects
between normal and test mode register accesses.
TRS is high during test mode register accesses,
and is low during normal mode register accesses.
RSTB Input
pull-up
B10 The active-low reset (RSTB) signal provides an
asynchronous S/UNI-QUAD reset. RSTB is a
Schmitt triggered input with an integral pull-up
resistor.
ALE Input
pull-up
C11 The address latch enable (ALE) is active-high and
latches the address bus A[7:0] when low. When
ALE is high, the internal address latches are
transparent. It allows the S/UNI-QUAD to interface
to a multiplexed address/data bus. ALE has an
integral pull-up resistor.
INTB Output
Open-
drain
C10 The active-low interrupt (INTB) signal goes low
when a S/UNI-QUAD interrupt source is active and
that source is unmasked. The S/UNI-QUAD may be
enabled to report many alarms or events via
interrupts.
Examples of interrupt sources are loss of signal
(LOS), loss of frame (LOF), line AIS, line remote
defect indication (LRDI) detect, loss of pointer
(LOP), path AIS, path remote defect indication
detect and others.
INTB is tristated when the interrupt is acknowledged
via an appropriate register access. INTB is an open
drain output.
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
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