PMC PM5345-RC Datasheet
PM5345 S/UNI-155
DATA SHEET
PMC-930305 ISSUE 4 SATURN USER NETWORK INTERFACE
PM5345
S/UNI-155
SATURN USER NETWORK INTERFACE
TELECOM STANDARD PRODUCT
DATA SHEET
ISSUE 4: JUNE 1998
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
PM5345 S/UNI-155
DATA SHEET
PMC-930305 ISSUE 4 SATURN USER NETWORK INTERFACE
PUBLIC REVISION HISTORY
Issue No. Issue Date Details of Change
4 June 1998 Data Sheet Reformatted — No
Change in Technical Content.
Generated R4 data sheet from
PMC-920404, R11.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
PM5345 S/UNI-155
DATA SHEET
PMC-930305 ISSUE 4 SATURN USER NETWORK INTERFACE
CONTENTS
1 FEATURES...............................................................................................1
1.1 THE RECEIVER SECTION: ..........................................................1
1.2 THE TRANSMITTER SECTION:....................................................1
2 APPLICATIONS........................................................................................1
3 REFERENCES.........................................................................................1
4 APPLICATION INFORMATION.................................................................1
5 INTERFACE EXAMPLES .........................................................................1
6 BLOCK DIAGRAM....................................................................................1
7 DESCRIPTION.........................................................................................1
8 PIN DIAGRAM..........................................................................................1
9 PIN DESCRIPTION..................................................................................1
10 FUNCTIONAL DESCRIPTION.................................................................1
10.1 SERIAL TO PARALLEL CONVERTER...........................................1
10.2 RECEIVE SECTION OVERHEAD PROCESSOR..........................1
10.2.1FRAMER.............................................................................1
10.2.2DESCRAMBLE ...................................................................1
10.2.3ERROR MONITOR..............................................................1
10.2.4LOSS OF SIGNAL ..............................................................1
10.2.5LOSS OF FRAME...............................................................1
10.3 RECEIVE LINE OVERHEAD PROCESSOR .................................1
10.3.1FERF DETECT ...................................................................1
10.3.2LINE AIS DETECT..............................................................1
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10.3.3ERROR MONITOR..............................................................1
10.4 TRANSPORT OVERHEAD EXTRACT PORT................................1
10.5 RECEIVE PATH OVERHEAD PROCESSOR.................................1
10.5.1POINTER INTERPRETER..................................................1
10.5.2SPE TIMING........................................................................1
10.5.3ERROR MONITOR..............................................................1
10.5.4PATH FERF DETECT..........................................................1
10.6 PATH OVERHEAD EXTRACT........................................................1
10.7 RECEIVE ATM CELL PROCESSOR .............................................1
10.7.1CELL DELINEATION...........................................................1
10.7.2DESCRAMBLER.................................................................1
10.7.3CELL FILTER AND HCS VERIFICATION............................1
10.7.4PERFORMANCE MONITOR...............................................1
10.7.5RECEIVE FIFO ...................................................................1
10.8 PARALLEL TO SERIAL CONVERTER...........................................1
10.9 TRANSMIT SECTION OVERHEAD PROCESSOR.......................1
10.9.1LINE AIS INSERT ...............................................................1
10.9.2BIP-8 INSERT.....................................................................1
10.9.3FRAMING AND IDENTITY INSERT....................................1
10.9.4SCRAMBLER......................................................................1
10.10 TRANSMIT LINE OVERHEAD PROCESSOR...............................1
10.10.1 BIP-24 CALCULATE.........................................................1
10.10.2 LINE FERF INSERT..........................................................1
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10.10.3 LINE FEBE INSERT .........................................................1
10.11 TRANSPORT OVERHEAD INSERT PORT...................................1
10.12 TRANSMIT PATH OVERHEAD PROCESSOR..............................1
10.12.1 POINTER GENERATOR...................................................1
10.12.2 BIP-8 CALCULATE...........................................................1
10.12.3 FEBE CALCULATE...........................................................1
10.12.4 ATH FERF INSERT...........................................................1
10.12.5 SPE MULTIPLEXER.........................................................1
10.13 PATH OVERHEAD INSERT...........................................................1
10.14 TRANSMIT ATM CELL PROCESSOR...........................................1
10.14.1 IDLE/UNASSIGNED CELL GENERATOR ........................1
10.14.2 SCRAMBLER....................................................................1
10.14.3 HCS GENERATOR ...........................................................1
10.14.4 TRANSMIT FIFO...............................................................1
10.15 LINE SIDE INTERFACE.................................................................1
10.15.1 RECEIVE INTERFACE.....................................................1
10.15.2 TRANSMIT INTERFACE...................................................1
10.16 DROP SIDE INTERFACE..............................................................1
10.16.1 RECEIVE INTERFACE.....................................................1
10.16.2 TRANSMIT INTERFACE...................................................1
10.17 MICROPROCESSOR INTERFACE ...............................................1
10.18 JTAG TEST ACCESS PORT..........................................................1
10.19 REGISTER MEMORY MAP...........................................................1
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11 NORMAL MODE REGISTER DESCRIPTION..........................................1
12 TEST FEATURES DESCRIPTION...........................................................1
12.1 TEST MODE REGISTER MEMORY MAP.....................................1
12.2 TEST MODE 0 DETAILS...............................................................1
12.3 JTA G TEST POR T..........................................................................1
13 OPERATION.............................................................................................1
14 FUNCTIONAL TIMING .............................................................................1
14.1 LINE SIDE RECEIVE INTERFACE................................................1
14.2 OVERHEAD ACCESS ...................................................................1
14.3 LINE SIDE TRANSMIT INTERFACE..............................................1
14.4 DROP SIDE RECEIVE INTERFACE..............................................1
14.5 DROP SIDE TRANSMIT INTERFACE ...........................................1
15 ABSOLUTE MAXIMUM RATINGS............................................................1
16 D.C. CHARACTERISTICS ........................................................................1
17 MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS..........1
18 S/UNI TIMING CHARA CTERISTICS........................................................1
19 ORDERING AND THERMAL INFORMATION ..........................................1
20 MECHANICAL INFORMATION.................................................................1
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PMC-930305 ISSUE 4 SATURN USER NETWORK INTERFACE
LIST OF REGISTERS
REGISTER 0X00: S/UNI MASTER RESET AND IDENTITY...............................1
REGISTER 0X01: S/UNI MASTER CONFIGURATION.......................................1
REGISTER 0X02: S/UNI MASTER INTERRUPT STATUS..................................1
REGISTER 0X04: S/UNI MASTER CLOCK MONITOR ......................................1
REGISTER 0X05: S/UNI MASTER CONTROL...................................................1
REGISTER 0X10: RSOP CONTROL/INTERRUPT ENABLE..............................1
REGISTER 0X11: RSOP STATUS/INTERRUPT STATUS ...................................1
REGISTER 0X12: RSOP SECTION BIP-8 LSB..................................................1
REGISTER 0X13: RSOP SECTION BIP-8 MSB.................................................1
REGISTER 0X14: TSOP CONTROL...................................................................1
REGISTER 0X15: TSOP DIAGNOSTIC..............................................................1
REGISTER 0X18: RLOP CONTROL/STATUS.....................................................1
REGISTER 0X19: RLOP INTERRUPT ENABLE/INTERRUPT STATUS.............1
REGISTER 0X1A: RLOP LINE BIP-24 LSB........................................................1
REGISTER 0X1B: RLOP LINE BIP-24................................................................1
REGISTER 0X1C: RLOP LINE BIP-24 MSB.......................................................1
REGISTER 0X1D: RLOP LINE FEBE LSB .........................................................1
REGISTER 0X1E: RLOP LINE FEBE .................................................................1
REGISTER 0X1F: RLOP LINE FEBE MSB.........................................................1
REGISTER 0X20: TLOP CONTROL...................................................................1
REGISTER 0X21: TLOP DIAGNOSTIC ..............................................................1
REGISTER 0X30: RPOP STATUS/CONTROL....................................................1
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REGISTER 0X31: RPOP INTERRUPT STATUS .................................................1
REGISTER 0X33: RPOP INTERRUPT ENABLE................................................1
REGISTER 0X37: RPOP PATH SIGNAL LABEL.................................................1
REGISTER 0X38: RPOP PATH BIP-8 LSB / LOAD METERS.............................1
REGISTER 0X39: RPOP PATH BIP-8 MSB ........................................................1
REGISTER 0X3A: RPOP PATH FEBE LSB.........................................................1
REGISTER 0X3B: RPOP PATH FEBE MSB........................................................1
REGISTER 0X40: TPOP CONTROL/DIAGNOSTIC............................................1
REGISTER 0X41: TPOP POINTER CONTROL..................................................1
REGISTER 0X42: TPOP SOURCE CONTROL...................................................1
REGISTER 0X45: TPOP ARBITRARY POINTER LSB .......................................1
REGISTER 0X46: TPOP ARBITRARY POINTER MSB ......................................1
REGISTER 0X48: TPOP PATH SIGNAL LABEL .................................................1
REGISTER 0X49: TPOP PATH STATUS..............................................................1
REGISTER 0X50: RACP CONTROL/STATUS ....................................................1
REGISTER 0X51: RACP INTERRUPT ENABLE/STATUS ..................................1
REGISTER 0X52: RACP MATCH HEADER PATTERN .......................................1
REGISTER 0X53: RACP MATCH HEADER MASK.............................................1
REGISTER 0X54: RACP CORRECTABLE HCS ERROR COUNT......................1
REGISTER 0X55: RACP UNCORRECTABLE HCS ERROR COUNT ................1
REGISTER 0X60: TACP CONTROL/STATUS......................................................1
REGISTER 0X61: TACP IDLE/UNASSIGNED CELL HEADER PATTERN..........1
REGISTER 0X62: TACP IDLE/UNASSIGNED CELL PAYLOAD
OCTET PATTERN.....................................................................................1
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REGISTER 0X80: MASTER TEST......................................................................1
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LIST OF FIGURES
FIGURE 1 - EXAMPLE 1. OPTICAL ATM ADAPTER INTERFACE...................1
FIGURE 2 - EXAMPLE 2. UTP-5 ATM ADAPTER INTERFACE........................1
FIGURE 3 - EXAMPLE 3. OC-12 ATM SWITCH PORT CARD INTERFACE....1
FIGURE 4 - RECOMMENDED INTERFACE WITH CY7B951 ...........................1
FIGURE 5 - RECOMMENDED INTERFACE WITH AD802................................1
FIGURE 6 - CELL DELINEATION STATE DIAGRAM.........................................1
FIGURE 7 - HCS VERIFICATION STATE DIAGRAM .........................................1
FIGURE 8 - DEFAULT TRANSPORT OVERHEAD VALUES..............................1
FIGURE 9 - DEFAULT PATH OVERHEAD VALUES...........................................1
FIGURE 10- OVERHEAD BYTE USAGE............................................................1
FIGURE 11- 16-BIT WORD WIDTH DATA STRUCTURE....................................1
FIGURE 12- 8-BIT WORD WIDTH DATA STRUCTURE......................................1
FIGURE 13- LOOPBACK OPERATION..............................................................1
FIGURE 14- BOUNDARY SCAN ARCHITECTURE............................................1
FIGURE 15- TAP CONTROLLER FINITE STATE MACHINE ..............................1
FIGURE 16- IN FRAME DECLARATION (BIT SERIAL
INTERFACE, RSER=1).......................................................................................1
FIGURE 17- IN FRAME DECLARATION (BYTE SERIAL
INTERFACE, RSER=0).......................................................................................1
FIGURE 18- OUT OF FRAME DECLARATION ..................................................1
FIGURE 19- LOSS OF SIGNAL DECLARATION/REMOVAL..............................1
FIGURE 20- LOSS OF FRAME DECLARATION/REMOVAL ..............................1
FIGURE 21- LINE AIS AND LINE FERF DECLARATION/REMOVAL.................1
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FIGURE 22- LOSS OF POINTER DECLARATION/REMOVAL...........................1
FIGURE 23- PATH AIS DECLARATION/REMOVAL............................................1
FIGURE 24- PATH YELLOW ALARM DECLARATION/REMOVAL......................1
FIGURE 25- TRANSPORT OVERHEAD EXTRACTION.....................................1
FIGURE 26- PATH OVERHEAD EXTRACTION..................................................1
FIGURE 27- TRANSPORT OVERHEAD INSERTION........................................1
FIGURE 28- PATH OVERHEAD INSERTION......................................................1
FIGURE 29- FRAME ALIGNMENT.....................................................................1
FIGURE 30- RECEIVE FIFO ..............................................................................1
FIGURE 31- TRANSMIT FIFO............................................................................1
FIGURE 32-........................................................................................................1
FIGURE 33- MICROPROCESSOR INTERFACE READ TIMING........................1
FIGURE 34- MICROPROCESSOR INTERFACE WRITE TIMING ......................1
FIGURE 35- LINE SIDE RECEIVE INTERFACE TIMING...................................1
FIGURE 36- RECEIVE ALARM OUTPUT TIMING .............................................1
FIGURE 37- RECEIVE OVERHEAD ACCESS TIMING......................................1
FIGURE 38- LINE SIDE TRANSMIT INTERFACE TIMING.................................1
FIGURE 39- TRANSMIT ALARM INPUT TIMING...............................................1
FIGURE 40- TRANSMIT OVERHEAD ACCESS TIMING....................................1
FIGURE 41- DROP SIDE RECEIVE INTERFACE TIMING (TSEN = 0)..............1
FIGURE 42- DROP SIDE RECEIVE INTERFACE TIMING (TSEN = 1)..............1
FIGURE 43- DROP SIDE TRANSMIT INTERFACE............................................1
FIGURE 44- JTAG PORT INTERFACE TIMING..................................................1
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LIST OF TABLES
TABLE 1 - ........................................................................................................1
TABLE 2 - ........................................................................................................1
TABLE 3 - ........................................................................................................1
TABLE 4 - ........................................................................................................1
TABLE 5 - ........................................................................................................1
TABLE 6 - INSTRUCTION REGISTER............................................................1
TABLE 7 - IDENTIFICATION REGISTER........................................................1
TABLE 8 - BOUNDARY SCAN REGISTER.....................................................1
TABLE 9 - ........................................................................................................1
TABLE 10 - ........................................................................................................1
TABLE 11 - MICROPROCESSOR INTERFACE READ ACCESS
(FIGURE 33) .......................................................................................................1
TABLE 12 - MICROPROCESSOR INTERFACE WRITE ACCESS
(FIGURE 34) .......................................................................................................1
TABLE 13 - LINE SIDE RECEIVE INTERFACE (FIGURE 35)...........................1
TABLE 14 - RECEIVE ALARM OUTPUT (FIGURE 36).....................................1
TABLE 15 - RECEIVE OVERHEAD ACCESS (FIGURE 37).............................1
TABLE 16 - LINE SIDE TRANSMIT INTERFACE (FIGURE 38)........................1
TABLE 17 - TRANSMIT ALARM INPUT (FIGURE 39) ......................................1
TABLE 18 - TRANSMIT OVERHEAD ACCESS (FIGURE 40)...........................1
TABLE 19 - DROP SIDE RECEIVE INTERFACE (FIGURE 41)........................1
TABLE 20 - DROP SIDE RECEIVE INTERFACE (FIGURE 42)........................1
TABLE 21 - DROP SIDE TRANSMIT INTERFACE (FIGURE 43)......................1
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TABLE 22 - JTAG PORT INTERFACE (FIGURE 44).........................................1
TABLE 23 - ........................................................................................................1
TABLE 24 - ........................................................................................................1
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1
FEATURES
Monolithic Saturn Network Interface that implements the ATM physical layer
•
for Broadband ISDN according to the ATM Forum User Network Interface
Specification and CCITT Recommendation I.432.
Operates at 155.52 MHz in conjunction with an external clock and data
•
recovery device. Provides on-chip parallel to serial and serial to parallel
circuits with pseudo ECL interfaces to process a duplex 155.52 Mbit/s STS3c/STM-1 data stream.
Supports a 19.44 Mbyte/s line interface option for devices requiring a byte-
•
serial STS-3c/STM-1 interface.
Provides 4 cell deep FIFO buffers in both transmit and receive paths with a
•
byte-wide or word-wide system side datapath interface.
Provides a generic 8-bit microprocessor bus interface for configuration,
•
control, and status monitoring.
Provides a standard 5 signal P1149.1 JTAG test port for boundary scan board
•
test purposes.
Low power, +5 Volt, CMOS technology.
•
160 pin high performance plastic quad flat pack (PQFP) package.
•
1.1 The receiver section:
Frames to the recovered 155.52 Mbit/s stream or to an 19.44 Mbyte/s stream
•
and descrambles the received STS-3c (STM-1) stream.
Interprets the received payload pointer (H1, H2), extracting the STS-3c
•
synchronous payload envelope (VC4) and path overhead.
Extracts ATM cells from the received STS-3c synchronous payload envelope
•
using ATM cell delineation and provides optional ATM cell payload
descrambling, header check sequence (HCS) error detection and error
correction, and idle/unassigned cell filtering.
Provides a generic 8 bit wide or 16 bit wide datapath interface to read
•
extracted cells from an internal four cell FIFO buffer.
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Extracts all transport overhead bytes and serializes them at 5.184 Mbit/s for
•
optional external processing.
Extracts all path overhead bytes and serializes them at 576 kbit/s for optional
•
external processing.
Detects loss of signal (LOS), out of frame (OOF), loss of frame (LOF), line
•
alarm indication signal (AIS), line far end receive failure (FERF), loss of
pointer (LOP), path alarm indication signal (AIS), and path yellow alarm.
Counts received section BIP-8 (B1) errors, received line BIP-24 (B2) errors,
•
line far end block errors (FEBE), received path BIP-8 (B3) errors and path far
end block erro rs (FEBE) for performance monitoring purposes.
Counts received HCS errored cells that are discarded, and received HCS
•
errored cells that are corrected and passed on for performance monitoring
purposes.
1.2 The transmitter section:
Provides an internal four cell FIFO into which cells are written using a generic
•
8 bit wide or 16 bit wide datapath interface
Provides idle/unassigned cell insertion, HCS generation/insertion, and ATM
•
cell payload scrambling.
Inserts ATM cells into the transmitted STS-3c (STM-1) synchronous payload
•
envelope using H4 framing.
Generates the transmit payload pointer (H1, H2) and inserts the path
•
overhead.
Optionally inserts externally generated path overhead bytes received via a
•
576 kbit/s serial interface.
Scrambles the transmitted STS-3c (STM-1) stream and inserts framing bytes
•
(A1, A2) and the identity byte (C1).
Optionally inserts externally generated transport overhead bytes received via
•
a 5.184 Mbit/s serial interface.
Interfaces to a downstream physical media device at 155.52 Mbit/s using
•
differential outputs. Alternately, the S/UNI can interface to a parallel to serial
converter at 19.44 Mbyte/s
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Optionally inserts path alarm indication signal (AIS), path yellow alarm
•
indication (PYEL), line alarm indication signal (AIS) and line far end receive
failure (FERF) indication.
Inserts path BIP-8 codes (B3), path far end block error (FEBE) indications,
•
line BIP-24 codes (B2), line far end block error (FEBE) indications, section
BIP-8 codes (B1) to allow performance monitoring at the far end.
Allows forced insertion of all zero s data (after scrambling) or corruption of
•
framing byte or section, line, or path BIP-8 codes for diagnostic purposes.
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2
APPLICATIONS
SONET/SDH Based ATM Switching Systems
•
SONET/SDH Based ATM Terminals
•
B-ISDN User-Network Interfaces
•
B-ISDN Network Node Interfaces
•
B-ISDN Test Equipment
•
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REFERENCES
•
ITU-T Recommendation I.432 - "B-ISDN User-Network Interface - Physical
Layer Specification", March 1993.
ANSI T1.624-1993 - "Broadband ISDN User-Network Interfaces - Rates and
•
Formats Specifications".
ATM Forum - ATM User-Network Interface Specification, V3.0, 1993.
•
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4
APPLICATION INFORMATION
The S/UNI is typically used to implement the core of an ATM User Network
Interface by which an ATM terminal is linked to an ATM switching system or ATM
switching systems are linked together using SONET/SDH compatible transport.
The S/UNI may find application at either end of terminal to switch links or switch
to switch links, both in private network (LAN) and public network (WAN)
situations.
In this application the S/UNI typically connects on its line side with a twisted pair
line receiver or optical receiver, plus a clock and data recovery device and a
twisted pair line driver or laser for the transmitter. In this application, the S/UNI is
loop timed internally (the recovered 155.52 MHz clock is used in the transmit
direction). The drop side interfaces directly with ATM adaptation layer
processors. The initial configuration and ongoing control and monitoring of the
S/UNI are normally provided via a generic microprocessor interface. The S/UNI
supports a "hardware-only" operating mode where an external microprocessor is
not required. Typical ATM Adapter card applications are shown in Figure 1 and
Figure 2.
Figure 1 - Example 1. Optical ATM Adapter Interface
Optical
Transmitter
Optical
Receiver
Clock
Recovery
PM5345
S/UNI
SATURN
USER NETWORK
INTERFACE
TDAT[15:0]
TSOC
TWRB
TCA
RCA
RDAT[7:0]
RSOC
RRDB
Transmit
AAL
Processor
ATM Terminal
Receive
AAL
Processor
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Figure 2 - Example 2. UTP-5 ATM Adapter Interface
Line Driver
&
Transformer
TDAT[15:0]
TSOC
TWRB
TCA
PM5345
Transmit
AAL
Processor
S/UNI
ATM Terminal
Receive
AAL
Processor
Transformer
&
Line Receiver
Clock
Recovery
SATURN
USER NETWORK
INTERFACE
RCA
RDAT[7:0]
RSOC
RRDB
Figure 3 shows a configuration in which the PM5345 S/UNI is used with a
PM5312 SONET/SDH Transport Overhead Terminating Transceiver (STTX) and a
PM5318 622 Mbit/s Serial/Parallel Converter (SIPO) to implement an ATM
backbone interface.
In this application, four STS-3/STM-1 ATM streams are multiplexed into a single
STS-12/STM-4 stream for transport over fiber optic cables. The function of the
PM5312, PM5318, clock recovery and clock synthesis are also available in the
PM5712B 622 Mbit/s SONET/SDH Line Interface Module (SLIM).
Figure 3 - Example 3. OC-12 ATM Switch Port Card Interface
STS-3c (STM-1)
ATM Termination
PM5345
S/UNI-155
OPTICAL
FACILITY
E/O
O/E
Clock
Synthesis
Serial /
Parallel
Conversion
Clock
Recovery
STS-3(STM-1) To STS-12 (STM-4) MUX
OOF
TOUT[7:0]
TCLK
RICLK
RIFP
RIN[7:0]
PM5312
STTX
#1
#2
#3
#4
ATM
SWITCH
CORE
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INTERFACE EXAMPLES
Figure 4 - Recommended Interface with CY7B951
FB
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Vcc
FB
10µF
0.1µF
Vcc
0.1µF
0.01µF
100
0.01µF
0.01µF
100
0.01µF
0.01µF
100
0.01µF
0.1µF
630
Ω
Ω
Ω
RAVD (141)
TAVD1 (15)
Ω
VT2 (24)
TXD+ (22)
TXD- (23)
TSER (26)
RSER (25)
TXCI+ (14)
TXCI- (13)
TXCO+ (19)
TXCO- (1 8 )
RXD+ (143)
RXD- (142)
PM 5345
RXC+ (139)
RXC- (138)
RAVS (140)
TAVS1 (16)
TAVS2 (21)
TAVD2 (20)
VT1 (17)
(14) TSER+
(13) TSER-
(15) TCLK+
(16) TCLK-
(21) R S E R +
(22) R S E R -
CY7B 951
(23) RCLK+
(24) RCLK-
(5) M ODE
59
312
330
330
330
V
REF
Vcc
10µF
Ω
59
Ω
Z0 = 50
Z0 = 50
Ω
312
Ω
Z0 = 50
Z0 = 50
Ω
330
Ω
Z0 = 50
Z0 = 50
Ω
330
Ω
Z0 = 50
Z0 = 50
Ω
330
Ω
Vcc
4.7k
Ω
10µF
(20) L FI
GPIN (8 1)
In Figure 4, the interface between the S/UNI and the Cypress CY7B951 is
shown.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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PM5345 S/UNI-155
DATA SHEET
PMC-930305 ISSUE 4 SATURN USER NETWORK INTERFACE
For optimal performance, the following guidelines should be followed:
• All power pins should be well decoupled, with the capacitors placed as close
as possible to the S/UNI power pins.
• Termination resistors and capacitors should be placed as close as possible to
the end of the transmission line.
• Source pull-down resistors should be placed as close as possible to the start
of the transmission line.
• Traces marked "Zo=50Ω" should be controlled impedance traces. These
traces should be kept as short as possible. Other controlled impedances can
be used. Contact PMC-Sierra's applications department for information on
using the S/UNI in "non-50Ω" controlled impedance environments.
• All inductors are Fair-Rite Products Corp #274-3019-446.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
9
PM5345 S/UNI-155
DATA SHEET
PMC-930305 ISSUE 4 SATURN USER NETWORK INTERFACE
Figure 5 - Recommended Interface with AD802
Transm it
PMD
155.52 MHz
Oscillator
(2) D ATAOU T+
(1) D ATAOU T-
AD802
(5) C L KOUT+
(4) C L KOUT-
59
312
330
330
330
REF
V
10µF
0.1µF
RAVD (141)
FB
FB
Vcc
10µF
Ω
Ω
59
312
Ω
Z0 = 50
Z0 = 50
Ω
Ω
Ω
0.1µF
Vcc
630
TAVD1 (15)
Ω
VT2 (24)
TXD+ (22)
TXD- (23)
TSER (26)
RSER (25)
0.01µF
Z0 = 50
Z0 = 50
Ω
330
Ω
Ω
Ω
100
Ω
0.01µF
TXCI+ (14)
TX C I- (1 3 )
TXCO+ (19)
TX C O- (18 )
0.01µF
Z0 = 50
Z0 = 50
Ω
330
Ω
Ω
Ω
100
Ω
RXD+ (14 3)
RXD- (142)
0.01µF
PM 5345
0.01µF
Z0 = 50
Z0 = 50
Ω
330
Ω
Ω
Ω
Vcc
Ω
100
0.01µF
RXC+ (13 9)
RXC- (138)
RAVS (140)
TAVS1 (16)
TAVS2 (21)
TAVD2 (20)
10µF
0.1µF
VT1 (17)
In Figure 5, the interface between the S/UNI and the Analog Devices AD802 is
shown. In addition to the AD802, a 155.52 MHz oscillator provides the transmit
clock to the S/UNI. Oscillator vendors include CTS Corporation, C-MAC Quartz
Crystals Ltd., and Connor Winfield.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
10
PM5345 S/UNI-155
DATA SHEET
PMC-930305 ISSUE 4 SATURN USER NETWORK INTERFACE
For optimal performance, the following guidelines should be followed:
• All power pins should be well decoupled, with the capacitors placed as close
as possible to the S/UNI power pins.
• Termination resistors and capacitors should be placed as close as possible to
the end of the transmission line.
• Source pull-down resistors should be placed as close as possible to the start
of the transmission line.
• Traces marked "Zo=50Ω" should be controlled impedance traces. These
traces should be kept as short as possible. Other controlled impedances can
be used. Contact PMC-Sierra's applications department for information on
using the S/UNI in "non-50Ω" controlled impedance environments.
• All inductors are Fair-Rite Products Corp #274-3019-446.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
11
PM5345 S/UNI-155
DATA SHEET
PMC-930305 ISSUE 4 SATURN USER NETWORK INTERFACE
6
POUT[7:0]
BLOCK DIAG RAM
VT2
VT1
TSER
TLAIS
TXCI+/-
TXCO+/-
TXD+/-
FPOUT Tx ATM
POCLK
OOF
PICLK
FPIN
FPOS
PIN[7:0]
RXC+/RXD+/-
Par/
Ser
L ine
Side
I/F
Ser/
Par
RSER
Tx
Section
O/H
Processor
Rx
Section
O/H
Processor
LOF
LOS
TFERFLAIS
Transport
Overhead
Line O/H
Processor
Line O/H
Processor
Transport
Overhead
FERF
TTOH
TTOHFP
Insert
Tx
Rx
Extract
RTOH
TTOHEN
TTOHCLK
RTOHFP
RTOHCLK
TPOH
TPOHCLK
TPOHFP
Path
Overhead
Insert
Processor
Processor
Path
Overhead
Extract
RPOH
RPOHFP
TPOHEN
Tx
Path
O/H
Rx
Path
O/H
RPOHCLK
TFP
LOP
TPAIS
PAIS
TPYEL
PYEL
RCLK
TCLK
Cell
Processor
Rx ATM
Cell
Processor
Microprocessor
A[7:0]
D[7:0]
ALE
I/F
CSB
WRB
Tx ATM
4 Cell
FIFO
Rx ATM
4 Cell
FIFO
RDB
RSTB
TDO
JTAG Test
Access Port
INTB
GPIN
TDI
TCK
TMS
Drop
Side
I/F
BUS8
TRSTB
TSEN
TSOC
TDAT[15:0]
TCA
TWRB
RSOC
RDAT[15:0]
RCA
RRDB
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
12
PM5345 S/UNI-155
DATA SHEET
PMC-930305 ISSUE 4 SATURN USER NETWORK INTERFACE
7
DESCRIPTION
The PM5345 S/UNI SATURN User Network Interface is a monolithic integrated
circuit that implements the SONET/SDH processing and ATM mapping functions
of a 155 Mbit/s ATM User-Network Interface.
The S/UNI receives SONET/SDH frames, via a bit serial or byte serial interface,
and processes section, line, and path overhead. It performs framing (A1, A2),
descrambling, detects alarm conditions, and monitors section, line, and path bit
interleaved parity (B1, B2, B3), accumulating error counts at each level for
performance monitoring purposes. Line and path far end block error indications
(Z2, G1) are also accumulated. The S/UNI interprets the received payload
pointers (H1, H2) and extracts the synchronous payload envelope which carries
the received ATM cell payload. In addition to its basic processing of the received
SONET/SDH overhead, the S/UNI provides convenient access to all overhead
bytes, which are extracted and serialized on lower rate interfaces, allowing
additional external processing of overhead.
The S/UNI frames to the ATM payload using cell delineation. HCS error
correction is provided. Idle/unassigned cells may be dropped according to a
programmable filter. Cells are also dropped upon detection of an uncorrectable
header check sequence error. The ATM cell payloads are descrambled. The
ATM cells that are passed are written to a four cell FIFO buffer. The received
cells are read from the FIFO using a generic 9 bit wide or 17 bit wide datapath
interface. Counts of received ATM cell headers that are errored and
uncorrectable and also those that are errored and correctable are accumulated
independently for performance monitoring purposes.
The S/UNI transmits SONET/SDH frames, via a bit serial or a byte serial
interface, and formats section, line, and path overhead appropriately. It performs
framing pattern insertion (A1, A2), scrambling, alarm signal insertion, and
creates section, line, and path bit interleaved parity (B1, B2, B3) as required to
allow performance monitoring at the far end. Line and path far end block error
indications (Z2, G1) are also inserted. The S/UNI generates the payload pointer
(H1, H2) and inserts the synchronous payload envelope which carries the ATM
cell payload. In addition to its basic formatting of the transmitted SONET/SDH
overhead, the S/UNI provides convenient access to all overhead bytes, which are
optionally inserted from lower rate serial interfaces, allowing external sourcing of
overhead. The S/UNI also supports the insertion of a large variety of errors into
the transmit stream, such as framing pattern errors, bit interleaved parity errors,
and illegal pointers, which are useful for system diagnostics and tester
applications.
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PM5345 S/UNI-155
DATA SHEET
PMC-930305 ISSUE 4 SATURN USER NETWORK INTERFACE
ATM cells are written to an internal four cell FIFO using a generic 9 bit wide or 17
bit wide datapath interface. Idle/unassigned cells are automatically inserted
when the internal FIFO contains less than one cell. The S/UNI provides
generation of the header check sequence and scrambles the payload of the ATM
cells. Each of these transmit ATM cell processing functions can be enabled or
bypassed.
No auxiliary clocks are required directly by the S/UNI as it operates from two
155.52 MHz clocks (bit serial line interface) or two 19.44 MHz clocks (byte serial
interface). The S/UNI is configured, controlled and monitored via a generic 8-bit
microprocessor bus interface. The S/UNI also provides a standard 5 signal
P1149.1 JTAG test port for boundary scan board test purposes.
The S/UNI is implemented in low power, +5 Volt, CMOS technology. It has TTL
and pseudo ECL (PECL) compatible inputs and outputs and is packaged in a
160 pin PQFP package.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
14
PM5345 S/UNI-155
5
2
DATA SHEET
PMC-930305 ISSUE 4 SATURN USER NETWORK INTERFACE
8
PIN DIAG RAM
The S/UNI is packaged in an 160 pin PQFP package having a body size of
28 mm by 28 mm and a pin pitch of 0.65 mm.
PIN3
PIN 160
POUT1
POUT2
POUT0
FPIN
RCLK
VSSO
VDDI
VDDO
PICLK
PIN7
PIN6
PIN5
PIN4
PIN2
PIN1
PIN0
RXD+
RXD-
RAVS
RAVD
RXC+
RXC-
RDAT1
VSSO
RDAT14
RDAT13
VDDO
RDAT1
RDAT11
VSSI
RDAT10
VSSO
RDAT9
RDAT8
RDAT7
VDDO
RDAT5
RDAT6
PIN 1
POUT3
POUT4
POUT5
POUT6
POUT7
VSSO
TCLK
VDDO
POCLK
FPOUT
FPOS/MLT
VSSI
TXCI-
TXCI+
TAVD1
TAVS1
VT1
TXCOTXCO+
TAVD2
TAVS2
TXD+
TXD-
VT2
RSER
TSER
TFP
TPAIS
TLAIS
TPYEL
TFERF
OOF
LOS
LOF
LOP
VSSO
PAIS
LAIS
PYEL
FERF
Index
PM5345
S/UNI
(Top View)
VSSO
PIN 121
PIN 120
RDAT4
RDAT3
RDAT2
RDAT1
VDDO
RDAT0
VSSO
RSOC
RCA
RRDB
BUS8
TSEN
RDB
WRB
D7
D6
D5
D4
VDDO
VDDI
TCK
VSSO
D3
D2
D1
D0
INTB
A7
A6
A5
A4
A3
A2
A1
A0
CSB
ALE
RSTB
TRSTB
GPIN
PIN 40
PIN 41 PIN 80
RTOHFP
TTOHEN
TPOHEN
TPOH
TPOHFP
VDDO
TPOHCLK
RPOHFP
RPOH
VSSO
RPOHCLK
TTOH
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
RTOH
TTOHFP
TTOHCLK
RTOHCLK
TWRB
VDDI
TCA
TSOC
TDAT0
TDAT1
TDAT2
TDAT3
TDAT4
TDAT5
TDAT6
TDAT7
VSSI
TDAT8
TDAT9
TDAT11
TDAT10
TDAT13
TDAT12
TDAT15
TDAT14
TDO
TDI
TMS
PIN 81
15
PM5345 S/UNI-155
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PMC-930305 ISSUE 4 SATURN USER NETWORK INTERFACE
9
PIN DESCRIPTION
Table 1 -
Pin Name Type Pin
Function
No.
RSER Input 25 The receive serial input (RSER) selects the
receive line interface. RSER is tied high to
select the 155.52 Mbit/s interface (on pins
RXC+, RXC-, RXD+, and RXD-). RSER is tied
low to select the 19.44 Mbyte/s interface (on
pins PICLK, PIN[7:0], and FPIN).
RXD+
RXD-
Input 143
142
The receive differential data inputs (RXD+,
RXD-) contain the 155.52 Mbit/s receive STS-
3c (STM-1) stream when the bit serial interface
is selected (RSER is tied high). RXD+/- is
sampled on the rising edge of RXC+/- (the
falling edge may be used by reversing RXC+/-
).
RXC+
RXC-
Input 139
138
The receive differential clock inputs (RXC+,
RXC-) contain the receive clock when the bit
serial interface is selected (RSER is tied high).
RXC+/- is nominally a 155.52 MHz, 50% duty
cycle clock. This clock is divided by eight
internally to produce RCLK when the bit serial
interface is selected and provide timing for the
S/UNI receive functions. RXD+/- is sampled
on the rising edge of RXC+/-.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
16
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