PMC PM5344-RI Datasheet
PM5344 SPTX
DATA SHEET
PMC-930531 ISSUE 6 SONET/SDH PATH TERMINATING TRANSCEIVER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
PM5344
SPTX
SONET/SDH PATH TERMINATING
TRANSCEIVER TELECOM
DATA SHEET
ISSUE 6: JULY 1998
PM5344 SPTX
DATA SHEET
PMC-930531 ISSUE 6 SONET/SDH PATH TERMINATING TRANSCEIVER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
PUBLIC REVISION HISTORY
Issue No Date of issue Details of Change
6 July 1998 Data Sheet Reformatted — No Change in
Technical Content.
Generated R5 data sheet from PMC-920813, P8
PM5344 SPTX
DATA SHEET
PMC-930531 ISSUE 6 SONET/SDH PATH TERMINATING TRANSCEIVER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
i
CONTENTS
1 FEATURES......................................................................................................................................1
1.1 THE RECEIVER SECTION:..............................................................................................1
1.2 THE TRANSMITTER SECTION:.......................................................................................3
2 APPLICATIONS...............................................................................................................................5
3 REFERENCES................................................................................................................................6
4 APPLICATION EXAMPLES.............................................................................................................7
5 BLOCK DIAGRAM...........................................................................................................................9
6 DESCRIPTION..............................................................................................................................10
7 PIN DIAGRAM...............................................................................................................................12
8 PIN DESCRIPTION.......................................................................................................................13
9 FUNCTIONAL DESCRIPTION......................................................................................................25
9.1 RECEIVE PATH OVERHEAD PROCESSOR...................................................................25
9.1.1 POINTER INTERPRETER................................................................................25
9.1.2 MULTIFRAME FRAMER...................................................................................29
9.1.3 SPE TIMING......................................................................................................30
9.1.4 ERROR MONITOR............................................................................................30
9.1.5 PATH OVERHEAD EXTRACT...........................................................................30
9.1.6 TANDEM CONNECTION ORIGINATE..............................................................31
9.1.7 RECEIVE ALARM PORT..................................................................................31
9.2 RECEIVE PATH TRACE BUFFER...................................................................................31
9.3 RECEIVE TELECOM BUS ALIGNER...............................................................................33
9.3.1 ELASTIC STORE..............................................................................................33
9.3.2 POINTER GENERATOR...................................................................................34
PM5344 SPTX
DATA SHEET
PMC-930531 ISSUE 6 SONET/SDH PATH TERMINATING TRANSCEIVER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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9.3.3 TANDEM CONNECTION ALARM.....................................................................36
9.4 TRANSMIT PATH OVERHEAD PROCESSOR................................................................37
9.4.1 BIP-8 CALCULATE...........................................................................................37
9.4.2 FEBE CALCULATE...........................................................................................37
9.4.3 TRANSMIT ALARM PORT................................................................................37
9.4.4 PATH OVERHEAD INSERT...............................................................................38
9.4.5 SPE MULTIPLEXER.........................................................................................38
9.4.6 GENERATED BUS CONTROLLER...................................................................38
9.5 TRANSMIT TELECOM BUS ALIGNER............................................................................39
9.5.1 ELASTIC STORE..............................................................................................40
9.5.2 POINTER GENERATOR...................................................................................40
9.5.3 TANDEM CONNECTION ALARM.....................................................................40
9.6 TRANSMIT PATH TRACE BUFFER................................................................................41
9.7 TELECOMBUS INTERFACE...........................................................................................41
9.8 MICROPROCESSOR INTERFACE.................................................................................41
9.9 REGISTER MEMORY MAP ............................................................................................41
10 NORMAL MODE REGISTER DESCRIPTION...............................................................................45
11 TEST FEATURES DESCRIPTION ..............................................................................................128
11.1 TEST MODE REGISTER MEMORY MAP.....................................................................128
11.2 I/O TEST MODE............................................................................................................130
12 OPERATION................................................................................................................................140
12.1 CONFIGURATION OPTIONS........................................................................................140
12.1.1 STS-1 (SINGLE AU3) MODE..........................................................................140
12.1.2 STS-3 (TRIPLE AU3) MODE ..........................................................................141
PM5344 SPTX
DATA SHEET
PMC-930531 ISSUE 6 SONET/SDH PATH TERMINATING TRANSCEIVER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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12.1.3 STS-3C (AU4) MODE.....................................................................................141
12.1.4 ORIGINATING TCTE MODE...........................................................................141
12.1.5 TRANSMIT TCTE TERMINATING MODE.......................................................141
12.1.6 PA TH AND TCTE TERMINATING MODE ........................................................141
12.1.7 RECEIVE TCTE BYPASS MODE....................................................................142
12.1.8 TRANSMIT TCTE BYPASS MODE.................................................................142
13 FUNCTIONAL TIMING ................................................................................................................143
13.1 RECEIVE SECTION......................................................................................................143
13.1.1 RECEIVE STREAM TIMING...........................................................................143
13.1.2 EXTERNAL PATH TERMINATION RECEIVE BUS TIMING............................144
13.1.3 DROP BUS TIMING ........................................................................................147
13.1.4 RECEIVE LOW-SPEED INTERFACE TIMING................................................150
13.1.5 RECEIVE ALARM STATUS TIMING................................................................153
13.2 TRANSMIT SECTION...................................................................................................155
13.2.1 GENERATED BUS TIMING.............................................................................155
13.2.2 ADD BUS TIMING...........................................................................................158
13.2.3 TRANSMIT LOW-SPEED INTERFACE TIMING..............................................161
13.2.4 TRANSMIT BUS TIMING ................................................................................163
13.2.5 ELASTIC STORE BYPASS TIMING................................................................166
14 ABSOLUTE MAXIMUM RATINGS...............................................................................................170
15 D.C. CHARACTERISTICS ...........................................................................................................171
16 MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS .............................................174
17 SPTX TIMING CHARACTERISTICS ...........................................................................................181
18 ORDERING AND THERMAL INFORMATION .............................................................................195
PM5344 SPTX
DATA SHEET
PMC-930531 ISSUE 6 SONET/SDH PATH TERMINATING TRANSCEIVER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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19 MECHANICAL INFORMATION....................................................................................................196
PM5344 SPTX
DATA SHEET
PMC-930531 ISSUE 6 SONET/SDH PATH TERMINATING TRANSCEIVER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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LIST OF REGISTERS
REGISTER 00H: SPTX MASTER CONFIGURATION..................................................................................46
REGISTER 01H: SPTX MASTER ALARM CONFIGURATION ....................................................................49
REGISTER 02H: SPTX MASTER PARITY CONFIGURATION ....................................................................51
REGISTER 03H: SPTX MASTER RESET AND IDENTITY.........................................................................53
REGISTER 04H: SPTX MASTER INTERRUPT STATUS #1........................................................................54
REGISTER 05H: SPTX MASTER INTERRUPT STATUS #2........................................................................55
REGISTER 06H: SPTX MASTER TRANSMIT CONTROL...........................................................................56
REGISTER 07H: SPTX MASTER LOOPBACK, ADD BUS CONTROL .......................................................57
REGISTER 08H: SPTX MASTER SIGNAL ACTIVITY MONITOR, ACCUMULATION TRIGGER ................58
REGISTER 10H, 50H, 90H: RPOP STATUS AND CONTROL.....................................................................60
REGISTER 11H, 51H, 91H: RPOP ALARM INTERRUPT STATUS .............................................................62
REGISTER 12H, 52H, 92H: RPOP POINTER INTERRUPT STATUS..........................................................63
REGISTER 13H, 53H, 93H: RPOP ALARM INTERRUPT...........................................................................65
REGISTER 14H, 54H, 94H: POINTER INTERRUPT ENABLE.................................................................... 67
REGISTER 15H, 55H, 95H: RPOP POINTER LSB.....................................................................................69
REGISTER 16H, 56H, 96H: RPOP POINTER MSB ....................................................................................70
REGISTER 17H, 57H, 97H: RPOP PATH SIGNAL LABEL ..........................................................................71
REGISTER 18H, 58H, 98H: RPOP PATH BIP-8 LSB...................................................................................72
REGISTER 19H, 59H, 99H: PATH BIP-8 MSB.............................................................................................73
REGISTER 1AH, 5AH, 9AH: RPOP FEBE LSB...........................................................................................74
REGISTER 1BH, 5BH, 9BH: RPOP FEBE MSB..........................................................................................75
REGISTER 1CH, 5CH, 9CH: RPOP TRIBUTARY MULTIFRAME STATUS AND CONTROL.......................76
REGISTER 1DH, 5DH, 9DH: RPOP TANDEM CONNECTION AND RING CONTROL...............................78
PM5344 SPTX
DATA SHEET
PMC-930531 ISSUE 6 SONET/SDH PATH TERMINATING TRANSCEIVER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
vi
REGISTER 1EH, 5EH, 9EH: RPOP TANDEM CONNECTION IEC COUNT LSB........................................80
REGISTER 1FH, 5FH, 9FH: RPOP TANDEM CONNECTION IEC COUNT MSB........................................81
REGISTER 24H, 64H, A4H: PMON RECEIVE POSITIVE POINTER JUSTIFICATION COUNT.................82
REGISTER 25H, 65H, A5H: PMON RECEIVE NEGATIVE POINTER JUSTIFICATION COUNT................83
REGISTER 26H, 66H, A6H: PMON TRANSMIT POSITIVE POINTER JUSTIFICATION COUNT...............84
REGISTER 27H, 67H, A7H: PMON TRANSMIT NEGATIVE POINTER JUSTIFICATION COUNT..............85
REGISTER 28H, 68H, A8H: RTAL CONTROL.............................................................................................86
REGISTER 29H, 69H, A9H: RTAL INTERRUPT STATUS AND DIAGNOSTIC............................................88
REGISTER 2AH, 6AH, AAH: RTAL ALARM AND DIAGNOSTIC CONTROL ...............................................91
REGISTER 30H, 70H, B0H: TPOP CONTROL............................................................................................93
REGISTER 31H, 71H, B1H: TPOP GENERATED BUS CONTROL.............................................................95
REGISTER 32H, 72H, B2H: TPOP SOURCE CONTROL............................................................................97
REGISTER 33H, 73H, B3H: TPOP CURRENT POINTER LSB ...................................................................98
REGISTER 34H, 74H, B4H: TPOP CURRENT POINTER MSB ..................................................................99
REGISTER 35H, 75H, B5H: TPOP PAYLOAD POINTER LSB...................................................................100
REGISTER 36H, 76H, B6H: TPOP PAYLOAD POINTER MSB..................................................................101
REGISTER 37H, 77H, B7H: TPOP PATH TRACE ......................................................................................102
REGISTER 38H, 78H, B8H: TPOP PATH SIGNAL LABEL ........................................................................103
REGISTER 39H, 79H, B9H: TPOP PATH STATUS ....................................................................................104
REGISTER 3AH, 7AH, BAH: TPOP PATH USER CHANNEL ....................................................................106
REGISTER 3BH, 7BH, BBH: TPOP PATH GROWTH #1 ...........................................................................107
REGISTER 3CH, 7CH, BCH: TPOP PATH GROWTH #2...........................................................................108
REGISTER 3DH, 7DH, BDH: TPOP TANDEM CONNECTION MAINTENANCE.......................................109
REGISTER 3EH: TPOP CONCATENATION LSB.......................................................................................110
PM5344 SPTX
DATA SHEET
PMC-930531 ISSUE 6 SONET/SDH PATH TERMINATING TRANSCEIVER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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REGISTER 3FH: TPOP CONCATENATION MSB......................................................................................111
REGISTER 40H, 80H, C0H: TTAL CONTROL...........................................................................................112
REGISTER 41H, 81H, C1H: TTAL INTERRUPT STATUS AND DIAGNOSTIC ..........................................114
REGISTER 42H, 82H, C2H: TTAL ALARM AND DIAGNOSTIC CONTROL ..............................................117
REGISTER 48H, 88H, C8H: SPTB CONTROL..........................................................................................119
REGISTER 49H, 89H, C9H: SPTB PATH TRACE IDENTIFIER STATUS...................................................121
REGISTER 4AH, 8AH, CAH: SPTB INDIRECT ADDRESS REGISTER....................................................123
REGISTER 4BH, 8BH, CBH: SPTB INDIRECT DATA REGISTER ............................................................124
REGISTER 4CH, 8CH, CCH: SPTB EXPECTED PATH SIGNAL LABEL ..................................................125
REGISTER 4DH, 8DH, CDH: SPTB PATH SIGNAL LABEL STATUS ........................................................126
REGISTER 100H: MASTER TEST ............................................................................................................129
TEST REGISTER 101H: (WRITE IN I/O TEST MODE) .............................................................................131
TEST REGISTER 102H: (WRITE IN I/O TEST MODE) .............................................................................132
TEST REGISTER 103H: (WRITE IN I/O TEST MODE) .............................................................................133
TEST REGISTER 104H: (WRITE IN I/O TEST MODE) .............................................................................134
TEST REGISTER 101H: (READ IN I/O TEST MODE)...............................................................................135
TEST REGISTER 102H: (READ IN I/O TEST MODE)...............................................................................136
TEST REGISTER 103H: (READ IN I/O TEST MODE)...............................................................................137
TEST REGISTER 104H: (READ IN I/O TEST MODE)...............................................................................138
TEST REGISTER 105H: (READ IN I/O TEST MODE)...............................................................................139
PM5344 SPTX
DATA SHEET
PMC-930531 ISSUE 6 SONET/SDH PATH TERMINATING TRANSCEIVER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
viii
LIST OF FIGURES
FIGURE 1 - 155 MBIT/S STS-3/STM-1 ADD-DROP OR TERMINAL MUX INTERFACE .......................7
FIGURE 2 - 622 MBIT/S STS-12/STM-4 ADD-DROP MULTIPLEXER AGGREGATE INTERFACE.......8
FIGURE 3 - POINTER INTERPRETATION STATE DIAGRAM..............................................................26
FIGURE 4 - POINTER GENERATION STATE DIAGRAM.....................................................................35
FIGURE 5 - STS-1 (SINGLE AU3) RECEIVE STREAM TIMING .......................................................143
FIGURE 6 - STS-3 (STM1 - AU3) RECEIVE STREAM TIMING.........................................................144
FIGURE 7 - STS-3C (STM1 - AU4) RECEIVE STREAM TIMING ......................................................144
FIGURE 8 - STS-1 MODE RECEIVE BUS TIMING............................................................................145
FIGURE 9 - STS-3 (STM1 - AU3) MODE RECEIVE BUS TIMING.....................................................146
FIGURE 10 - STS-3C (STM1 - AU4) MODE RECEIVE BUS TIMING..................................................147
FIGURE 11 - STS-1 MODE DROP BUS TIMING.................................................................................148
FIGURE 12 - STS-3 (STM1 - AU3) MODE DROP BUS TIMING..........................................................149
FIGURE 13 - STS-3C (STM1 - AU4) MODE DROP BUS TIMING........................................................150
FIGURE 14 - RECEIVE PATH OVERHEAD EXTRACTION TIMING ....................................................151
FIGURE 15 - RECEIVE ALARM PORT TIMING...................................................................................152
FIGURE 16 - RECEIVE TANDEM CONNECT MAINTENANCE INSERTION TIMING .........................153
FIGURE 17 - LOSS OF POINTER (LOP) DECLARATION/REMOVAL TIMING....................................153
FIGURE 18 - PATH AIS (PAIS) DECLARATION/REMOVAL TIMING....................................................154
FIGURE 19 - PATH FERF ALARM (PFERF) DECLARATION/REMOVAL TIMING...............................154
FIGURE 20 - LOSS OF MULTIFRAME (LOM) DECLARATION/REMOVAL TIMING............................155
FIGURE 21 - STS-1 MODE GENERATED BUS TIMING......................................................................156
FIGURE 22 - STS-3 (STM1 - AU3) MODE GENERATED BUS TIMING...............................................157
FIGURE 23 - STS-3C (STM1 - AU4) MODE GENERATED BUS TIMING............................................158
PM5344 SPTX
DATA SHEET
PMC-930531 ISSUE 6 SONET/SDH PATH TERMINATING TRANSCEIVER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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FIGURE 24 - STS-1 MODE ADD BUS TIMING....................................................................................159
FIGURE 25 - STS-3 (STM1 - AU3) MODE ADD BUS TIMING.............................................................160
FIGURE 26 - STS-3C (STM1 - AU4) MODE ADD BUS TIMING ..........................................................161
FIGURE 27 - TRANSMIT PATH OVERHEAD INSERTION TIMING ......................................................162
FIGURE 28 - TRANSMIT ALARM PORT TIMING ................................................................................163
FIGURE 29 - STS-1 MODE TRANSMIT BUS TIMING .........................................................................164
FIGURE 30 - STS-3 (STM1 - AU3) MODE TRANSMIT BUS TIMING ..................................................165
FIGURE 31 - STS-3C (STM1 - AU4) MODE TRANSMIT BUS TIMING................................................166
FIGURE 32 - STS-1 (SINGLE AU3) RECEIVE ELASTIC STORE BYPASS TIMING ...........................166
FIGURE 33 - STS-3 (STM1 - AU3) RECEIVE ELASTIC STORE BYPASS TIMING.............................167
FIGURE 34 - STS-3C (STM1 - AU4) RECEIVE ELASTIC STORE BYPASS TIMING..........................167
FIGURE 35 - STS-1 (SINGLE AU3) TRANSMIT ELASTIC STORE BYPASS TIMING.........................168
FIGURE 36 - STS-3 (STM1 - AU3) TRANSMIT ELASTIC STORE BYPASS TIMING..........................168
FIGURE 37 - STS-3C (STM1 - AU4) TRANSMIT ELASTIC STORE BYPASS TIMING........................169
FIGURE 38 - MICROPROCESSOR INTERFACE READ TIMING (INTEL MODE)...............................175
FIGURE 39 - MICROPROCESSOR INTERFACE READ TIMING (MOTOROLA MODE).....................176
FIGURE 40 - MICROPROCESSOR INTERFACE WRITE TIMING (INTEL MODE)..............................178
FIGURE 41 - MICROPROCESSOR INTERFACE WRITE TIMING (MOTOROLA MODE)....................179
FIGURE 42 - RECEIVE LINE INPUT TIMING......................................................................................182
FIGURE 43 - RECEIVE ALARM OUTPUT TIMING..............................................................................183
FIGURE 44 - RECEIVE OVERHEAD AND ALARM PORT OUTPUT TIMING......................................184
FIGURE 45 - RECEIVE TANDEM CONNECTION INPUT TIMING.......................................................185
FIGURE 46 - DROP BUS INPUT TIMING............................................................................................185
FIGURE 47 - DROP BUS OUTPUT TIMING........................................................................................186
PM5344 SPTX
DATA SHEET
PMC-930531 ISSUE 6 SONET/SDH PATH TERMINATING TRANSCEIVER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
x
FIGURE 48 - GENERATED BUS INPUT TIMING.................................................................................187
FIGURE 49 - GENERATED BUS OUTPUT TIMING.............................................................................188
FIGURE 50 - ADD BUS INPUT TIMING...............................................................................................189
FIGURE 51 - TRANSMIT OVERHEAD INPUT TIMING........................................................................190
FIGURE 52 - TRANSMIT OVERHEAD OUTPUT TIMING....................................................................190
FIGURE 53 - TRANSMIT ALARM PORT INPUT TIMING..................................................................... 191
FIGURE 54 - TRANSMIT STREAM INPUT TIMING.............................................................................192
FIGURE 55 - TRANSMIT STREAM OUTPUT TIMING.........................................................................193
FIGURE 56 - 160 PIN COPPER LEADFRAME PLASTIC QUAD FLAT PACK (R SUFFIX):.................196
PM5344 SPTX
DATA SHEET
PMC-930531 ISSUE 6 SONET/SDH PATH TERMINATING TRANSCEIVER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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LIST OF TABLES
TABLE 1- PIN DESCRIPTION.....................................................................................................................13
TABLE 2- PATH SIGNAL LABEL MATCH/MISMATCH.................................................................................32
TABLE 3- REGISTER MEMORY MAP.........................................................................................................41
TABLE 4- RECEIVE ELASTIC STORE DEPTH CONTROL........................................................................89
TABLE 5- TRANSMIT ELASTIC STORE DEPTH CONTROL ....................................................................115
TABLE 6- TEST MODE REGISTER MEMORY MAP.................................................................................128
TABLE 7- D.C. CHARACTERISTICS.........................................................................................................171
TABLE 8- MICROPROCESSOR INTERFACE READ ACCESS (FIGURE 38, FIGURE 39)......................174
TABLE 9- MICROPROCESSOR INTERFACE WRITE ACCESS (FIGURE 40, FIGURE 41).....................177
TABLE 10 - RECEIVE LINE INPUT TIMING (FIGURE 42)................................................................181
TABLE 11 - RECEIVE ALARM OUTPUT TIMING (FIGURE 43)........................................................182
TABLE 12 - RECEIVE OVERHEAD AND ALARM PORT OUTPUT TIMING (FIGURE 44)................183
TABLE 13 - RECEIVE TANDEM CONNECTION INPUT TIMING (FIGURE 45)................................184
TABLE 14 - DROP BUS INPUT TIMING (FIGURE 46)......................................................................185
TABLE 15 - DROP BUS OUTPUT TIMING (FIGURE 47)..................................................................186
TABLE 16 - GENERATED BUS INPUT TIMING (FIGURE 48)...........................................................187
TABLE 17 - GENERATED BUS OUTPUT TIMING (FIGURE 49).......................................................187
TABLE 18 - ADD BUS INPUT TIMING (FIGURE 50).........................................................................188
TABLE 19 - TRANSMIT OVERHEAD INPUT TIMING (FIGURE 51)..................................................189
TABLE 20 - TRANSMIT OVERHEAD OUTPUT TIMING (FIGURE 52)..............................................190
TABLE 21 - TRANSMIT ALARM PORT INPUT TIMING (FIGURE 53)...............................................191
TABLE 22 - TRANSMIT STREAM INPUT TIMING (FIGURE 54).......................................................191
TABLE 23 - TRANSMIT STREAM OUTPUT TIMING (FIGURE 55)...................................................192
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DATA SHEET
PMC-930531 ISSUE 6 SONET/SDH PATH TERMINATING TRANSCEIVER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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TABLE 24 - ORDERING INFORMATION...........................................................................................195
TABLE 25 - THERMAL INFORMATION .............................................................................................195
PM5344 SPTX
DATA SHEET
PMC-930531 ISSUE 6 SONET/SDH PATH TERMINATING TRANSCEIVER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
1
1
FEATURES
·
Monolithic SONET/SDH Path Terminating Transceiver that terminates the path
overhead of one or three STS-1 (AU3) paths or a single STS-3c (AU4) path.
·
Maps one or three STS-1 (AU3) payloads or a single STS-3c (AU4) payload
to system timing reference, accommodating plesiochronous timing offsets
between the references through pointer processing.
·
Operates at 19.44 MHz or 6.48 MHz, processing a duplex 19.44 Mbyte/s or
6.48 Mbyte/s data stream.
·
Supports line loopback from line side receive stream to transmit stream and
diagnostic loopback from ADD bus interface to DROP bus interface.
·
Operates in conjunction with the PM5343 STXC, or with the PM5312 STTX
and PM5318 SIPO to form a complete physical interface up to photonics.
·
Provides a generic 8-bit microprocessor bus interface for configuration,
control, and status monitoring.
·
Low power, +5 Volt, CMOS technology, TTL compatible inputs and outputs.
·
160 pin plastic quad flat pack (PQFP) package.
1.1 The receiver section:
·
Operates in STS-3 (AU3) or STS-3c (AU4) mode.
·
Accepts a byte serial line side multiplex of three STS-1 (AU3) streams or a
single STS-3c (AU4) stream, interprets the STS (AU) pointer bytes (H1, H2,
and H3), and extracts the synchronous payload envelope(s) and inser ts the
synchronous payload envelope(s) into a bus referenced to system timing,
using pointer processing.
·
Extracts and processes the three STS-1 (AU3) path overhead streams or the
single STS-3c (AU4) path overhead stream.
·
Detects loss of pointer (LOP).
·
Detects loss of tributary multiframe (LOM).
·
Detects path alarm indication signal (AIS).
PM5344 SPTX
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PMC-930531 ISSUE 6 SONET/SDH PATH TERMINATING TRANSCEIVER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
2
·
Detects path FERF alarm.
·
Extracts and serializes the entire path overhead from the three STS-1 (AU3)
or single STS-3c (AU4) stream. Identifies the positions of the path overhead
bytes in the serialized streams.
·
Extracts the path signal label (C2) byte into an internal register and detects
for path signal label unstable and for signal label mismatch with the expected
signal label that is downloaded by the microprocessor.
·
Extracts the 64 byte or 16 byte path trace (J1) message into an internal
register bank.
·
Detects for unstable path trace message and mismatch with the expected
path trace message that is downloaded by the microprocessor.
·
Detects received path BIP-8 and counts received path BIP-8 errors for
performance monitoring purposes. Path BIP-8 errors are also available on an
output pin. BIP-8 errors are selectable to be treated on a bit basis or block
basis.
·
Counts received path far end block errors (FEBEs) for performance
monitoring purposes.
·
Extracts the three STS-1 (AU3) payloads or single STS-3c (AU4) payload and
presents it on a byte serial bus.
·
Supports Telecombus interfaces by indicating the location of the STS
identification byte (C1), the path trace byte(s) (J1), the first tributary overhead
byte(s) (V1), and all synchronous payload envelope bytes in the byte serial
stream. Also generates bus parity.
·
Accomodates phase and frequency differences between the receive stream
and the DROP bus via pointer adjustments in the DROP bus.
·
Supports tandem connection origination applications by sourcing a new
tandem path maintenance byte (Z5) reporting the received BIP-8 errors and
the data link message and correcting subsequent path BIP-8 bytes (B3) to
reflect the change in Z5.
·
Supports tandem connection termination applications by accumulating the
incoming error count (IEC) and extracting the tandem connection data link
carried in the tandem path maintenance byte (Z5).
PM5344 SPTX
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PMC-930531 ISSUE 6 SONET/SDH PATH TERMINATING TRANSCEIVER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
3
·
Maintains existing pointer value during incoming signal failures in tandem
path terminating mode.
·
Maintains the existing tributary multiframe sequence on the H4 byte until a
new phase alignment has been verified.
·
Provides a "Telecombus" line side receive interface when path termination is
done by an upstream device.
·
Provides a serial alarm port communication of FEBE and path FERF alarms
to the transmit stream in the returning direction.
1.2 The transmitter section:
·
Operates in STS-1 (AU3) or STS-3c (AU4) mode.
·
Accepts a byte serial multiplex of three STS-1 (AU3) streams or an STS-3c
(AU4) stream, extracts the synchronous payload envelope(s) and inserts the
synchronous payload envelope(s) with a generated pointer into the transmit
system, using pointer processing.
·
Supports system side "Telecombus" interfaces by accepting indications of the
location of the STS identification byte (C1), the path trace byte(s) (J1), the
first tributary overhead byte(s) (V1), and all synchronous payload envelope
bytes in the byte serial stream.
·
Provides line side "Telecombus" interface on the transmit stream indicating
the location of the STS identification byte (C1), the path trace byte(s) (J1), the
first tributary overhead byte(s) (V1), and all synchronous payload envelope
bytes.
·
Accomodates phase and frequency differences between the ADD bus and
the transmit stream via pointer adjustments in the transmit stream.
·
Optionally inserts STS path alarm indication signal (AIS).
·
Optionally inserts STS path FERF alarm.
·
Inserts the path overhead bytes in the three STS-1 (AU3) or single STS-3c
(AU4) stream. The path overhead bytes may be sourced from internal
registers or from bit serial path overhead input streams. Path overhead
insertion may also be disabled.
·
Optionally calculates and inserts path BIP-8 error detection codes.
PM5344 SPTX
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PMC-930531 ISSUE 6 SONET/SDH PATH TERMINATING TRANSCEIVER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
4
·
Optionally inserts the path FEBE count into the path status byte (G1) based
on BIP-8 errors detected in the receive path.
·
Inserts the path signal label (C2) byte from an internal register.
·
Inserts the 64 byte or 16 byte path trace (J1) message from an internal
register bank.
·
Errors may be inserted in the path BIP8 byte (B3) for diagnostic purposes.
·
Optionally inserts all-ones payload data for unequipped operations.
·
Optionally generates cyclical tributary multiframe pattern.
·
Supports in-band error reporting of BIP-8 and path alarms in the path status
byte (G1).
PM5344 SPTX
DATA SHEET
PMC-930531 ISSUE 6 SONET/SDH PATH TERMINATING TRANSCEIVER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
5
2
APPLICATIONS
·
SONET/SDH Add Drop Multiplexers
·
SONET/SDH Terminal Multiplexers
·
SONET/SDH Cross Connects
·
SONET/SDH Tandem Path Termination Equipment
·
SONET/SDH Test Equipment
PM5344 SPTX
DATA SHEET
PMC-930531 ISSUE 6 SONET/SDH PATH TERMINATING TRANSCEIVER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
6
3
REFERENCES
1. American National Standard for Telecommunications - Digital Hierarchy Optical Interface Rates and Formats Specification, ANSI T1.105-1988.
2. American National Standard for Telecommunications - Layer 1 In-Service
Digital Transmission Performance Monitoring, T1X1.3/93-005R1, April 1993.
3. Bell Communications Research - SONET Transport Systems: Common
Generic Criteria, TR-TSY-000253, Issue 2, December 1991.
4. CCITT Study Group XVIII - Report R 105, Geneva, 9 - 19 June 1992.
5. CCITT Recommendation G781M, 13 October, 1992.
6. ETSI DE/TM1015, "Generic Functional Requirement for SDH Transmission
Equipment", Version 0.4, February 1993.
7. CCITT Study Group XVII - Contribution D2166 - "Tandem Connection /
Tandem Connection Bundle Maintenance - Working Solution", June 1992.
PM5344 SPTX
DATA SHEET
PMC-930531 ISSUE 6 SONET/SDH PATH TERMINATING TRANSCEIVER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
7
4
APPLICATION EXAMPLES
The following two examples show the SPTX used in typical SONET/SDH network
equipment applications. In the first example, the SPTX is paired with the PM5343
STXC 155 Mbit/s Section and Line overhead terminating transceiver to provide a
complete 155 Mbit/s SONET STS-3 or STS-3c/SDH STM-1 interface. In the
second example, four SPTX chips are used in conjunction with the PM5312
STTX 622 Mbit/s Section and Line overhead terminating transceiver to provide a
complete 622 Mbit/s SONET STS-12/SDH STM-4 interface. In both cases
external clock recovery and synthesis is available from a number of commercial
sources (additional information is available from PMC).
Figure 1 - 155 Mbit/s STS-3/STM-1 Add-Drop or Terminal Mux Interface
RECEIVE
ALARM DETECT
SIGNALS
TRANSMIT
ALARM INSERT
SIGNALS
TRANSMIT
TRANSPORT
OVERHEAD
ACCESS
RSD+/-
O/E
E/O
RXD+/-
RXC+/-
TXD+/-
PM5343 STXC
155 Mbit/s
Transport O verhead
Transceiver
Clock/Data
Recover
y
TXCI+/-
Clock
Generation
MICRO BUS
FOR CONFIG,
STATUS
AND CONTROL
RECEIVE
ALARM DETECT
SIGNALS
TRANSMIT
ALARM INSERT
SIGNALS
TRANSMIT
PATH
OVERHEAD
ACCESS
PM5344 SPTX
Path
Termin a ting
Transceiver
GTICLK
TICLK
TIFP
TIN[7:0]
TCK
FPOUT
TD[7:0 ]
GRICLK
RICLK
ROFP
ROU T [7:0]
PICLK
IFP
RD[7 :0]
DCK
DC1J1V1
DD[7 :0]
DPL
DDP
Telecombus
Drop
Interface
ACK
AC1J1V1
AD[7:0]
APL
ADP
Telecombus
Add
Interface
RECEIVE
PATH
OVERHEAD
ACCESS
MICRO BUS
FOR CONFIG,
STATUS
AND CONTROL
RECEIVE
TRANSPORT
OVERHEAD
ACCESS
PM5344 SPTX
DATA SHEET
PMC-930531 ISSUE 6 SONET/SDH PATH TERMINATING TRANSCEIVER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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Figure 2 - 622 Mbit/s STS-12/STM-4 Add-Drop Multiplexer Aggregate
Interface
ADD-DROP
MUX
BACKPLANE
E/O
O/E
PM5318
SIPO
PM5312
STTX
Clock
S
y
nthesis
Clock
Recover
y
OOF
TOUT[7:0]
TCLK
RICLK
RIFP
RIN[7:0]
PM5344
SPTX
#1
#2
#3
#4
OPTICAL
FACILIT Y
STS-3(STM -1) To STS-12 (S TM-4) MUX
STS-3c (S TM-1)
Path T e rm in at io n
PM5344 SPTX
DATA SHEET
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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5
BLOCK DIAGRAM
PIC LK /RCK
IFP/RC 1J1V 1
PIN[7:0]/RD[7:0]
TCK
TD[7:0]
Tr ip le S T S - 1 (A U 3 ) /
Single STS-3c (AU4)
Receiv e Path Overhead
Process or
(3 x RPOP)
Tr ip le S T S - 1 (A U 3 ) /
Single STS-3c (AU4)
Path Tra ce B u ffer
(3 x SPTB)
Telecombu s
Interfac e
AD[7:0]
ADP
AC1J1V 1
APL
ACK
GC1J1V1
GPL
GFP
DD[7:0]
DDP
DC1J1V 1
DPL
DCK
LO
P
[3:
1
]
PA
IS
[3:
1
]
P
F
E
R
F
[3
:1
]
R
P
O
H
C
K
[3
:1
]
R
P
O
H
F
P
[3
:1
]
R
P
O
H
[3
:1
]
B
IP
E
[3
:1
]
R
T
C
E
N
[3
:1
]
R
T
C
O
H
[3
:1
]
Tr ip le T r a n s mi t
Telec o mbus
Aligner/Interface
(3 x TTA L)
D
F
P
GD[1:0]
LOM
[3
:1
]
Tr ip le Re c eiv e
Teleco mbus
A ligner/In terface
(3 x RTAL)
Microprocessor
Inter f a c e
C
S
B
R
D
B
W
R
B
AL
E
A[
8:
0]
D[7
:0
]
M
B
E
B
R
S
T
B
IN
T
B
GDP
TPAIS [3 :1 ]
TFP
RPL
RDP
FPO UT
TC1J1V1
TDP
TPL
R
A
D
T
P
O
H
E
N
[3
:1
]
T
P
O
H
[3
:1
]
T
P
O
H
F
P
[3
:1
]
T
P
O
H
C
K
[3
:1
]
T
A
F
P
TA
C
K
TA
D
GMFP
Tr ip le S T S - 1 (A U 3 ) /
Single STS-3c (A U4)
Transmit Path Overhead
Processor
(3 x TPOP)
DP
A
IS
[3
:1
]
PM5344 SPTX
DATA SHEET
PMC-930531 ISSUE 6 SONET/SDH PATH TERMINATING TRANSCEIVER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
10
6
DESCRIPTION
The PM5344 SPTX SONET/SDH Path Terminating Transceiver is a monolithic
integrated circuit that implements payload alignment and path termination for
three STS-1 (AU3) paths or a single STS-3c (AU4) path, mapping these payloads
onto a Telecombus-like system backplane.
The SPTX operates in conjunction with the PM5343 STXC SONET/SDH
Transport Terminating Transceiver to form a complete system for terminating
section, line, and path overhead of a SONET STS-3 (SDH STM-1) or SONET
STS-1 electrical interface. Four SPTX devices operate in conjunction with the
PM5712 SLIM SONET/SDH Line Interface Module to form a complete system for
terminating section, line, and path overhead of a SONET STS-12 (SDH STM-4)
electrical interface.
The SPTX provides receive path termination for a SONET STS-1, STS-3 or STS3c stream, or equivalently, an AU3 or an SDH STM-1 stream carrying three AU3s
or one AU4. The SPTX interprets the received payload pointers (H1, H2) and
extracts the synchronous payload envelope (virtual container). The extracted
SPE (VC) is placed on a Telecombus DROP bu s. Frequency offsets (e.g., due to
plesiochronous network boundaries, or the loss of a primary reference timing
source) and phase differences (due to normal network operation) between the
received data stream and the DROP bus are accommodated by pointer
adjustments in the DROP bus. In addition to its basic processing of the received
SONET/SDH overhead, the SPTX provides convenient access to all overhead
bytes, which are extracted and serialized on lower rate interfaces, allowing
additional external processing of overhead, if desired.
The SPTX provides transmit path origination for a SONET STS-1, STS-3 or STS3c stream, or equivalently, an AU3 or an SDH STM-1 stream carrying three AU3s
or one AU4. The SPTX generates the transmit payload pointers (H1, H2) and
inserts the synchronous payload envelope (virtual container) from a Telecombus
ADD bus into the transmit stream. Frequency offsets (e.g., due to
plesiochronous network boundaries, or the loss of a primary reference timing
source) and phase differences (due to normal network operation) between the
transmit data stream and the ADD bus are accommodated by pointer
adjustments in the transmit stream. In addition to its basic processing of the
transmit SONET/SDH overhead, the SPTX provides convenient access to all
overhead bytes, which are inserted serially on lower rate interfaces, allowing
additional external sourcing of overhead, if desired. The SPTX also supports the
insertion of a large variety of errors into the transmit stream, such as bit
interleaved parity errors, and inverted NDF flags, which are useful for system
PM5344 SPTX
DATA SHEET
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
11
diagnostics and tester applications.The SPTX supports in-band error reporting
where the path status byte (G1) inserted in the DROP bus reflects the number of
BIP-8 errors detected and the path FERF status. The SPTX can be
programmed to pass the path status byte on the ADD bus through unmodified.
This feature allows the transmit path processor to be located remotely to the
receive processor without having to incur the cost of routing an alarm port.
The SPTX supports tandem connection termination applications where the
tandem connection maintenance byte (Z5) carries the incoming BIP-8 error
count, a tandem data link, and a path AIS code. The incoming error count is
accumulated and the receive data link is serialized for external processing. A
new data link can be inserted from a low speed serial input. An incoming signal
failure alarm (ISF) is used to convey path AIS in place of all-ones in the pointer
(H1, H2).
The SPTX maintains a large number of statistics for performance monitoring
purposes. BIP-8 errors, and tandem path incoming error counts are
accumulated. In addition, the SPTX is selectable to accumulate positive and
negative pointer justifications that it receives or justifications that it generates on
the DROP bus. It also accumulates positive and negative pointer justifications in
the transmit stream. Excessive justifications may be indicative of clock
synchronization failures.
In STS-3c, STS-3 (AU4, three AU3s) applications, no auxiliary high speed clocks
are required as the SPTX operates from a set of plesiochronous 19.44 MHz
clocks. In STS-1 (single AU3) applications, the SPTX operates from a set of
plesiochronous 6.48 MHz clocks. The SPTX is configured, controlled and
monitored via a generic 8-bit microprocessor bus interface.
The SPTX is implemented in low power, +5 Volt, CMOS technology. It has TTL
compatible inputs and outputs and is packaged in a 160 pin PQFP package.
PM5344 SPTX
DATA SHEET
PMC-930531 ISSUE 6 SONET/SDH PATH TERMINATING TRANSCEIVER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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7
PIN DIAGRAM
The SPTX is packaged in an 160 pin PQFP package having a body size of
28 mm by 28 mm and a pin pitch of 0.65 mm.
PIN 1
PIN 160
TOP
VIEW
PIN 40
PIN 41 PIN 80
PIN 81
PIN 120
PIN 121
TPAIS [3]
TDP
TPL
TC1J1V1
VDDO
VSSO
TD [0]
TD [1]
TD [2]
TD [3]
TD [4]
VDDO
TD[5]
VSSO
TD [6]
TD [7]
TFP
FPOUT
TCK
VDDI
VSSI
PICLK/RCK
IFP/RC1J1V1
PIN [0 ]/R D [0]
PIN [1 ]/R D [1]
PIN [2 ]/R D [2]
PIN [3 ]/R D [3]
PIN [4 ]/R D [4]
PIN [5 ]/R D [5]
PIN [6 ]/R D [6]
PIN [7 ]/R D [7]
RPL
RDP
MBEB
ALE
A [0]
A [1]
A [2]
A [3]
A [4]
A [5]
A [6]
A [7]
A [8]/TRS
RSTB
CSB
D [0]
D [1]
D [2]
VSSO
VDDO
D [3]
D [4]
D [5]
D [6]
D [7]
INTB
RDB/E
WRB/R
WB
VDDI
VSSI
VDDO
VSSO
LOP [1]
LOP [2]
LOP [3]
PAIS [1]
PAIS [2]
PAIS [3]
PFERF [1]
PFERF [2]
PFERF [3]
LOM [1]
VDDO
VSSO
LOM [2]
LOM [3]
BIPE [1]
BIPE [2]
BIPE [3]
APL
AC1J1V1
AD [0 ]
AD [1 ]
AD [2 ]
AD [3 ]
AD [4 ]
AD [5 ]
AD [6 ]
AD [7 ]
ACK
GFP
GMFP
GD [O]
GD [1 ]
GC1J1V1
GPL
VDDO
VSSO
VDDI
VSSI
GDP
DCK
DFP
DD [0]
DD [1]
DD [2]
DD [3]
DD [4]
DD [5]
DD [6]
VDDO
VSSO
DD [7]
DC1J1V1
DPL
DDP
DP A IS [1 ]
DP A IS [2 ]
DP A IS [3 ]
TP O HEN [3 ]
TP O HEN [2 ]
TP O HEN [1 ]
TP O H [2]
TP O H [1]
ADP
TPOHFP [2]
TPOHFP [1]
TP O H [3]
VSSO
TPOHCK [1]
TPOHFP [3]
TPOHCK [3]
TPOHCK [2]
VDDO
TAD
TAFP
TACK
VDDI
VSSI
RAD
RTCEN [3]
RTCEN [2]
RTCEN [1]
RTCOH [3]
RTCOH [2]
RTCOH [1]
RP O H [3]
RP O H [2]
RP O H [1]
VSSO
RP O HFP [2 ]
RP O HFP [1 ]
RPOHCK [1]
RP O HFP [3 ]
VDDO
TPAIS [
2]
TPAIS [
1]
RPOHCK [3]
RPOHCK [2]
PM5344
SPTX
Index
PM5344 SPTX
DATA SHEET
PMC-930531 ISSUE 6 SONET/SDH PATH TERMINATING TRANSCEIVER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
13
8
PIN DESCRIPTION
Table 1 - Pin Description
Pin Name Type Pin
No.
Function
PICLK / Input 22 The parallel input clock (PICLK) provides timing for sampling t he receive
SONET/SDH stream, P I N[7:0] when external path term i nation is disabled. PICLK
is nominally a 19.44 MHz or 6.48 MHz, 50% duty cycle clock. Inputs PIN[7:0] and
IFP are sampled on the ris i ng edge of PICLK. Inputs RPL and RDP are ignored.
Outputs LOP[3:1], PAIS[3:1], and PFERF[3:1] are updated on the rising edge of
PICLK.
RCK The RECEIVE bus clock (RCK) provides t i m i ng for the RE CEIVE bus interface
when external path termi nation is enabled. RCK is nominally a 19.44 MHz or 6.48
MHz, 50% duty cycle clock. Outputs LOP[3:1], LOM[3:1], PAIS[3:1], PFERF[3:1],
BIPE[3:1], RAD, RPOH[3:1], RPOHFP[3:1], are RPOHCLK[3:1] are inactive.
Inputs RTCEN[3:1] and RTCOH[3:1] are ignored. Inputs RD[7:0], RC1J1V1, RPL,
and RDP are sampled on the rising edge of RCK.
PIN[7]
PIN[6]
PIN[5]
PIN[4]
PIN[3]
PIN[2]
PIN[1]
PIN[0] /
Input 31
30
29
28
27
26
25
24
The parallel receive data bus (PIN[7:0]) carries t he SONET/SDH frame in byte
serial format when external path termination is dis abled. PIN[7] is the most
significant bit (c orresponding to bit 1 of each serial word, the f i rst bit transmitted).
PIN[0] is the least significant bit (corres pondi ng t o bi t 8 of each serial word, the last
bit transmitted). PIN[7:0] is sampled on t he rising edge of PICLK.
RD[7]
RD[6]
RD[5]
RD[4]
RD[3]
RD[2]
RD[1]
RD[0]
The RECEIVE bus data (RD[7:0]) carries the SONET/SDH frame in byte serial
format when external path termination is enabled. RD[7] is the most significant bi t
(corresponding to bit 1 of each s erial word, the first bit transmit t ed). RD[0] is the
least significant bi t (corresponding to bit 8 of each seri al word, the l ast bit
transmitted). RD[7:0] is sampled on the risi ng edge of RCK.
PM5344 SPTX
DATA SHEET
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
14
Pin Name Type Pin
No.
Function
IFP / Input 23 The active high framing posit i on signal (IFP) indicates when the fi rst byte of the
synchronous payload envelope (SPE byte 1 of STS-1 #1) is available on the
PIN[7:0] bus when external path termination is disabled. Note that IFP has a fixed
relationship to the SONET/SDH frame; the start of the SPE is determined by the
STS (AU) pointer and may change relative to IFP. IFP is sampled on the rising
edge of PICLK.
RC1J1V1 The receive composite timing si gnal (RC1J1V1) indicates the frame, payload and
tributary multiframe boundaries on the RECEIVE bus when external path
termination is enabled. RC1J1V1 pulses high with the RECEIVE bus payload
active signal (RPL) set low to mark the first STS-1 identif i cation byte or equivalently
the STM identificat i on byte. RC1J1V1 pulses high with RPL set high to mark the
path trace byte (J1). Optionally, the RC1J 1V 1 signal pulses high with RPL set hi gh
on the V1 byte to indicate tributary multiframe boundaries. RC1J1V1 is sampled on
the rising edge of RCK.
RPL Input 32 The RECEIVE bus payload active signal (RPL) indicates when RD[7:0] is carrying
a payload byte. I t is set high during path overhead and payload bytes and low
during transport overhead bytes. RPL is set high during the H3 byte to indicat e a
negative pointer justificati on event and set low during t he byte following H3 to
indicate a positive pointer just i fication event. RPL is ignored when external path
termination is di sabled. RPL is sampled on the rising edge of RCK .
RDP Input 33 The RECEIVE bus data parity signal (RDP) indicates the parity of the RECEI VE
bus signals. The RECEI VE data bus (RD[7:0]) is always included in parity
calculations. Internal register bits controls the inclusion of t he RPL and RC1J1V1
signals in parity calculations and the sense (odd/even) of the parity. RDP is
ignored when external path term i nation is disabled. RDP is sampled on the rising
edge of RCK.
RPOHCK[3]
RPOHCK[2]
RPOHCK[1]
Output 158
157
156
The receive path overhead clocks (RPOHCK[3:1]) provide timing t o process the
BIPE[3:1] signal s, to insert tandem pat h i ncoming error count and data link, and to
sample the extracted path overhead for the corresponding STS-1 (AU3) stream.
RPOHCK[3:1] are nominally 576 kHz clocks. In STS-3c (AU4) mode or STS-1
mode, only RPOHCK[1] is active. RTCEN[3:1], and RTCOH[3:1] are sampled on
the rising edge of the corres pondi ng RPOHCK signal. BIPE[3:1], RPOH[3:1] and
RPOHFP[3:1] are updated on the falling edge of the corres ponding RPOHCK
signal.
RPOHCK[1] provides timing for the serial receive alarm indication port (RAD),
which is updated on the falling edge of RPOHCK[1].
RPOHCK[3:1] are inactive when external path termination is enabled.
PM5344 SPTX
DATA SHEET
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Pin Name Type Pin
No.
Function
RPOH[3]
RPOH[2]
RPOH[1]
Output 150
149
148
The receive path overhead data signals (RPOH[3:1]) contai n the path overhead
bytes (J1, B3, C2, G1, F2, H4, Z3, Z4, and Z5) extracted from the path overhead of
the corresponding STS-1 (AU3) stream. In STS-3c (AU4) mode or STS-1 mode,
only RPOH[1] is active. Each RPOH signal is updated on the falling edge of the
corresponding RPOHCK signal.
RPOH[3:1] are inactive when external pat h termination is enabled.
RPOHFP[3]
RPOHFP[2]
RPOHFP[1]
Output 155
152
151
The receive path overhead frame position signals (RPOHFP[3:1]) may be used to
locate the individual path overhead bits in the path overhead data stream for the
corresponding STS-1 (AU3) stream. Each RPOHFP[3:1] signal is logic 1 when bit
1 (the most signific ant bit) of the path trace byte (J1) is present in the
corresponding RPOH stream. In STS-3c (AU4) mode or STS-1 mode, only
RPOHFP[1] is active. Each RPOHFP signal is updated on the falling edge of the
corresponding RPOHCK signal.
RPOHFP[1] may be used to located the BIP error count and path FERF indicati on
bits on the receive alarm port data signal (RAD). RPOHFP[1] is logic 1 when t he
first of eight BIP error positions from the first S T S-1 (AU3) or the STS-3c (AU4)
stream is present on the rec ei ve alarm data signal (RAD).
RPOHFP[3:1] are inactive when external path termination is enabled.
RTCEN[3]
RTCEN[2]
RTCEN[1]
Input 144
143
142
The receive tandem connection overhead insert enable signals (RTCEN[3:1])
control the insertion of incoming error count and data l i nk i n the tandem connection
maintenance byte (Z5), on a bit-by-bit basis. When RTCEN is set high, the data on
the corresponding RTCOH stream is inserted into the associ ated bit in the Z5 byte.
RTCEN has significance only dur i ng t he the J1 byte positions in the RPOHCK
clock sequence and is ignored at all ot her t i mes. In STS-3c (AU4) mode or STS-1
mode, only RTCEN[1] is signific ant. RTCE N i s sampled on the rising edge of the
corresponding RPOHCK signal.
RTCEN[3:1] are ignored when external path termination is enabled.
RTCOH[3]
RTCOH[2]
RTCOH[1]
Input 147
146
145
The receive tandem connection overhead data signals (RTCOH[3:1]) contai n the
incoming error count and data link m essage to be inserted i nto the tandem
connection maintenance byte (Z5). When RTCEN is set high, the values sampled
on RTCOH is inserted into t he Z5 byte. When RTCEN is set low, t he I EC field of
Z5 reports the incoming path BIP error count and the data li nk field is set to all
ones. In STS-3c (AU4) mode or STS-1 mode, only RTCEN[1] is significant.
RTCOH is sampled on the rising edge of the corresponding RPOHCK signal.
RTCOH[3:1] are ignored when external path termination is enabled.
PM5344 SPTX
DATA SHEET
PMC-930531 ISSUE 6 SONET/SDH PATH TERMINATING TRANSCEIVER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
16
Pin Name Type Pin
No.
Function
BIPE[3]
BIPE[2]
BIPE[1]
Output 80
79
78
The bit interleaved parity error signals (B IPE[3:1]) signal is s et hi gh for one
RPOHCK period for each path BIP-8 error detec t ed (up to eight per frame) or once
if any of the BIP-8 bits are i n error dependi ng on whet her BIP-8 errors are treated
on a bit or block basis. Pat h BIP-8 errors are detected by comparing the extracted
path BIP-8 byte (B3) with the comput ed BIP-8 for the previous frame. In STS-3c
(AU4) mode or STS-1 mode, only BIP[1] is acti ve. BIPE[3:1] is updated on t he
falling edge of RPOHCK.
BIPE[3:1] are inactive when external path termination i s enabled.
RAD Output 139 The receive alarm port data signal (RAD) contains the pat h B IP error count and the
path FERF status of the t hree receive STS-1 (AU3) streams or the single STS-3c
(AU4) stream. RAD is updated on the falling edge of RPOHCK[1].
RAD is inactive when external path t ermination is enabled.
LOP[3]
LOP[2]
LOP[1]
Output 66
65
64
The loss of pointer signals (LOP [3:1]) indicate the loss of poi nter state in the
associated SONET/S DH stream. LOP is set high when invalid STS pointers are
received in eight consecutive frames, or if eight consecutive enabled NDFs are
detected in the corresponding ST S-1 (AU3) stream. The loss of pointer s t ate is
exited (LOP set low) when the same valid STS pointer, with disabled NDF, is
detected for three consecutive frames. In STS-3c (AU4) mode, only LOP[1] is
active and loss of pointer state (LOP[1]) depends only on the first of three H1, H2
bytes; the value of the concatenation indicators do not affect LOP[1] signal. In
STS-1 mode, only LOP[1] is active. LOP[3:1] are updated on the ris i ng edge of
PICLK.
LOP[3:1] are inactive when external pat h termination is enabled.
PAIS[3]
PAIS[2]
PAIS[1]
Output 69
68
67
The path alarm indicati on signals (PAI S[3:1]) indicate the STS path AIS state
associated with the SO NE T/SDH stream. PAIS is set hi gh when an al l ones
pattern is observed in the STS-1 pointer bytes (H1, and H2) for three consecuti ve
frames in the corresponding STS-1 (AU3) stream. Path AIS is removed when the
same valid pointer with normal NDF i s detected for three consecutive frames or a
single valid pointer with NDF set is received. In STS-3c (AU4) mode, only PAI S[1]
is active and depends only on the firs t of three H1, H2 bytes; the value of the
concatenation indicators do not affect PAIS[1]. In STS-1 mode, only PAIS[ 1] is
active. PAI S[3:1] are updated on the rising edge of P ICLK.
PAIS[3:1] are inactive when external path termination is enabled.
PFERF[3]
PFERF[2]
PFERF[1]
Output 72
71
70
The path far end receive failure signals (PFERF[3:1]) indicate the STS path FERF
state associated wi t h the SONET/SDH stream. PFERF is set high when the path
FERF alarm bit (bit 5) of the STS path status (G1) byte is set high for five
consecutive frames. STS path FERF is removed when bit 5 of the G1 byte is set
low for five consecutive frames. In STS-3c (AU4) mode and STS-1 mode, only
PFERF[1] is active. PFERF[3:1] are updated on the ris i ng edge of PICLK.
PFERF[3:1] are inactive when exter nal pat h termination is enabled.
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