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PM5342-BI
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PMC PM5342-BI Datasheet

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PM5342 SPECTRA-155
DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
PM5342
SPECTRA-155
SONET/SDH PAYLOAD
EXTRACTOR/ALIGNER
PROPRIET A R Y A ND CONFIDENTIAL
ISSUE 4: AUGUST 1998
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
PM5342 SPECTRA-155
DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER

CONTENTS

1 FEATURES ..........................................................................................1
2 APPLICATIONS ...................................................................................6
3 REFERENCES.....................................................................................6
4 APPLICATION EXAMPLE....................................................................8
5 BLOCK DIAGRAM .............................................................................13
6 DESCRIPTION ..................................................................................17
7 PIN DIAGRAMS.................................................................................19
8 PIN DESCRIPTION (256) ..................................................................27
9 FUNCTIONAL DESCRIPTION.........................................................108
10 REGISTER DESCRIPTION .............................................................144
11 TEST FEATURES DESCRIPTION ..................................................410
12 OPERATION ....................................................................................425
13 FUNCTIONAL TIMING.....................................................................441
14 ABSOLUTE MAXIMUM RATINGS...................................................486
15 D.C. CHARACTERISTICS ...............................................................487
16 MICROPROCESSOR INTERFACE TIMING
CHARACTERISTICS .......................................................................492
17 SPECTRA-155 TIMING CHARACTERISTICS.................................500
18 ORDERING AND THERMAL INFORMATION..................................533
19 MECHANICAL INFORMATION ........................................................534
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE i
PM5342 SPECTRA-155
DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER

LIST OF REGISTERS

REGISTER ADDRESS 00H: SPECTRA-155 CONFIGURATION ...............153
REGISTER ADDRESS 01H: SPECTRA-155 SECTION/LINE
CONTROL/ENABLE ........................................................................155
REGISTER ADDRESS 02H: SPECTRA-155 SECTION/LINE
INTERRUPT STATUS......................................................................157
REGISTER ADDRESS 03H: SPECTRA-155 RESET, IDENTITY,
ACCUMULATION TRIGGER ...........................................................159
REGISTER ADDRESS 04H: TLOP CONTROL..........................................161
REGISTER ADDRESS 05H: TLOP DIAGNOSTIC .....................................162
REGISTER ADDRESS 06H: TLOP TRANSMIT K1....................................163
REGISTER ADDRESS 07H: TLOP TRANSMIT K2....................................164
REGISTER ADDRESS 08H: RLOP CONTROL/STATUS...........................165
REGISTER ADDRESS 09H: RLOP INTERRUPT ENABLE AND
STATUS ...........................................................................................168
REGISTER ADDRESS 0AH: RLOP B2 ERROR COUNT #1......................170
REGISTER ADDRESS 0DH: RLOP REI ERROR COUNT #1....................171
REGISTER ADDRESS 10H: RSOP CONTROL .........................................172
REGISTER ADDRESS 11H: RSOP INTERRUPT STATUS........................174
REGISTER ADDRESS 12H: RSOP B1 ERROR COUNT #1......................176
REGISTER ADDRESS 14H: SPECTRA-155 OUTPUT PORT...................177
REGISTER ADDRESS 15H: SPECTRA-155 INPUT PORT
INTERRUPT ENABLE .....................................................................178
REGISTER ADDRESS 17H: SPECTRA-155 RING CONTROL .................179
REGISTER 18H: TSOP CONTROL............................................................181
REGISTER 19H: TSOP DIAGNOSTIC.......................................................182
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DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
REGISTER 1AH: SPECTRA-155 TRANSMIT Z1/S1..................................183
REGISTER 1BH: TSOP TRANSMIT Z0 .....................................................184
REGISTER 1CH: SPECTRA-155 OVERHEAD UNUSED BYTES
CONTROL .......................................................................................185
REGISTER ADDRESS 1DH: SPECTRA-155 RECEIVE LINE AIS
CONTROL .......................................................................................187
REGISTER ADDRESS 1EH: SPECTRA-155 LINE RDI CONTROL...........189
REGISTER ADDRESS 1FH: SPECTRA-155 INPUT PORT
STATUS/VALUE...............................................................................191
REGISTER 20H: RASE INTERRUPT ENABLE .........................................193
REGISTER 21H: RASE INTERRUPT STATUS ..........................................194
REGISTER 22H: RASE CONFIGURATION/CONTROL.............................196
REGISTER 23H: RASE SF ACCUMULATION PERIOD.............................198
REGISTER 26H: RASE SF SATURATION THRESHOLD..........................199
REGISTER 28H: RASE SF DECLARING THRESHOLD............................200
REGISTER 2AH: RASE SF CLEARING THRESHOLD..............................201
REGISTER 2CH: RASE SD ACCUMULATION PERIOD............................202
REGISTER 2FH: RASE SD SATURATION THRESHOLD .........................203
REGISTER 31H: RASE SD DECLARING THRESHOLD ...........................204
REGISTER 33H: RASE SD CLEARING THRESHOLD..............................205
REGISTER ADDRESS 35H: RASE RECEIVE K1......................................206
REGISTER ADDRESS 36H: RASE RECEIVE K2......................................207
REGISTER 37H: RASE RECEIVE Z1/S1...................................................208
REGISTER 38H: SSTB SECTION TRACE CONTROL..............................209
REGISTER 39H: SSTB SECTION TRACE STATUS..................................211
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DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
REGISTER 3AH: SSTB SECTION TRACE INDIRECT ADDRESS ............213
REGISTER 3BH: SSTB SECTION TRACE INDIRECT DATA ....................214
REGISTER 40H: CRSI CLOCK RECOVERY CONTROL, STATUS
AND INTERRUPT ............................................................................215
REGISTER 41H: CRSI PHASE LOCK LOOP MODE SELECT..................217
REGISTER 42H: CSPI CLOCK SYNTHESIS CONTROL, STATUS
AND INTERRUPT ............................................................................218
REGISTER 78H: SPECTRA-155 PRS GENERATOR CONTROL .............220
REGISTER 79H: SPECTRA-155 PRS MONITOR DROP
CONTROL .......................................................................................222
REGISTER 7AH: SPECTRA-155 PRS MONITOR ADD CONTROL ..........224
REGISTER 7BH: SPECTRA-155 PRS MONITOR INTERRUPT
STATUS ...........................................................................................226
REGISTER 7CH: SPECTRA-155 PRS MONITOR DROP COUNT............227
REGISTER 7EH: SPECTRA-155 PRS MONITOR ADD COUNT ...............228
REGISTER 80H: SPECTRA-155 CLOCK CONTROL................................229
REGISTER 81H: SPECTRA-155 RECEIVE OVERHEAD OUTPUT
CONTROL .......................................................................................231
REGISTER 82H: SPECTRA-155 TRANSMIT OVERHEAD INPUT
CONTROL .......................................................................................233
REGISTER 83H: SPECTRA-155 SECTION ALARM OUTPUT
CONTROL .......................................................................................235
REGISTER 84H: SPECTRA-155 RALM[1] OUTPUT CONTROL...............236
REGISTER 85H: SPECTRA-155 RALM[2] OUTPUT CONTROL ..............237
REGISTER 86H: SPECTRA-155 RALM[3] OUTPUT CONTROL ..............238
REGISTER 87H: SPECTRA-155 DATA MODE CONFIGURATION ...........239
REGISTER 88H: SPECTRA-155 PATH AND DS3 RECEIVE AIS
CONTROL #1...................................................................................241
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DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
REGISTER 89H: SPECTRA-155 PATH AND DS3 RECEIVE AIS
CONTROL #2...................................................................................243
REGISTER 8AH: SPECTRA-155 PATH AND DS3 RECEIVE AIS
CONTROL #3...................................................................................245
REGISTER 90H, 98H, A0H: D3MD CONTROL..........................................247
REGISTER 91H, 99H, A1H: D3MD INTERRUPT STATUS ........................248
REGISTER 92H, 9AH, A2H: D3MD INTERRUPT ENABLE .......................249
REGISTER 94H, 9CH, A4H: D3MA CONTROL..........................................250
REGISTER 95H, 9DH, A5H: D3MA INTERRUPT STATUS ........................251
REGISTER 96H, 9EH, A6H: D3MA INTERRUPT ENABLE........................252
REGISTER B0H, C0H, D0H: TPIP STATUS AND CONTROL
(EXTD=0).........................................................................................253
REGISTER B0H, C0H, D0H: TPIP STATUS AND CONTROL
(EXTD=1).........................................................................................255
REGISTER B1H, C1H, D1H: TPIP ALARM INTERRUPT STATUS
(EXTD=0).........................................................................................256
REGISTER B2H, C2H, D2H: TPIP POINTER INTERRUPT
STATUS ...........................................................................................257
REGISTER B3H, C3H, D3H: TPIP ALARM INTERRUPT ENABLE
(EXTD=0).........................................................................................259
REGISTER B3H, C3H, D3H: TPIP ALARM INTERRUPT ENABLE
(EXTD=1).........................................................................................261
REGISTER B4H, C4H, D4H: TPIP POINTER INTERRUPT
ENABLE...........................................................................................262
REGISTER B5H, C5H, D5H: TPIP POINTER LSB.....................................264
REGISTER B6H, C6H, D6H: TPIP POINTER MSB....................................265
REGISTER B8H, C8H, D8H: TPIP PATH BIP-8 LSB .................................267
REGISTER BCH, CCH, DCH: TPIP TRIBUTARY MULTIFRAME
STATUS AND CONTROL ................................................................268
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DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
REGISTER BDH, CDH, DDH: TPIP BIP CONTROL ..................................270
REGISTER E0H: SPECTRA-155 CLOCK SYNTHESIS SOURCE
SELECT ...........................................................................................272
REGISTER E1H: SPECTRA-155 CLOCK RECOVERY SOURCE
SELECT ...........................................................................................273
REGISTER E3H: SPECTRA-155 TRANSMIT PATH AIS CONTROL
#1 .....................................................................................................274
REGISTER E4H: SPECTRA-155 TRANSMIT PATH AIS CONTROL
#2 .....................................................................................................276
REGISTER E5H: SPECTRA-155 TRANSMIT PATH AIS CONTROL
#3 / AUXILIARY SIGNAL INTERRUPT STATUS..............................278
REGISTER E6H: SPECTRA-155 AUXILIARY SECTION/LINE
INTERRUPT STATUS......................................................................280
REGISTER E7H: SPECTRA-155 AUXILIARY PATH INTERRUPT
STATUS #1 ......................................................................................282
REGISTER E8H: SPECTRA-155 AUXILIARY PATH INTERRUPT
STATUS #2 ......................................................................................284
REGISTER E9H: SPECTRA-155 AUXILIARY PATH INTERRUPT
STATUS #3 ......................................................................................286
REGISTER EAH: SPECTRA-155 AUXILIARY PATH ENHANCED
INTERRUPT STATUS......................................................................288
REGISTER EBH: SPECTRA-155 TRACE MESSAGE MODE 2
INTERRUPT STATUS......................................................................289
REGISTER ECH: SPECTRA-155 TRACE MESSAGE MODE 2
STATUS ...........................................................................................291
REGISTER EDH: SPECTRA-155 AUTO TRACE MESSAGE MODE
1/2 CONTROL .................................................................................292
REGISTER EFH: SPECTRA-155 RECEIVE CONCAT PATH AIS,
RDI AND ENHANCED RDI CONTROL #1......................................294
REGISTER F0H: SPECTRA-155 RECEIVE PATH AIS CONTROL
#2 .....................................................................................................296
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DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
REGISTER F1H: SPECTRA-155 RECEIVE PATH AIS CONTROL
#3 .....................................................................................................299
REGISTER F2H: SPECTRA-155 PATH REI/RDI CONTROL #2................302
REGISTER F3H: SPECTRA-155 PATH REI/RDI CONTROL #3................304
REGISTER F4H: SPECTRA-155 ENHANCED PATH RDI
CONTROL #1...................................................................................306
REGISTER F5H: SPECTRA-155 ENHANCED PATH RDI
CONTROL #2...................................................................................309
REGISTER F6H: SPECTRA-155 ENHANCED PATH RDI
CONTROL #3...................................................................................312
REGISTER F7H: SPECTRA-155 AUXILIARY SECTION/LINE
INTERRUPT ENABLE .....................................................................315
REGISTER F8H: SPECTRA-155 AUXILIARY PATH INTERRUPT
ENABLE #1......................................................................................316
REGISTER F9H: SPECTRA-155 AUXILIARY PATH INTERRUPT
ENABLE #2......................................................................................317
REGISTER FAH: SPECTRA-155 AUXILIARY PATH INTERRUPT
ENABLE #3......................................................................................318
REGISTER FBH: SPECTRA-155 AUXILIARY PATH ENHANCED
INTERRUPT ENABLE .....................................................................319
REGISTER FCH: SPECTRA-155 AUXILIARY PATH STATUS #1..............320
REGISTER FDH: SPECTRA-155 AUXILIARY PATH STATUS #2..............321
REGISTER FEH: SPECTRA-155 AUXILIARY PATH STATUS #3 ..............322
REGISTER 100H: SPECTRA-155 PATH/MAPPER
CONFIGURATION ...........................................................................323
REGISTER 101H: SPECTRA-155 RECEIVE PATH AIS CONTROL
#1 .....................................................................................................325
REGISTER 102H: SPECTRA-155 PATH REI/RDI CONTROL #1 ..............328
REGISTER 103H: SPECTRA-155 PATH/MAPPER INTERRUPT
STATUS ...........................................................................................330
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DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
REGISTER 104H: SPECTRA-155 PATH INTERRUPT STATUS #1 ..........331
REGISTER 105H: SPECTRA-155 PATH INTERRUPT STATUS #2 ..........332
REGISTER 106H: SPECTRA-155 PATH TRANSMIT CONTROL..............333
REGISTER 107H: SPECTRA-155 PATH LOOPBACK, ADD BUS
CONTROL .......................................................................................334
REGISTER 108H: SPECTRA-155 SIGNAL ACTIVITY MONITOR.............335
REGISTER 109H: SPECTRA-155 PARITY CONFIGURATION .................337
REGISTER 110H, 150H, 190H: RPOP STATUS AND CONTROL
(EXTD=0).........................................................................................339
REGISTER 110H, 150H, 190H: RPOP STATUS AND CONTROL
(EXTD=1).........................................................................................341
REGISTER 111H, 151H, 191H: RPOP ALARM INTERRUPT
STATUS (EXTD=0) .........................................................................343
REGISTER 111H, 151H, 191H: RPOP ALARM INTERRUPT
STATUS (EXTD=1) .........................................................................344
REGISTER 112H, 152H, 192H: RPOP POINTER INTERRUPT
STATUS ...........................................................................................345
REGISTER 113H, 153H, 193H: RPOP ALARM INTERRUPT
ENABLE (EXTD=0)..........................................................................347
REGISTER 113H, 153H, 193H: RPOP ALARM INTERRUPT
ENABLE (EXTD=1)..........................................................................349
REGISTER 114H, 154H, 194H: RPOP POINTER INTERRUPT
ENABLE...........................................................................................350
REGISTER 115H, 155H, 195H: RPOP POINTER LSB..............................352
REGISTER 116H, 156H, 196H: RPOP POINTER MSB .............................353
REGISTER 117H, 157H, 197H: RPOP PATH SIGNAL LABEL...................355
REGISTER 118H, 158H, 198H: RPOP PATH BIP-8 LSB...........................356
REGISTER 11AH, 15AH, 19AH: RPOP PATH REI LSB.............................357
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PM5342 SPECTRA-155
DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
REGISTER 11CH, 15CH, 19CH: RPOP TRIBUTARY MULTIFRAME
STATUS AND CONTROL ................................................................358
REGISTER 11DH, 15DH, 19DH: RPOP TANDEM CONNECTION
AND RING CONTROL .....................................................................360
REGISTER 11EH, 15EH, 19EH: RPOP TANDEM CONNECTION
IEC COUNT LSB..............................................................................363
REGISTER 124H, 164H, 1A4H: PMON RECEIVE POSITIVE
POINTER JUSTIFICATION COUNT................................................364
REGISTER 125H, 165H, 1A5H: PMON RECEIVE NEGATIVE
POINTER JUSTIFICATION COUNT................................................365
REGISTER 126H, 166H, 1A6H: PMON TRANSMIT POSITIVE
POINTER JUSTIFICATION COUNT................................................366
REGISTER 127H, 167H, 1A7H: PMON TRANSMIT NEGATIVE
POINTER JUSTIFICATION COUNT................................................367
REGISTER 128H, 168H, 1A8H: RTAL CONTROL .....................................368
REGISTER 129H, 169H, 1A9H: RTAL INTERRUPT STATUS AND
CONTROL .......................................................................................370
REGISTER 12AH, 16AH, 1AAH: RTAL ALARM AND DIAGNOSTIC
CONTROL .......................................................................................373
REGISTER 130H, 170H, 1B0H: TPOP CONTROL ....................................375
REGISTER 131H, 171H, 1B1H: TPOP GENERATED BUS
CONTROL .......................................................................................377
REGISTER 133H, 173H, 1B3H: TPOP CURRENT POINTER LSB ...........380
REGISTER 135H, 175H, 1B5H: TPOP PAYLOAD POINTER LSB ............381
REGISTER 137H, 177H, 1B7H: TPOP PATH TRACE ...............................383
REGISTER 138H, 178H, 1B8H: TPOP PATH SIGNAL LABEL ..................384
REGISTER 139H, 179H, 1B9H: TPOP PATH STATUS..............................385
REGISTER 13AH, 17AH, 1BAH: TPOP PATH USER CHANNEL ..............388
REGISTER 13BH, 17BH, 1BBH: TPOP PATH GROWTH #1 .....................389
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DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
REGISTER 13CH, 17CH, 1BCH: TPOP PATH GROWTH #2 ....................390
REGISTER 13DH, 17DH, 1BDH: TPOP TANDEM CONNECTION
MAINTENANCE...............................................................................391
REGISTER 13EH: TPOP CONCATENATION LSB ....................................392
REGISTER 140H, 180H, 1C0H: TTAL CONTROL .....................................394
REGISTER 141H, 181H, 1C1H: TTAL INTERRUPT STATUS AND
CONTROL .......................................................................................396
REGISTER 142H, 182H, 1C2H: TTAL ALARM AND DIAGNOSTIC
CONTROL .......................................................................................399
REGISTER 148H, 188H, 1C8H: SPTB CONTROL ....................................401
REGISTER 149H, 189H, 1C9H: SPTB PATH TRACE IDENTIFIER
STATUS ...........................................................................................403
REGISTER 14AH, 18AH, 1CAH: SPTB INDIRECT ADDRESS
REGISTER.......................................................................................405
REGISTER 14BH, 18BH, 1CBH: SPTB INDIRECT DATA
REGISTER.......................................................................................406
REGISTER 14CH, 18CH, 1CCH: SPTB EXPECTED PATH SIGNAL
LABEL..............................................................................................407
REGISTER 14DH, 18DH, 1CDH: SPTB PATH SIGNAL LABEL
STATUS ...........................................................................................408
REGISTER ADDRESS 200H: SPECTRA-155 MASTER TEST..................413
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE x
PM5342 SPECTRA-155
DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER

LIST OF FIGURES

FIGURE 1 - STS-3 (STM-1/AU3), STS-3C (STM-1/AU4)
APPLICATION .........................................................................8
FIGURE 2 - DS3 APPLICATION ...............................................................9
FIGURE 3 - SERIAL HDLC APPLICATION.............................................10
FIGURE 4 - STS-3/STM-1 AGGREGATE/TRIBUTARY/CROSS-
CONNECT APPLICATION.....................................................11
FIGURE 5 - STS-3/STM-1 AGGREGATE/TRIBUTARY/CROSS-
CONNECT CARD..................................................................11
FIGURE 6 - PACKET OVER SONET APPLICATION..............................12
FIGURE 7 - PACKET OVER SONET ROUTER WAN CARD .................12
FIGURE 8 - NORMAL MODE..................................................................13
FIGURE 9 - LOOPBACK MODES...........................................................14
FIGURE 10 - PIN DIAGRAM: BYTE TELECOMBUS MODE
(SMODE[2:0]=000) ................................................................20
FIGURE 11 - PIN DIAGRAM: NIBBLE TELECOMBUS MODE
(SMODE[2:0]=001) ................................................................21
FIGURE 12 - PIN DIAGRAM: SERIAL TELECOMBUS MODE
(SMODE[2:0]=010) ................................................................22
FIGURE 13 - PIN DIAGRAM: BYTE DATA MODE
(SMODE[2:0]=011) ................................................................23
FIGURE 14 - PIN DIAGRAM: NIBBLE DATA MODE
(SMODE[2:0]=100) ................................................................24
FIGURE 15 - PIN DIAGRAM: SERIAL DATA MODE
(SMODE[2:0]=101) ................................................................25
FIGURE 16 - PIN DIAGRAM: SERIAL DS3 MODE
(SMODE[2:0]=110) ................................................................26
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DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
FIGURE 17 - SPECTRA-155 TYPICAL JITTER TOLERANCE AT
155 MBIT/S..........................................................................109
FIGURE 18 - POINTER INTERPRETATION STATE DIAGRAM ............. 116
FIGURE 19 - POINTER GENERATION STATE DIAGRAM ....................125
FIGURE 20 - INPUT OBSERVATION CELL (IN_CELL)..........................422
FIGURE 21 - OUTPUT CELL (OUT_CELL) ............................................423
FIGURE 22 - BIDIRECTIONAL CELL (IO_CELL) ...................................423
FIGURE 23 - LAYOUT OF OUTPUT ENABLE AND
BIDIRECTIONAL CELLS.....................................................424
FIGURE 24 - INTERFACING SPECTRA-155 TO ECL OR PECL...........432
FIGURE 25 - SINGLE ENDED DRIVING DIFFERENTIAL
ALOS+/- INPUTS.................................................................433
FIGURE 26 - SINGLE ENDED DRIVING DIFFERENTIAL
RRCLK+/- OR TRCLK+/- INPUTS.......................................434
FIGURE 27 - BOUNDARY SCAN ARCHITECTURE...............................435
FIGURE 28 - TAP CONTROLLER FINITE STATE MACHINE ................437
FIGURE 29 - RECEIVE OVERHEAD CLOCK AND DATA
ALIGNMENT (R64SEL=0)...................................................441
FIGURE 30 - RECEIVE OVERHEAD CLOCK AND DATA
ALIGNMENT (R64SEL=1)...................................................441
FIGURE 31 - RECEIVE SELECTABLE OVERHEAD CLOCK
AND DATA ALIGNMENT (R64SEL=0).................................442
FIGURE 32 - RECEIVE SELECTABLE OVERHEAD CLOCK
AND DATA ALIGNMENT (R64SEL=1).................................443
FIGURE 33 - RECEIVE SECTION/LINE DCC CLOCK AND DATA
ALIGNMENT........................................................................444
FIGURE 34 - RECEIVE LINE DCC CLOCK AND DATA
ALIGNMENT........................................................................445
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DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
FIGURE 35 - TRANSMIT OVERHEAD CLOCK AND DATA
ALIGNMENT (T64SEL=0) ...................................................446
FIGURE 36 - TRANSMIT OVERHEAD CLOCK AND DATA
ALIGNMENT (T64SEL=1) ...................................................446
FIGURE 37 - TRANSMIT SELECTABLE OVERHEAD CLOCK
AND DATA ALIGNMENT (T64SEL=0) .................................447
FIGURE 38 - TRANSMIT SELECTABLE OVERHEAD CLOCK
AND DATA ALIGNMENT (T64SEL=1) .................................448
FIGURE 39 - TRANSMIT DATA LINK CLOCK AND DATA
ALIGNMENT........................................................................449
FIGURE 40 - TRANSPORT OVERHEAD EXTRACTION (STS-
3/3C)....................................................................................450
FIGURE 41 - TRANSPORT OVERHEAD INSERTION (STS-
3/3C)....................................................................................451
FIGURE 42 - RECEIVE PATH OVERHEAD EXTRACTION
TIMING ................................................................................452
FIGURE 43 - RECEIVE TANDEM CONNECT MAINTENANCE
INSERTION TIMING............................................................453
FIGURE 44 - TRANSMIT PATH OVERHEAD INSERTION
TIMING ................................................................................454
FIGURE 45 - RECEIVE RING CONTROL PORT....................................455
FIGURE 46 - RECEIVE PATH ALARM PORT TIMING ...........................457
FIGURE 47 - TRANSMIT RING CONTROL PORT .................................459
FIGURE 48 - TRANSMIT ALARM PORT TIMING...................................460
FIGURE 49 - STS-1 (STM-0/AU3) BYTE MODE DROP BUS
TIMING ................................................................................461
FIGURE 50 - STS-1 (STM-0/AU3) NIBBLE MODE DROP BUS
TIMING ................................................................................462
FIGURE 51 - STS-1/3 (STM-0/AU3, STM-1/AU3) SERIAL MODE
DROP BUS TIMING.............................................................463
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DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
FIGURE 52 - STS-3 (STM-1/AU3) BYTE MODE DROP BUS
TIMING ................................................................................464
FIGURE 53 - STS-3 (STM-1/AU3) NIBBLE MODE DROP BUS
TIMING ................................................................................465
FIGURE 54 - STS-3C (STM-1/AU4) BYTE MODE DROP BUS
TIMING ................................................................................466
FIGURE 55 - STS-3C (STM-1/AU4) NIBBLE MODE DROP BUS
TIMING ................................................................................467
FIGURE 56 - STS-1 (STM-0/AU3) BYTE MODE GENERATED
BUS TIMING........................................................................468
FIGURE 57 - STS-1 (STM-0/AU3) NIBBLE MODE GENERATED
BUS TIMING........................................................................469
FIGURE 58 - STS-3 (STM-1/AU3) BYTE MODE GENERATED
BUS TIMING........................................................................470
FIGURE 59 - STS-3 (STM-1/AU3) NIBBLE MODE GENERATED
BUS TIMING........................................................................471
FIGURE 60 - STS-3C (STM-1/AU4) BYTE MODE GENERATED
BUS TIMING........................................................................472
FIGURE 61 - STS-3C (STM-1/AU4) NIBBLE MODE
GENERATED BUS TIMING.................................................473
FIGURE 62 - STS-1 (STM-0/AU3) BYTE MODE ADD BUS
TIMING ................................................................................474
FIGURE 63 - STS-1 (STM-0/AU3) NIBBLE MODE ADD BUS
TIMING ................................................................................475
FIGURE 64 - STS-1/3 (STM-0/AU3, STM-1/AU3) SERIAL MODE
ADD BUS TIMING ...............................................................476
FIGURE 65 - STS-3 (STM-1/AU3) BYTE MODE ADD BUS
TIMING ................................................................................477
FIGURE 66 - STS-3 (STM-1/AU3) NIBBLE MODE ADD BUS
TIMING ................................................................................478
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DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
FIGURE 67 - STS-3C (STM-1/AU4) BYTE MODE ADD BUS
TIMING ................................................................................479
FIGURE 68 - STS-3C (STM-1/AU4) NIBBLE MODE ADD BUS
TIMING ................................................................................480
FIGURE 69 - STS-1/3C (STM-0/AU3, STM-1/AU4) BYTE DATA
MODE RECEIVE BUS TIMING ...........................................481
FIGURE 70 - STS-1/3C (STM-0/AU3, STM-1/AU4) NIBBLE
DATA MODE RECEIVE BUS TIMING..................................481
FIGURE 71 - STS-1/3 (STM-0/AU3, STM-1/AU3) SERIAL DATA
MODE RECEIVE BUS TIMING ...........................................482
FIGURE 72 - STS-1/3C (STM-0/AU3, STM-1/AU4) BYTE DATA
MODE TRANSMIT BUS TIMING.........................................483
FIGURE 73 - STS-1/3C (STM-0/AU3, STM-1/AU4) NIBBLE
DATA MODE TRANSMIT BUS TIMING...............................483
FIGURE 74 - STS-1/3 (STM-0/AU3, STM-1/AU3) SERIAL DATA
MODE TRANSMIT BUS TIMING.........................................484
FIGURE 75 - STS-1/3 (STM-0/AU3, STM-1/AU3) DS3 MODE
RECEIVE BUS TIMING .......................................................485
FIGURE 76 - STS-1/3 (STM-0/AU3, STM-1/AU3) DS3 MODE
TRANSMIT BUS TIMING.....................................................485
FIGURE 77 - MICROPROCESSOR INTERFACE READ
ACCESS TIMING (INTEL MODE) .......................................493
FIGURE 78 - MICROPROCESSOR INTERFACE READ
ACCESS TIMING (MOTOROLA MODE) .............................494
FIGURE 79 - MICROPROCESSOR INTERFACE WRITE
ACCESS TIMING (INTEL MODE) .......................................497
FIGURE 80 - MICROPROCESSOR INTERFACE WRITE
ACCESS TIMING (MOTOROLA MODE) .............................498
FIGURE 81 RECEIVE LINE INPUT INTERFACE TIMING......................501
FIGURE 82 - RECEIVE LINE OUTPUT TIMING.....................................503
FIGURE 83 - RECEIVE ALARM SIGNAL OUTPUT TIMING ..................504
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PM5342 SPECTRA-155
DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
FIGURE 84 - RECEIVE PATH OVERHEAD AND ALARM PORT
OUTPUT TIMING ................................................................505
FIGURE 85 - RING CONTROL PORT OUTPUT TIMING .......................506
FIGURE 86 - RECEIVE TANDEM CONNECTION INPUT
TIMING. ...............................................................................507
FIGURE 87 - TELECOM DROP BUS (BYTE AND NIBBLE)
INPUT TIMING ....................................................................508
FIGURE 88 - TELECOM DROP BUS (SERIAL) INPUT TIMING ............509
FIGURE 89 - TELECOM DROP BUS (BYTE AND NIBBLE)
OUTPUT TIMING ................................................................510
FIGURE 90 - TELECOM DROP BUS (SERIAL) OUTPUT TIMING ........511
FIGURE 91 - DATA MODE RECEIVE BUS (BYTE AND NIBBLE)
OUTPUT TIMING ................................................................513
FIGURE 92 - DS3 AND DATA MODE RECEIVE BUS (SERIAL)
OUTPUT TIMING ................................................................515
FIGURE 93 - GENERATED BUS INPUT TIMING...................................516
FIGURE 94 - GENERATED BUS (BYTE AND NIBBLE) OUTPUT
TIMING ................................................................................517
FIGURE 95 - TELECOM ADD BUS (BYTE AND NIBBLE) INPUT
TIMING ................................................................................519
FIGURE 96 - TELECOM ADD BUS (SERIAL) INPUT TIMING ...............520
FIGURE 97 - DATA MODE TRANSMIT BUS (BYTE AND
NIBBLE) INPUT TIMING......................................................521
FIGURE 98 - DATA MODE TRANSMIT BUS NIBBLE OUTPUT
TIMING ................................................................................522
FIGURE 99 - DS3 AND DATA MODE TRANSMIT BUS (SERIAL)
INPUT TIMING ....................................................................523
FIGURE 100 - TRANSMIT PATH OVERHEAD INPUT TIMING................524
FIGURE 101 - TRANSMIT ALARM PORT INPUT TIMING .......................525
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PM5342 SPECTRA-155
DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
FIGURE 102 - TRANSMIT TRANSPORT OVERHEAD INPUT
TIMING ................................................................................527
FIGURE 103 - TRANSMIT RING CONTROL PORT INPUT
TIMING ................................................................................528
FIGURE 104 - TRANSMIT OVERHEAD OUTPUT TIMING ......................529
FIGURE 105 - LINE SIDE TRANSMIT INTERFACE TIMING ...................530
FIGURE 106 - JTAG PORT INTERFACE TIMING ....................................531
FIGURE 107 - 256 PIN SUPER BALL GRID ARRAY (B SUFFIX): ...........534
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DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER

LIST OF TABLES

TABLE 1 - SYSTEM SIDE MODES AND SS[34:0] BUS
MAPPINGS............................................................................15
TABLE 2 - LINE SIDE INTERFACE SIGNALS (20) ..............................27
TABLE 3 - SECTION AND LINE STATUS/OVERHEAD
INTERFACE SIGNALS (36)...................................................32
TABLE 4 - PATH STATUS/OVERHEAD INTERFACE
SIGNALS (37)........................................................................47
TABLE 5 - SYSTEM SIDE INTERFACE SIGNALS (38) .......................59
TABLE 6 - BYTE TELECOMBUS MODE (SMODE[2:0]=000) ..............62
TABLE 7 - NIBBLE TELECOMBUS MODE (SMODE[2:0]=001)...........69
TABLE 8 - SERIAL TELECOMBUS MODE (SMODE[2:0]=010)...........76
TABLE 9 - BYTE DATA MODE (SMODE[2:0]=011) ..............................83
TABLE 10 - NIBBLE DATA MODE (SMODE[2:0]=100) ..........................87
TABLE 11 - SERIAL DATA MODE (SMODE[2:0]=101) ..........................91
TABLE 12 - SERIAL DS3 MODE (SMODE[2:0]=110) .............................95
TABLE 13 - MICROPROCESSOR INTERFACE SIGNALS (25).............98
TABLE 14 - MISCELLANEOUS INTERFACE SIGNALS (11) ...............100
TABLE 15 - POWER SIGNALS (89).....................................................102
TABLE 16 - PATH SIGNAL LABEL MATCH/MISMATCH STATE
TABLE. ................................................................................122
TABLE 17 - ASYNCHRONOUS DS3 MAPPING TO STS-1
(STM-0/AU3)........................................................................127
TABLE 18 - DS3 AIS FORMAT. ............................................................128
TABLE 19 - DS3 DESYNCHRONIZER CLOCK GAPPING
ALGORITHM. ......................................................................130
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PM5342 SPECTRA-155
DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
TABLE 20 - DS3 SYNCHRONIZER BIT STUFFING
ALGORITHM. ......................................................................131
TABLE 21 - SYSTEM SIDE ADD BUS CONFIGURATION
OPTIONS ............................................................................141
TABLE 22 - SYSTEM SIDE DROP BUS CONFIGURATION
OPTIONS ............................................................................141
TABLE 23 - NORMAL MODE REGISTER MEMORY MAP...................144
TABLE 24 - RECEIVE SONET/SDH MODE SETTING. ........................153
TABLE 25 - TRANSMIT SONET/SDH MODE SETTING. .....................154
TABLE 26 - TRANSPORT OVERHEAD NATIONAL AND
UNUSED BYTES.................................................................186
TABLE 27 - ROHSEL[2:0] CODEPOINTS. ...........................................232
TABLE 28 - TOHSEL[2:0] CODEPOINTS.............................................234
TABLE 29 - RXSEL[1:0] CODEPOINTS FOR STS-1 #2. .....................298
TABLE 30 - RXSEL[1:0] CODEPOINTS FOR STS-1 #3. .....................301
TABLE 31 - RXSEL[1:0] CODEPOINTS FOR STS-1 #1 AND
STS-3C................................................................................327
TABLE 32 - RECEIVE ESD[1:0] CODEPOINTS...................................371
TABLE 33 - TRANSMIT ESD[1:0] CODEPOINTS. ...............................397
TABLE 34 - TEST MODE REGISTER ADDRESS MAP. .......................410
TABLE 35 - TEST MODE 0 PRIMARY INPUT READ
REGISTERS. .......................................................................414
TABLE 36 - TEST MODE 0 PRIMARY OUTPUT WRITE
REGISTERS. .......................................................................416
TABLE 37 - JTAG INSTRUCTION REGISTER LENGTH - 3
BITS.....................................................................................418
TABLE 38 - BOUNDARY SCAN REGISTER. .......................................419
TABLE 39 - RASE-BERM CONFIGURATION FOR SDH STM-0..........429
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PM5342 SPECTRA-155
DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
TABLE 40 - RASE-BERM CONFIGURATION FOR SDH STM-1..........429
TABLE 41 - RASE-BERM CONFIGURATION FOR SONET
STS-1 ..................................................................................430
TABLE 42 - RASE-BERM CONFIGURATION FOR SONET
STS-3 ..................................................................................430
TABLE 43 - D.C. CHARACTERISTICS. ...............................................487
TABLE 44 - MICROPROCESSOR INTERFACE READ
ACCESS..............................................................................492
TABLE 45 - MICROPROCESSOR INTERFACE WRITE
ACCESS..............................................................................496
TABLE 46 - RECEIVE LINE INPUT INTERFACE TIMING....................500
TABLE 47 - RECEIVE LINE OUTPUT TIMING.....................................502
TABLE 48 - RECEIVE ALARM SIGNAL OUTPUT TIMING ..................504
TABLE 49 - RECEIVE PATH OVERHEAD AND ALARM PORT
OUTPUT TIMING ................................................................505
TABLE 50 - RECEIVE RING CONTROL PORT OUTPUT
TIMING ................................................................................506
TABLE 51 - RECEIVE TANDEM CONNECTION INPUT TIMING.........507
TABLE 52 - TELECOM DROP BUS (BYTE AND NIBBLE)
INPUT TIMING ....................................................................508
TABLE 53 - TELECOM DROP BUS (SERIAL) INPUT TIMING ............509
TABLE 54 - TELECOM DROP BUS (BYTE AND NIBBLE)
OUTPUT TIMING ................................................................510
TABLE 55 - TELECOM DROP BUS (SERIAL) OUTPUT TIMING ........511
TABLE 56 - DATA MODE RECEIVE BUS (BYTE AND NIBBLE)
OUTPUT TIMING ................................................................512
TABLE 57 - DS3 RECEIVE BUS INPUT TIMING .................................514
TABLE 58 - DS3 AND DATA MODE RECEIVE BUS (SERIAL)
OUTPUT TIMING ................................................................515
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PM5342 SPECTRA-155
DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
TABLE 59 - GENERATED BUS INPUT TIMING ...................................516
TABLE 60 - GENERATED BUS (BYTE AND NIBBLE) OUTPUT
TIMING ................................................................................517
TABLE 61 - TELECOM ADD BUS (BYTE AND NIBBLE) INPUT
TIMING ................................................................................518
TABLE 62 - TELECOM ADD BUS (SERIAL) INPUT TIMING ...............520
TABLE 63 - DATA MODE TRANSMIT BUS (BYTE AND
NIBBLE) INPUT TIMING......................................................521
TABLE 64 - DATA MODE TRANSMIT BUS NIBBLE OUTPUT
TIMING ................................................................................522
TABLE 65 - DS3 AND DATA MODE TRANSMIT BUS (SERIAL)
INPUT TIMING ....................................................................523
TABLE 66 - TRANSMIT PATH OVERHEAD INPUT TIMING................524
TABLE 67 - TRANSMIT ALARM PORT INPUT TIMING .......................525
TABLE 68 - TRANSMIT TRANSPORT OVERHEAD INPUT
TIMING ................................................................................526
TABLE 69 - TRANSMIT RING CONTROL PORT INPUT
TIMING ................................................................................528
TABLE 70 - TRANSMIT OVERHEAD OUTPUT TIMING ......................529
TABLE 71 - LINE SIDE TRANSMIT INTERFACE TIMING ...................530
TABLE 72 - JTAG PORT INTERFACE..................................................531
TABLE 73 - ORDERING INFORMATION. ............................................533
TABLE 74 - THERMAL INFORMATION................................................533
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PM5342 SPECTRA-155
DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
1 FEATURES
• Monolithic SONET/SDH PAYLOAD EXTRACTOR/ALIGNER for use in STS-1
(STM-0/AU3), STS-3 (STM-1/AU3) or STS-3c (STM-1/AU4) interface applications, operating at serial interface speeds of up to 155.52 Mbit/s.
• Provides integrated clock recovery and clock synthesis to allow a direct
interface to optical modules.
• Provides termination for SONET Section and Line, SDH Regenerator Section
and Multiplexer Section transport overhead, and path overhead of one or three STS-1 (STM-0/AU3) paths or a single STS-3c (STM-1/AU4) path.
• Maps one or three STS-1 (STM-0/AU3) payloads or a single STS-3c
(STM-1/AU4) payload to system timing reference, accommodating plesiochronous timing offsets between the references through pointer processing.
• Maps a DS3 bit stream into a STS-1 (STM-0/AU3) frame or three DS3 bit
streams into a STS-3 (STM-1/AU3) frame.
• Provides clear-channel mapping of three 49.536 Mbit/s or 48.384 Mbit/s
arbitrary data streams into an STS-3 (STM-1/AU3) frame or a single arbitrary data stream into an STS-1 (STM-0/AU3) frame. Provides clear-channel mapping of a single 149.76 Mbit/s arbitrary data stream into an STS-3c (STM-1/AU4) frame.
• Provides versatile datamode interface and optional x^43+1 payload
scrambling/descrambling to support Packet Over SONET applications.
• Supports line loopback from the line side receive stream to the transmit
stream and diagnostic loopback from a Telecom ADD bus interface to a Telecom DROP bus interface.
• Provides a standard 5 signal P1149.1 JTAG test port for boundary scan board
test purposes.
• Provides a generic 8-bit microprocessor bus interface for configuration,
control, and status monitoring.
• Low power +5 Volt CMOS. Device has PECL and TTL compatible inputs and
TTL outputs.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 1
PM5342 SPECTRA-155
DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
• 256 pin Super BGA package. Supports Industrial Temperature Range (-40°C
to 85°C) operation.

1.1 SONET Section and Line / SDH Regenerator and Multiplexer Section

• Frames to the STS-1 (STM-0/AU3) or STS-3/3c (STM-1/AU3/AU4) receive
stream and inserts the framing bytes (A1, A2) and the STS identification byte (J0) into the transmit stream; descrambles the receive stream and scrambles the transmit stream.
• Calculates and compares the bit interleaved parity (BIP) error detection codes
(B1, B2) for the receive stream and calculates and inserts B1 and B2 in the transmit stream; accumulates near end errors (B1, B2) and far end errors (M1) and inserts line remote error indications (REI) into the Z2 (M1) growth byte based on received B2 errors.
• Detects signal degrade (SD) and signal fail (SF) threshold crossing alarms
based on received B2 errors.
• Extracts and serializes the order wire channels (E1, E2), the data
communication channels (D1-D3, D4-D12) and the section user channel (F1) from the receive stream, and inserts the corresponding signals into the transmit stream.
• Extracts and serializes the automatic protection switch (APS) channel (K1,
K2) bytes, filtering and extracting them into internal registers for the receive stream. Inserts the APS channel into the transmit stream.
• Extracts and filters the synchronization status message (Z1/S1) byte into an
internal register for the receive stream. Inserts the synchronization status message (Z1/S1) byte into the transmit stream.
• Extracts a 64 byte or 16 byte section trace (J0) message using an internal
register bank for the receive stream. Detects an unstable section trace message or mismatch with an expected message, and optionally inserts Line and Path AIS on the system DROP side upon either of these conditions. Inserts a 64 byte or 16 byte section trace (J0) message using an internal register bank for the transmit stream.
• Detects loss of signal (LOS), out of frame (OOF), loss of frame (LOF), line
remote defect indication (RDI), line alarm indication signal (AIS), and protection switching byte failure alarms on the receive stream. Optionally returns line RDI in the transmit stream.
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PM5342 SPECTRA-155
DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
• Provides a transmit and receive ring control port, allowing alarm and
maintenance signal control and status to be passed between mate SPECTRA-155s for ring-based add drop multiplexer and line multiplexer applications.
• Configurable to force Line AIS in the transmit stream.

1.2 SONET Path / SDH High Order Path

• Accepts a multiplex of three STS-1 (STM-0/AU3) streams or a single STS-3c
(STM-1/AU4) stream, interprets the STS (AU) pointer bytes (H1, H2, and H3), extracts the synchronous payload envelope(s) and processes the path overhead for the receive stream.
• Constructs a byte serial multiplex of three STS-1 (STM-0/AU3) streams or an
STS-3c (STM-1/AU4) stream on the transmit side.
• Detects loss of pointer (LOP), loss of tributary multiframe (LOM), path alarm
indication signal (PAIS) and path (auxiliary and enhanced) remote defect indication (RDI) for the receive stream. Optionally inserts path alarm indication signal (PAIS), path remote defect indication (RDI) and path remote anomaly indication (RAI) in the transmit stream.
• Extracts and serializes the entire path overhead from the three STS-1
(STM-0/AU3) or the single STS-3c (STM-1/AU4) receive streams. Inserts the path overhead bytes in the three STS-1 (STM-0/AU3) or single STS-3c (STM-1/AU4) stream for the transmit stream. The path overhead bytes may be sourced from internal registers or from bit serial path overhead input streams. Path overhead insertion may also be disabled.
• Extracts the received path signal label (C2) byte into an internal register and
detects for path signal label unstable and for signal label mismatch with the expected signal label that is downloaded by the microprocessor. Inserts the path signal label (C2) byte from an internal register for the transmit stream.
• Extracts a 64 byte or 16 byte path trace (J1) message using an internal
register bank for the receive stream. Detects an unstable path trace message or mismatch with an expected message, and inserts Path RAI upon either of these conditions. Inserts a 64 byte or 16 byte path trace (J1) message using an internal register bank for the transmit stream.
• Detects received path BIP-8 and counts received path BIP-8 errors for
performance monitoring purposes. BIP-8 errors are selectable to be treated on a bit basis or block basis. Optionally calculates and inserts path BIP-8 error detection codes for the transmit stream.
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PM5342 SPECTRA-155
DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
• Counts received path remote error indications (REIs) for performance
monitoring purposes. Optionally inserts the path REI count into the path status byte (G1) basis on bit or block BIP-8 errors detected in the receive path. Reporting of BIP-8 errors is on a bit or block bases independent of the accumulation of BIP-8 errors.
• Supports tandem connection origination applications by sourcing a new
tandem path maintenance byte (Z5) reporting the received BIP-8 errors and the data link message and correcting subsequent path BIP-8 bytes (B3) to reflect the change in Z5.
• Supports tandem connection termination applications by accumulating the
incoming error count (IEC) and extracting the tandem connection data link carried in the tandem path maintenance byte (Z5).
• Maintains existing pointer value during incoming signal failures in tandem
path terminating mode.
• Maintains the existing tributary multiframe sequence on the H4 byte until a
new phase alignment has been verified.
• Provides a serial alarm port communication of path REI and path RDI alarms
to the transmit stream of a mate SPECTRA-155 in the returning direction.

1.3 System Side Interfaces

• Supports Telecombus interfaces by indicating/accepting the location of the
STS identification byte (C1), optionally the path trace byte(s) (J1), optionally the first tributary overhead byte(s) (V1), and all synchronous payload envelope bytes in the byte serial stream.
• Supports serial and nibble "Telecombus" interfaces by indicating/accepting
the location of the STS identification byte (C1), the path trace byte(s) (J1), optionally the first tributary overhead byte(s) (V1), and all synchronous payload envelope bytes in the stream.
• For Telecombus interfaces, accommodates phase and frequency differences
between the receive/transmit streams and the DROP/ADD busses via pointer adjustments.
• Supports serial, nibble and byte data mode interfaces by sourcing the
appropriate clock.
• For data mode interfaces, optionally applies a X
43
+1 scrambler/descrambler
to the stream.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 4
PM5342 SPECTRA-155
DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
• Supports a bit serial DS3 data interface for mapping into and out of STS-1
(STM-0/AU3) or STS-3 (STM-1/AU3) SPEs.
• For the DS3 interface, provides optional insertion of framed DS3 AIS in both
the ADD and DROP directions.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 5
PM5342 SPECTRA-155
DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
2 APPLICATIONS
• SONET/SDH Add Drop Multiplexers
• SONET/SDH Terminal Multiplexers
• SONET/SDH Line Multiplexers
• SONET/SDH Cross Connects
• SONET/SDH Tandem Path Termination Equipment
• SONET/SDH Test Equipment
• Switches and Hubs
• Routers
3 REFERENCES
• American National Standard for Telecommunications - Digital Hierarchy -
Optical Interface Rates and Formats Specification, ANSI T1.105-1991.
• American National Standard for Telecommunications - Layer 1 In-Service
Digital Transmission Performance Monitoring, T1X1.3/93-005R1, April 1993.
• American National Standard for Telecommunications – Synchronous Optical
Network (SONET) – Tandem Connection Maintenance, ANSI T1.105.05-
1994.
• Committee T1 Contribution, "Draft of T1.105 - SONET Rates and Formats",
T1X1.5/94-033R2-1994.
• Bell Communications Research - SONET Transport Systems: Common
Generic Criteria, GR-253-CORE Issue 2, December 1995.
• ETS 300 417-1-1, "Generic Functional Requirements for Synchronous Digital
Hierarchy (SDH) Equipment", January, 1996.
• ITU, Recommendation G.707 - "Network Node Interface For The
Synchronous Digital Hierarchy", 1996.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 6
PM5342 SPECTRA-155
DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
• ITU Recommendation G.781, - “Structure of Recommendations on Equipment
for the Synchronous Digital Hierarchy (SDH)”, January, 1994.
• ITU Recommendation G.783, “Characteristics of Synchronous Digital
Hierarchy (SDH) Equipment Functional Blocks”, 28 October, 1996.
• ITU Recommendation O.151, “Error Performance measuring Equipment
Operating at the Primary Rate and Above”, October, 1992.
• ITU Study Group XVII - Contribution D2166 - "Tandem Connection / Tandem
Connection Bundle Maintenance - Working Solution", June 1992.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 7
PM5342 SPECTRA-155
DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
4 APPLICATION EXAMPLE
The SPECTRA-155 is used to implement an STS-1 (STM-0/AU3), STS-3 (STM-1/AU3) or STS-3c (STM-1/AU4) line Interface. The SPECTRA-155 may find application in many different types of SONET/SDH network elements including switches, terminal multiplexers, and add-drop multiplexers. In such applications, on the line side the SPECTRA-155 typically interfaces directly to electrical optical modules. On the system side, the SPECTRA-155 can directly interface to an Telecombus, a DS3 signal source or a data source (i.e. HDLC controller).
Figure 1 - STS-3 (STM-1/AU3), STS-3c (STM-1/AU4) Application
TRANSMIT TRANSPORT AND PATH OVERHEAD ACCESS
TRANSMIT SECTION, LINE, PATH ALARM INSERT SIGNALS
SMODE[2:0]="000"
E/O
O/E
TXD+/-
RXD+/-
RECEIVE TRANSPORT AND PATH OVERHEAD ACCESS
PM5342
SPECTRA-155
RECEIVE SECTION, LINE, PATH ALARM DETECT SIGNALS
MICRO BUS FOR CONFIG, STATUS AND CONTROL
ACK
AC1J1V1
APL
AD[7:0]
ADP
DCK
DC1J1V1
DPL
DD[7:0]
DDP
Telecombus Add Interface
Telecombus Drop Interface to PM5362, TUPP-PLUS
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 8
PM5342 SPECTRA-155
DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
Figure 2 - DS3 Application
TRANSMIT TRANSPORT AND PATH OVERHEAD ACCESS
TRANSMIT SECTION, LINE, PATH ALARM INSERT SIGNALS
SMODE[2:0]="110"
44.736 MHz*
E/O
O/E
TXD+/-
RXD+/-
RECEIVE TRANSPORT AND PATH OVERHEAD ACCESS
PM5342
SPECTRA-155
RECEIVE SECTION, LINE, PATH ALARM DETECT SIGNALS
DS3TICLK[3:1]
DS3TDAT[3:1]
DS3ROCLK[3:1]
DS3RDAT[3:1]
DS3RICLK[3:1]
MICRO BUS FOR CONFIG, STATUS AND CONTROL
TICLK
TCLK TDAT
3 * PM7345 SUNI-PDH
3 * PM8313 D3MX
RCLK
RDAT
44.928 MHz
* For the PM7345, the 44.736 MHz clock can be fed directly to the DS3TICLK input
or
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 9
PM5342 SPECTRA-155
A
DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
Figure 3 - Serial HDLC Application
TRANSMIT TRANSPORT AND PATH OVERHEAD ACCESS
TRA NSMIT SECTIO N, LINE, PATH ALARM INSERT SIGNALS
SMODE[2:0]="101"
E/O
O/E
TXD+/-
RXD+/-
RECEIVE TRANSPORT AND PATH OVERHEAD
CCESS
PM5342
SPECTRA-155
RECEIVE SEC TION, L INE, PATH ALARM DETECT SIGNALS
SDM TOCL K[3:1]
SDM TICLK [3:1]
SDMTDAT[3:1]
SDM ROCL K[3:1]
SDMRDAT[3:1]
MICRO BUS FOR CONFIG, STATUS AND CONTROL
TCLK[0]
TDA T[0]
3 * PM7364 FREEDM
RCLK[0] RDAT[0]
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 10
PM5342 SPECTRA-155
DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
Figure 4 - STS-3/STM-1 Aggregate/Tributary/Cross-Connect Application
TRANSMIT TRANSPORT A ND PATH OVERHE AD ACCESS
TRANSMIT SECTION, LINE PATH ALARM INSERT SIGNALS
SMODE[2:0]="000"
8 BIT
TELECOMBUS
INTERFACE
19.44 CLK REF
OPT. TX
OPT. RX
19.44 CLK REF
TRCLK+/-
TXD+ /-
RXD+/-
RRCLK+/-
RECEIVE TRANSPORT A ND PATH OVERHE AD ACCESS
PM5342
SPECTRA-155
RECEIVE SECTION, LINE PATH ALARM DETECT SIGNALS
ACK
AD[7:0 ], ADP
AC1J1
APL
DD[7:0], DDP
DC1J1
DPL
DCK
MICROBUS FOR CONFIG, STATUS AND CONTROL
TUPP-PLUS
ID[7:0 ], IDP
IC1J 1
IPL
SCLK
PM5362
OD[7 :0], ODP
OTV5
OTPL
TPOH
Figure 5 - STS-3/STM-1 Aggregate/Tributary/Cross-Connect Card
PM5342
SPECTRA-155
PM5362
TUPP
Plus
PM5371
TUDX
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 11
PM5342 SPECTRA-155
DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
Figure 6 - Packet Over SONET Application
19.44 CLK REF
OPT. TX
OPT. RX
19.44 CLK REF
TRANSMIT TRANSPORT AND PATH OVERHEAD ACCESS
TRCLK+/-
TXD+/-
RXD+/-
RRCLK+/-
RECEIVE TRANSPORT AND PATH OVERHEAD ACCESS
TRANSMIT SECTION, LINE PATH ALARM INSERT SIGNALS
PM5342
SPECTRA-155
RECEIVE SECTION, LINE PATH ALARM DETECT SIGNALS
SMODE[2:0]="011"
DMTOCLK
DMTICLK
DMTDAT[7::0]
DMROC LK
DMRDAT[7:0]
MICROBUS FOR CONFIG, STATUS AND CONTROL
TCLKI
TDATO [7:0]
RCLKI
RDATI[7:0]
Figure 7 - Packet Over SONET Router WAN Card
TDAT[ 15:0]
Packet
Over
SONET
HDLC
Processor
RDAT[15:0]
INTERFACE
INTERFACE)
TFCLK
TENB
TDA
TSOP
TPRTY
TMOD
TEOP TERR
RFCLK
RENB
RDA
RSOP
RPRTY
RMOD
REOP RERR
PACKET
OVER
SONET
(TO BUS
PM534 2
SAR
SPECTR A-155
Packet Over
SONET HDLC
Processor
BUS
Interface
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 12
PM5342 SPECTRA-155
DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
5 BLOCK DIAGRAM
Figure 8 - NORMAL MODE
TLRDI/TRCPFP
RLAIS/TRCPCLK
TLAIS/TRCPDAT
TSLDCLK, TOWCLK
TSLD, TSOW, TSUC
TLD, TLOW, TOH
TLDCLK, TOHCLK
TTOH
TTOHFP
TTOHCLK
TTOHEN
TCLK, TFP
TPOH[3:1]
TPOHFP[3:1]
TPOHCLK[3:1]
TPOHEN[3:1]
TAD, TAFP, TACK
SCPO[1:0]
SCPI[1:0]
TDO
TDI
TCK
TMS
TRSTB
TRCLK+
TRCLK-
TXC
TXD+
TXD-
TBYP TATP
RATP RBYP
RXD-
RXD+
RRCLK+
RRCLK-
ALOS+
ALOS-
Tx Line
I/F
Rx Line
I/F
C1, C2
Tx Ring
Control Port
Clock
Synthesis
(CSPI)
Clock and
Data
Recovery
(CRSI)
Rx Ring
Control Port
LOS/RRCPFP
LAIS/RRCPDAT
LRDI/RRCPCLK
Tx
Section O/H
Processor
(TSOP)
Section
Trace
Buffer
(SSTB)
Rx
Section O/H
Processor
(RSOP)
LOF, SALM
RSLDCLK,ROWCLK
RSLD, RSOW, RSUC
Path
Trace
RPOHCLK[3:1]
RALM[3:1]
RTCEN[3:1]
Serial
Control
Port
Path
Trace Buffer #3 (SPTB #3)
RTCOH[3:1]
JTAG Test
Access Port
Tx Telecom
Aligner #1
(TTAL #1)
Tx Telecom
Aligner #2
(TTAL #2)
Tx Telecom
Aligner #3
(TTAL #3)
Rx Telecom
Aligner #1
(RTAL #1)
Rx Telecom
Aligner #2
(RTAL #2)
Rx Telecom
Aligner #3
(RTAL #3)
Microprocessor
RAD
D[7:0]
B3E[3:1]
3
ADD Bus
PRBS
Generator/
3
3
3
3
3
3
I/F
ALE
CSB
INTB
RSTB
A[7:0]
MBEB
RDB/E
WRB/RWB
Monitor
DS3 Mapper
Add Side #1
(D3MA #1)
DS3 Mapper
Add Side #2
(D3MA #2)
DS3 Mapper
Add Side #3
(D3MA #3)
Tx Pointer
Interpreter #1
(TPIP #1)
Tx Pointer
Interpreter #2
(TPIP #2)
Tx Pointer
Interpreter #3
(TPIP #3)
DROP Bus
PRBS
Generator/
Monitor
DS3 Mapper
Add Side #1
(D3MA #1)
DS3 Mapper
Add Side #2
(D3MA #2)
DS3 Mapper
Add Side #3
(D3MA #3)
System
Side
I/F
SMODE[2:0]
SS[34:0]
Transport
O/H
Insert
Tx Path O/H
Processor #1
Path Trace
Buffer #1
(SPTB #1)
RXC, RCLK, RFP
(TPOP #1)
Tx Path O/H
Processor #2
(TPOP #2)
Tx Path O/H
Processor #3
(TPOP #3)
Buffer #2
(SPTB #2)
Rx Path O/H
Processor #1
(RPOP #1)
Rx Path O/H
Processor #2
(RPOP #2)
Rx Path O/H
Processor #3
(RPOP #3)
RPOH[3:1]
RPOHFP[3:1]
Tx
Line O/H
Processor
(TLOP)
Rx
Line O/H
Processor
(RLOP)
Transport
O/H
Extract
RTOH
RTOHFP
TRIS_OHB
RLDCLK, ROHCLK
RTOHCLK
RLD, RLOW, ROH
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 13
PM5342 SPECTRA-155
DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
Figure 9 - LOOPBACK MODES
LINE
LOOPBACK
(LLE=1)
Tx Line
I/F
Rx Line
I/F
Tx Ring
Control Port
Clock
Synthesis
(CSPI)
Clock and
Data
Recovery
(CRSI)
Rx Ring
Control Port
Tx
Section O/H
Processor
(TSOP)
Section
DIAGNOSTIC
Trace
LOOPBACK
Buffer (SSTB)
(DLE=1)
Rx
Section O/H
Processor
(RSOP)
Tx
Line O/H
Processor
(TLOP)
Rx
Line O/H
Processor
(RLOP)
Transport
O/H
Insert
Transport
O/H
Extract
Path Trace
Buffer #1
(SPTB #1)
Tx Path O/H
Processor #1
(TPOP #1)
Tx Path O/H
Processor #2
(TPOP #2)
Tx Path O/H
Processor #3
(TPOP #3)
Path
SYSTEM SIDE
Trace
LINE LOOPBACK
Buffer #2
Buffer #3
(SPTB #2)
(SPTB #3)
Rx Path O/H
Processor #1
(RPOP #1)
Rx Path O/H
Processor #2
(RPOP #2)
Rx Path O/H
Processor #3
(RPOP #3)
Serial
Control
Path Trace
(SLLBEN=1)
Port
JTAG Test
Access Port
Tx Telecom
Aligner #1 (TTAL #1)
Tx Telecom
Aligner #2 (TTAL #2)
Tx Telecom
Aligner #3 (TTAL #3)
Rx Telecom
Aligner #1 (RTAL #1)
Rx Telecom
Aligner #2 (RTAL #2)
Rx Telecom
Aligner #3 (RTAL #3)
Microprocessor
I/F
3
ADD Bus
PRBS
Generator/
3
Monitor
DS3 Mapper Add Side #1
(D3MA #1)
DS3 Mapper Add Side #2
(D3MA #2)
3
DS3 Mapper Add Side #3
(D3MA #3)
Tx Pointer
Interpreter #1
(TPIP #1)
Tx Pointer
Interpreter #2
(TPIP #2)
3
Tx Pointer
Interpreter #3
(TPIP #3)
3
DROP Bus
PRBS
Generator/
3
Monitor
DS3 Mapper Add Side #1
(D3MA #1)
DS3 Mapper Add Side #2
(D3MA #2)
3
DS3 Mapper Add Side #3
(D3MA #3)
System
Side
I/F
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 14
PM5342 SPECTRA-155
]
]
]DD[0]
]
]
]DD[1]
]
]
]DD[2]
]
]DD[3]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]AD[0]
]
]
]AD[1]
]
]
]AD[2]
]
]AD[3]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]GD[0]
]
]GD[1]
]
]
]
]
]
]
]
]
]
]
]
]
DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
Table 1 - System side modes and SS[34:0] bus mappings.
Signal Byte
Telecombus Mode
SMODE=000 SMODE=001 SMODE=010 SMODE=011 SMODE=100 SMODE=101 SMODE=110
SS[0]DCK DCK SDCK[1
SS[1]DFP DFP Res. Input Res. Input Res. Input Res. Input Res. Input
SS[2]DD[0
SS[3]DD[1
SS[4]DD[2
SS[5]DD[3
SS[6]DD[4
SS[7]DD[5
SS[8]DD[6
SS[9]DD[7
SS[10]DPL DPL SDPL[1
SS[11]DC1J1V1 DC1J1V1 SDPL[2
SS[12]DDP DDP SDPL[3
SS[13]ACK ACK SACK[1
SS[14]AD[0
SS[15]AD[1
SS[16]AD[2
SS[17]AD[3
SS[18]AD[4
SS[19]AD[5
SS[20]AD[6
SS[21]AD[7
SS[22]APL APL SAPL[1
SS[23]AC1J1V1 AC1J1V1 SAPL[2
SS[24]ADP ADP SAPL[3
SS[25]GFP GFP SDFP[1
SS[26]GMFP GMFP SDFP[2
SS[27]GD[0
SS[28]GD[1
SS[29]GPL GPL Res. Output Res. Output Res. Output SDMTOCLK[3]Res. Output
SS[30]GC1J1V1 GC1J1V1 Res. Output Res. Output Res. Output Res. Output Res. Output
SS[31]GDP GDP Res. Output Res. Output Res. Output Res. Output Res. Output
SS[32]DTPAIS[1
SS[33]DTPAIS[2
SS[34]DTPAIS[3
Nibble Telecombus Mode
Res. Output SDC1J1V1[3]DMRDAT[4]Res. Output SDMROCLK[3]DS3ROCLK[3
Res. Output SDD[1
Res. Output SDD[2
Res. Output SDD[3
Res. Input SAC1J1V1[3]DMTDAT[4]Res. Input Res. Input DS3RAIS[3
Res. Input SAD[1
Res. Input SAD[2
Res. Input SAD[3
DTPAIS[1
DTPAIS[2
DTPAIS[3
Serial Telecombus Mode
SDCK[2
SDCK[3
SDC1J1V1[1]DMRDAT[2]DMRDAT[2]SDMROCLK[1]DS3ROCLK[1
SDC1J1V1[2]DMRDAT[3]DMRDAT[3]SDMROCLK[2]DS3ROCLK[2
SACK[2
SACK[3
SAC1J1V1[1]DMTDAT[2]DMTDAT[2]Res. Input DS3RAIS[1
SAC1J1V1[2]DMTDAT[3]DMTDAT[3]Res. Input DS3RAIS[2
SDFP[3
Res. Output DMTOCLK DMTOCLK SDMTOCLK[2]Res. Output
SDTPAIS[1
SDTPAIS[2
SDTPAIS[3
Byte Data Mode
DMROCLK DMROCLK Res. Input DS3RICLK[1
DMRDAT[0]DMRDAT[0]Res. Input DS3RICLK[2
DMRDAT[1]DMRDAT[1]Res. Input DS3RICLK[3
DMRDAT[5]Res. Output SDMRDAT[1
DMRDAT[6]Res. Output SDMRDAT[2
DMRDAT[7]Res. Output SDMRDAT[3
Res. Output Res. Output Res. Output Res. Output
Res. Output Res. Output Res. Output Res. Output
Res. Output Res. Output Res. Output Res. Output
DMTICLK DMTICLK SDMTICLK[1]DS3TICLK[1
DMTDAT[0]DMTDAT[0]SDMTICLK[2]DS3TICLK[2
DMTDAT[1]DMTDAT[1]SDMTICLK[3]DS3TICLK[3
DMTDAT[5]Res. Input SDMTDAT[1
DMTDAT[6]Res. Input SDMTDAT[2
DMTDAT[7]Res. Input SDMTDAT[3
Res. Input Res. Input Res. Input Res. Input
Res. Input Res. Input Res. Input Res. Input
Res. Input Res. Input Res. Input Res. Input
Res. Input DMTMSN Res. Input Res. Input
Res. Input Res. Input Res. Input Res. Input
Res. Input Res. Input SDMTOCLK[1]Res. Output
Res. Input Res. Input Res. Input DS3TAIS[1
Res. Input Res. Input Res. Input DS3TAIS[2
Res. Input Res. Input Res. Input DS3TAIS[3
Nibble Data Mode
Serial Data Mode
Serial DS3 Mode
DS3RDAT[1
DS3RDAT[2
DS3RDAT[3
DS3TDAT[1
DS3TDAT[2
DS3TDAT[3
Notes on System Side Modes and SS[34:0] bus mappings:
1. Res. Input pins are Reserved Input pins which must be strapped low. Failure to connect these pins may cause malfunction or damage to the SPECTRA-155.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 15
PM5342 SPECTRA-155
DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
2. Res. Output pins are Reserved Output pins which must be left unconnected.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 16
PM5342 SPECTRA-155
DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
6 DESCRIPTION
The PM5342 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER (SPECTRA-155) terminates the transport and path overhead of STS-1 (STM-0/AU3) and STS-3/3c (STM-1/AU3/AU4) streams at 51.84 Mbit/s and 155.52 Mbit/s respectively. The SPECTRA-155 implements significant functions for a SONET/SDH compliant line interface.
The SPECTRA-155 receives SONET/SDH frames via a bit serial interface, recovers clock and data, and terminates the SONET/SDH section (regenerator section), line (multiplexer section), and path. It performs framing (A1, A2), descrambling, detects alarm conditions, and monitors section and line bit interleaved parity (BIP) (B1, B2), accumulating error counts at each level for performance monitoring purposes. B2 errors are also monitored to detect signal fail and signal degrade threshold crossing alarms. Line remote error indications (M1) are also accumulated. A 16 or 64 byte section trace (J0) message may be buffered and compared against an expected message. In addition, the SPECTRA-155 interprets the received payload pointers (H1, H2), detects path alarm conditions, detects and accumulates path BIPs (B3), monitors and accumulates path Remote Error Indications (REIs), accumulates and compares the 16 or 64 byte path trace (J1) message against an expected result and extracts the synchronous payload envelope (virtual container). All transport and path overhead bytes are extracted and serialized on lower rate interfaces, allowing additional external processing of overhead, if desired.
The extracted SPE (VC) is either placed on a Telecombus DROP bus, serialized into DS3 streams, or serialized into data streams. For Telecombus applications, frequency offsets (e.g., due to plesiochronous network boundaries, or the loss of a primary reference timing source) and phase differences (due to normal network operation) between the received data stream and the DROP bus are accommodated by pointer adjustments in the DROP bus. For the DS3 application, the SPECTRA-155 demaps the three DS3s from the STS-3 (STM-1/AU3) SPE and provides serialized bit streams with derived clocks. For data applications, the SPECTRA-155 either presents the extracted SPE (VC) as a byte/nibble serial stream with an associated clock or presents the STS-3 (STM-1/AU3) SPE into three bit serial streams with associated clocks.
The SPECTRA-155 transmits SONET/SDH frames, via a bit serial interface, and formats section (regenerator section), line (multiplexer section), and path overhead appropriately. The SPECTRA-155 provides transmit path origination for a SONET/SDH STS-1 (STM-0/AU3), STS-3 (STM-1/AU3) or STS-3c (STM-1/AU4) stream. It performs framing pattern insertion (A1, A2), scrambling, alarm signal insertion, and creates section and line BIPs (B1, B2) as required to allow performance monitoring at the far end. Line remote error indications (M1)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 17
PM5342 SPECTRA-155
DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
are optionally inserted. A 16 or 64 byte section trace (J0) message may be inserted. In addition, the SPECTRA-155 generates the transmit payload pointers (H1, H2), creates and inserts the path BIP, optionally inserts a 16 or 64 byte path trace (J1) message, optionally inserts the path status byte (G1). In addition to its basic processing of the transmit SONET/SDH overhead, the SPECTRA-155 provides convenient access to all overhead bytes, which are inserted serially on lower rate interfaces, allowing additional external sourcing of overhead, if desired. The SPECTRA-155 also supports the insertion of a large variety of errors into the transmit stream, such as framing pattern errors and BIP errors, which are useful for system diagnostics and tester applications.
The inserted SPE (VC) is either sourced from a Telecombus ADD stream, from DS3 serial streams or from data streams. For Telecombus applications, the SPECTRA-155 maps the SPE from a Telecombus ADD bus into the transmit stream. Frequency offsets (e.g., due to plesiochronous network boundaries, or the loss of a primary reference timing source) and phase differences (due to normal network operation) between the transmit data stream and the ADD bus are accommodated by pointer adjustments in the transmit stream. For the DS3 application, the SPECTRA-155 maps three DS3s into a STS-3 (STM-1/AU3) SPE. For the data applications, the SPECTRA-155 maps a byte/nibble serial data stream into a STS-1 (STM-0/AU3) SPE or STS-3c (STM-1/AU4) SPE transmit stream or maps three bit serial streams into a STS-3 (STM-1/AU3) SPE transmit stream.
The SPECTRA-155 supports tandem connection termination applications where the tandem connection maintenance byte (Z5) carries the incoming BIP-8 error count (IEC), a tandem data link, and a path AIS code (ISF). The incoming error count is accumulated and the receive data link is serialized for external processing. A new data link can be inserted from a low speed serial input. An incoming signal failure alarm (ISF) is used to convey path AIS in place of all-ones in the pointer (H1, H2).
The transmitter and receiver are independently configurable to allow for asymmetric interfaces. Ring control ports are provide to pass control and status information between mate transceivers. The SPECTRA-155 is configured, controlled and monitored via a generic 8-bit microprocessor bus interface.
The SPECTRA-155 is implemented in low power, +5 Volt, CMOS technology. It has TTL and pseudo ECL (PECL) compatible inputs and outputs and is packaged in a 256 pin SBGA package.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 18
PM5342 SPECTRA-155
DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
7 PIN DIAGRAMS
The SPECTRA-155 is available in a 256 pin SBGA package having a body size of 27 mm by 27 mm and a ball pitch of 1.27 mm. There are seven pinout diagrams; each corresponds to a different system side mode (SMODE) configuration.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 19
PM5342 SPECTRA-155
DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
Figure 10 - Pin diagram: Byte Telecombus Mode (SMODE[2:0]=000)
2019181716151413121110987654321
SS[2]/
SS[5]/
VSS VSS VSS SMODE[1]
A
VSS VDD VDD SMODE[0]
B
VSS VDD VDD NC3 SMODE[2]
C
TMS TCK TDO VDD TRIS_OHB
D
B3E[3] RSTB TRSTB TDI TPOHCLK[2] TPOH[1] TPOHCLK[1] SCPI[1]
E
DD[0]
SS[1]/ DFP
SS[9]/
DD[3]
DD[7]
SS[4]/
SS[8]/
DD[2]
DD[6]
SS[3]/
SS[6]/
DD[1]
DD[4]
SS[0]/
VDD
DCK
SS[12]/
SS[10]/
SS[7]/ DD[5]
SS[15]/
AD[1]
SS[14]/
AD[0]
SS[13]/
ACK
SS[11]/
DC1J1V1
SS[19]/
SS[18]/
SS[17]/
SS[16]/
VSS VSS
AD[5]
SS[21]/
AD[4]
AD[7]
SS[20]/
AD[3]
AD[6]
VDD
AD[2]
VSS
DDP
DPL
SS[22]/
APL
SS[23]/
AC1J1V1
SS[25]/
GFP
SS[24]/
SS[28]/
SS[32]/
ADP
GD[1]
SS[26]/
SS[29]/
GMFP
GPL
SS[27]/
SS[31]/
GD[0]
GDP
SS[30]/
VDD TPOHFP[3] TPOHFP[2] VDD TPOH[2] TPOHFP[1] TPOHEN[1]
GC1J1V1
SCPO[0] TPOH[3] VSS VSS VSS
DTPAIS[1]
SS[33]/
SCPO[1] TPOHCLK[3] VDD VDD VSS
DTPAIS[2]
SS[34]/
TPOHEN[3] TPOHEN[2] VDD VDD VSS
DTPAIS[3]
A
B
C
D
E
B3E[2] RALM[2] RALM[3] RAD SCPI[0] ALE CSB WRB/RWB
F
RTCOH[3] RTCEN[3] RALM[1] VDD VDD RDB/E MBEB A[0]
G
RTCOH[1] RTCOH[2] RTCEN[2] B3E[1] INTB A[1] A[3] VSS
H
VSS RPOH[3] RPOHCLK[3] RTCEN[1] A[2] A[4] A[5] A[6]
J
VSS RPOHFP[3] RPOHCLK[2] VDD
K
RXC RPOH[2] RPOHFP[2] RCLK VDD D[1] D[2] VSS
L
RFP RPOHCLK[1] RPOH[1] LOF D[6] D[4] D[3] VSS
M
VSS RPOHFP[1] SALM RLDCLK TACK TFP D[7] D[5]
N
LOS ROHCLK ROH VDD VDD TCLK TTOHFP TAFP
P
RLD RLOW RSUC RSLD TLD TSLDCLK TSLD TAD
R
RSLDCLK ROWCLK RSOW RTOHFP TSOW TTOHCLK TOH TOHCLK
T
LAIS LRDI RTOHCLK VDD RBYP RAVD2 NC_A RAVS4 ALOS- NC_B TAVD3 TAVD1 RLAIS VDD TLRDI TTOHEN VDD TLOW TSUC TLDCLK
U
VSS VDD VDD RTOH RAVS2 RAVS1 QAVS1 RAVD4 ALOS+ RAVD3 QAVD3 TAVS3 TAVD2 NC5 NC1 NC2 TOWCLK VDD VDD VSS
V
VSS VDD VDD TATP C1 RAVD1 RRCLK- RAVS3 RXD+ RXD- QAVS2 TRCLK+ TAVS1 NC4 TBYP TXD+ TTOH VDD VDD VSS
W
VSS VSS VSS RATP C2 QAVD1 RRCLK+ NC_F NC_C NC_D QAVD2 TRCLK- NC_E TAVS2 TLAIS TXD- TXC VSS VSS VSS
Y
BOTTOM VIEW
A[7] A[8] A[9] D[0]
2019181716151413121110987654321
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 20
PM5342 SPECTRA-155
DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
Figure 11 - Pin diagram: Nibble Telecombus Mode (SMODE[2:0]=001)
2019181716151413121110987654321
SS[2]/
SS[5]/
VSS VSS VSS SMODE[1]
A
VSS VDD VDD SMODE[0]
B
VSS VDD VDD NC3 SMODE[2]
C
TMS TCK TDO VDD TRIS_OHB
D
B3E[3] RSTB TRSTB TDI TPOHCLK[2] TPOH[1] TPOHCLK[1] SCPI[1]
E
DD[0]
SS[1]/ DFP
SS[9]/
DD[3]
Res. Output
SS[4]/
SS[8]/
DD[2]
Res. Output
SS[3]/
SS[6]/
DD[1]
Res. Output
SS[0]/
VDD
DCK
VSS
SS[12]/
DDP
SS[10]/
DPL
SS[7]/
Res. Output
SS[15]/
AD[1]
SS[14]/
AD[0]
SS[13]/
ACK
SS[11]/
DC1J1V1
SS[19]/
Res. Input
SS[18]/
Res. Input
SS[17]/
AD[3]
SS[16]/
AD[2]
VSS VSS
SS[21]/
Res. Input
SS[20]/
Res. Input
VDD
SS[22]/
APL
SS[23]/
AC1J1V1
SS[25]/
GFP
SS[24]/
SS[28]/
SS[32]/
ADP
GD[1]
SS[26]/
SS[29]/
GMFP
GPL
SS[27]/
SS[31]/
GD[0]
GDP
SS[30]/
VDD TPOHFP[3] TPOHFP[2] VDD TPOH[2] TPOHFP[1] TPOHEN[1]
GC1J1V1
SCPO[0] TPOH[3] VSS VSS VSS
DTPAIS[1]
SS[33]/
SCPO[1] TPOHCLK[3] VDD VDD VSS
DTPAIS[2]
SS[34]/
TPOHEN[3] TPOHEN[2] VDD VDD VSS
DTPAIS[3]
A
B
C
D
E
B3E[2] RALM[2] RALM[3] RAD SCPI[0] ALE CSB WRB/RWB
F
RTCOH[3] RTCEN[3] RALM[1] VDD VDD RDB/E MBEB A[0]
G
RTCOH[1] RTCOH[2] RTCEN[2] B3E[1] INTB A[1] A[3] VSS
H
VSS RPOH[3] RPOHCLK[3] RTCEN[1] A[2] A[4] A[5] A[6]
J
VSS RPOHFP[3] RPOHCLK[2] VDD
K
RXC RPOH[2] RPOHFP[2] RCLK VDD D[1] D[2] VSS
L
RFP RPOHCLK[1] RPOH[1] LOF D[6] D[4] D[3] VSS
M
VSS RPOHFP[1] SALM RLDCLK TACK TFP D[7] D[5]
N
LOS ROHCLK ROH VDD VDD TCLK TTOHFP TAFP
P
RLD RLOW RSUC RSLD TLD TSLDCLK TSLD TAD
R
RSLDCLK ROWCLK RSOW RTOHFP TSOW TTOHCLK TOH TOHCLK
T
LAIS LRDI RTOHCLK VDD RBYP RAVD2 NC_A RAVS4 ALOS- NC_B TAVD3 TAVD1 RLAIS VDD TLRDI TTOHEN VDD TLOW TSUC TLDCLK
U
VSS VDD VDD RTOH RAVS2 RAVS1 QAVS1 RAVD4 ALOS+ RAVD3 QAVD3 TAVS3 TAVD2 NC5 NC1 NC2 TOWCLK VDD VDD VSS
V
VSS VDD VDD TATP C1 RAVD1 RRCLK- RAVS3 RXD+ RXD- QAVS2 TRCLK+ TAVS1 NC4 TBYP TXD+ TTOH VDD VDD VSS
W
VSS VSS VSS RATP C2 QAVD1 RRCLK+ NC_F NC_C NC_D QAVD2 TRCLK- NC_E TAVS2 TLAIS TXD- TXC VSS VSS VSS
Y
BOTTOM VIEW
A[7] A[8] A[9] D[0]
2019181716151413121110987654321
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 21
PM5342 SPECTRA-155
DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
Figure 12 - Pin diagram: Serial Telecombus Mode (SMODE[2:0]=010)
2019181716151413121110987654321
SS[2]/
SS[5]/
VSS VSS VSS SMODE[1]
A
VSS VDD VDD SMODE[0]
B
VSS VDD VDD NC3 SMODE[2]
C
TMS TCK TDO VDD TRIS_OHB
D
B3E[3] RSTB TRSTB TDI TPOHCLK[2] TPOH[1] TPOHCLK[1] SCPI[1]
E
SDCK[2]
SS[1]/
Res. Input
SDC1J1V1[2]
SS[4]/
SDC1J1V1[1]
SS[3]/
SDCK[3]
SS[0]/
SDCK[1]
SS[9]/ SDD[3]
SS[8]/ SDD[2]
SS[6]/
SDC1J1V1[3]
VDD
VSS
SS[12]/ SDPL[3]
SS[10]/ SDPL[1]
SS[7]/
SDD[1]
SS[15]/ SACK[3]
SS[14]/ SACK[2]
SS[13]/ SACK[1]
SS[11]/ SDPL[2]
SS[19]/
SAD[1]
SS[18]/
SAC1J1V1[3]
SS[17]/
SAC1J1V1[2]
SS[16]/
SAC1J1V1[1]
VSS VSS
SS[21]/ SAD[3]
SS[20]/ SAD[2]
VDD
SS[22]/
SAPL[1]
SS[23]/
SAPL[2]
SS[25]/
SDFP[1]
SS[24]/
SS[28]/
SS[32]/
SAPL[3]
Res. Output
SS[26]/
SS[29]/
SDFP[2]
Res. Output
SS[27]/
SS[31]/
SDFP[3]
Res. Output
SS[30]/
VDD TPOHFP[3] TPOHFP[2] VDD TPOH[2] TPOHFP[1] TPOHEN[1]
Res. Output
SCPO[0] TPOH[3] VSS VSS VSS
SDTPAIS[1]
SS[33]/
SCPO[1] TPOHCLK[3] VDD VDD VSS
SDTPAIS[2]
SS[34]/
TPOHEN[3] TPOHEN[2] VDD VDD VSS
SDTPAIS[3]
A
B
C
D
E
B3E[2] RALM[2] RALM[3] RAD SCPI[0] ALE CSB WRB/RWB
F
RTCOH[3] RTCEN[3] RALM[1] VDD VDD RDB/E MBEB A[0]
G
RTCOH[1] RTCOH[2] RTCEN[2] B3E[1] INTB A[1] A[3] VSS
H
VSS RPOH[3] RPOHCLK[3] RTCEN[1] A[2] A[4] A[5] A[6]
J
VSS RPOHFP[3] RPOHCLK[2] VDD
K
RXC RPOH[2] RPOHFP[2] RCLK VDD D[1] D[2] VSS
L
RFP RPOHCLK[1] RPOH[1] LOF D[6] D[4] D[3] VSS
M
VSS RPOHFP[1] SALM RLDCLK TACK TFP D[7] D[5]
N
LOS ROHCLK ROH VDD VDD TCLK TTOHFP TAFP
P
RLD RLOW RSUC RSLD TLD TSLDCLK TSLD TAD
R
RSLDCLK ROWCLK RSOW RTOHFP TSOW TTOHCLK TOH TOHCLK
T
LAIS LRDI RTOHCLK VDD RBYP RAVD2 NC_A RAVS4 ALOS- NC_B TAVD3 TAVD1 RLAIS VDD TLRDI TTOHEN VDD TLOW TSUC TLDCLK
U
VSS VDD VDD RTOH RAVS2 RAVS1 QAVS1 RAVD4 ALOS+ RAVD3 QAVD3 TAVS3 TAVD2 NC5 NC1 NC2 TOWCLK VDD VDD VSS
V
VSS VDD VDD TATP C1 RAVD1 RRCLK- RAVS3 RXD+ RXD- QAVS2 TRCLK+ TAVS1 NC4 TBYP TXD+ TTOH VDD VDD VSS
W
VSS VSS VSS RATP C2 QAVD1 RRCLK+ NC_F NC_C NC_D QAVD2 TRCLK- NC_E TAVS2 TLAIS TXD- TXC VSS VSS VSS
Y
BOTTOM VIEW
A[7] A[8] A[9] D[0]
2019181716151413121110987654321
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 22
PM5342 SPECTRA-155
DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
Figure 13 - Pin diagram: Byte Data Mode (SMODE[2:0]=011)
2019181716151413121110987654321
SS[2]/
SS[5]/
VSS VSS VSS SMODE[1]
A
VSS VDD VDD SMODE[0]
B
VSS VDD VDD NC3 SMODE[2]
C
TMS TCK TDO VDD TRIS_OHB
D
B3E[3] RSTB TRSTB TDI TPOHCLK[2] TPOH[1] TPOHCLK[1] SCPI[1]
E
DMRDAT[0]
SS[1]/
Res. Input
DMRDAT[3]
SS[4]/
DMRDAT[2]
SS[3]/
DMRDAT[1]
SS[0]/
DMROCLK
SS[9]/
DMRDAT[7]
SS[8]/
DMRDAT[6]
SS[6]/
DMRDAT[4]
VDD
VSS
SS[12]/
Res. Output
SS[10]/
Res. Output
SS[7]/
DMRDAT[5]
SS[15]/
DMTDAT[1]
SS[14]/
DMTDAT[0]
SS[13]/
DMTICLK
SS[11]/
Res. Output
SS[19]/
DMTDAT[5]
SS[18]/
DMTDAT[4]
SS[17]/
DMTDAT[3]
SS[16]/
DMTDAT[2]
VSS VSS
SS[21]/
DMTDAT[7]
SS[20]/
DMTDAT[6]
VDD
SS[22]/
Res. Input
SS[23]/
Res. Input
SS[25]/
Res. Input
SS[24]/
SS[28]/
SS[32]/
Res. Input
DMTOCLK
SS[26]/
SS[29]/
Res. Input
Res. Output
SS[27]/
SS[31]/
Res. Input
Res. Output
SS[30]/
VDD TPOHFP[3] TPOHFP[2] VDD TPOH[2] TPOHFP[1] TPOHEN[1]
Res. Output
SCPO[0] TPOH[3] VSS VSS VSS
Res. Input
SS[33]/
SCPO[1] TPOHCLK[3] VDD VDD VSS
Res. Input
SS[34]/
TPOHEN[3] TPOHEN[2] VDD VDD VSS
Res. Input
A
B
C
D
E
B3E[2] RALM[2] RALM[3] RAD SCPI[0] ALE CSB WRB/RWB
F
RTCOH[3] RTCEN[3] RALM[1] VDD VDD RDB/E MBEB A[0]
G
RTCOH[1] RTCOH[2] RTCEN[2] B3E[1] INTB A[1] A[3] VSS
H
VSS RPOH[3] RPOHCLK[3] RTCEN[1] A[2] A[4] A[5] A[6]
J
VSS RPOHFP[3] RPOHCLK[2] VDD
K
RXC RPOH[2] RPOHFP[2] RCLK VDD D[1] D[2] VSS
L
RFP RPOHCLK[1] RPOH[1] LOF D[6] D[4] D[3] VSS
M
VSS RPOHFP[1] SALM RLDCLK TACK TFP D[7] D[5]
N
LOS ROHCLK ROH VDD VDD TCLK TTOHFP TAFP
P
RLD RLOW RSUC RSLD TLD TSLDCLK TSLD TAD
R
RSLDCLK ROWCLK RSOW RTOHFP TSOW TTOHCLK TOH TOHCLK
T
LAIS LRDI RTOHCLK VDD RBYP RAVD2 NC_A RAVS4 ALOS- NC_B TAVD3 TAVD1 RLAIS VDD TLRDI TTOHEN VDD TLOW TSUC TLDCLK
U
VSS VDD VDD RTOH RAVS2 RAVS1 QAVS1 RAVD4 ALOS+ RAVD3 QAVD3 TAVS3 TAVD2 NC5 NC1 NC2 TOWCLK VDD VDD VSS
V
VSS VDD VDD TATP C1 RAVD1 RRCLK- RAVS3 RXD+ RXD- QAVS2 TRCLK+ TAVS1 NC4 TBYP TXD+ TTOH VDD VDD VSS
W
VSS VSS VSS RATP C2 QAVD1 RRCLK+ NC_F NC_C NC_D QAVD2 TRCLK- NC_E TAVS2 TLAIS TXD- TXC VSS VSS VSS
Y
BOTTOM VIEW
A[7] A[8] A[9] D[0]
2019181716151413121110987654321
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 23
PM5342 SPECTRA-155
DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
Figure 14 - Pin diagram: Nibble Data Mode (SMODE[2:0]=100)
2019181716151413121110987654321
SS[2]/
SS[5]/
VSS VSS VSS SMODE[1]
A
VSS VDD VDD SMODE[0]
B
VSS VDD VDD NC3 SMODE[2]
C
TMS TCK TDO VDD TRIS_OHB
D
B3E[3] RSTB TRSTB TDI TPOHCLK[2] TPOH[1] TPOHCLK[1] SCPI[1]
E
DMRDAT[0]
SS[1]/
Res. Input
DMRDAT[3]
SS[4]/
DMRDAT[2]
SS[3]/
DMRDAT[1]
SS[0]/
DMROCLK
SS[9]/
Res. Output
SS[8]/
Res. Output
SS[6]/
Res. Output
VDD
VSS
SS[12]/
Res. Output
SS[10]/
Res. Output
SS[7]/
Res. Output
SS[15]/
DMTDAT[1]
SS[14]/
DMTDAT[0]
SS[13]/
DMTICLK
SS[11]/
Res. Output
SS[19]/
Res. Input
SS[18]/
Res. Input
SS[17]/
DMTDAT[3]
SS[16]/
DMTDAT[2]
VSS VSS
SS[21]/
Res. Input
SS[20]/
Res. Input
VDD
SS[22]/
Res. Input
SS[23]/
Res. Input
SS[25]/
DMTMSN
SS[24]/
SS[28]/
SS[32]/
Res. Input
DMTOCLK
SS[26]/
SS[29]/
Res. Input
Res. Output
SS[27]/
SS[31]/
Res. Input
Res. Output
SS[30]/
VDD TPOHFP[3] TPOHFP[2] VDD TPOH[2] TPOHFP[1] TPOHEN[1]
Res. Output
SCPO[0] TPOH[3] VSS VSS VSS
Res. Input
SS[33]/
SCPO[1] TPOHCLK[3] VDD VDD VSS
Res. Input
SS[34]/
TPOHEN[3] TPOHEN[2] VDD VDD VSS
Res. Input
A
B
C
D
E
B3E[2] RALM[2] RALM[3] RAD SCPI[0] ALE CSB WRB/RWB
F
RTCOH[3] RTCEN[3] RALM[1] VDD VDD RDB/E MBEB A[0]
G
RTCOH[1] RTCOH[2] RTCEN[2] B3E[1] INTB A[1] A[3] VSS
H
VSS RPOH[3] RPOHCLK[3] RTCEN[1] A[2] A[4] A[5] A[6]
J
VSS RPOHFP[3] RPOHCLK[2] VDD
K
RXC RPOH[2] RPOHFP[2] RCLK VDD D[1] D[2] VSS
L
RFP RPOHCLK[1] RPOH[1] LOF D[6] D[4] D[3] VSS
M
VSS RPOHFP[1] SALM RLDCLK TACK TFP D[7] D[5]
N
LOS ROHCLK ROH VDD VDD TCLK TTOHFP TAFP
P
RLD RLOW RSUC RSLD TLD TSLDCLK TSLD TAD
R
RSLDCLK ROWCLK RSOW RTOHFP TSOW TTOHCLK TOH TOHCLK
T
LAIS LRDI RTOHCLK VDD RBYP RAVD2 NC_A RAVS4 ALOS- NC_B TAVD3 TAVD1 RLAIS VDD TLRDI TTOHEN VDD TLOW TSUC TLDCLK
U
VSS VDD VDD RTOH RAVS2 RAVS1 QAVS1 RAVD4 ALOS+ RAVD3 QAVD3 TAVS3 TAVD2 NC5 NC1 NC2 TOWCLK VDD VDD VSS
V
VSS VDD VDD TATP C1 RAVD1 RRCLK- RAVS3 RXD+ RXD- QAVS2 TRCLK+ TAVS1 NC4 TBYP TXD+ TTOH VDD VDD VSS
W
VSS VSS VSS RATP C2 QAVD1 RRCLK+ NC_F NC_C NC_D QAVD2 TRCLK- NC_E TAVS2 TLAIS TXD- TXC VSS VSS VSS
Y
BOTTOM VIEW
A[7] A[8] A[9] D[0]
2019181716151413121110987654321
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 24
PM5342 SPECTRA-155
DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
Figure 15 - Pin diagram: Serial Data Mode (SMODE[2:0]=101)
2019181716151413121110987654321
SS[5]/
SDMROCLK
[2]
SS[4]/
SDMROCLK
[1]
SS[3]/
Res. Input
SS[0]/
Res. Input
SS[9]/
SDMRDAT[3]
SS[8]/
SDMRDAT[2]
SS[6]/
SDMROCLK
[3]
VDD
VSS VSS VSS SMODE[1]
A
VSS VDD VDD SMODE[0]
B
VSS VDD VDD NC3 SMODE[2]
C
TMS TCK TDO VDD TRIS_OHB
D
B3E[3] RSTB TRSTB TDI TPOHCLK[2] TPOH[1] TPOHCLK[1] SCPI[1]
E
SS[2]/
Res. Input
SS[1]/
Res. Input
VSS
SS[12]/
Res. Output
SS[10]/
Res. Output
SS[7]/
SDMRDAT[1]
SS[15]/
SDMTICLK[3]
SS[14]/
SDMTICLK[2]
SS[13]/
SDMTICLK[1]
SS[11]/
Res. Output
SS[19]/
SDMTDAT[1]
SS[18]/
Res. Input
SS[17]/
Res. Input
SS[16]/
Res. Input
VSS VSS
SS[21]/
SDMTDAT[3]
SS[20]/
SDMTDAT[2]
VDD
SS[22]/
Res. Input
SS[23]/
Res. Input
SS[25]/
Res. Input
SS[28]/
SS[24]/
Res. Input
SS[26]/
Res. Input
SS[27]/
SDMTOCLK
[1]
SS[30]/
Res. Output
SS[32]/
SDMTOCLK
[2]
SS[29]/
SDMTOCLK
[3]
SS[31]/
Res. Output
VDD TPOHFP[3] TPOHFP[2] VDD TPOH[2] TPOHFP[1] TPOHEN[1]
SCPO[0] TPOH[3] VSS VSS VSS
Res. Input
SS[33]/
SCPO[1] TPOHCLK[3] VDD VDD VSS
Res. Input
SS[34]/
TPOHEN[3] TPOHEN[2] VDD VDD VSS
Res. Input
A
B
C
D
E
B3E[2] RALM[2] RALM[3] RAD SCPI[0] ALE CSB WRB/RWB
F
RTCOH[3] RTCEN[3] RALM[1] VDD VDD RDB/E MBEB A[0]
G
RTCOH[1] RTCOH[2] RTCEN[2] B3E[1] INTB A[1] A[3] VSS
H
VSS RPOH[3] RPOHCLK[3] RTCEN[1] A[2] A[4] A[5] A[6]
J
VSS RPOHFP[3] RPOHCLK[2] VDD
K
RXC RPOH[2] RPOHFP[2] RCLK VDD D[1] D[2] VSS
L
RFP RPOHCLK[1] RPOH[1] LOF D[6] D[4] D[3] VSS
M
VSS RPOHFP[1] SALM RLDCLK TACK TFP D[7] D[5]
N
LOS ROHCLK ROH VDD VDD TCLK TTOHFP TAFP
P
RLD RLOW RSUC RSLD TLD TSLDCLK TSLD TAD
R
RSLDCLK ROWCLK RSOW RTOHFP TSOW TTOHCLK TOH TOHCLK
T
LAIS LRDI RTOHCLK VDD RBYP RAVD2 NC_A RAVS4 ALOS- NC_B TAVD3 TAVD1 RLAIS VDD TLRDI TTOHEN VDD TLOW TSUC TLDCLK
U
VSS VDD VDD RTOH RAVS2 RAVS1 QAVS1 RAVD4 ALOS+ RAVD3 QAVD3 TAVS3 TAVD2 NC5 NC1 NC2 TOWCLK VDD VDD VSS
V
VSS VDD VDD TATP C1 RAVD1 RRCLK- RAVS3 RXD+ RXD- QAVS2 TRCLK+ TAVS1 NC4 TBYP TXD+ TTOH VDD VDD VSS
W
VSS VSS VSS RATP C2 QAVD1 RRCLK+ NC_F NC_C NC_D QAVD2 TRCLK- NC_E TAVS2 TLAIS TXD- TXC VSS VSS VSS
Y
BOTTOM VIEW
A[7] A[8] A[9] D[0]
2019181716151413121110987654321
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 25
PM5342 SPECTRA-155
DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
Figure 16 - Pin diagram: Serial DS3 Mode (SMODE[2:0]=110)
2019181716151413121110987654321
SS[5]/
DS3ROCLK
[2]
SS[4]/
DS3ROCLK
[1]
SS[3]/
DS3RICLK[3]
SS[0]/
DS3RICLK[1]
SS[9]/
DS3RDAT[3]
SS[8]/
DS3RDAT[2]
SS[6]/
DS3ROCLK
[3]
VDD
VSS VSS VSS SMODE[1]
A
VSS VDD VDD SMODE[0]
B
VSS VDD VDD NC3 SMODE[2]
C
TMS TCK TDO VDD TRIS_OHB
D
B3E[3] RSTB TRSTB TDI TPOHCLK[2] TPOH[1] TPOHCLK[1] SCPI[1]
E
SS[2]/
DS3RICLK[2]
SS[1]/
Res. Input
VSS
SS[12]/
Res. Output
SS[10]/
Res. Output
SS[7]/
DS3RDAT[1]
SS[15]/
DS3TICLK[3]
SS[14]/
DS3TICLK[2]
SS[13]/
DS3TICLK[1]
SS[11]/
Res. Output
SS[19]/
DS3TDAT[1]
SS[18]/
DS3RAIS[3]
SS[17]/
DS3RAIS[2]
SS[16]/
DS3RAIS[1]
VSS VSS
SS[21]/
DS3TDAT[3]
SS[20]/
DS3TDAT[2]
VDD
SS[22]/
Res. Input
SS[23]/
Res. Input
SS[25]/
Res. Input
SS[24]/
SS[28]/
SS[32]/
Res. Input
Res. Output
SS[26]/
SS[29]/
Res. Input
Res. Output
SS[27]/
SS[31]/
Res. Output
Res. Output
SS[30]/
VDD TPOHFP[3] TPOHFP[2] VDD TPOH[2] TPOHFP[1] TPOHEN[1]
Res. Output
SCPO[0] TPOH[3] VSS VSS VSS
DS3TAIS[1]
SS[33]/
SCPO[1] TPOHCLK[3] VDD VDD VSS
DS3TAIS[2]
SS[34]/
TPOHEN[3] TPOHEN[2] VDD VDD VSS
DS3TAIS[3]
A
B
C
D
E
B3E[2] RALM[2] RALM[3] RAD SCPI[0] ALE CSB WRB/RWB
F
RTCOH[3] RTCEN[3] RALM[1] VDD VDD RDB/E MBEB A[0]
G
RTCOH[1] RTCOH[2] RTCEN[2] B3E[1] INTB A[1] A[3] VSS
H
VSS RPOH[3] RPOHCLK[3] RTCEN[1] A[2] A[4] A[5] A[6]
J
VSS RPOHFP[3] RPOHCLK[2] VDD
K
RXC RPOH[2] RPOHFP[2] RCLK VDD D[1] D[2] VSS
L
RFP RPOHCLK[1] RPOH[1] LOF D[6] D[4] D[3] VSS
M
VSS RPOHFP[1] SALM RLDCLK TACK TFP D[7] D[5]
N
LOS ROHCLK ROH VDD VDD TCLK TTOHFP TAFP
P
RLD RLOW RSUC RSLD TLD TSLDCLK TSLD TAD
R
RSLDCLK ROWCLK RSOW RTOHFP TSOW TTOHCLK TOH TOHCLK
T
LAIS LRDI RTOHCLK VDD RBYP RAVD2 NC_A RAVS4 ALOS- NC_B TAVD3 TAVD1 RLAIS VDD TLRDI TTOHEN VDD TLOW TSUC TLDCLK
U
VSS VDD VDD RTOH RAVS2 RAVS1 QAVS1 RAVD4 ALOS+ RAVD3 QAVD3 TAVS3 TAVD2 NC5 NC1 NC2 TOWCLK VDD VDD VSS
V
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 26
PM5342 SPECTRA-155
DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER

8 PIN DESCRIPTION (256)

Table 2 - Line Side Interface Signals (20)
Pin Name
Pin Type
PIN No.
Function
RBYP Input U16 The receive bypass (RBYP) input selects whether
to bypass the CRU. If RBYP is high, the internal CRU is bypassed and RRCLK+/- should contain the receive line clock used to sample RXD+/-. If RBYP is low, the internal CRU is used and RRCLK+/- should contain the reference clock.
RXD+ RXD-
PECL Input
W12 W11
The receive differential data inputs (RXD+, RXD-) contain the 155.52 Mbit/s receive STS-3/3c (STM-1/AU3/AU4) stream or the 51.84 Mbit/s receive STS-1 (STM-0/AU3) stream. RXD+/- are sampled on the rising edge of RRCLK+/- when clock recovery is disabled (the falling edge may be used by reversing RRCLK+/-). Otherwise the receive clocks are recovered from the RXD+/- bit stream. RXD+/- is expected to be NRZ encoded.
Clock recovery bypass is selectable using the RBYP input signal.
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PM5342 SPECTRA-155
DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
Pin Name
RRCLK+ RRCLK-
Pin Type
PECL/ Schmitt TTL Input
PIN No.
Y14 W14
Function
The receive differential reference clock inputs (RRCLK+, RRCLK-) contain a jitter-free 19.44 MHz or 6.48 MHz reference clock when clock recovery is enabled. When clock recovery is bypassed, RRCLK+/- is nominally a 155.52 MHz or 51.84 MHz, 50% duty cycle clock and provide timing for the SPECTRA-155 receive functions. In this case, RXD+/- is sampled on the rising edge of RRCLK+/-.
Clock recovery bypass is selectable using the RBYP input signal. In addition, RRCLK+/- can also be used to provide the clock synthesis unit's clock reference using the TREFSRC bit in the SPECTRA-155 Clock Synthesis Control and Status register.
The 6.48 MHz reference clock supports only STS­1 (STM-0/AU3) operation when clock recovery is enabled.
ALOS+ ALOS-
PECL/ Schmitt TTL Input
V12 U12
The 19.44 MHz reference clock supports both STS-1 (STM-0/AU3) and STS-3/3c (STM­1/AU3/AU4) operation when clock recovery is enabled.
For TTL operation, please refer to the Operations section.
The analog loss of signal (ALOS+/-) differential inputs are used to indicate a loss of receive signal power. When ALOS+/- is asserted, the data on the receive data (RXD+/-) pins is forced to all zeros and the phase locked loop switches to the reference clock (RRCLK+/- or TRCLK+/-) to keep the recovered clock in range.
These inputs must be DC coupled. Please refer to the Operation section for a discussion of PECL interfacing issues.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 28
PM5342 SPECTRA-155
DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
Pin Name
Pin Type
PIN No.
Function
RCLK Output L17 The receive clock (RCLK) output provides a timing
reference for the SPECTRA-155 receive line interface outputs. For STS-3/3c (STM­1/AU3/AU4) operation, RCLK is nominally 19.44 MHz. For STS-1 (STM-0/AU3) RCLK is nominally
6.48. RCLK is a divide by eight of the recovered clock or the RRCLK+/- inputs as determined using the RBYP input signal.
When not used, RCLK can be held low using the RCLKEN bit in the SPECTRA-155 Clock Control register.
RXC Output L20 The receive clock (RXC) output provides a 51.84
MHz timing reference. RXC is a 51.84 MHz, nominally 50% duty cycle clock. For STS-3/3c (STM-1/AU3/AU4) mode, RXC is a divide by three of the recovered clock or the RRCLK+/- inputs as determined using the RBYP input signal. For STS-1 (STM-0/AU3) mode, RXC is the recovered clock or the RRCLK+/- inputs as determined using the RBYP input signal.
RFP Tristate
Output
When not used, RXC can be held low using the RXCEN bit in the SPECTRA-155 Clock Control register.
M20 The receive frame pulse (RFP) output is an 8 KHz
signal derived from the receive line clock. RFP is pulsed high for one RCLK cycle every 2430 RCLK cycles for STS-3c (STM-1/AU4) or every 810 RCLK cycles for STS-1 (STM-0/AU3). A single discontinuity in RFP position occurs if a change of frame alignment occurs.
RFP can be tristated using the TRIS_OHB input and the ROH_TS bit in the SPECTRA-155 Receive Overhead Output Control register. On reset, RFP will be tristate if TRIS_OHB is low.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 29
PM5342 SPECTRA-155
DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
Pin Name
Pin Type
PIN No.
Function
TBYP Input W6 The transmit bypass (TBYP) input selects whether
to bypass the CSU. If TBYP is high, the internal CSU is bypassed and TRCLK+/- should contain the transmit line clock used to output data on TXD+/-. If TBYP is low, the internal CSU is used and TRCLK+/- should contain the reference clock.
TRCLK+ TRCLK-
PECL/ Schmitt TTL Input
W9 Y9
The transmit differential reference clock inputs (TRCLK+, TRCLK-) are a jitter-free 19.44 MHz or
6.48 MHz reference clock when clock synthesis is enabled. When clock synthesis is bypassed, TRCLK+/- is nominally a 155.52 MHz or 51.84 MHz, 50% duty cycle clock. This clock provides timing for the SPECTRA-155 transmit functions. TRCLK+/- may be left unconnected when SPECTRA-155 loop timing is enabled using the SPECTRA-155 Configuration Register.
Clock synthesis bypass is selectable using the TBYP input signal. In addition, TRCLK+/- can also be used to provide the clock recovery unit's clock reference using the RREFSRC bit in the SPECTRA-155 Clock Recovery Control and Status register.
The 6.48 MHz reference clock supports only STS­1 (STM-0/AU3) operation when clock synthesis is enabled.
The 19.44 MHz reference clock supports both STS-1 (STM-0/AU3) and STS-3/3c (STM­1/AU3/AU4) operation when clock synthesis is enabled.
For TTL operation, please refer to the Operations section.
TXC Output Y4 The transmit clock (TXC) output is available when
STS-1 (STM-0/AU3) mode of operation is selected using the SPECTRA-155 Configuration register. In STS-1 mode, TXD+/- are updated on the falling edge of TXC.
When not used, TXC can be held low using the TXCEN bit in the SPECTRA-155 Clock Control register.
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PM5342 SPECTRA-155
DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
Pin Name
TXD+ TXD-
Pin Type
PIN No.
Output W5
Y5
Function
The transmit differential data outputs (TXD+, TXD­) contain the 155.52 Mbit/s transmit STS-3/3c (STM-1/AU3/AU4) stream or the 51.84 Mbit/s transmit STS-1 (STM-0/AU3) stream. When the STS-1 (STM-0/AU3) stream is selected, TXD+/­are updated on the falling edge of TXC. TXD+/- is NRZ encoded.
TCLK Output P3 The transmit byte clock (TCLK) output provides a
timing reference for the SPECTRA-155 transmit line interface outputs. For STS-3/3c (STM­1/AU3/AU4) operation, TCLK is nominally 19.44 MHz. For STS-1 (STM-0/AU3) TCLK is nominally
6.48. TCLK is a divide by eight of the synthesized clock or the TRCLK+/- inputs as determined using the TBYP input signal.
When not used, TCLK can be held low using the TCLKEN bit in the SPECTRA-155 Clock Control register.
TFP Tristate
Output
C1
Analog W16
C2
N3 The active high transmit framing position (TFP)
signal is an 8 KHz timing marker for the transmitter. TFP goes high for a single TCLK period once every 2430 in STS-3/3c (STM-1/AU3/AU4) mode or 810 in STS-1 (STM-0/AU3) mode TCLK cycles. TFP is updated on the rising edge of TCLK.
TFP can be tristate using the TRIS_OHB input and the TOH_TS bit in the SPECTRA-155 Transmit Overhead Input Control register. On reset, TFP will be tristate if TRIS_OHB is low.
The analog C1 and C2 pins are provided for
Y16
connecting an external loop-filter capacitor. A 1 nF ceramic capacitor is required.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 31
PM5342 SPECTRA-155
DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
Table 3 - Section and Line Status/Overhead Interface Signals (36)
Pin Name Pin
Type
PIN No.
Function
TRIS_OHB Input D16 The active low tristate overhead (TRIS_OHB)
input enables software registers to control the tristating of the overhead output signals, RSLD, RSLDCLK, TSLDCLK, ROHCLK, ROH, RFP, TOHCLK and TFP. When TRIS_OHB is low, tristating of outputs RSLD, RSLDCLK, ROHCLK, ROH and RFP are controlled using the SPECTRA-155 Receive Overhead Output Control register while outputs TSLDCLK, TOHCLK and TFP are controlled using the SPECTRA-155 Transmit Overhead Input Control register. When TRIS_OHB is high, the above outputs are always driven.
TRIS_OHB has an integral pull up resistor.
SALM Output N18 The section alarm (SALM) output is set high
when an out of frame (OOF), loss of signal (LOS), loss of frame (LOF), line alarm indication signal (LAIS) or line remote defect indication (LRDI) alarm is detected. Each alarm indication can be independently enabled using bits in the SPECTRA-155 Section Alarm Output Control register. SALM is set low when none of the enabled alarms are active.
The out of frame (OOF) alarm is indicated while the SPECTRA-155 is unable to find a valid framing pattern (A1, A2) in the incoming stream. The SALM is configured to indicate only the OOF condition as a default after a device reset to optionally provide a dedicated output pin for this alarm. Please refer to the (optionally) dedicated output pins for LOS, LOF, LAIS and LRDI for the description of these alarms.
SALM is updated on the rising edge of RCLK.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 32
PM5342 SPECTRA-155
DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
Pin Name Pin
Type
PIN No.
Function
LOS/ Output P20 Loss of signal (LOS) is active when the ring
control port is disabled. Loss of signal (LOS) is set high when a violating period (20 ± 2.5 µs) of consecutive all zeros patterns is detected in the incoming stream. LOS is set low when two valid framing words (A1, A2) are detected, and during the intervening time (125 µs), no violating period of all zeros patterns is observed. LOS is updated on the rising edge of RCLK.
RRCPFP The receive ring control port frame position
(RRCPFP) signal identifies bit positions in the receive ring control port data (RRCPDAT) when the ring control port is enabled (the enabling and disabling of the ring control port is controlled by a bit in the SPECTRA-155 Section/Line Control/Enable Register). RRCPFP is high during the filtered K1, K2 bit positions, the change of APS value bit position, the protection switch byte failure bit position, and the send line AIS and send line RDI bit positions in the RRCPDAT stream. RRCPFP is normally connected to the TRCPFP input of a mate SPECTRA-155 in ring-based add-drop multiplexer applications. RRCPFP is updated on the falling edge of RRCPCLK.
LOF Output M17 The loss of frame (LOF) signal is set high when
an out of frame state persists for 3 ms. LOF is set low when an in frame state persists for 3 ms. LOF is updated on the rising edge of RCLK.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 33
PM5342 SPECTRA-155
DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
Pin Name Pin
Type
PIN No.
Function
LRDI/ Output U19 The line remote defect indication (LRDI) signal
is active when the ring control port is disabled. LRDI is set high when line RDI is detected in the incoming stream. LRDI is declared when a 110 binary pattern is detected in bits 6, 7, and 8 of the K2 byte for three or five consecutive frames. LRDI is removed when any pattern other than 110 is detected in bits 6, 7, and 8 of the K2 byte for three or five consecutive frames. This alarm indication is also available through register access. LRDI is updated on the rising edge of RCLK.
RRCPCLK The receive ring control port clock (RRCPCLK)
signal provides timing for the receive ring control port when the ring control port is enabled (the enabling and disabling of the ring control port is controlled by a bit in the SPECTRA-155 Section/Line Control/Enable Register). RRCPCLK is nominally a 3.24 MHz, 50% duty cycle clock and is normally connected to the TRCPCLK input of a mate SPECTRA-155 in ring-based add-drop multiplexer applications. RRCPFP and RRCPDAT are updated on the falling edge of RRCPCLK.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 34
PM5342 SPECTRA-155
DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
Pin Name Pin
Type
PIN No.
Function
LAIS/ Output U20 The line alarm indication (LAIS) signal is active
when the ring control port is disabled. LAIS is set high when line AIS is detected in the incoming stream. LAIS is declared when a 111 binary pattern is detected in bits 6, 7, and 8 of the K2 byte for three or five consecutive frames. LAIS is removed when any pattern other than 111 is detected in bits 6, 7, and 8 of the K2 byte for three or five consecutive frames. This alarm indication is also available through register access. LAIS is updated on the rising edge of RCLK.
RRCPDAT The receive ring control port data (RRCPDAT)
signal contains the receive ring control port data stream when the ring control port is enabled (the enabling and disabling of the ring control port is controlled by a bit in the SPECTRA-155 Section/Line Control/Enable Register). The receive ring control port data consists of the filtered K1, K2 byte values, the change of APS value bit position, the protection switch byte failure status bit position, the send line AIS and send line RDI bit positions, and the line REI bit positions. RRCPDAT is normally connected to the TRCPDAT input of a mate SPECTRA-155 in ring-based add-drop multiplexer applications. RRCPDAT is updated on the falling edge of RRCPCLK.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 35
PM5342 SPECTRA-155
DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
Pin Name Pin
Type
PIN No.
Function
RLAIS/ Input U8 The receive line AIS insertion (RLAIS) signal
controls the insertion of line AIS in the receive outgoing stream, when the ring control port is disabled. When RLAIS is high, line AIS is inserted in the outgoing stream. Line AIS is also optionally inserted automatically upon detection of loss of signal, loss of frame, section trace alarms or line AIS in the incoming stream. RLAIS is sampled on the rising edge of RCLK.
TRCPCLK The transmit ring control port clock (TRCPCLK)
signal provides timing for the transmit ring control port when the ring control port is enabled (the enabling and disabling of the ring control port is controlled by a bit in the SPECTRA-155 Section/Line Control/Enable Register). TRCPCLK is nominally a 3.24 MHz, 50% duty cycle clock and is normally connected to the RRCPCLK output of a mate SPECTRA-155 in ring-based add-drop multiplexer applications. TRCPFP and TRCPDAT are sampled on the rising edge of TRCPCLK.
RSLDCLK Tristate
Output
T20 The receive section/line DCC clock (RSLDCLK)
can either be used to clock out the section or line DCC as selected using the RDLSEL bit in the SPECTRA-155 Receive Overhead Output Control register.
When section DCC is selected, RSLDCLK is a 192 KHz clock used to update the RSLD output. RSLDCLK is generated by gapping a 216 KHz clock.
When line DCC is selected, RSLDCLK is a 576 KHz clock used to update the RSLD output. RSLDCLK is generated by gapping a 2.16 MHz clock.
RSLDCLK can be tristate using the TRIS_OHB input and the RSLD_TS bit in the SPECTRA-155 Receive Overhead Output Control register. On reset, RSLDCLK will be tristate if TRIS_OHB is low.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 36
PM5342 SPECTRA-155
DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
Pin Name Pin
Type
RSLD Tristate
Output
PIN
Function
No.
R17 The receive section/line DCC (RSLD) signal
contains the section data communications channel (D1-D3) or the line data communications channel (D4-D12) as selected using the RDLSEL bit in the SPECTRA-155 Receive Overhead Output Control register.
RSLD can be tristate using the TRIS_OHB input and the RSLD_TS bit in the SPECTRA-155 Receive Overhead Output Control register. On reset, RSLD will be tristate if TRIS_OHB is low. RSLD is updated on the falling edge of RSLDCLK.
ROWCLK Output T19 The receive order wire clock (ROWCLK) is a 64
KHz clock used to update the RSOW, RSUC, and RLOW outputs. If selected using the R64SEL bit in the SPECTRA-155 Receive Overhead Output Control register, ROWCLK is generated by gapping a 72 KHz clock; otherwise, ROWCLK is not gapped.
RSOW Output T18 The receive section order wire (RSOW) signal
contains the section order wire channel (E1) extracted from the incoming stream. RSOW is updated on the falling edge of ROWCLK.
RSUC Output R18 The receive section user channel (RSUC) signal
contains the section user channel (F1) extracted from the incoming stream. RSUC is updated on the falling edge of ROWCLK.
RLOW Output R19 The receive line order wire (RLOW) signal
contains the line order wire channel (E2) extracted from the incoming stream. RLOW is updated on the falling edge of ROWCLK.
RLDCLK Output N17 The receive line DCC clock (RLDCLK) is a 576
KHz clock used to update the RLD output. RLDCLK is generated by gapping a 2.16 MHz clock.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 37
PM5342 SPECTRA-155
DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
Pin Name Pin
Type
PIN No.
Function
RLD Output R20 The receive line DCC (RLD) signal contains the
line data communications channel (D4 - D12) extracted from the incoming stream. RLD is updated on the falling edge of RLDCLK.
ROHCLK Tristate
Output
P19 The receive overhead clock (ROHCLK) can be
selected to clock out either the section orderwire (E1), the line orderwire (E2), the line user channel (F1) or the automatic protection switch channel (K1, K2). Selection of the receive overhead clock is made using the ROHSEL bits in the SPECTRA-155 Receive Overhead Output Control register.
When either orderwire or user channel clocks are selected, ROHCLK is a 64 KHz clock used to update the ROH output. If selected using the R64SEL bit in the SPECTRA-155 Receive Overhead Output Control register, ROHCLK is generated by gapping a 72 KHz clock; otherwise, ROHCLK is not gapped.
When the receive automatic protection switch channel clock is selected, ROHCLK is a 128 KHz clock used to update the ROH output. ROHCLK is generated by gapping a 144 KHz clock.
ROHCLK can be tristate using the TRIS_OHB input and the ROH_TS bit in the SPECTRA-155 Receive Overhead Output Control register. On reset, ROHCLK will be tristate if TRIS_OHB is low.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 38
PM5342 SPECTRA-155
DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
Pin Name Pin
Type
ROH Tristate
Output
PIN
Function
No.
P18 The receive overhead (ROH) output can be
selected to carry either the section orderwire (E1), the line orderwire (E2), the line user channel (F1) or the automatic protection switch channel (K1, K2). Selection is made using the ROHSEL bits in the SPECTRA-155 Receive Overhead Output Control register.
ROH can be tristate using the TRIS_OHB input and the ROH_TS bit in the SPECTRA-155 Receive Overhead Output Control register. On reset, ROH will be tristate if TRIS_OHB is low. ROH is updated on the falling edge of ROHCLK.
RTOHCLK Output U18 The receive transport overhead clock
(RTOHCLK) is nominally a 5.184 MHz or 1.728 MHz clock that provides timing to process the extracted receive transport overhead, RTOH. RTOHCLK is a gapped 6.48 MHz clock when accessing the transport overhead of an STS-3/3c (STM-1/AU3/AU4) stream. RTOHCLK is a gapped 2.16 MHz clock when accessing the transport overhead of an STS-1 (STM-0/AU3) stream.
RTOH Output V17 The receive transport overhead (RTOH) signal
contains the receive transport overhead bytes (A1, A2, J0, Z0, B1, E1, F1, D1-D3, H1-H3, B2, K1, K2, D4-D12, Z1/S1, Z2/M1, and E2) extracted from the incoming stream. RTOH is updated on the falling edge of RTOHCLK.
RTOHFP Output T17 The receive transport overhead frame position
(RTOHFP) signal is used to locate the individual receive transport overhead bits in the receive transport overhead, RTOH. RTOHFP is set high while bit 1 (the most significant bit) of the first framing byte (A1) is present in the RTOH stream. RTOHFP is updated on the falling edge of RTOHCLK.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 39
PM5342 SPECTRA-155
DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
Pin Name Pin
Type
PIN No.
Function
TLRDI/ Input U6 The active high transmit line remote defect
indication (TLRDI) signal controls the insertion of a remote defect indication in the outgoing stream when the ring control port is disabled. When TLRDI is set high, bits 6, 7, and 8 of the K2 byte are set to the pattern 110. Line RDI may also be inserted using the LRDI bit in the TLOP Control Register, or upon detection of loss of signal, loss of frame, or line AIS in the receive stream, using the bits in the SPECTRA-155 Line RDI Control Register. The TLRDI input takes precedence over the TTOH and TTOHEN inputs. TLRDI is sampled on the rising edge of TCLK.
TRCPFP The transmit ring control port frame position
(TRCPFP) signal identifies bit positions in the transmit ring control port data (TRCPDAT) when the ring control port is enabled (the enabling and disabling of the ring control port is controlled by a bit in the SPECTRA-155 Section/Line Control/Enable Register). TRCPFP is high during the filtered K1, K2 bit positions, the change of APS value bit position, the protection switch byte failure bit position, and the send line AIS and send line RDI bit positions in the TRCPDAT stream. TRCPFP is normally connected to the RRCPFP output of a mate SPECTRA-155 in ring-based add-drop multiplexer applications. TRCPFP is sampled on the rising edge of TRCPCLK.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 40
PM5342 SPECTRA-155
DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
Pin Name Pin
Type
PIN No.
Function
TLAIS/ Input Y6 The active high transmit line alarm indication
signal (TLAIS) controls the insertion of line AIS in the outgoing stream when the ring control port is disabled. When TLAIS is set high, the complete frame (except the section overhead or regenerator section) is overwritten with the all ones pattern (before scrambling). The TLAIS input takes precedence over the TTOH and TTOHEN inputs. TLAIS is sampled on the rising edge of TCLK.
TRCPDAT The transmit ring control port data (TRCPDAT)
signal contains the transmit ring control port data stream when the ring control port is enabled (the enabling and disabling of the ring control port is controlled by a bit in the SPECTRA-155 Section/Line Control/Enable Register). The transmit ring control port data consists of the filtered K1, K2 byte values, the change of APS value bit position, the protection switch byte failure status bit position, the send line AIS and send line RDI bit positions, and the line REI bit positions. TRCPDAT is normally connected to the RRCPDAT output of a mate SPECTRA-155 in ring-based add-drop multiplexer applications. TRCPDAT is sampled on the rising edge of TRCPCLK.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 41
PM5342 SPECTRA-155
DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
Pin Name Pin
Type
TSLDCLK Tristate
Output
PIN
Function
No.
R3 The transmit section/line DCC clock (TSLDCLK)
can either be used to clock in the section or line DCC as selected using the TDLSEL bit in the SPECTRA-155 Transmit Overhead Input Control register.
When section DCC is selected, TSLDCLK is a 192 KHz clock used to sample the TSLD input. TSLDCLK is generated by gapping a 216 KHz clock.
When line DCC is selected, TSLDCLK is a 576 KHz clock used to sample the TSLD input. TSLDCLK is generated by gapping a 2.16 MHz clock.
TSLDCLK can be tristate using the TRIS_OHB input and the TSLDCLK_TS bit in the SPECTRA-155 Transmit Overhead Input Control register. On reset, TSLDCLK will be tristate if TRIS_OHB is low.
TSLD Input R2 The transmit section/line DCC (TSLD) signal
contains the section data communications channel (D1-D3) or the line data communications channel (D4-D12) as selected using the TDLSEL bit in the SPECTRA-155 Transmit Overhead Input Control register. The TTOHEN input takes precedence over TSLD. TSLD is sampled on the rising edge of TSLDCLK.
TOWCLK Output V4 The transmit order wire clock (TOWCLK) is a 64
KHz clock used to sample the TSOW, TSUC, and TLOW inputs. If selected using the T64SEL bit in the SPECTRA-155 Transmit Overhead Input Control register, TOWCLK is generated by gapping a 72 KHz clock; otherwise, TOWCLK is not gapped.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 42
PM5342 SPECTRA-155
DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
Pin Name Pin
Type
PIN No.
Function
TSOW Input T4 The transmit section order wire (TSOW) signal
contains the section order wire channel (E1) inserted into the outgoing stream. The TTOHEN input takes precedence over TSOW. TSOW is sampled on the rising edge of TOWCLK.
TSUC Input U2 The transmit section user channel (TSUC)
signal contains the section user channel (F1) inserted into the outgoing stream. The TTOHEN input takes precedence over TSUC. TSUC is sampled on the rising edge of TOWCLK.
TLOW Input U3 The transmit line order wire (TLOW) signal
contains the line order wire channel (E2) inserted into the outgoing stream. The TTOHEN input takes precedence over TLOW. TLOW is updated on the rising edge of TOWCLK.
TLDCLK Output U1 The transmit line DCC clock (TLDCLK) is a 576
KHz clock used to sample the TLD input. TLDCLK is generated by gapping a 2.16 MHz clock.
TLD Input R4 The transmit line DCC (TLD) signal contains the
line data communications channel (D4 - D12) inserted into the outgoing stream. The TTOHEN input takes precedence over TLD. TLD is sampled on the rising edge of TLDCLK.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 43
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DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
Pin Name Pin
Type
TOHCLK Tristate
Output
PIN
Function
No.
T1 The transmit overhead clock (TOHCLK) can be
selected to clock in either the section orderwire (E1), the line orderwire (E2), the line user channel (F1) or the automatic protection switch channel (K1, K2). Selection of the transmit overhead clock is made using the TOHSEL bits in the SPECTRA-155 Transmit Overhead Input Control register.
When either orderwire or user channel clocks are selected, TOHCLK is a 64 KHz clock used to sample the TOH input. If selected using the T64SEL bit in the SPECTRA-155 Transmit Overhead Input register, TOHCLK is generated by gapping a 72 KHz clock; otherwise, TOHCLK is not gapped.
When the transmit automatic protection switch channel clock is selected, TOHCLK is a 128 KHz clock used to sample the TOH input. TOHCLK is generated by gapping a 144 KHz clock.
TOHCLK can be tristate using the TRIS_OHB input and the TOHCLK_TS bit in the SPECTRA-155 Transmit Overhead Input Control register. On reset, TOHCLK will be tristate if TRIS_OHB is low.
TOH Input T2 The transmit overhead (TOH) input can be
selected to carry either the section orderwire (E1), the line orderwire (E2), the line user channel (F1) or the automatic protection switch channel (K1, K2). Selection is made using the TOHSEL bits in the SPECTRA-155 Transmit Overhead Input Control register. The TTOHEN and TPOHEN inputs take precedence over TOH. TOH is sampled on the rising edge of TOHCLK.
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DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
Pin Name Pin
Type
PIN No.
Function
TTOH Input W4 The transmit transport overhead bus (TTOH)
contains the transport overhead bytes (A1, A2, J0, Z0, E1, F1, D1-D3, H3, K1, K2, D4-D12, Z1/S1, Z2/M1, and E2) and error masks (H1, H2, B1, and B2) which may be inserted, or used to insert bit interleaved parity errors or payload pointer bit errors into the overhead byte positions in the outgoing stream. Insertion is controlled by the TTOHEN input. TTOH is sampled on the rising edge of TTOHCLK.
TTOHFP Output P2 The transmit transport overhead frame position
(TTOHFP) signal is used to locate the individual transport overhead bits in the transport overhead bus, TTOH. TTOHFP is set high while bit 1 (the most significant bit) of the first framing byte (A1) is expected in the incoming stream. TTOHFP is updated on the falling edge of TTOHCLK.
TTOHCLK Output T3 The transmit transport overhead clock
(TTOHCLK) is nominally a 5.184 MHz (1.728 MHz for STS-1) clock that provides timing for upstream circuitry that sources the transport overhead, TTOH. TTOHCLK is a gapped 6.48 MHz clock when accessing the transport overhead of STS-3/3c (STM-1/AU3/AU4) streams. TTOHCLK is a gapped 2.16 MHz clock when accessing the transport overhead of an STS-1 (STM-0/AU3) stream.
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DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
Pin Name Pin
Type
PIN No.
Function
TTOHEN Input U5 The transmit transport overhead insert enable
(TTOHEN) signal controls the source of the transport overhead data which is inserted in the transmit stream. While TTOHEN is high during the most significant bit of a TTOH byte, values sampled on the TTOH input are inserted into the corresponding transport overhead bit positions (for the A1, A2, J0, Z0, E1, F1, D1-D3, H3, K1, K2, D4-D12, Z1/S1, Z2/M1, and E2 bytes). While TTOHEN is low during the most significant bit of a TTOH byte, the default values are inserted into these transport overhead byte positions. The TTOHEN input take precedence over TOH.
A high level on TTOHEN during most significant bit of TTOH for the H1, H2, B1, or B2 bytes enables an error mask. While the error mask is enabled, a high level on TTOH causes the corresponding H1, H2, B1 or B2 bit positions to be inverted. When the section trace enable (STEN) bit is a logic 1, the J0 byte contents are sourced from the section trace buffer, regardless of the state of TTOHEN. A low level on TTOH allows the corresponding bit positions to pass through the SPECTRA-155 uncorrupted. TTOHEN is sampled on the rising edge of TTOHCLK.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 46
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DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
Table 4 - Path Status/Overhead Interface Signals (37)
Pin Name Pin
Type
B3E[3]
Output E20 B3E[2] B3E[1]
PIN No.
F20 H17
Function
The bit interleaved parity error signals (B3E[3:1]) signal is set high for one RPOHCLK period for each path BIP-8 error detected (up to eight per frame) or once if any of the BIP-8 bits are in error depending on whether BIP-8 errors are treated on a bit or block basis. Path BIP-8 errors are detected by comparing the extracted path BIP-8 byte (B3) with the computed BIP-8 for the previous frame. In STS-3c (STM-1/AU4) mode or STS-1 (STM-0/AU3) mode, only B3E[1] is active. B3E[3:1] is updated on the falling edge of RPOHCLK.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 47
PM5342 SPECTRA-155
DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
Pin Name Pin
Type
PIN No.
Function
RALM[1] Output G18 The Receive Alarm (RALM[1]) signal is the
logical OR of the LOP[1], PAIS[1], PRDI[1] , PERDI[1], LOM[1], LOPCON and PAISCON states. Each alarm can be individually enabled using bits in the SPECTRA-155 RALM[1] Output Control register. RALM[1] is updated on the falling edge of RCLK.
The loss of pointer signal (LOP[1]) indicates the loss of pointer state in STS-1 (STM­0/AU3) #1 of an STS-3 (STM-1/AU3) SONET/SDH stream. LOP[1] is set high when invalid STS-1 (STM-0/AU3) pointers are received in eight consecutive frames, or if eight consecutive enabled NDFs are detected in the STS-1 (STM-0/AU3) #1 stream. LOP[1] is active in STS-3c (STM-1/AU4) and STS-1 (STM-0/AU3) modes.
The path alarm indication signal (PAIS[1]) indicates the path AIS state associated with the STS-1 (STM-0/AU3) #1 of an STS-3 (STM-1/AU3) SONET/SDH stream. PAIS[1] is set high when an all ones pattern is observed in the STS-1 (STM-0/AU3) pointer bytes (H1 and H2) for three consecutive frames in the STS-1 (STM-0/AU3) #1 stream. PAIS[1] is active in STS-3c (STM-1/AU4) and STS-1 (STM-0/AU3) modes.
The path remote defect indication signal (PRDI[1]) indicates the path remote state associated with the STS-1 (STM-0/AU3) #1 of an STS-3 (STM-1/AU3) SONET/SDH stream. PRDI[1] is set high when the path RDI alarm bit (bit 5) of the path status (G1) byte is set high for five or ten consecutive frames. PRDI[1] is active in STS-3c (STM-1/AU4) and STS-1 (STM-0/AU3) modes.
The path enhanced remote defect indication signal (PERDI[1]) indicates the path enhanced remote state associated with the
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DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
Pin Name Pin
Type
PIN No.
Function
STS-1 (STM-0/AU3) #1 of an STS-3 (STM­1/AU3) SONET/SDH stream. PERDI[1] is set high when the path ERDI alarm code (bits 5,6,7) of the path status (G1) byte is set to the same alarm codepoint for five or ten consecutive frames. EPRDI[1] is active in STS-3c (STM-1/AU4) and STS-1 (STM-0/AU3) modes.
The loss of multiframe signal (LOM[1]) indicates the tributary multiframe synchronization status associated with the STS-1 (STM-0/AU3) #1 of an STS-3 (STM­1/AU3) SONET/SDH stream. LOM[1] is set high if a correct four frame sequence is not detected in eight frames. LOM[[1] is active in STS-3c (STM-1/AU4) and STS-1 (STM-0/AU3) modes.
The loss of pointer concatenation and path AIS concatenation signals (LOPCON and PAISCON) are the concatenated alarms for STS-3c (STM-1/AU4) SONET/SDH stream.
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DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
Pin Name Pin
Type
PIN No.
Function
RALM[2] Output F19 The Receive Alarm (RALM[2]) signal is the
logical OR of the LOP[2], PAIS[2], PRDI[2], PERDI[2] and LOM[2] states. Each alarm can be individually enabled using bits in the SPECTRA-155 RALM[2] Output Control register. RALM[2] is updated on the falling edge of RCLK.
The loss of pointer signal (LOP[2]) indicates the loss of pointer state in STS-1 (STM­0/AU3) #2 of an STS-3 (STM-1/AU3) SONET/SDH stream. LOP[2] is set high when invalid STS-1 (STM-0/AU3) pointers are received in eight consecutive frames, or if eight consecutive enabled NDFs are detected in the STS-1 (STM-0/AU3) #2 stream.
The path alarm indication signal (PAIS[2]) indicates the path AIS state associated with the STS-1 (STM-0/AU3) #2 of an STS-3 (STM-1/AU3) SONET/SDH stream. PAIS[2] is set high when an all ones pattern is observed in the STS-1 (STM-0/AU3) pointer bytes (H1 and H2) for three consecutive frames in the STS-1 (STM-0/AU3) #2 stream.
The path remote defect indication signal (PRDI[2]) indicates the path remote state associated with the STS-1 (STM-0/AU3) #2 of an STS-3 (STM-1/AU3) SONET/SDH stream. PRDI[2] is set high when the path RDI alarm bit (bit 5) of the path status (G1) byte is set high for five or ten consecutive frames.
The path enhanced remote defect indication signal (PERDI[2]) indicates the path enhanced remote state associated with the STS-1 (STM-0/AU3) #2 of an STS-3 (STM­1/AU3) SONET/SDH stream. PERDI[2] is set high when the path ERDI alarm code (bits 5,6,7) of the path status (G1) byte is set to the same alarm codepoint for five or ten consecutive frames.
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DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
Pin Name Pin
Type
PIN No.
Function
The loss of multiframe signal (LOM[2]) indicates the tributary multiframe synchronization status associated with the STS-1 (STM-0/AU3) #2 of an STS-3 (STM­1/AU3) SONET/SDH stream. LOM[2] is set high if a correct four frame sequence is not detected in eight frames.
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DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
Pin Name Pin
Type
PIN No.
Function
RALM[3] Output F18 The Receive Alarm (RALM[3]) signal is the
logical OR of the LOP[3], PAIS[3], PRDI[3], PERDI[3] and LOM[3] states. Each alarm can be individually enabled using bits in the SPECTRA-155 RALM[3] Output Control register. RALM[3] is updated on the falling edge of RCLK.
The loss of pointer signal (LOP[3]) indicates the loss of pointer state in STS-1 (STM­0/AU3) #3 of an STS-3 (STM-1/AU3) SONET/SDH stream. LOP[3] is set high when invalid STS-1 (STM-0/AU3) pointers are received in eight consecutive frames, or if eight consecutive enabled NDFs are detected in the STS-1 (STM-0/AU3) #3 stream.
The path alarm indication signal (PAIS[3]) indicates the path AIS state associated with the STS-1 (STM-0/AU3) #3 of an STS-3 (STM-1/AU3) SONET/SDH stream. PAIS[3] is set high when an all ones pattern is observed in the STS-1 (STM-0/AU3) pointer bytes (H1 and H2) for three consecutive frames in the STS-1 (STM-0/AU3) #3 stream.
The path remote defect indication signal (PRDI[3]) indicates the path remote state associated with the STS-1 (STM-0/AU3) #3 of an STS-3 (STM-1/AU3) SONET/SDH stream. PRDI[3] is set high when the path RDI alarm bit (bit 5) of the path status (G1) byte is set high for five or ten consecutive frames.
The path enhanced remote defect indication signal (PERDI[3]) indicates the path enhanced remote state associated with the STS-1 (STM-0/AU3) #3 of an STS-3 (STM­1/AU3) SONET/SDH stream. PERDI[3] is set high when the path ERDI alarm code (bits 5,6,7) of the path status (G1) byte is set to the same alarm codepoint for five or ten consecutive frames.
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DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
Pin Name Pin
Type
PIN No.
Function
The loss of multiframe signal (LOM[3]) indicates the tributary multiframe synchronization status associated with the STS-1 (STM-0/AU3) #3 of an STS-3 (STM­1/AU3) SONET/SDH stream. LOM[3] is set high if a correct four frame sequence is not detected in eight frames.
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PM5342 SPECTRA-155
DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
Pin Name Pin
Type
RPOHCLK[3]
Output J18 RPOHCLK[2] RPOHCLK[1]
PIN No.
K18 M19
Function
The receive path overhead clocks (RPOHCLK[3:1]) provide timing to process the B3E[3:1] signals, to insert tandem path incoming error count and data link, and to sample the extracted path overhead for the corresponding STS-1 (STM-0/AU3) stream. RPOHCLK[3:1] are nominally 576 KHz clocks. RPOHCLK[3:1] is a gapped 648 KHz clock. In STS-3c (STM-1/AU4) mode or STS-1 (STM-0/AU3) mode, only RPOHCLK[1] is active. RTCEN[3:1], and RTCOH[3:1] are sampled on the rising edge of the corresponding RPOHCLK signal. B3E[3:1], RPOH[3:1] and RPOHFP[3:1] are updated on the falling edge of the corresponding RPOHCLK signal.
RPOHCLK[1] provides timing for the serial receive alarm indication port (RAD), which is updated on the falling edge of RPOHCLK[1].
RPOH[3] RPOH[2] RPOH[1]
Output J19
L19 M18
The receive path overhead data signals (RPOH[3:1]) contain the path overhead bytes (J1, B3, C2, G1, F2, H4, Z3, Z4, and Z5) extracted from the path overhead of the corresponding STS-1 (STM-0/AU3) stream. In STS-3c (STM-1/AU4) mode or STS-1 (STM-0/AU3) mode, only RPOH[1] is active. Each RPOH signal is updated on the falling edge of the corresponding RPOHCLK signal.
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DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
Pin Name Pin
Type
RPOHFP[3]
Output K19 RPOHFP[2] RPOHFP[1]
PIN No.
L18 N19
Function
The receive path overhead frame position signals (RPOHFP[3:1]) may be used to locate the individual path overhead bits in the path overhead data stream for the corresponding STS-1 (STM-0/AU3) stream. Each RPOHFP[3:1] signal is logic 1 when bit 1 (the most significant bit) of the path trace byte (J1) is present in the corresponding RPOH stream. In STS-3c (STM-1/AU4) mode or STS-1 (STM-0/AU3) mode, only RPOHFP[1] is active. Each RPOHFP signal is updated on the falling edge of the corresponding RPOHCLK signal.
RPOHFP[1] may be used to located the BIP error count and path RDI indication bits on the receive alarm port data signal (RAD). RPOHFP[1] is logic 1 when the first of eight BIP error positions from the first STS-1 (STM-0/AU3) or the STS-3c (STM-1/AU4) stream is present on the receive alarm data signal (RAD).
RTCEN[3] RTCEN[2] RTCEN[1]
Input G19
H18 J17
The receive tandem connection overhead insert enable signals (RTCEN[3:1]) control the insertion of incoming error count and data link in the tandem connection maintenance byte (Z5), on a bit-by-bit basis. When RTCEN is set high, the data on the corresponding RTCOH stream is inserted into the associated bit in the Z5 byte. RTCEN has significance only during the J1 byte positions in the RPOHCLK clock sequence and is ignored at all other times. In STS-3c (STM-1/AU4) mode or STS-1 (STM-0/AU3) mode, only RTCEN[1] is significant. RTCEN is sampled on the rising edge of the corresponding RPOHCLK signal.
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DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
Pin Name Pin
Type
RTCOH[3]
Input G20 RTCOH[2] RTCOH[1]
PIN No.
H19 H20
Function
The receive tandem connection overhead data signals (RTCOH[3:1]) contain the incoming error count and data link message to be inserted into the tandem connection maintenance byte (Z5). When RTCEN is set high, the values sampled on RTCOH is inserted into the Z5 byte. When RTCEN is set low, the IEC field of Z5 reports the incoming path BIP error count and the data link field is either set to all ones or passed through unmodified. In STS-3c (STM-1/AU4) mode or STS-1 (STM-0/AU3) mode, only RTCEN[1] is significant. RTCOH is sampled on the rising edge of the corresponding RPOHCLK signal.
RAD Output F17 The receive alarm port data signal (RAD)
contains the path BIP error count and the path remote alarm indication status of the three receive STS-1 (STM-0/AU3) streams or the single STS-3c (STM-1/AU4) stream. In addition, the RAD contains the transmit K1 and K2 bytes.
TPOH[3] TPOH[2] TPOH[1]
Input A4
D3 E3
RAD is updated on the falling edge of RPOHCLK[1].
The transmit path overhead data signals (TPOH[3:1]) contain the path overhead bytes (J1, C2, G1, F2, Z3, Z4, and Z5) and error mask (B3 and H4) which may be inserted, or used to insert BIP and multiframe sequence bit errors into the path overhead byte positions in the transmit stream. Insertion is controlled by the corresponding TPOHEN input, or by bits in internal registers. In STS-3c (STM-1/AU4) mode or STS-1 (STM-0/AU3) mode, only TPOH[1] is significant. Each TPOH input is sampled on the rising edge of the corresponding TPOHCLK output.
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DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
Pin Name Pin
Type
TPOHEN[3]
Input C5 TPOHEN[2] TPOHEN[1]
PIN No.
C4 D1
Function
The transmit path overhead insert enable signals (TPOHEN[3:1]), together with internal register bits, control the source of the path overhead data which is inserted in the transmit stream. While TPOHEN is high, values sampled on the TPOH input are inserted into the corresponding path overhead bit position (for the J1, C2, G1, F2, Z3, Z4, and Z5 bytes). While TPOHEN is low, values obtained from internal registers are inserted into these path overhead bit positions. The TPOHEN input take precedence over TOH.
A high level on TPOHEN during the B3 or H4 bit positions enables an error mask. While the error mask is enabled, a high level on input TPOH causes the corresponding B3 or H4 bit position to be inverted. A low level on TPOH allows the corresponding bit position to pass through the SPECTRA-155 uncorrupted. In STS-3c (STM-1/AU4) mode or STS-1 (STM-0/AU3) mode, only TPOHEN[1] is significant. Each TPOHEN input is sampled on the rising edge of the corresponding TPOHCLK output.
TPOHCLK[3] TPOHCLK[2] TPOHCLK[1]
Output B4
E4 E2
The transmit path overhead clocks (TPOHCLK[3:1]) provide timing to update the corresponding path overhead stream, TPOH. In STS-3c (STM-1/AU4) mode or STS-1 (STM-0/AU3) mode, TPOHCLK[1] is a 576kHz clock and TPOHCLK[3:2] are inactive. TPOH and TPOHEN are sampled on the rising edge of the corresponding TPOHCLK.
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DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
Pin Name Pin
Type
TPOHFP[3]
Output D6 TPOHFP[2] TPOHFP[1]
PIN No.
D5 D2
Function
The path overhead frame position signals (TPOHFP[3:1]) may be used to locate the individual path overhead bits in the overhead data stream, TPOH. TPOHFP is logic 1 when bit 1 (the most significant bit) of the Path Trace byte (J1) is present in the TPOH stream. In STS-3c (STM-1/AU4) mode or STS-1 (STM-0/AU3) mode, only TPOHFP[1] is active. Each TPOHFP output is updated on the falling edge of the corresponding TPOHCLK output.
TAD Input R1 The transmit alarm port data signal (TAD)
contains the path REI count and the path PRDI status of the three associated receive STS-1 (STM-0/AU3) streams or the single STS-3c (STM-1/AU4) stream. In addition, the TAD input contains the K1 and K2 bytes from a mate SPECTRA-155.
TAD is sampled on the rising edge of TACK.
TAFP Input P1 The transmit alarm port frame pulse signal
(TAFP) marks the first bit of the transmit alarm message in each SONET/SDH frame. TAFP is pulsed high to mark the first path REI bit location of the first STS-1 (STM-0/AU3) stream or the first path REI bit location of the single STS-3c (STM-1/AU4) stream. TAFP is sampled on the rising edge of TACK.
TACK Input N4 The transmit alarm port clock (TACK)
provides timing for transmit alarm port. TACK is nominally a 576 KHz clock. Inputs TAD and TAFP are sampled on the rising edge of TACK.
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DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
Table 5 - System Side Interface Signals (38)
Pin Name Pin
Type
SMODE[2]
Input C16 SMODE[1] SMODE[0]
PIN No.
A17 B17
Function
The system mode select (SMODE[2:0]) signal is used to select the operation of the system side interface. SMODE[2:0] selects the operation of system signals SS[34:0] and in some cases the direction of the signals. SMODE[2:0] should be strapped to one of the codepoints below:
000 -Byte Telecombus Mode
001 -Nibble Telecombus Mode
010 -Serial Telecombus Mode
011 -Byte Data Mode
100 -Nibble Data Mode
101 -Serial Data Mode
110 -Serial DS3 Mode
111 -Reserved
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DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
Pin Name Pin
Type
SS[0]
SS[1]
SS[2]
SS[3]
SS[4]
SS[5]
SS[6]
SS[7]
SS[8]
SS[9]
SS[10]
SS[11]
SS[12]
SS[13]
I/O
Input
I/O
I/O
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
PIN No.
D15
B16
A16
C15
B15
A15
C14
D13
B14
A14
C13
D12
B13
C12
Function
The system (SS[34:0]) signals are used to interface the SPECTRA-155 to data sinks and sources. The signal descriptions are listed below for the modes selected using the SMODE[2:0] inputs.
SS[14]
SS[15]
SS[16]
SS[17]
SS[18]
SS[19]
SS[20]
SS[21]
SS[22]
SS[23]
SS[24]
SS[25]
SS[26]
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
B12
A12
D11
C11
B11
A11
C10
B10
B9
C9
A8
D9
B8
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DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
Pin Name Pin
Type
SS[27]
SS[28]
SS[29]
SS[30]
SS[31]
SS[32]
SS[33]
SS[34]
I/O
Output
Output
Output
Output
Input
Input
Input
PIN No.
C8
A7
B7
D8
C7
A6
B6
C6
Function
The system (SS[34:0]) signals are used to interface the SPECTRA-155 to data sinks and sources. The signal descriptions are listed below for the modes selected using the SMODE[2:0] inputs.
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PM5342 SPECTRA-155
DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
Table 6 - Byte Telecombus Mode (SMODE[2:0]=000)
Pin Name Pin
Type
PIN No.
Function
SS[0]/DCK Input D15 The DROP bus clock (DCK) provides timing for
the DROP bus interface. DCK is nominally a
19.44 MHz or 6.48 MHz, 50% duty cycle clock. Frequency offsets between RCLK and DCK are accommodated by pointer justification events on the DROP bus. DFP is sampled on the rising edge of DCK. Outputs DPL, DC1J1V1, DDP and DD[7:0] are updated on the rising edge of DCK.
SS[1]/DFP Input B16 The active high DROP bus reference frame
position signal (DFP) indicates when the first byte of the synchronous payload envelope (SPE byte 1 of STS-1 #1) is available on the DD[7:0] bus. Note that DFP has a fixed relationship to the SONET/SDH frame; the start of the SPE is determined by the STS (AU) pointer and may change relative to DFP. DFP is sampled on the rising edge of DCK.
SS[2]/DD[0] SS[3]/DD[1] SS[4]/DD[2] SS[5]/DD[3] SS[6]/DD[4] SS[7]/DD[5] SS[8]/DD[6] SS[9]/DD[7]
Output A16
C15 B15 A15 C14 D13 B14 A14
The DROP bus data (DD[7:0]) contains the SONET/SDH receive payload data. The transport overhead bytes, with the exception of the H1, H2 pointer bytes, are set to zeros. The fixed stuff columns in a tributary mapped SPE (VC) may also be optionally set to zero or NPI. DD[7] is the most significant bit (corresponding to bit 1 of each serial word, the first bit transmitted). DD[0] is the least significant bit (corresponding to bit 8 of each serial word, the last bit transmitted). DD[7:0] is updated on the rising edge of DCK.
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DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
Pin Name Pin
Type
PIN No.
Function
SS[10]/DPL Output C13 The active high DROP bus payload active
signal (DPL) indicates when the DD[7:0] is carrying a payload byte. It is set high during path overhead and payload bytes and low during transport overhead bytes. DPL is set high during the H3 byte to indicate a negative pointer justification event and set low during the byte following H3 to indicate a positive pointer justification event. DPL is updated on the rising edge of DCK.
SS[11]/ DC1J1V1
Output D12 The DROP bus composite timing signal
(DC1J1V1) indicates the frame, payload and tributary multiframe boundaries on the DROP data bus DD[7:0]. DC1J1V1 pulses high with the DROP bus payload active signal (DPL) set low to mark the first STS-1 (STM-0/AU3) Identification byte or equivalently the STM identification byte (C1). DC1J1V1 pulses high with DPL set high to mark the path trace byte (J1). Optionally, the DC1J1V1 signal pulses high on the V1 byte to indicate tributary multiframe boundaries. DC1J1V1 is updated on the rising edge of DCK.
SS[12]/DDP Output B13 The DROP bus data parity signal (DDP)
indicates the parity of the DROP bus signals. The DROP data bus (DD[7:0]) is always included in parity calculations. The internal register bits control the inclusion of the DPL and DC1J1V1 signals in parity calculation and the sense (odd/even) of the parity. DDP is updated on the rising edge of DCK.
SS[13]/ACK Input C12 The ADD bus clock (ACK) provides timing for
the ADD bus and the GENERATED bus interfaces. ACK is nominally a 19.44 MHz or
6.48 MHz, 50% duty cycle clock. Inputs AD[7:0], APL, AC1J1V1, GFP and GMFP are sampled on the rising edge of ACK. Outputs GPL, GC1J1V1, and GD[1:0] are updated on the rising edge of ACK.
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DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
Pin Name Pin
Type
SS[14]/
Input B12
AD[0]
SS[15]/
AD[1]
SS[16]/
AD[2]
SS[17]/
AD[3]
SS[18]/
AD[4]
SS[19]/
AD[5]
SS[20]/
AD[6]
PIN No.
A12
D11
C11
B11
A11
C10
Function
The ADD bus data (AD[7:0]) contains the SONET/SDH transmit payload data. The transport overhead bytes, except the H1 and H2 pointer bytes, are ignored. The phase relation of the SPE (VC) to the transport frame is determined by the ADD bus composite timing signal (AC1J1V1) or optionally by interpreting the H1 and H2 pointer bytes. AD[7] is the most significant bit (corresponding to bit 1 of each serial word, the first bit transmitted). AD[0] is the least significant bit (corresponding to bit 8 of each serial word, the last bit transmitted). AD[7:0] is sampled on the rising edge of ACK.
SS[21]/
B10
AD[7]
SS[22]/APL Input B9 The ADD bus payload active signal (APL)
indicates when AD[7:0] is carrying a payload byte. It is set high during path overhead and payload bytes and low during transport overhead bytes. APL is set high during the H3 byte to indicate a negative pointer justification event and set low during the byte following H3 to indicate a positive pointer justification event. APL is sampled on the rising edge of ACK.
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PM5342 SPECTRA-155
DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
Pin Name Pin
Type
SS[23]/
Input C9 The ADD bus composite timing signal
AC1J1V1
PIN No.
Function
(AC1J1V1) identifies the frame, payload and tributary multiframe boundaries on the ADD data bus AD[7:0]. AC1J1V1 pulses high with the ADD bus payload active signal (APL) set low to mark the first STS-1 (STM-0/AU3) Identification byte or equivalently the STM identification byte (C1). Optionally, the AC1J1V1 pulses high with APL set high to mark the path trace byte (J1). Optionally, the AC1J1V1 signal pulses high on the V1 byte to indicate tributary multiframe boundaries.
Optional marking of the J1 and V1 bytes are controlled using the DISJ1V1 bit in the SPECTRA-155 Path/Mapper Configuration register. Setting DISJ1V1 bit high enables pointer interpretation on the ADD bus. Valid H1 and H2 pointer bytes must be provided on the ADD data bus (AD[7:0]) to allow the J1 position to be identified. Optionally, the H4 byte could be provided on the ADD data bus to allow the V1 position to be identified.
AC1J1V1 is sampled on the rising edge of ACK.
SS[24]/ADP Input A8 The ADD bus data parity signal (ADP) indicates
the parity of the ADD bus signals. The ADD data bus (AD[7:0]) is always included in parity calculations. Internal register bits controls the inclusion of the APL and AC1J1V1 signals in parity calculations and the sense (odd/even) of the parity. ADP is sampled on the rising edge of ACK.
SS[25]/GFP Input D9 The active high GENERATED bus reference
frame position signal (GFP) indicates when the first byte of the synchronous payload envelope (SPE byte 1 of STS-1 #1) is available on the GD[1:0] bus. Note that GFP has a fixed relationship to the SONET/SDH frame; the start of the SPE is determined by the STS (AU) pointer and may change relative to GFP. GFP is sampled on the rising edge of ACK.
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DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
Pin Name Pin
Type
SS[26]/
Input B8 The active high GENERATED reference
GMFP
SS[27]/
Output C8 GD[0] SS[28]/ GD[1]
PIN No.
A7
Function
multiframe position signal (GMFP) is used to align the SONET/SDH tributary multiframe boundary on the GENERATED bus . GMFP should be brought high for a single ACK period every 9720 ACK cycles, or multiples thereof. GMFP may be tied low if such synchronization is not required. A pulse on GMFP realigns the GENERATED bus to be the first of four frames in the multiframe. I.e., the frame containing the V1 bytes. In STS-1 (STM-0/AU3) mode, GMFP is sampled one ACK cycle after the J1 indication on GC1J1V1. In STS-3/3c (STM-1/AU3/AU4) modes, GMFP is sampled three ACK cycles after the J1 indication. GMFP is ignored at other byte positions. GMFP is sampled on the rising edge of ACK.
The GENERATED bus data (GD[1:0]) contains cyclical multiframe count carried in the H4 byte. The sequence is initialized to 'b01 by a high pulse on GMFP, and increments at the byte following J1. GD[1:0] is updated on the rising edge of ACK.
SS[29]/GPL Output B7 The GENERATED bus payload active signal
(GPL) indicates when GD[1:0] is carrying a payload byte. GPL distinguishes between payload and transport overhead timeslots in the GENERATED bus. Since the GENERATED bus is expected to have fixed timing relationship with the ADD bus, access modules may use GPL to locate payload timeslots in the ADD bus. GPL is updated on the rising edge of ACK.
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DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
Pin Name Pin
Type
SS[30]/
Output D8 The GENERATED bus composite timing signal GC1J1V1
PIN No.
Function
(GC1J1V1) identifies the frame, payload and tributary multiframe boundaries on the GENERATED data bus GD[1:0]. GC1J1V1 pulses high with the GENERATED bus payload active signal (GPL) set low to mark the first STS-1 (STM-0/AU3) Identification byte or equivalently the STM identification byte (C1). GC1J1V1 pulses high with GPL set high to mark the path trace byte (J1). The GC1J1V1 signal pulses high on the V1 byte to indicate tributary multiframe boundaries. Since the GENERATED bus is expected to have fixed timing relationship with the ADD bus, access modules may use GC1J1V1 to located the frame, payload and tributary multiframe boundaries on the ADD bus. GC1J1V1 is updated on the rising edge of ACK.
SS[31]/GDP Output C7 The GENERATED bus data parity signal (GDP)
indicates the parity of the GENERATED bus signals. The GENERATED data bus (GD[1:0]) is always included in parity calculations. The internal register bits control the inclusion of the GPL and GC1J1V1 signals in parity calculation and the sense (odd/even) of the parity. GDP is updated on the rising edge of ACK.
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DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
Pin Name Pin
Type
SS[32]/
Input A6
DTPAIS[1]
SS[33]/
DTPAIS[2]
SS[34]/
DTPAIS[3]
PIN No.
B6
C6
Function
The active high DROP bus or Transmit path alarm indication signals (DTPAIS[3:1]) controls the insertion of path AIS in the DROP bus DD[7:0] or the transmit stream. The function of each DTPAIS[3:1] input pin is independently controlled by the TPAIS_EN bits in the Transmit Path AIS Control #1, Transmit Path AIS Control #2, and Transmit Path AIS Control #3 registers.
In STS-3 mode, each DTPAIS[3:1] corresponds to a separate STS-1. DTPAIS[1] corresponds to STS#1, DTPAIS[2] corresponds to STS#2 and DTPAIS[3] corresponds to STS#3. In STS-3c (STM-1/AU4) mode or STS-1 (STM-0/AU3) mode, only DTPAIS[1] is significant.
A high level on DTPAIS forces the insertion of the all ones pattern into the complete SPE and the payload pointer bytes (H1, H2, and H3). Path AIS insertion can also be inserted via register access or in response to ISF code in terminating tandem connection termination equipment applications.
DTPAIS[3:1] is sampled on the rising edge of DCK for DROP bus or TCLK for transmit stream Path AIS insertion.
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PM5342 SPECTRA-155
DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
Table 7 - Nibble Telecombus Mode (SMODE[2:0]=001)
Pin Name Pin
Type
PIN No.
Function
SS[0]/DCK Input D15 The DROP bus clock (DCK) provides timing for
the DROP bus interface. For nibble mode, DCK is nominally a 38.88 MHz or 12.96 MHz, 50% duty cycle clock. Frequency offsets between RCLK and DCK/2 are accommodated by pointer justification events on the DROP bus. DFP is sampled on the rising edge of DCK. Outputs DPL, DC1J1V1, DDP and DD[3:0] are updated on the rising edge of DCK.
SS[1]/DFP Input B16 The active high DROP bus reference frame
position signal (DFP) indicates when the first nibble of the synchronous payload envelope (upper nibble of SPE byte 1 of STS-1 #1) is available on the DD[3:0] bus. Note that DFP has a fixed relationship to the SONET/SDH frame; the start of the SPE is determined by the STS (AU) pointer and may change relative to DFP. DFP is sampled on the rising edge of DCK.
SS[2]/DD[0] SS[3]/DD[1] SS[4]/DD[2] SS[5]/DD[3]
SS[6]
SS[7]
SS[8]
SS[9]
Output A16
C15 B15 A15
Output C14
D13
B14
A14
The DROP bus data (DD[3:0]) contains the SONET/SDH receive payload data. The transport overhead nibbles, with the exception of the H1, H2 pointer nibbles, are set to zeros. The fixed stuff columns in a tributary mapped SPE (VC) may also be optionally set to zero or NPI. DD[3] is the most significant bit (corresponding to bit 1 or 5 of each serial word, the bit received first or fifth, respectively). DD[0] is the least significant bit (corresponding to bit 4 or 8 of each serial word, the fourth or last bit received, respectively). DD[3:0] is updated on the rising edge of DCK.
Reserved.
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PM5342 SPECTRA-155
DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
Pin Name Pin
Type
PIN No.
Function
SS[10]/DPL Output C13 The active high DROP bus payload active
signal (DPL) indicates when the DD[3:0] is carrying a payload nibble. It is set high during path overhead and payload nibbles and low during transport overhead nibbles. DPL is set high during the H3 nibbles to indicate a negative pointer justification event and set low during the nibbles following H3 to indicate a positive pointer justification event. DPL is updated on the rising edge of DCK.
SS[11]/
DC1J1V1
Output D12 The DROP bus composite timing signal
(DC1J1V1) indicates the frame, payload and tributary multiframe boundaries on the DROP data bus DD[3:0]. DC1J1V1 pulses high with the DROP bus payload active signal (DPL) set low to mark the most significant nibble of the first STS-1 (STM-0/AU3) Identification byte or equivalently the most significant nibble of the STM identification byte (C1). DC1J1V1 pulses high with DPL set high to mark the most significant nibble of the path trace byte (J1). Optionally, the DC1J1V1 signal pulses high on the most significant nibble of the V1 byte to indicate tributary multiframe boundaries. DC1J1V1 is updated on the rising edge of DCK.
SS[12]/DDP Output B13 The DROP bus data parity signal (DDP)
indicates the parity of the DROP bus signals. The DROP data bus (DD[3:0]) is always included in parity calculations. The internal register bits control the inclusion of the DPL and DC1J1V1 signals in parity calculation and the sense (odd/even) of the parity. DDP is updated on the rising edge of DCK.
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DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
Pin Name Pin
Type
PIN No.
Function
SS[13]/ACK Input C12 The ADD bus clock (ACK) provides timing for
the ADD bus and the GENERATED bus interfaces. ACK is nominally a 38.88 MHz or
12.96 MHz, 50% duty cycle clock for nibble mode operation. Inputs AD[3:0], APL, AC1J1V1, GFP and GMFP are sampled on the rising edge of ACK. Outputs GPL, GC1J1V1, and GD[1:0] are updated on the rising edge of ACK.
SS[14]/
AD[0]
SS[15]/
AD[1]
Input B12
A12
The ADD bus data (AD[3:0]) contains the SONET/SDH transmit payload data. The transport overhead nibbles, except the H1 and H2 pointer nibbles, are ignored. The phase relation of the SPE (VC) to the transport frame is determined by the ADD bus composite timing
SS[16]/
AD[2]
D11
signal (AC1J1V1) or optionally by interpreting the H1 and H2 pointer nibbles. AD[3] is the most significant bit (corresponding to bit 1 or 5
SS[17]/
AD[3]
C11
of each serial word, the bit transmitted first or fifth, respectively). AD[0] is the least significant bit (corresponding to bit 4 or 8 of each serial word, the fourth or last bit transmitted, respectively). AD[3:0] is sampled on the rising edge of ACK.
SS[18]
SS[19]
SS[20]
SS[21]
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Input B11
A11
C10
B10
Reserved. Should be tied low when operating in Telecombus nibble mode.
PM5342 SPECTRA-155
DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
Pin Name Pin
Type
PIN No.
Function
SS[22]/APL Input B9 The ADD bus payload active signal (APL)
indicates when AD[3:0] is carrying a payload nibble. It is set high during path overhead and payload nibbles and low during transport overhead nibbles. APL is set high during the H3 nibbles to indicate a negative pointer justification event and set low during the nibbles following H3 to indicate a positive pointer justification event.
The SPECTRA-155 only samples the most significant nibble of a byte to determine the validity of the byte. The least significant nibble sample is ignored. APL is sampled on the rising edge of ACK.
SS[23]/
AC1J1V1
Input C9 The ADD bus composite timing signal
(AC1J1V1) identifies the frame, payload and tributary multiframe boundaries on the ADD data bus AD[3:0]. AC1J1V1 pulses high with the ADD bus payload active signal (APL) set low to mark the most significant nibble of the first STS-1 (STM-0/AU3) Identification byte or equivalently the most significant nibble of the STM identification byte (C1). Optionally, the AC1J1V1 pulses high with APL set high to mark the most significant nibble of the path trace byte (J1). Optionally, the AC1J1V1 signal pulses high on the most significant nibble of the V1 byte to indicate tributary multiframe boundaries.
Optional marking of the J1 and V1 bytes are controlled using the DISJ1V1 bit in the SPECTRA-155 Path/Mapper Configuration register. Setting DISJ1V1 bit high enables pointer interpretation on the ADD bus. Valid H1 and H2 pointer bytes must be provided on the ADD data bus (AD[3:0]) to allow the J1 position to be identified. Optionally, the H4 byte could be provided on the ADD data bus to allow the V1 position to be identified.
AC1J1V1 is sampled on the rising edge of ACK.
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DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
Pin Name Pin
Type
PIN No.
Function
SS[24]/ADP Input A8 The ADD bus data parity signal (ADP) indicates
the parity of the ADD bus signals. The ADD data bus (AD[3:0]) is always included in parity calculations. Internal register bits controls the inclusion of the APL and AC1J1V1 signals in parity calculations and the sense (odd/even) of the parity. ADP is sampled on the rising edge of ACK.
SS[25]/GFP Input D9 The active high GENERATED bus reference
frame position signal (GFP) indicates when the most significant nibble of the first byte of the synchronous payload envelope (SPE byte 1 of STS-1 #1) is available on the GD[1:0] bus. Note that GFP has a fixed relationship to the SONET/SDH frame; the start of the SPE is determined by the STS (AU) pointer and may change relative to GFP. GFP is sampled on the rising edge of ACK.
SS[26]/
GMFP
Input B8 The active high GENERATED reference
multiframe position signal (GMFP) is used to align the SONET/SDH tributary multiframe boundary on the GENERATED bus . GMFP should be brought high for a single ACK period every 2*9720 ACK cycles, or multiples thereof to identify the most significant nibble of the V1 byte. GMFP may be tied low if such synchronization is not required. A pulse on GMFP realigns the GENERATED bus to be the first of four frames in the multiframe. I.e., the frame containing the V1 bytes. In STS-1 (STM-0/AU3) mode, GMFP is sampled two ACK cycle after the J1 indication on GC1J1V1. In STS-3/3c (STM-1/AU3/AU4) modes, GMFP is sampled six ACK cycles after the J1 indication. GMFP is ignored at other nibble positions. GMFP is sampled on the rising edge of ACK.
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PM5342 SPECTRA-155
DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
Pin Name Pin
Type
SS[27]/
Output C8
GD[0]
SS[28]/
GD[1]
PIN No.
A7
Function
The GENERATED bus data (GD[1:0]) contains cyclical multiframe count carried in the H4 byte. The sequence is initialized to 'b01 by a high pulse on GMFP, and increments at the nibble following J1 nibbles. GD[1:0] is updated on the rising edge of ACK.
SS[29]/GPL Output B7 The GENERATED bus payload active signal
(GPL) indicates when GD[1:0] is carrying a payload byte. GPL distinguishes between payload and transport overhead timeslots in the GENERATED bus. Since the GENERATED bus is expected to have fixed timing relationship with the ADD bus, access modules may use GPL to locate payload timeslots in the ADD bus. GPL is updated on the rising edge of ACK.
SS[30]/
GC1J1V1
Output D8 The GENERATED bus composite timing signal
(GC1J1V1) identifies the frame, payload and tributary multiframe boundaries on the GENERATED data bus GD[1:0]. GC1J1V1 pulses high with the GENERATED bus payload active signal (GPL) set low to mark the most significant nibble of the first STS-1 (STM-0/AU3) Identification byte or equivalently the most significant nibble of the STM identification byte (C1). GC1J1V1 pulses high with GPL set high to mark the most significant nibble of the path trace byte (J1). The GC1J1V1 signal pulses high on the most significant nibble of the V1 byte to indicate tributary multiframe boundaries. Since the GENERATED bus is expected to have fixed timing relationship with the ADD bus, access modules may use GC1J1V1 to locate the frame, payload and tributary multiframe boundaries on the ADD bus. GC1J1V1 is updated on the rising edge of ACK.
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DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
Pin Name Pin
Type
PIN No.
Function
SS[31]/GDP Output C7 The GENERATED bus data parity signal (GDP)
indicates the parity of the GENERATED bus signals. The GENERATED data bus (GD[1:0]) is always included in parity calculations. The internal register bits control the inclusion of the GPL and GC1J1V1 signals in parity calculation and the sense (odd/even) of the parity. GDP is updated on the rising edge of ACK.
SS[32]/
DTPAIS[1]
SS[33]/
DTPAIS[2]
Input A6
B6
The active high DROP bus or Transmit path alarm indication signals (DTPAIS[3:1]) controls the insertion of path AIS in the DROP bus DD[3:0] or the transmit stream. The function of each DTPAIS[3:1] input pin is independently controlled by the TPAIS_EN bits in the Transmit
SS[34]/
DTPAIS[3]
C6
Path AIS Control #1, Transmit Path AIS Control #2, and Transmit Path AIS Control #3 registers.
In STS-3 mode, each DTPAIS[3:1] corresponds to a separate STS-1. DTPAIS[1] corresponds to STS#1, DTPAIS[2] corresponds to STS#2 and DTPAIS[3] corresponds to STS#3. In STS-3c (STM-1/AU4) mode or STS-1 (STM-0/AU3) mode, only DTPAIS[1] is significant.
A high level on DTPAIS forces the insertion of the all ones pattern into the complete SPE and the payload pointer bytes (H1, H2, and H3). Path AIS insertion can also be inserted via register access or in response to ISF code in terminating tandem connection termination equipment applications.
DTPAIS[3:1] is sampled on the rising edge of DCK for DROP bus or TCLK for transmit stream Path AIS insertion.
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DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
Table 8 - Serial Telecombus Mode (SMODE[2:0]=010)
Pin Name Pin
Type
SS[0]/SDCK[1]
Input D15 SS[2]/SDCK[2] SS[3]/SDCK[3]
PIN No.
A16 C15
Function
The Serial DROP bus clocks (SDCK[3:1]) provide timing for the three STS-1 (STM-0/AU3) DROP bus interfaces. SDCK[1] corresponds to the STS-1 (STM-0/AU3) #1 of a STS-3 (STM-1/AU3) stream while SDCK[3] corresponds to the STS-1 (STM-0/AU3) #3 of a STS-3 (STM-1/AU3) stream.
SDCK is nominally a 51.84 MHz, 50% duty cycle clock. Frequency offsets between RCLK and SDCK/8 are accommodated by pointer justification events on the DROP bus. SDFP[3:1] are sampled on the rising edge of the corresponding SDCK. Outputs SDPL, SDC1J1V1 and SDD are updated on the rising edge of the corresponding SDCK.
SS[1] Input B16 Reserved. Should be strapped low in this
mode of operation.
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DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
Pin Name Pin
Type
SS[4]/
Output B15
SDC1J1V1[1]
SS[5]/
SDC1J1V1[2]
SS[6]/
SDC1J1V1[3]
PIN No.
A15
C14
Function
The serial DROP bus composite timing signals (SDC1J1V1[3:1]) indicates the frame, payload and tributary multiframe boundaries on the serial DROP data signals SDD[3:1]. SDC1J1V1[1] corresponds to the STS-1 (STM-0/AU3) #1 of a STS-3 (STM-1/AU3) stream while SDC1J1V1[3] corresponds to the STS-1 (STM-0/AU3) #3 of a STS-3 (STM-1/AU3) stream.
SDC1J1V1 pulses high with the DROP bus payload active signal (SDPL) set low to mark the most significant bit of the STS-1 (STM-0/AU3) Identification byte or equivalently the most significant bit of the STM identification byte (C1). SDC1J1V1 pulses high with SDPL set high to mark the most significant bit of the path trace byte (J1). Optionally, the SDC1J1V1 signal pulses high on the most significant bit of the V1 byte to indicate tributary multiframe boundaries. SDC1J1V1 is updated on the rising edge of SDCK.
SS[7]/SDD[1] SS[8]/SDD[2] SS[9]/SDD[3]
Output D13
B14 A14
The Serial DROP bus data (SDD[3:1]) contains the SONET/SDH receive payload data. SDD[1] corresponds to the STS-1 (STM-0/AU3) #1 of a STS-3 (STM-1/AU3) stream while SDD[3] corresponds to the STS-1 (STM-0/AU3) #3 of a STS-3 (STM-1/AU3) stream.
The transport overhead bits, with the exception of the H1, H2 pointer bits, are set to zeros. The fixed stuff columns in a tributary mapped SPE (VC) may also be optionally set to zero or NPI. Bits are output on SDD in the order they were received from the line.
SDD is updated on the rising edge of SDCK.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 77
PM5342 SPECTRA-155
DATA SHEET PMC-970133 ISSUE 4 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER
Pin Name Pin
Type
SS[10]
Output C13
/SDPL[1]
SS[11]
/SDPL[2]
SS[12]
/SDPL[3]
SS[13]/
Input C12
SACK[1]
SS[14]/
SACK[2]
SS[15]/
SACK[3]
PIN No.
D12
B13
B12
A12
Function
The active high serial DROP bus payload active signals (SDPL[3:1]) indicates when the associated SDD[3:1] is carrying a payload bit. SDPL[1] corresponds to the STS-1 (STM-0/AU3) #1 of a STS-3 (STM-1/AU3) stream while SDPL[3] corresponds to the STS-1 (STM-0/AU3) #3 of a STS-3 (STM-1/AU3) stream.
SDPL is set high during path overhead and payload bits and low during transport overhead bits. SDPL is set high during the H3 bits to indicate a negative pointer justification event and set low during the eight bits following the H3 bits to indicate a positive pointer justification event. SDPL is updated on the rising edge of SDCK.
The serial ADD bus clock (SACK[3:1]) signals provides timing for the serial ADD bus interface. SACK[1] corresponds to the STS-1 (STM-0/AU3) #1 of a STS-3 (STM-1/AU3) stream while SACK[3] corresponds to the STS-1 (STM-0/AU3) #3 of a STS-3 (STM-1/AU3) stream.
SACK is nominally a 51.84 MHz, 50% duty cycle clock for serial mode operation. Inputs SAD[3:1], SAPL[3:1], and SAC1J1V1[3:1] are sampled on the rising edge of the corresponding SACK[3:1] clock.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 78
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