PMC PM5315 Datasheet
PMC-Sierra,Inc.
Preliminary
SPECTRA-2488
SONET/SDH Payload Extractor/Aligner for 2488 Mbit/s
PM5315
FEATURES
• Monolithic SONET/SDH Payload
Extractor/Aligner for use in interface
applications, operating at serial
interface speeds of up to 2488 Mbit/s:
single STS-48c (STM-16/AU4-16c);
•
single STS-48 (STM-16/AU4-
•
4c/AU4/AU3/TU3);
quad STS-12c (STM-4/AU4-4c);
•
quad STS-12 (STM-
•
4/AU4/AU3/TU3).
• In single STS-48/STM-16 mode,
supports a duplex 16-bit 155.52 MHz
differential PECL line side interface for
direct connection to external clock
recovery, clock synthesis and
serializer-deserializer components.
• In quad STS-12/STM-4 mode,
supports four duplex 8-bit 77.76 MHz
TTL compatible line side interfaces for
direct connection to external clock
recovery, clock synthesis and
serializer-deserializer components.
• Provides termination for SONET
Section, Line and Path overhead or
SDH Regenerator Section, Multiplexer
Section and High Order Path
overhead.
• In single STS-48/STM-16 mode
provides a 32-bit 77.76 MHz ADD and
DROP TelecomBus.
• In quad STS-12/STM-4 mode provides
four 8-bit 77.76 MHz ADD and DROP
TelecomBus Interfaces.
• Maps SONET/SDH payloads to
system timing, accommodating
plesiochronous timing offsets between
the line and system timing references,
through pointer processing.
• The entire SONET/SDH transport and
path overheads are extracted to and
inserted from dedicated pins.
• Frames to the SONET/SDH receive
stream and inserts framing bytes and
STS identification into the transmit
stream and processes or inserts the
transport overhead.
• Interprets or generates the STS (AU)
pointer bytes (H1, H2, H3), extracts or
inserts the synchronous payload
envelope(s) and processes or inserts
the path overhead.
• Provides Time Slot Interchange (TSI)
function at the ADD and DROP
TelecomBus Interfaces for grooming
any legal mix of SONET/SDH paths.
• Supports Automatic Protection
Switching (APS):
Ring control port communication of
•
path REI and path RDI alarms;
Filters the APS channel (K1,K2)
•
bytes into internal registers; inserts
the APS channel into the transmit
stream.
• Supports line loopback from the line
side receive stream to the transmit
stream and diagnostic loopback from
an ADD TelecomBus interface to a
DROP TelecomBus interface.
• Provides a standard five signal IEEE
1149.1 JTAG test port for boundary
scan board test purposes.
BLOCK DIAGRAM
Status
Information
Rx Ring
Control
Port
OC-48 Mode:
16-bit x 155.52
Mbit/s PECL
4 x OC-12 Mode:
4 x 8-bit x 77.76
Mbit/s TTL
OC-48 Mode:
16-bit x 155.52
Mbit/s PECL
4 x OC-12 Mode:
4 x 8-bit x 77.76
Mbit/s TTL
Rx Line
Interface
Tx Line
Interface
Rx APS
Sync
Extractor
&
Bit Error
Monitor
RX Transport
O/H Processor
SONET/SDH
Reporting
Controller
Section
Processor
Tx Transport
O/H Processor
Tx Ring
Control Port
Receive O/H Clock,
Frame Pulse
Receive Transport
Overhead
Receive Section/Line
DCC and Clock
Section
Trace
Processor
Alarm
Trace
Receive Path
Bit-interleaved
Parity Error
Path
Trace
Processor
Rx Path O/H
Processor
Path
Trace
Processor
Tx Path O/H
Processor
Overhead
(STS-12) Receive Path Processing Slice
Drop Bus
Rx
Telecom
Aligner
(STS-12) Transmit Path Processing Slice
Tx
Telecom
Aligner
JTAG Test
Access Port
PRBS
Generator/
Monitor
Add Bus
PRBS
Generator/
Monitor
Tx Pointer
Interpreter
(STS/AU-
TU3)
Mode
Rx Timeslot
Interchange
Tx
TelecomBus
System
Interface
Microprocessor Interface
Rx
TelecomBus
System
Interface
Tx Timeslot
Interchange
OC-48 Mode:
32-bit x 77.76 Mbit/s
TelecomBus
4 x OC-12 Mode:
4 x 8-bit x 77.76
Mbit/s TelecomBus
Alarm
Reporting
OC-48 Mode:
32-bit x 77.76 Mbit/s
TelecomBus
4 x OC-12 Mode:
4 x 8-bit x 77.76
Mbit/s TelecomBus
Transmit O/H
Clock, Frame
Transmit
Section/Line
DCC Clock
PMC-2000326 (p1) PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE © Copyright PMC-Sierra, Inc. 2000
Pulse
Control
and
Status
Information
Transmit
Transport
O/H
Transmit Path
O/H
Test Data
Quad 622
or 2488
16-bit
Microprocessor
Bus
Preliminary
PM5315 SPECTRA-2488
SONET/SDH Payload Extractor/Aligner for 2488 Mbit/s
• Provides a generic 16-bit
microprocessor bus interface for
configuration, control, and status
monitoring.
• Low power 1.8 V CMOS core logic with
3.3 V CMOS/TTL compatible digital
inputs and digital outputs. PECL inputs
and outputs are 3.3 V compatible.
• Industrial temperature range (-40°C to
+85°C).
• 520 pin Super BGA package.
APPLICATIONS
• Channelized STS-48/STM-16 or
4 x STS-12/STM-4 Interfaces for:
•
•
•
•
•
TYPICAL APPLICATIONS
STS-48/STM-16 APPLICATION WITH VT/TU POINTER PROCESSING/ALIGNMENT
ACK
AJ0J1[4:1]
APL[4:1]
DD1[7:0], DDP[1]
DJ0J1[1]
DPL[1]
DCK
DD2[7:0], DDP[2]
DJ0J1[2]
DPL[2]
DCK
DD3[7:0], DDP[3]
DJ0J1[3]
DPL[3]
DCK
DD4[7:0], DDP[4]
DJ0J1[4]
DPL[4]
DCK
PM5363
TUPP+622
PM5363
TUPP+622
PM5363
TUPP+622
PM5363
TUPP+622
2488 Mbit/s
Optical
Interface
Optical
Transceiver
Clock/Data
Recovery
Clock
Synthesis
Serial/
Parallel
Converter
16-bit x
155.52
Mbit/s
AD[31:0], ADP[4:1]
PM5315
SPECTRA-
2488
Optical Cross Connects;
Digital Cross Connects;
Router and Switch Line Cards;
ADM Aggregate Cards for TDM and
Multiservice applications;
Terminal Multiplexers.
To VT/TU Cross-
Connect or
Tributary Cards
STS-48/STM-16 APPLICATION WITH POS/ATM PROCESSING
AD[31:0], ADP[4:1]
AJ0J1[4:1]
DD[31:0], DDP[4:1]
DJ0J1[4:1]
2488 Mbit/s
Optical
Interface
Optical
Transceiver
Head Office:
PMC-Sierra, Inc.
#105 - 8555 Baxter Place
Burnaby, B.C. V5A 4V7
Canada
Tel: 604.415.6000
Fax: 604.415.6200
PM5315
SPECTRA-2488
Clock/Data
Recovery
Clock
Synthesis
Serial/
Parallel
Converter
16-bit x
155.52
Mbit/s
To order documentation,
send email to:
document@pmc-sierra.com
or contact the head office,
Attn: Document Coordinator
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
ACK
APL[4:1]
DPL[4:1]
DCK
DFP
PM7390
S/UNI-MACH48
All product documentation is available
on our web site at:
http://www.pmc-sierra.com
For corporate information,
send email to:
info@pmc-sierra.com
Drop
Add
POS-PHY
Level 3/
UTOPIA
Level 3
PMC-2000326 (p1)
© Copyright PMC-Sierra,
Inc. 2000. All rights reserved.
March 2000
To a
Datalink-
Layer
Device
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