PMC PM4354-PI Datasheet

RELEASED

DATASHEET

PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1

PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

PM4354

COMET-QUAD

FOUR CHANNEL COMBINED E1/T1/J1

TRANSCEIVER/FRAMER

DATASHEET

RELEASED

ISSUE 6: MAY 2001

PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000

RELEASED

DATASHEET

PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1

PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

1 FEATURES........................................................................................................................ 1

1.1 RECEIVER SECTION: ......................................................................................... 2

1.2 TRANSMITTER SECTION:.................................................................................. 3

2 APPLICATIONS................................................................................................................. 6

3 REFERENCES .................................................................................................................. 7

4 APPLICATION EXAMPLE ...............................................................................................10

5 BLOCK DIAGRAM........................................................................................................... 11

6 DESCRIPTION ................................................................................................................ 12

7 PIN DIAGRAM................................................................................................................. 14

8 PIN DESCRIPTION ......................................................................................................... 16

9 FUNCTIONAL DESCRIPTION ........................................................................................ 33

9.1 QUADRANTS ..................................................................................................... 33

9.2 RECEIVE INTERFACE.......................................................................................33

9.3 CLOCK AND DATA RECOVERY (CDRC) .......................................................... 36

9.4 RECEIVE JITTER ATTENUATOR (RJAT) ......................................................... 38

9.5 T1 INBAND LOOPBACK CODE DETECTOR (IBCD)........................................ 39

9.6 T1 PULSE DENSITY VIOLATION DETECTOR (PDVD).................................... 39

9.7 T1 FRAMER (T1-FRMR) .................................................................................... 39

9.8 E1 FRAMER (E1-FRMR).................................................................................... 40

9.9 RECEIVE ELASTIC STORE (RX-ELST)............................................................ 46

9.10 SIGNALING EXTRACTOR (SIGX)..................................................................... 47

9.11 PERFORMANCE MONITOR COUNTERS (T1/E1-PMON) ...............................47

9.12 T1 AUTOMATIC PERFORMANCE REPORT GENERATION (APRM) .............. 48

9.13 T1 ALARM INTEGRATOR (ALMI) ...................................................................... 48

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PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

9.14 HDLC RECEIVER (RDLC) .................................................................................49

9.15 BIT ORIENTED CODE DETECTOR (RBOC) ....................................................49

9.16 RECEIVE PER-CHANNEL SERIAL CONTROLLER (RPSC) ............................ 50

9.17 PSEUDO RANDOM BINARY SEQUENCE GENERATION AND DETECTION

(PRBS) ...............................................................................................................50

9.18 BACKPLANE RECEIVE SYSTEM INTERFACE (BRIF)..................................... 50

9.19 BACKPLANE TRANSMIT SYSTEM INTERFACE (BTIF) .................................. 54

9.20 TRANSMIT PER-CHANNEL SERIAL CONTROLLER (TPSC) .......................... 57

9.21 TRANSMIT ELASTIC STORE (TX-ELST) .........................................................58

9.22 T1 BASIC TRANSMITTER (T1-XBAS) ..............................................................58

9.23 E1 TRANSMITTER (E1-TRAN).......................................................................... 59

9.24 T1 INBAND LOOPBACK CODE GENERATOR (XIBC) ..................................... 59

9.25 PULSE DENSITY ENFORCER (XPDE)............................................................. 59

9.26 T1 SIGNALING ALIGNER (SIGA) ...................................................................... 59

9.27 BIT ORIENTED CODE GENERATOR (XBOC).................................................. 60

9.28 HDLC TRANSMITTER (TDPR).......................................................................... 60

9.29 TRANSMIT JITTER ATTENUATOR (TJAT) ....................................................... 61

9.30 LINE TRANSMITTER ......................................................................................... 66

9.31 TIMING OPTIONS (TOPS) ................................................................................ 66

9.32 JTAG TEST ACCESS PORT .............................................................................. 66

9.33 MICROPROCESSOR INTERFACE ...................................................................66

10 NORMAL MODE REGISTER DESCRIPTION ................................................................ 68

10.1 NORMAL MODE REGISTER MEMORY MAP ................................................... 68

11 TEST FEATURES DESCRIPTION................................................................................ 328

11.1 JTAG TEST PORT ...........................................................................................328

12 OPERATION.................................................................................................................. 331

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE ii

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PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1

PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

12.1 CONFIGURING THE COMET-QUAD FROM RESET ..................................... 331

12.2 SERVICING INTERRUPTS.............................................................................. 338

12.3 USING THE PERFORMANCE MONITORING FEATURES ............................338

12.4 USING THE INTERNAL HDLC TRANSMITTER..............................................343

12.5 USING THE INTERNAL HDLC RECEIVER ..................................................... 346

12.6 T1 AUTOMATIC PERFORMANCE REPORT FORMAT ..................................350

12.7 USING THE TRANSMIT LINE PULSE GENERATOR ..................................... 352

12.8 USING THE LINE RECEIVER.......................................................................... 372

12.9 USING THE PRBS GENERATOR AND DETECTOR ......................................381

12.10 USING THE PER-CHANNEL SERIAL CONTROLLERS AND SIGX ............... 381

12.10.1 INITIALIZATION .................................................................................. 381

12.10.2 DIRECT ACCESS MODE.................................................................... 382

12.10.3 INDIRECT ACCESS MODE ................................................................382

12.11 T1/E1 FRAMER LOOPBACK MODES............................................................. 383

12.11.1 LINE LOOPBACK................................................................................ 383

12.11.2 PAYLOAD LOOPBACK .......................................................................383

12.11.3 PER-CHANNEL LOOPBACK .............................................................. 384

12.11.4 DIAGNOSTIC DIGITAL LOOPBACK...................................................385

12.12 RSYNC GENERATION .................................................................................... 385

12.13 BACKPLANE CONFIGURATION..................................................................... 386

12.13.1 RECEIVE CLOCK MASTER: FULL T1/E1 MODE SETTINGS ...........387

12.13.2 RECEIVE CLOCK MASTER: NX64KBIT/S MODE SETTINGS .......... 388

12.13.3 RECEIVE CLOCK MASTER: CLEAR CHANNEL MODE SETTINGS 388

12.13.4 RECEIVE CLOCK SLAVE: FULL T1/E1 MODE SETTINGS............... 389

12.13.5 RECEIVE CLOCK SLAVE: H-MVIP MODE SETTINGS...................... 389

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE iii

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PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1

PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

12.13.6 RECEIVE CLOCK SLAVE: FULL T1/E1 WITH CCS H-MVIP MODE

SETTINGS .......................................................................................... 391

12.13.7 TRANSMIT CLOCK MASTER: FULL T1/E1 MODE SETTINGS ........392

12.13.8 TRANSMIT CLOCK MASTER: NX64KBIT/S MODE SETTINGS .......393

12.13.9 TRANSMIT CLOCK MASTER: CLEAR CHANNEL MODE SETTINGS393

12.13.10 TRANSMIT CLOCK SLAVE: FULL T1/E1 MODE SETTINGS .......... 394

12.13.11 TRANSMIT CLOCK SLAVE: CLEAR CHANNEL MODE SETTINGS394

12.13.12 TRANSMIT CLOCK SLAVE: H-MVIP MODE SETTINGS................. 395

12.13.13 TRANSMIT CLOCK SLAVE: FULL T1/E1 WITH CCS H-MVIP MODE

SETTINGS .......................................................................................... 397

12.14 H-MVIP DATA FORMAT ................................................................................... 398

12.15 JTAG SUPPORT .............................................................................................. 401

12.15.1 TAP CONTROLLER ............................................................................ 403

13 FUNCTIONAL TIMING .................................................................................................. 410

13.1 BACKPLANE RECEIVE SERIAL CLOCK AND DATA INTERFACE TIMING ... 410

13.2 BACKPLANE RECEIVE H-MVIP TIMING ........................................................ 415

13.3 BACKPLANE TRANSMIT SERIAL CLOCK AND DATA INTERFACE TIMING 416

13.4 BACKPLANE TRANSMIT H-MVIP TIMING ..................................................... 424

14 ABSOLUTE MAXIMUM RATINGS ................................................................................ 426

15 D.C. CHARACTERISTICS ............................................................................................427

16 MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS.............................. 429

17 COMET-QUAD TIMING CHARACTERISTICS ............................................................. 433

17.1 RSTB TIMING .................................................................................................. 433

17.2 XCLK INPUT TIMING....................................................................................... 433

17.3 TRANSMIT BACKPLANE INTERFACE (FIGURE 83, FIGURE 84)................. 434

17.4 RECEIVE BACKPLANE INTERFACE (FIGURE 85, FIGURE 86) ................... 437

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE iv

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PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1

PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

18 ORDERING AND THERMAL INFORMATION............................................................... 445

19 MECHANICAL INFORMATION .....................................................................................446

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE v

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DATASHEET

PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1

PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

LIST OF FIGURES

FIGURE 1 - WIRELESS BASE STATION APPLICATION....................................................... 10

FIGURE 2 - V5.2 INTERFACE APPLICATION........................................................................ 10

FIGURE 3 - COMET-QUAD BLOCK DIAGRAM ..................................................................... 11

FIGURE 4 - PIN DIAGRAM ..................................................................................................... 15

FIGURE 5 - EXTERNAL ANALOG INTERFACE CIRCUITS...................................................34

FIGURE 6: - T1 JITTER TOLERANCE .................................................................................... 37

FIGURE 7: - COMPLIANCE WITH ITU-T SPECIFICATION G.823 FOR E1 INPUT JITTER .. 38

FIGURE 8: - CRC MULTIFRAME ALIGNMENT ALGORITHM................................................. 43

FIGURE 9: - RECEIVE CLOCK MASTER: FULL T1/E1 ..........................................................51

FIGURE 10: - RECEIVE CLOCK MASTER: NX64KBIT/S .........................................................51

FIGURE 11: - RECEIVE CLOCK MASTER: CLEAR CHANNEL ...............................................52

FIGURE 12: - RECEIVE CLOCK SLAVE: FULL T1/E1.............................................................. 52

FIGURE 13: - RECEIVE CLOCK SLAVE: H-MVIP..................................................................... 52

FIGURE 14: - RECEIVE CLOCK SLAVE: FULL T1/E1 WITH CCS H-MVIP .............................53

FIGURE 15: - TRANSMIT CLOCK MASTER: FULL T1/E1 .......................................................54

FIGURE 16: - TRANSMIT CLOCK MASTER: NX64KBIT/S ...................................................... 55

FIGURE 17: - TRANSMIT CLOCK MASTER: CLEAR CHANNEL............................................. 55

FIGURE 18: - TRANSMIT CLOCK SLAVE: FULL T1/E1 ........................................................... 55

FIGURE 19: - TRANSMIT CLOCK SLAVE: CLEAR CHANNEL ................................................ 56

FIGURE 20: - TRANSMIT CLOCK SLAVE: H-MVIP.................................................................. 56

FIGURE 21: - TRANSMIT CLOCK SLAVE: FULL T1/E1 WITH CCS H-MVIP........................... 57

FIGURE 22: - TJAT JITTER TOLERANCE................................................................................ 63

FIGURE 23: - TJAT MINIMUM JITTER TOLERANCE VS. XCLK ACCURACY......................... 64

FIGURE 24: - TJAT JITTER TRANSFER...................................................................................65

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE vi

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DATASHEET

PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1

PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

FIGURE 25 - TRANSMIT TIMING OPTIONS ........................................................................... 91

FIGURE 26: - FER COUNT VS. BER (E1 MODE)................................................................... 340

FIGURE 27: - CRCE COUNT VS. BER (E1 MODE)................................................................ 341

FIGURE 28: - FER COUNT VS. BER (T1 ESF MODE) ........................................................... 341

FIGURE 29: - CRCE COUNT VS. BER (T1 ESF MODE) ........................................................ 342

FIGURE 30: - CRCE COUNT VS. BER (T1 SF MODE) ..........................................................343

FIGURE 31: - TYPICAL DATA FRAME ....................................................................................349

FIGURE 32: - EXAMPLE MULTI-PACKET OPERATIONAL SEQUENCE ...............................349

FIGURE 33: - LINE LOOPBACK.............................................................................................. 383

FIGURE 34: - PAYLOAD LOOPBACK ..................................................................................... 384

FIGURE 35: - DIAGNOSTIC DIGITAL LOOPBACK................................................................. 385

FIGURE 36 - RSYNC GENERATION ..................................................................................... 386

FIGURE 37: - BOUNDARY SCAN ARCHITECTURE ..............................................................402

FIGURE 38: - TAP CONTROLLER FINITE STATE MACHINE ................................................404

FIGURE 39: - INPUT OBSERVATION CELL (IN_CELL) ......................................................... 407

FIGURE 40: - OUTPUT CELL (OUT_CELL) OR ENABLE CELL (ENABLE)........................... 408

FIGURE 41: - BIDIRECTIONAL CELL (IO_CELL)................................................................... 409

FIGURE 42: - LAYOUT OF OUTPUT ENABLE AND BIDIRECTIONAL CELLS ...................... 409

FIGURE 43: - T1 RECEIVE CLOCK MASTER : FULL T1/E1 MODE ...................................... 410

FIGURE 44: - E1 RECEIVE CLOCK MASTER : FULL T1/E1 MODE ..................................... 410

FIGURE 45: - T1 RECEIVE CLOCK MASTER: NX64KBIT/S MODE ...................................... 411

FIGURE 46: - E1 RECEIVE CLOCK MASTER : NX64KBIT/S MODE ..................................... 411

FIGURE 47: - T1/E1 RECEIVE CLOCK MASTER : CLEAR CHANNEL MODE ......................412

FIGURE 48: - T1 RECEIVE CLOCK SLAVE: FULL T1/E1 MODE ........................................... 412

FIGURE 49: - E1 RECEIVE CLOCK SLAVE: FULL T1/E1 MODE........................................... 412

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE vii

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PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1

PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

FIGURE 50: - E1 RECEIVE CLOCK SLAVE: FULL T1/E1 MODE (CMS=1) ...........................413

FIGURE 51: - T1 RECEIVE 2.048 MHZ CLOCK SLAVE: FULL T1/E1 MODE ........................ 413

FIGURE 52: - CONCENTRATION HIGHWAY INTERFACE TIMING, EXAMPLE 1 .................. 414

FIGURE 53: - CONCENTRATION HIGHWAY INTERFACE TIMING, EXAMPLE 2 .................. 414

FIGURE 54: - RECEIVE CLOCK SLAVE: H-MVIP MODE ........................................................ 415

FIGURE 55: - T1 RECEIVE CLOCK SLAVE: H-MVIP MODE................................................... 415

FIGURE 56: - E1 RECEIVE CLOCK SLAVE: H-MVIP MODE................................................... 416

FIGURE 57: - TRANSMIT BACKPLANE: CMS=0, FE=1, DE=1, BTFP IS INPUT..................... 417

FIGURE 58: - TRANSMIT BACKPLANE: CMS=0, FE=1, DE=0, BTFP IS INPUT..................... 417

FIGURE 59: - TRANSMIT BACKPLANE: CMS=1, FE=1, DE=1, BTFP IS INPUT..................... 417

FIGURE 60: - TRANSMIT BACKPLANE: CMS=1, FE=0, DE=1, BTFP IS INPUT..................... 417

FIGURE 61: - TRANSMIT BACKPLANE: CMS=0, FE=1, DE=1, BTFP IS OUTPUT ................ 417

FIGURE 62: - TRANSMIT BACKPLANE: CMS=0, FE=1, DE=0, BTFP IS OUTPUT ................ 418

FIGURE 63: - T1 TRANSMIT CLOCK MASTER : FULL T1/E1 MODE..................................... 418

FIGURE 64: - E1 TRANSMIT CLOCK MASTER : FULL T1/E1 MODE ....................................418

FIGURE 65: - T1 TRANSMIT CLOCK MASTER: NX64KBIT/S MODE (DE=1, FE=0) .............419

FIGURE 66: - E1 TRANSMIT CLOCK MASTER : NX64KBIT/S MODE (DE=1, FE=0) ............ 419

FIGURE 67: - T1 TRANSMIT CLOCK MASTER: NX64KBIT/S MODE (DE=0, FE=0) ..............419

FIGURE 68: - E1 TRANSMIT CLOCK MASTER: NX64KBIT/S MODE (DE=0, FE=0) .............. 420

FIGURE 69: - T1/E1 TRANSMIT CLOCK MASTER : CLEAR CHANNEL MODE ....................420

FIGURE 70: - T1 TRANSMIT CLOCK SLAVE: FULL T1/E1 MODE .........................................421

FIGURE 71: - E1 TRANSMIT CLOCK SLAVE : FULL T1/E1 MODE ........................................ 421

FIGURE 72: - T1 TRANSMIT 2.048 MHZ CLOCK SLAVE : FULL T1/E1 MODE...................... 422

FIGURE 73: - T1/E1 TRANSMIT CLOCK SLAVE : CLEAR CHANNEL MODE ......................... 422

FIGURE 74: - CONCENTRATION HIGHWAY INTERFACE TIMING, EXAMPLE1 .................... 423

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE viii

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PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1

PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

FIGURE 75: - CONCENTRATION HIGHWAY INTERFACE TIMING, EXAMPLE 2 .................. 423

FIGURE 76: - TRANSMIT CLOCK SLAVE: H-MVIP MODE .....................................................424

FIGURE 77: - T1 TRANSMIT CLOCK SLAVE: H-MVIP MODE ................................................ 424

FIGURE 78: - E1 TRANSMIT CLOCK SLAVE: H-MVIP MODE ................................................ 425

FIGURE 79: - MICROPROCESSOR INTERFACE READ TIMING.......................................... 430

FIGURE 80: - MICROPROCESSOR INTERFACE WRITE TIMING........................................432

FIGURE 81: - RSTB TIMING ................................................................................................... 433

FIGURE 82: - XCLK INPUT TIMING........................................................................................ 433

FIGURE 83 - BACKPLANE TRANSMIT INPUT TIMING DIAGRAM ...................................... 434

FIGURE 84 - BACKPLANE TRANSMIT OUTPUT TIMING DIAGRAM ..................................436

FIGURE 85 - BACKPLANE RECEIVE INPUT TIMING DIAGRAM ......................................... 438

FIGURE 86 - BACKPLANE RECEIVE OUTPUT TIMING DIAGRAM..................................... 439

FIGURE 87: - H-MVIP TRANSMIT DATA AND FRAME PULSE TIMING ................................ 440

FIGURE 88: - H-MVIP RECEIVE DATA TIMING......................................................................441

FIGURE 89: - TRANSMIT LINE INTERFACE TIMING ............................................................ 442

FIGURE 90: - JTAG PORT INTERFACE TIMING.................................................................... 443

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE ix

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DATASHEET

PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1

PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

LIST OF TABLES

TABLE 1: - EXTERNAL COMPONENT DESCRIPTIONS ..................................................... 35

TABLE 2 : - TERMINATION RESISTORS, TRANSFORMER RATIOS AND TRL.................. 35

TABLE 3: - E1-FRMR FRAMING STATES ............................................................................ 44

TABLE 4 - NORMAL MODE REGISTER MEMORY MAP ....................................................68

TABLE 5 - TJAT FIFO OUTPUT CLOCK SOURCE ............................................................88

TABLE 6 - TJAT PLL SOURCE............................................................................................. 89

TABLE 7 - TRANSMIT TIMING OPTIONS SUMMARY ........................................................ 89

TABLE 8 - LOSS OF SIGNAL THRESHOLDS ...................................................................103

TABLE 9 - RECEIVE BACKPLANE NX64KBIT/S MODE SELECTION.............................. 126

TABLE 10 - RECEIVE BACKPLANE RATE..........................................................................128

TABLE 11 - E1 RECEIVE BACKPLANE FRAME PULSE CONFIGURATIONS................... 131

TABLE 12 - RECEIVE BACKPLANE BIT OFFSET FOR CMS = 0....................................... 137

TABLE 13 - RECEIVE BACKPLANE BIT OFFSET FOR CMS = 1....................................... 137

TABLE 14 - TRANSMIT BACKPLANE NX64KBIT/S MODE SELECTION........................... 141

TABLE 15 - TRANSMIT BACKPLANE RATE .......................................................................143

TABLE 16 - TRANSMIT BACKPLANE BIT OFFSET FOR CMS = 0 ....................................150

TABLE 17 - TRANSMIT BACKPLANE BIT OFFSET FOR CMS = 1 ....................................150

TABLE 18 - T1 FRAMING MODES....................................................................................... 152

TABLE 19 - LOOPBACK CODE CONFIGURATIONS.......................................................... 157

TABLE 20 - SIGX INDIRECT REGISTER MAP.................................................................... 170

TABLE 21 - SIGX INDIRECT REGISTERS 10H - 1FH: CURRENT TIMESLOT/CHANNEL

SIGNALING DATA ......................................................................................................................172

TABLE 22 - SIGX INDIRECT REGISTERS 20H - 3FH: DELAYED TIMESLOT/CHANNEL

SIGNALING DATA ...................................................................................................................... 172

TABLE 23 - INDIRECT REGISTERS 40H - 5FH: PER-TIMESLOT CONFIGURATION ......173

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE x

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PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1

PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

TABLE 24 - SIGX PER-CHANNEL T1 DATA CONDITIONING ............................................ 174

TABLE 25 - SIGX PER-CHANNEL E1 DATA CONDITIONING ............................................174

TABLE 26 - T1 FRAMING FORMATS .................................................................................. 177

TABLE 27 - T1 ZERO CODE SUPPRESSION FORMATS................................................... 177

TABLE 28 - TRANSMIT IN-BAND CODE LENGTH ............................................................. 179

TABLE 29 - T1 FRAMING MODES....................................................................................... 192

TABLE 30 - TPSC INDIRECT REGISTER MAP................................................................... 208

TABLE 31 - TPSC INDIRECT REGISTERS 20H-3FH: PCM DATA CONTROL BYTE......... 210

TABLE 32 - TPSC TRANSMIT DATA CONDITIONING ........................................................ 211

TABLE 33 - TRANSMIT TEST PATTERN MODES .............................................................. 211

TABLE 34 - TRANSMIT ZERO CODE SUPPRESSION FORMATS ....................................212

TABLE 35 - TPSC INDIRECT REGISTERS 40H-5FH: IDLE CODE BYTE.......................... 213

TABLE 36 - TPSC INDIRECT REGISTERS 60H-7FH: SIGNALING/E1 CONTROL BYTE .213

TABLE 37 - TRANSMIT PER-TIMESLOT DATA MANIPULATION....................................... 214

TABLE 38 - A-LAW DIGITAL MILLIWATT PATTERN ...........................................................214

TABLE 39 - µ-LAW DIGITAL MILLIWATT PATTERN ........................................................... 215

TABLE 40 - RPSC INDIRECT REGISTER MAP .................................................................. 219

TABLE 41 - RPSC INDIRECT REGISTERS 20H-3FH: PCM DATA CONTROL BYTE ........221

TABLE 42 - RECEIVE TEST PATTERN MODES ................................................................. 221

TABLE 43 - RPSC INDIRECT REGISTERS 40H-5FH: DATA TRUNK CONDITIONING CODE BYTE 222

TABLE 44 - RPSC INDIRECT REGISTERS 61H-7FH: SIGNALING TRUNK CONDITIONING BYTE 223

TABLE 45 - NMNI SETTINGS .............................................................................................. 232

TABLE 46 - E1 SIGNALING INSERTION MODE .................................................................233

TABLE 47 - E1 TIMESLOT 0 BIT 1 INSERTION CONTROL SUMMARY............................ 235

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE xi

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PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1

PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

TABLE 48 - NATIONAL BITS CODEWORD SELECT .......................................................... 243

TABLE 49 - G.704 CRC-4 MULTIFRAME .............................................................................244

TABLE 50 - EXAMPLE SA BIT PROGRAMMING ................................................................245

TABLE 51 - TIMESLOT 0 BIT POSITION ALLOCATION ..................................................... 260

TABLE 52 - SIGNALING MULTIFRAME TIMESLOT 16, FRAME 0 BIT POSITIONS .......... 263

TABLE 53 - E1-FRMR CODEWORD SELECT..................................................................... 265

TABLE 54 - RECEIVE PACKET BYTE STATUS................................................................... 294

TABLE 55 - CLOCK SYNTHESIS MODE .............................................................................299

TABLE 56 - ALOS DETECTION/CLEARANCE THRESHOLDS........................................... 320

TABLE 57 - BOUNDARY SCAN REGISTER........................................................................ 329

TABLE 58 - DEFAULT SETTINGS........................................................................................ 331

TABLE 59 - ESF FRAME FORMAT...................................................................................... 332

TABLE 60 - SF FRAME FORMAT ........................................................................................334

TABLE 61 - T1DM FRAME FORMAT ................................................................................... 335

TABLE 62 - E1 FRAME FORMAT......................................................................................... 336

TABLE 63 - PMON POLLING SEQUENCE ..........................................................................337

TABLE 64 - ESF FDL PROCESSING ................................................................................... 338

TABLE 65: - PMON COUNTER SATURATION LIMITS (E1 MODE) ..................................... 339

TABLE 66: - PMON COUNTER SATURATION LIMITS (T1 MODE) .....................................339

TABLE 67: - PERFORMANCE REPORT MESSAGE STRUCTURE AND CONTENTS .......350

TABLE 68: - PERFORMANCE REPORT MESSAGE STRUCTURE NOTES ....................... 351

TABLE 69: - PERFORMANCE REPORT MESSAGE CONTENTS....................................... 351

TABLE 70 - T1.102 TRANSMIT WAVEFORM VALUES FOR T1 LONG HAUL (LBO 0 DB):353

TABLE 71 - T1.102 TRANSMIT WAVEFORM VALUES FOR T1 LONG HAUL (LBO 7.5 DB):

354

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE xii

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PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1

PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

TABLE 72 - T1.102 TRANSMIT WAVEFORM VALUES FOR T1 LONG HAUL (LBO 15 DB):

355

TABLE 73 - T1.102 TRANSMIT WAVEFORM VALUES FOR T1 LONG HAUL (LBO 22.5 DB):

356

TABLE 74 - T1.102 TRANSMIT WAVEFORM VALUES FOR T1 SHORT HAUL (0 - 110 FT.):

357

TABLE 75 - T1.102 TRANSMIT WAVEFORM VALUES FOR T1 SHORT HAUL (110 – 220 FT.): 358

TABLE 76 - T1.102 TRANSMIT WAVEFORM VALUES FOR T1 SHORT HAUL (220 – 330 FT.): 359

TABLE 77 - T1.102 TRANSMIT WAVEFORM VALUES FOR T1 SHORT HAUL (330 – 440 FT.): 360

TABLE 78 - T1.102 TRANSMIT WAVEFORM VALUES FOR T1 SHORT HAUL (440 – 550 FT.): 361

TABLE 79 - T1.102 TRANSMIT WAVEFORM VALUES FOR T1 SHORT HAUL (550 – 660 FT.): 362

TABLE 80 - TR62411 TRANSMIT WAVEFORM VALUES FOR T1 LONG HAUL (LBO 0 DB):

363

TABLE 81 - TR62411 TRANSMIT WAVEFORM VALUES FOR T1 SHORT HAUL (0 - 110 FT.):364

TABLE 82 - TR62411 TRANSMIT WAVEFORM VALUES FOR T1 SHORT HAUL (110 – 220 FT.): 365

TABLE 83 - TR62411 TRANSMIT WAVEFORM VALUES FOR T1 SHORT HAUL (220 – 330 FT.): 366

TABLE 84 - TR62411 TRANSMIT WAVEFORM VALUES FOR T1 SHORT HAUL (330 – 440 FT.): 367

TABLE 85 - TR62411 TRANSMIT WAVEFORM VALUES FOR T1 SHORT HAUL (440 – 550 FT.): 368

TABLE 86 - TR62411 TRANSMIT WAVEFORM VALUES FOR T1 SHORT HAUL (550 – 660 FT.): 369

TABLE 87 - TRANSMIT WAVEFORM VALUES FOR E1 120 OHM:.................................... 370

TABLE 88 - TRANSMIT WAVEFORM VALUES FOR E1 75 OHM:...................................... 371

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE xiii

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PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1

PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

TABLE 89 - LINE RECEIVER CONFIGURATION REGISTERS .......................................... 372

TABLE 90 - LINE RECEIVER RAM PROGRAMMING REGISTERS ................................... 373

TABLE 91 - SEQUENCE TO FOLLOW RLPS RAM PROGRAMMING................................ 374

TABLE 92 - RLPS EQUALIZER RAM TABLE (T1 MODE) ...................................................375

TABLE 93 - RLPS EQUALIZER RAM TABLE (E1 MODE) ................................................... 378

TABLE 94: - DATA AND CAS T1 H-MVIP FORMAT .............................................................. 399

TABLE 95: - DATA AND CAS E1 H-MVIP FORMAT.............................................................. 399

TABLE 96: - CCS T1 H-MVIP FORMAT ................................................................................400

TABLE 97: - CCS E1 H-MVIP FORMAT ................................................................................ 400

TABLE 98: - ABSOLUTE MAXIMUM RATINGS .................................................................... 426

TABLE 99: - D.C. CHARACTERISTICS ................................................................................427

TABLE 100: - MICROPROCESSOR INTERFACE READ ACCESS........................................ 429

TABLE 101: - MICROPROCESSOR INTERFACE WRITE ACCESS...................................... 431

TABLE 102: - RTSB TIMING ................................................................................................... 433

TABLE 103: - XCLK INPUT (FIGURE 82) ............................................................................... 433

TABLE 104 - TRANSMIT BACKPLANE INTERFACE ............................................................434

TABLE 105 - RECEIVE BACKPLANE INTERFACE ............................................................... 437

TABLE 106: - H-MVIP TRANSMIT TIMING (FIGURE 87) ....................................................... 440

TABLE 107: - H-MVIP RECEIVE TIMING (FIGURE 88).......................................................... 441

TABLE 108: - TRANSMIT LINE INTERFACE TIMING (FIGURE 89) ...................................... 441

TABLE 109: - JTAG PORT INTERFACE .................................................................................442

TABLE 110: - ORDERING INFORMATION ............................................................................. 445

TABLE 111: - THERMAL INFORMATION................................................................................ 445

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE xiv

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PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1

PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

1 FEATURES

• Monolithic device which integrates four, full-featured T1 and E1 framers and T1 and E1 short haul and long haul line interfaces.

• Software selectable between T1/J1 and E1 operation on a per-device basis.

• Meets or exceeds T1 and E1 shorthaul and longhaul network access specifications including ANSI

T1.102, T1.403, T1.408, AT&T TR 62411, ITU-T G.703, G.704 as well as ETSI 300-011, CTR-4, CTR12 and CTR-13.

• Provides encoding and decoding of B8ZS, HDB3 and AMI line codes.

• Provides receive equalization, clock recovery and line performance monitoring.

• Provides transmit and receive jitter attenuation.

• Provides digitally programmable long haul and short haul line build out.

• Provides four full-featured HDLC controllers, each with 128-byte transmit and receive FIFO buffers.

• Automatically generates and transmits DS-1 performance report messages to ANSI T1.231 and ANSI

T1.408 specifications.

• Supports Nx64Kbit/s fractional bandwidth backplane.

• Supports transfer of PCM data to/from 1.544MHz and 2.048MHz system-side devices. Also supports

a fractional T1 or E1 system interface with independent backplane receive/backplane transmit Nx64Kbit/s rates. Supports a 2.048 MHz system-side interface for T1 mode without external clock gapping.

• Supports 8.192 Mbit/s, H-100 compatible, H-MVIP on the system interface for all T1 or E1 links, a separate 8.192 Mbit/s H-MVIP system interface for all T1 or E1 CAS channels and a separate 8.192 Mbit/s H-MVIP system interface for all T1 or E1 CCS, V5.1/V5.2, and GR.303 channels.

• Provides a selectable, per channel independent de-jittered T1 or E1 recovered clock for system timing and redundancy.

• Provides PRBS generators and detectors on each tributary for error testing at DS1, E1 and Nx64Kbit/s rates as recommended in ITU-T O.151 and O.152.

• Provides robbed bit signaling extraction and insertion on a per-DS0 basis.

• Register level compatibility with the PM4388 TOCTL Octal T1 Framer, the PM6388 EOCTL Octal E1

Framer, the PM4351 COMET E1/T1 transceiver, and the PM8315 TEMUX T1/E1 Framer with integrated Mapper and M13 MUX.

• Provides an 8-bit microprocessor bus interface for configuration, control, and status monitoring.

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PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

• Uses line rate system clock.

• Provides an IEEE P1149.1 (JTAG) compliant test access port (TAP) and controller for boundary scan

test.

• Implemented in a low power 5 V tolerant 2.5/3.3 V CMOS technology.

• Available in a high density 208-pin fine pitch PBGA (17 mm by 17 mm) package.

• Provides a -40°C to +85°C Industrial temperature operating range.

1.1 Receiver section:

• Typical signal recovery of up to -43dB at 1024kHz (E1) and up to -44dB at 772kHz (T1/J1).

• Guaranteed minimum signal recovery of -32dB at 1024kHz (E1) and -36dB at 772kHz (T1/J1).

• Recovers clock and data using a digital phase locked loop for high jitter tolerance.

• Frames to ITU-T G.704 basic and CRC-4 multiframe formatted E1 signals. The framing procedures

are consistent ITU-T G.706 specifications.

• Frames to DSX/DS-1 signals in SF and ESF formats.

• Frames to TTC JT-G704 multiframe formatted J1 signals. Supports the alternate CRC-6 calculation

for Japanese applications. Frames in the presence of and detects the “Japanese Yellow” alarm.

• Tolerates more than 0.3 UI peak-to-peak, high frequency jitter as required by AT&T TR 62411 and Bellcore TR-TSY-000170.

• Detects violations of the ANSI T1.403 12.5% pulse density rule over a moving 192-bit window.

• Provides loss of signal detection as per ITU-T G.775 and ANSI T1.231. Red, Yellow, and AIS alarm

detection and integration are according to ANSI T1.231 specifications.

• Provides programmable in-band loopback activate and deactivate code detection.

• Supports line and path performance monitoring according to AT&T and ANSI specifications.

Accumulators are provided for counting ESF CRC-6 errors, framing bit errors, line code violations and loss of frame or change of frame alignment events.

• Provides performance monitoring counters sufficiently large as to allow performance monitor counter polling at a minimum rate of once per second. Optionally, updates the performance monitoring counters and interrupts the microprocessor once per second, timed to the receive line.

Based on actual results using PIC-22 gauge cable emulation. Refer to the COMET-QUAD Evaluator

Board for design recommendations (PMC-1991237).

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PM4354 COMET-QUAD

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• Provides ESF bit-oriented code detection and an HDLC/LAPD interface for terminating the ESF facility data link.

• Supports polled or interrupt-driven servicing of the HDLC interface.

• Extracts the data link in ESF mode and extracts a datalink in the E1 national use bits.

• Extracts 4-bit codewords from the E1 national use bits as specified in ETS 300 233

• Extracts up to three HDLC links, to an H-MVIP Bus, to support the D-channel for ISDN Primary Rate

Interfaces and the C-channels for V5.1/V5.2 interfaces. Detects the V5.2 link identification signal.

• Provides a two-frame elastic store buffer for backplane rate adaptation that performs controlled slips and indicates slip occurrence and direction.

• Provides DS-1 robbed bit signaling extraction, with optional data inversion, programmable idle code substitution, digital milliwatt code substitution, bit fixing, and two superframes of signaling debounce on a per-channel basis.

• Frames to the E1 signaling multiframe alignment when enabled and extracts channel associated signaling. Alternatively, a common channel signaling data link may be extracted from timeslot 16.

• Indicates signaling state change, and two superframes of signaling debounce on a per-DS0 basis.

• Provides trunk conditioning which forces programmable trouble code substitution and signaling

conditioning on all channels or on selected channels.

• Provides diagnostic, line loopbacks and per-DS0 payload loopback.

• A pseudo-random sequence user selectable from 2

–1, 215 –1 or 220 –1, may be detected in the T1/E1 stream in either the backplane receive or backplane transmit directions. The detector counts pattern errors using a 24-bit saturating PRBS error counter.

• Provides four single-rail PCM and signaling data outputs for 1.544 Mbit/s or 2.048 Mbit/s backplane buses.

1.2 Transmitter section:

• Supports transfer of transmitted single rail PCM and signaling data from 1.544 Mbit/s and 2.048 Mbit/s backplane buses.

• Generates DSX-1 shorthaul and DS-1 longhaul pulses with programmable pulse shape compatible with AT&T, ANSI and ITU requirements.

• Generates E1 pulses compliant to G.703 recommendations.

• Provides a digitally programmable pulse shape extending up to 5 transmitted bit periods for custom

long haul pulse shaping applications.

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PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

• Provides line outputs that are current limited and may be tristated for protection or in redundant applications.

• Provides a digital phase locked loop for generation of a low jitter transmit clock complying with all jitter attenuation, jitter transfer and residual jitter specifications of AT&T TR 62411 and ETSI TBR 12 and TBR 13.

• Provides a FIFO buffer for jitter attenuation and rate conversion in the transmit path.

• Provides a two-frame payload slip buffer to allow independent backplane and line timing.

• A pseudo-random sequence user selectable from 2

–1, 215 –1 or220 –1, may be inserted into or

detected from the T1 or E1 stream in either the backplane receive or backplane transmit directions.

• Transmits G.704 basic and CRC-4 multiframe formatted E1 signals or D4, SF or ESF formatted DSX/DS-1 signals.

• Transmits the “Japanese Yellow” alarm. Transmits TTC JT-G704 multiframe formatted J1 signals. Supports the alternate ESF CRC-6 calculation for Japanese applications.

• Supports unframed mode and framing bit, CRC, or data link by-pass.

• Provides signaling insertion, programmable idle code substitution, digital milliwatt code substitution,

and data inversion on a per channel basis.

• Provides trunk conditioning which forces programmable trouble code substitution and signaling conditioning on all channels or on selected channels.

• Provides minimum ones density through Bell (bit 7), GTE or DDS zero code suppression on a per channel basis.

• Detects violations of the ANSI T1.403 12.5% pulse density rule over a moving 192-bit window and optionally stuffs ones to maintain minimum ones density.

• Allows insertion of framed or unframed in-band loopback code sequences.

• Allows insertion of a data link in ESF mode. Optionally inserts a datalink in the E1 national use bits.

• Supports 4-bit codeword insertion in the E1 national use bits as specified in ETS 300 233

• Inserts, from an H-MVIP bus, up to three HDLC links to support the D-channel for ISDN Primary Rate

Interfaces and the C-channels for V5.1/V5.2 interfaces.

• Supports transmission of the alarm indication signal (AIS) and the Yellow alarm signal. Supports “Japanese Yellow” alarm generation.

• Provides ESF bit-oriented code generation.

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PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1

PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

Synchronous System Interfaces:

• Provides an 8.192 Mbit/s H-MVIP data interface for synchronous access to all the T1 DS0s or E1 timeslots. Compatible with H-MVIP PCM backplanes supporting 8.192 Mbit/s.

• Provides an 8.192 Mbit/s H-MVIP interface for synchronous access to all channel associated signaling (CAS) bits for all T1 DS0s or E1 timeslots. The CAS bits occupy one nibble of every byte on the HMVIP interfaces and are repeated over the entire T1 or E1 multi-frame.

• Provides an 8.192 Mbit/s H-MVIP interface for common channel signaling (CCS) channels as well as V5.1 and V5.2 channels. In T1 mode DS0 24 is available through this interface. In E1 mode timeslots 15, 16 and 31 are available through this interface.

• All links accessed via the H-MVIP interface will be synchronously timed to the common H-MVIP clock and frame alignment signals: CMV8MCLK, CMVFPB, CMVFPC

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE 5

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PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1

PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

2 APPLICATIONS

• Wireless Base Station, Transceiver or Digital Loop Carrier

• DSLAM

• Metro Optical Access Equipment

• Voi ce Gateway

• Enterprise Router

• SONET/SDH Multiplexer

• Channel and Data Service Units (CSU/DSU)

• Digital Private Branch Exchanges (PBX)

• Digital Access Cross-Connect Systems (DACS)

• ISDN Primary Rate Interfaces (PRI)

• Test Equipment

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE 6

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PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1

PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

3 REFERENCES

1. ANSI - T1.101-1987 - American National Standard for Telecommunications - Digital Hierarchy

- Timing Synchronization.

2. ANSI - T1.102-1993 - American National Standard for Telecommunications - Digital Hierarchy

- Electrical Interfaces.

3. ANSI - T1.107-1995 - American National Standard for Telecommunications - Digital Hierarchy

- Formats Specification.

4. ANSI - T1.231-1993 - American National Standard for Telecommunications - Layer 1 InService Digital Transmission Performance Monitoring

5. ANSI - T1.403-1995 - American National Standard for Telecommunications - Carrier to Customer Installation - DS-1 Metallic Interface Specification.

6. ANSI - T1.408-1990 - American National Standard for Telecommunications - Integrated Services Digital Network (ISDN) Primary Rate - Customer Installation Metallic Interfaces Layer 1 Specification.

7. T1M1.3/91-003R3 - American National Standard for Telecommunications - In-Service Digital Transmission Performance Monitoring Draft Standard.

8. TA-TSY-000147 - Bell Communications Research - DS-1 Rate Digital Service Monitoring Unit Functional Specification, Issue 1, October, 1987.

9. AT&T - PUB 54016 - Requirements For Interfacing Digital Terminal Equipment To Services Employing The Extended Superframe Format, October 1984.

10. AT&T - TR 62411 - Accunet T1.5 - Service Description and Interface Specification, December 1990.

11. AT&T - TR 62411 - Accunet T1.5 - Service Description and Interface Specification, Addendum 1, March 1991.

12. AT&T - TR 62411 - Accunet T1.5 - Service Description and Interface Specification, Addendum 2, October 1992.

13. AT&T - Interface Specification - Concentration Highway Interface - November 1990.

14. TR-TSY-000170 - Bellcore – Digital Cross-Connect System Requirements and Objectives, Issue 1, November 1985.

15. TR-N1WT-000233 - Bell Communications Research - Wideband and Broadband Digital Cross-Connect Systems Generic Criteria, Issue 3, November 1993.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE 7

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PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1

PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

16. TR-NWT-000303 - Bell Communications Research - Integrated Digital Loop Carrier Generic Requirements, Objectives, and Interface, Issue 2, December, 1992.

17. TR-TSY-000499 - Bell Communications Research - Transport Systems Generic Requirements (TSGR): Common Requirement, Issue 5, December, 1993.

18. TR-TSY-000820 - Bell Communications Research - OTGR: Network Maintenance Transport Surveillance - Generic Digital Transmission Surveillance, Section 5.1, Issue 1, June 1990.

19. ETSI - ETS 300 011 - ISDN Primary Rate User-Network Interface Specification and Test Principles, 1992.

20. ETSI - ETS 300 233 - Access Digital Section for ISDN Primary Rates.

21. ETSI - ETS 300 324-1 - Signaling Protocols and Switching (SPS); V interfaces at the Digital Local Exchange (LE) V5.1 Interface for the Support of Access Network (AN) Part 1: V5.1 Interface Specification, February 1994.

22. ETSI - ETS 300 347-1 - Signaling Protocols and Switching (SPS); V Interfaces at the Digital Local Exchange (LE) V5.2 Interface for the Support of Access Network (AN) Part 1: V5.2 Interface Specification, September 1994.

23. ETSI - CTR 4 - Integrated Services Digital Network (ISDN); Attachment requirements for terminal equipment to connect to an ISDN using ISDN primary rate access, November 1995.

24. ETSI - CTR 12 - Business Telecommunications (BT); Open Network Provision (ONP) technical requirements; 2 048 kbit/s digital unstructured leased lines (D2048U) Attachment requirements for terminal equipment interface, December 1993.

25. ETSI - CTR 13 - Business Telecommunications (BTC); 2 048 kbit/s digital structured leased lines (D2048S); Attachment requirements for terminal equipment interface, January 1996.

26. FCC Rules - Part 68.308 - Signal Power Limitations.

27. ITU-T - Recommendation G.703 - Physical/Electrical Characteristics of Hierarchical Digital Interface, Geneva, 1991.

28. ITU-T - Recommendation G.704 - Synchronous Frame Structures Used at Primary Hierarchical Levels, July 1995.

29. ITU-T - Recommendation G.706 - Frame Alignment and CRC Procedures Relating to G.704 Frame Structures, 1991.

30. ITU-T - Recommendation G.732 – Characteristics of Primary PCM Multiplex Equipment Operating at 2048 kbit/s, 1993.

31. ITU-T - Recommendation G.711 – Pulse Code Modulation (PCM) of Voice Frequencies, 1993.

32. ITU-T - Recommendation G.775 - Loss of Signal (LOS), November 1994.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE 8

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PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1

PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

33. ITU-T Recommendation G.802, - Interworking Between Networks Based on Different Digital Hierarchies and Speech Encoding Laws, 1993.

34. ITU-T Recommendation G.823, - The Control of Jitter and Wander Within Digital Networks Which are Based on the 2048 kbit/s Hierarchy, 1993.

35. ITU-T Recommendation G.964, - V-Interfaces at the Digital Local Exchange (LE) - V5.1 Interface (Based on 2048 kbit/s) for the Support of Access Network (AN), June 1994.

36. ITU-T Recommendation G.965, - V-Interfaces at the Digital Local Exchange (LE) - V5.2 Interface (Based on 2048 kbit/s) for the Support of Access Network (AN), March 1995.

37. ITU-T - Recommendation I.431 - Primary Rate User-Network Interface – Layer 1 Specification, 1993.

38. ITU-T Recommendation O.151, - Error Performance Measuring Equipment For Digital Systems at the Primary Bit Rate and Above, 1988.

39. ITU-T Recommendation O.152 - Error Performance Measuring Equipment for Bit Rates of 64 kbit/s and N X 64 kbit/s, October 1992

40. ITU-T Recommendation O.153 - Basic Parameters for the Measurement of Error Performance at Bit Rates below the Primary Rate, October 1992.

41. ITU-T Recommendation Q.921 - ISDN User-Network Interface Data Link Layer Specification, March 1993.

42. International Organization for Standardization, ISO 3309:1984 - High-Level Data Link Control Procedures -- Frame Structure.

43. TTC Standard JT-G703 - Physical/Electrical Characteristics of Hierarchical Digital Interfaces,

1995.

44. TTC Standard JT-G704 - Frame Structures on Primary and Secondary Hierarchical Digital Interfaces, 1995.

45. TTC Standard JT-G706 - Frame Synchronization and CRC Procedure

46. TTC Standard JT-I431 - ISDN Primary Rate User-Network Interface Layer 1 - Specification,

1995.

47. Nippon Telegraph and Telephone Corporation - Technical Reference for High-Speed Digital Leased Circuit Services, Third Edition, 1990.

48. GO-MVIP - Multi-Vendor Integration Protocol, MVIP-90 Release 1.1, 1994.

49. GO-MVIP – H-MVIP Standard, Release 1.1a, 1997.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE 9

RELEASED

PM4354 COMET-QUAD

DATASHEET

PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1

TRANSCEIVER / FRAMER

4 APPLICATION EXAMPLE

Figure 1 - Wireless Base Station Application

Fibre Optics

Public

DS3

PM8313

PM5342

SPECTRA

D3MX

Basestation

Switch Fabric

PM43 54 COMET-Qua d

Switched

Telephone

PM43 54 COMET-Qua d

Network

Base Station Controller

Figure 2 - V5.2 Interface Application

PM5342

SPECTRA

-155

Intel or

Motorola

µµµµP

PM5362

TUPP+

PM7364

FREEDM-32

Switch Fabric

T1/E1/J1

PM4354 COMET-Quad

Framer

T1/E1/J1

LH/SH

LIU

Software

Selectable

T1/E1/J1

Framer

T1/E1/J1 Longhaul/ Shorthaul

LIU

PM4354 COMET-Quad

V5.2

4 x E1

Bundle

PM4351 COMET

CDMA/TDMA/GSM

Base Transceiver Station

●●●●

T1/E1/J1

LH/SH

Framer

LIU

PM4354 COMET-Quad

µµµµP

Access Concentrator

Int el or Mo torola

Switch Fabr ic

FREEDM-32

Tx/Rx

Subsystem

µµµµ

Linecard Linecard

●●●●

Linecard

PM7364

Central Office Switch

Subs cribers

STM-1

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE 10

●●●●●●●●●●●●

RELEASED

PM4354 COMET-QUAD

DATASHEET

PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1

TRANSCEIVER / FRAMER

5 BLOCK DIAGRAM

Figure 3 - COMET-QUAD Block Diagram

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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE 11

RELEASED

DATASHEET

PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1

PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

6 DESCRIPTION

The PM4354 Four Channel Combined E1/T1/J1 Transceiver and Framer (COMET-QUAD) is a feature-rich monolithic integrated circuit suitable for use in long haul and short haul T1, J1 and E1 systems with a minimum of external circuitry. The COMET-QUAD is software configurable, allowing feature selection without changes to external wiring.

Analog circuitry is provided to allow direct reception of long haul E1 and T1/J1 compatible signals typically with up to 43 dB cable loss at 1024 kHz (E1) and up to 44 dB cable loss at 772 kHz (T1/J1) using a minimum of external components. Typically, only line protection, a transformer and a line termination resistor are required.

The COMET-QUAD recovers clock and data from the line and frames to incoming data. In T1 mode, it can frame to SF and ESF signal formats. In E1 mode, the COMET-QUAD frames to basic G.704 E1 signals and CRC-4 multiframe alignment signals, and automatically performs the G.706 interworking procedure. AMI, HDB3 and B8ZS line codes are supported.

The COMET-QUAD supports detection of various alarm conditions such as loss of signal, pulse density violation, Red alarm, Yellow alarm, and AIS alarm in T1 mode and loss of signal, loss of frame, loss of signaling multiframe and loss of CRC multiframe in E1 mode. The COMET-QUAD also supports reception of remote alarm signal, remote multiframe alarm signal, and alarm indication signal in E1 mode. The presence of Yellow and AIS patterns in T1 mode and remote alarm and AIS patterns in E1 mode is detected and indicated. In T1 mode, the COMET-QUAD integrates Yellow, Red, and AIS alarms as per industry specifications. In E1 mode, the COMETQUAD integrates Red and AIS alarms.

Performance monitoring with accumulation of CRC-6 errors, framing bit errors, line code violations, and loss of frame events are provided in T1 mode. In E1 mode, CRC-4 errors, far end block errors, framing bit errors, and line code violation are monitored and accumulated.

The COMET-QUAD provides one receive HDLC controller per channel for the detection and termination of messages in the ESF facility data link (T1), national use bits (E1), or in any arbitrary timeslot (T1 or E1). In T1 mode, the COMET-QUAD also detects the presence of in-band loop back codes and ESF bit oriented codes. Detection and optional debouncing of the 4-bit Sa-bit codewords defined in ITU-T G.704 and ETSI 300-233 is supported. An interrupt may be generated on any change of state of the Sa codewords.

Dual (transmit and receive) elastic stores for slip buffering and rate adaptation to backplane timing are provided, as is a signaling extractor that supports signaling debounce, signaling freezing, idle code substitution, digital milliwatt tone substitution, data inversion, and signaling bit fixing on a perchannel basis. Receive side data and signaling trunk conditioning is also provided.

In T1 mode, the COMET-QUAD generates framing for SF and ESF formats. In E1 mode, the COMET-QUAD generates framing for a basic G.704 E1 signal. The signaling multiframe

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE 12

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PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1

PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

alignment structure and the CRC multiframe structure may be optionally inserted. Framing can be optionally disabled.

Internal analog circuitry allows direct transmission of long haul and short haul T1 and E1 compatible signals using a minimum of external components. Typically, only line protection, a transformer and an optional line termination resistor are required. Digitally programmable pulse shaping allows transmission of DSX-1 compatible signals up to 655 feet from the cross-connect, E1 short haul pulses into 120 ohm twisted pair or 75 ohm coaxial cable, E1 long haul pulses into 120 ohm twisted pair as well as long haul DS-1 pulses into 100 ohm twisted pair with integrated support for LBO filtering as required by the FCC rules. In addition, the programmable pulse shape extending over 5-bit periods allows customization of short haul and long haul line interface circuits to application requirements.

In the transmit path, the COMET-QUAD supports signaling insertion, idle code substitution, digital milliwatt tone substitution, data inversion, and zero code suppression on a per-channel basis. Zero code suppression may be configured to Bell (bit 7), GTE, or DDS standards, and can also be disabled. Transmit side data and signaling trunk conditioning is also provided. Signaling bit transparency from the backplane may be enabled.

The COMET-QUAD provides one transmit HDLC controller per channel. These controllers may be used for the transmission of messages in the ESF data link (T1), national use bits (E1), or in any timeslot (T1 or E1). In T1 mode, the COMET-QUAD can be configured to generate in-band loop back codes and ESF bit oriented codes. In E1 mode, transmission of the 4-bit Sa codewords defined in ITU-T G.704 and ETSI 300-233 is supported.

To provide for V5 applications where up to three HDLC channels are contained in each E1, the COMET-QUAD provides a CCS H-MVIP interface. This interface allows the HDLC channels to be inserted or extracted for external processing.

Each channel of the COMET-QUAD can generate a low jitter transmit clock from a variety of clock references, and also provides jitter attenuation in the receive path. A low jitter recovered T1 clock can be routed outside the COMET-QUAD for network timing applications.

Serial PCM interfaces to each T1/E1 framer allow 1.544 Mbit/s or 2.048 Mbit/s backplane receive/backplane transmit system interfaces to be directly supported. Tolerance of gapped clocks allows other backplane rates to be supported with a minimum of external logic.

For synchronous backplane systems, 8.192 Mbit/s H-MVIP interfaces are provided for access to PCM data, channel associated signaling (CAS) and common channel signaling (CCS) for each T1 or E1. The CCS signaling H-MVIP interface is independent of the 64 Kbit/s PCM and CAS H-MVIP access. The use of the H-MVIP interface requires that common clocks and frame pulse be used along with T1/E1 elastic stores.

The COMET-QUAD is configured, controlled and monitored via a generic 8-bit microprocessor bus through which all internal registers are accessed. All sources of interrupts can be masked and acknowledged through the microprocessor interface.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE 13

RELEASED

DATASHEET

PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1

PM4354 COMET-QUAD

TRANSCEIVER / FRAMER

7 PIN DIAGRAM

The COMET-QUAD is packaged in a 208-pin PBGA package having a body size of 17mm by 17mm and a ball pitch of 1.0 mm. The center 16 balls are not used as signal I/Os and are thermal balls.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE 14

RELEASED

PM4354 COMET-QUAD

DATASHEET

PMC-1990315 ISSUE 6 FOUR CHANNEL COMBINED E1/T1/J1

TRANSCEIVER / FRAMER

Figure 4 - Pin Diagram

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

D (2) D (1)

D (3) VSS33 (1) D (0) TXTIP1 (1) TAVS3 (1) TXTIP2 (1) RAVD2 (1) RAVD1 (1) RAVD1 (2) RAVS2 (2)

D (4) D (5) VDD33 (1) TAVS2 (1) TXCM (1) TAVS1 (1) RXTIP (1) QAVD (1) RVREF (2)

VSS33 (2) D (6) D (7) VDD33 (2)

CASBRD_

RPC M (1 )

CMVFPC CMVFPB BTCLK (1)

VDDC25

(1)

V SSC 25

(2)

VDDC25

(3)

MVBTD CCSBTD

VDDC25

(4)

TXR I N G 1

TAVD2 (1)TAVD3 (1)TAVD1 (1)

(1)

BRCLK ( 1) BRSIG ( 1) BRFP (1)

CASBTD_B

TPC M ( 1 )

V SSC 25

(1)

VDDQ33

(1)

V SS33 ( 3)

BTC LK (3 )

CMV8MC

V SSQ 33

BTSIG (1 )

VDDC25

V SSC 25

(1)

BTFP (1) GND GND GND GND BTPCM (2) BTFP (2)

(2)

RES[4] GND GND GND GND XCLK BTSIG (2) RES[3]

(3)

VDD33 (3) GND GND GND GND

MVBRD_C

(4)

CSBRD

TXR I N G 2

RAVS2 (1) RAVS1 (1) RES (5) Q AVS (1) RXTIP (2) TA VS1 (2) TXCM (2) TA VD2 (2) RD B A (10) A (9)

(1)

RXRI N G

RVREF (1) RAVS1 (2) RAVD2 (2) TXTIP2 (2) TAVS3 (2) TXTIP1 (2) A (1) A (3) A (5)

(1)

208 PBGA

GND GND GND GND

TOP VIEW

RXRI N G

(2)

TXR I N G 2

TAVS2 (2) A (0) A (2) A (4) A (6)

(2)

TA V D 1 ( 2) TA V D 3 (2 )

TXR I N G 1

VSS33 (9) A (7) A (8)

(2)

RSTB A LE WRB C SB

BRPCM (2) VSS33 (5) INTB BRCLK (2)

V SSC 25

BRFP (2) BRSIG (2) VDD33 (5)

(5)

V SSQ 33

VDDQ33

(2)

V SS33 ( 6) RE S[ 1]

VDDC25

BTC LK (2 )

(5)

VDDC25

(6)

V SSC 25

(7)

V SSC 25

CTCLK

(2)

(8)

(6)

BTFP (3) VSS33 (8) BTSIG (3) BTPCM (3)

BRC LK (3) VDD33 (4) RES[2] TAV S2 (3)

BRPCM (3) BRSIG (3) TRSTB TXTIP1 (3) TXCM (3) TAVS1 (3) RXTIP (3) RES (6) RVREF (4)

BRFP (3) VSS33 (4) TM S

TD O TC K TD I TA V D 2 ( 3 ) TA V D3 ( 3) TA V D 1 (3 )

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

TXR I N G 2

RAVS2 (3) RAVS1 (3) CA VS C AVD RXTIP (4) TAVS1 (4) TXCM (4) BTFP (4) VDD33 (6) BRPCM (4) BRC LK (4)

(3)

TXR I N G 1

TAVS3 (3) TXTIP2 (3) RAVD2 (3) RAV D1 (3) RAVS1 (4) RAVS2 (4)

(3)

RXRI N G

RVREF (3) RAVD1 (4) RAVD2 (4) TXTIP2 (4) TAVS3 (4)

(3)

RXRI N G

TA VD1 (4) TA VD3 (4) TA VD2 (4) VSS33 (7) BRFP (4) BRSIG (4)

(4)

TXR I N G 2

(4)

VDDC25

BTCLK (4) BTSIG (4) BTPCM (4)

(7)

TAVS2 (4) TXTIP1 (4) QA VD (2) PIO RSYNC

TXR I N G 1

QAV S (2) RES (8) RES (7)

(4)

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE 15

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