PMC PM4328-PI Datasheet
STANDARD PRODUCT
DATASHEET
PMC-2011596 ISSUE 1 HIGH DENSITY T1/E1 FRAMER
PM4328 TECT3
AND M13 MULTIPLEXER
PM4328
TECT3
HIGH DENSITY T1/E1 FRAMER WITH
INTEGRATED M13 MULTIPLEXER
DATASHEET
PROPRIETARY AND CONFIDENTIAL
ISSUE 1: AUGUST 2001
PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000
STANDARD PRODUCT
DATASHEET
PMC-2011596 ISSUE 1 HIGH DENSITY T1/E1 FRAMER
PM4328 TECT3
AND M13 MULTIPLEXER
CONTENTS
1 FEATURES...............................................................................................1
2 APPLICATIONS...................................................................................... 11
3 REFERENCES .......................................................................................12
4 APPLICATION EXAMPLES....................................................................15
5 BLOCK DIAGRAM..................................................................................16
5.1 TOP LEVEL BLOCK DIAGRAM...................................................16
5.2 M13 MULTIPLEXER MODE BLOCK DIAGRAM..........................18
5.3 DS3 FRAMER ONLY BLOCK DIAGRAM.....................................18
6 DESCRIPTION .......................................................................................20
7 PIN DIAGRAM ........................................................................................25
8 PIN DESCRIPTION ................................................................................26
9 FUNCTIONAL DESCRIPTION ...............................................................55
9.1 T1 FRAMER (T1-FRMR)..............................................................55
9.2 E1 FRAMER (E1-FRMR) .............................................................55
9.3 PERFORMANCE MONITOR COUNTERS (T1/E1-PMON) .........62
9.4 BIT ORIENTED CODE DETECTOR (RBOC) ..............................63
9.5 HDLC RECEIVER (RDLC)...........................................................63
9.6 T1 ALARM INTEGRATOR (ALMI)................................................64
9.7 ELASTIC STORE (ELST) ............................................................65
9.8 SIGNALING ELASTIC STORES (RX-SIG-ELST AND TX_SIG-
ELST)...........................................................................................65
9.9 SIGNALING EXTRACTOR (SIGX)...............................................66
PROPRIETARY AND CONFIDENTIAL i
STANDARD PRODUCT
DATASHEET
PMC-2011596 ISSUE 1 HIGH DENSITY T1/E1 FRAMER
PM4328 TECT3
AND M13 MULTIPLEXER
9.10 RECEIVE PER-CHANNEL SERIAL CONTROLLER (RPSC) ......67
9.11 BASIC TRANSMITTER (XBAS)...................................................67
9.12 E1 TRANSMITTER (E1-TRAN) ...................................................68
9.13 TRANSMIT PER-CHANNEL SERIAL CONTROLLER (TPSC) ....68
9.14 SIGNALING ALIGNER (SIGA) .....................................................68
9.15 BIT ORIENTED CODE GENERATOR (XBOC)............................69
9.16 HDLC TRANSMITTERS (TDPR) .................................................69
9.17 T1 AUTOMATIC PERFORMANCE REPORT GENERATION
(APRM) ........................................................................................70
9.18 RECEIVE AND TRANSMIT DIGITAL JITTER ATTENUATOR (RJAT,
TJAT) ...........................................................................................71
9.19 TIMING OPTIONS (TOPS) ..........................................................77
9.20 PSEUDO RANDOM BINARY SEQUENCE GENERATION AND
DETECTION (PRBS) ...................................................................77
9.21 PSEUDO RANDOM PATTERN GENERATION AND DETECTION
(PRGD) ........................................................................................77
9.22 DS3 FRAMER (DS3-FRMR) ........................................................78
9.23 PERFORMANCE MONITOR ACCUMULATOR (DS3-PMON) .....80
9.24 DS3 TRANSMITTER (DS3-TRAN) ..............................................81
9.25 M23 MULTIPLEXER (MX23)........................................................82
9.26 DS2 FRAMER (DS2-FRMR) ........................................................82
9.27 M12 MULTIPLEXER (MX12)........................................................84
9.28 EGRESS SYSTEM INTERFACE (ESIF) ......................................85
9.29 INGRESS SYSTEM INTERFACE (ISIF) ......................................91
9.30 EXTRACT SCALEABLE BANDWIDTH INTERCONNECT (EXSBI)
.....................................................................................................96
PROPRIETARY AND CONFIDENTIAL ii
STANDARD PRODUCT
DATASHEET
PMC-2011596 ISSUE 1 HIGH DENSITY T1/E1 FRAMER
PM4328 TECT3
AND M13 MULTIPLEXER
9.31 INSERT SCALEABLE BANDWIDTH INTERCONNECT (INSBI) .97
9.32 SCALEABLE BANDWIDTH INTERCONNECT PISO (SBIPISO).98
9.33 SCALEABLE BANDWIDTH INTERCONNECT SIPO (SBISIPO).98
9.34 JTAG TEST ACCESS PORT........................................................98
9.35 MICROPROCESSOR INTERFACE .............................................98
10 NORMAL MODE REGISTER DESCRIPTION...................................... 118
11 TEST FEATURES DESCRIPTION ....................................................... 119
11.1 JTAG TEST PORT.....................................................................121
12 OPERATION.........................................................................................134
12.1 DS3 FRAME FORMAT...............................................................134
12.2 SERVICING INTERRUPTS .......................................................136
12.3 USING THE PERFORMANCE MONITORING FEATURES.......136
12.4 USING THE INTERNAL FDL TRANSMITTER...........................140
12.5 USING THE INTERNAL DATA LINK RECEIVER.......................144
12.6 T1 AUTOMATIC PERFORMANCE REPORT FORMAT.............148
12.7 USING THE PER-CHANNEL SERIAL CONTROLLERS............150
12.8 T1/E1 FRAMER LOOPBACK MODES ......................................151
12.9 DS3 LOOPBACK MODES .........................................................154
12.10 SBI BUS DATA FORMATS.........................................................157
12.11 H-MVIP DATA FORMAT.............................................................166
12.12 SERIAL CLOCK AND DATA FORMAT.......................................170
12.13 PRGD PATTERN GENERATION...............................................170
12.14 JTAG SUPPORT........................................................................175
13 FUNCTIONAL TIMING .........................................................................183
PROPRIETARY AND CONFIDENTIAL iii
STANDARD PRODUCT
DATASHEET
PMC-2011596 ISSUE 1 HIGH DENSITY T1/E1 FRAMER
PM4328 TECT3
AND M13 MULTIPLEXER
13.1 DS3 LINE SIDE INTERFACE TIMING .......................................183
13.2 DS3 SYSTEM SIDE INTERFACE TIMING ................................185
13.3 SBI DROP BUS INTERFACE TIMING .......................................187
13.4 SBI ADD BUS INTERFACE TIMING..........................................188
13.5 EGRESS H-MVIP LINK TIMING ................................................188
13.6 INGRESS H-MVIP LINK TIMING...............................................189
13.7 EGRESS SERIAL CLOCK AND DATA INTERFACE TIMING ....190
13.8 INGRESS SERIAL CLOCK AND DATA INTERFACE TIMING ...195
14 ABSOLUTE MAXIMUM RATINGS........................................................199
15 D.C. CHARACTERISTICS....................................................................200
16 MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS......202
17 TECT3 TIMING CHARACTERISTICS ..................................................206
18 ORDERING AND THERMAL INFORMATION ......................................234
19 MECHANICAL INFORMATION.............................................................235
LIST OF FIGURES
FIGURE 1: CHANNELIZED DS3 CIRCUIT EMULATION APPLICATION .........15
FIGURE 2: HIGH DENSITY FRAME RELAY APPLICATION ............................15
FIGURE 3: TECT3 BLOCK DIAGRAM..............................................................17
FIGURE 4: M13 MULTIPLEXER BLOCK DIAGRAM ........................................18
FIGURE 5: DS3 FRAMER ONLY MODE BLOCK DIAGRAM............................19
FIGURE 6: PIN DIAGRAM ................................................................................25
FIGURE 7: CRC MULTIFRAME ALIGNMENT ALGORITHM ............................59
PROPRIETARY AND CONFIDENTIAL iv
STANDARD PRODUCT
DATASHEET
PMC-2011596 ISSUE 1 HIGH DENSITY T1/E1 FRAMER
PM4328 TECT3
AND M13 MULTIPLEXER
FIGURE 8: DJAT JITTER TOLERANCE T1 MODES ........................................73
FIGURE 9: DJAT JITTER TOLERANCE E1 MODES........................................74
FIGURE 10: DJAT MINIMUM JITTER TOLERANCE VS. XCLK ACCURACY T1
MODES..........................................................................................75
FIGURE 11: DJAT MINIMUM JITTER TOLERANCE VS. XCLK ACCURACY E1
MODES..........................................................................................75
FIGURE 12: DJAT JITTER TRANSFER T1 MODES.........................................76
FIGURE 13: DJAT JITTER TRANSFER E1 MODES ........................................76
FIGURE 14: CLOCK MASTER: NXCHANNEL..................................................86
FIGURE 15: CLOCK MASTER: CLEAR CHANNEL..........................................87
FIGURE 16: CLOCK SLAVE: EFP ENABLED...................................................87
FIGURE 17: CLOCK SLAVE: EXTERNAL SIGNALING....................................88
FIGURE 18: CLOCK SLAVE: CLEAR CHANNEL .............................................88
FIGURE 19: CLOCK SLAVE: H-MVIP...............................................................89
FIGURE 20: CLOCK MASTER: SERIAL DATA AND H-MVIP CCS...................90
FIGURE 21: CLOCK MASTER: FULL T1/E1 ....................................................92
FIGURE 22: CLOCK MASTER: NXCHANNEL..................................................92
FIGURE 23: CLOCK MASTER: CLEAR CHANNEL..........................................93
FIGURE 24: CLOCK SLAVE: EXTERNAL SIGNALING....................................93
FIGURE 25: CLOCK SLAVE: H-MVIP...............................................................94
FIGURE 26: CLOCK SLAVE: SERIAL DATA AND H-MVIP CCS ......................95
FIGURE 27: DS3 FRAME STRUCTURE ........................................................134
FIGURE 28: FER COUNT VS. BER (E1 MODE) ............................................138
FIGURE 29: CRCE COUNT VS. BER (E1 MODE)..........................................139
PROPRIETARY AND CONFIDENTIAL v
STANDARD PRODUCT
DATASHEET
PMC-2011596 ISSUE 1 HIGH DENSITY T1/E1 FRAMER
PM4328 TECT3
AND M13 MULTIPLEXER
FIGURE 30: FER COUNT VS. BER (T1 ESF MODE).....................................139
FIGURE 31: CRCE COUNT VS. BER (T1 ESF MODE)..................................140
FIGURE 32: CRCE COUNT VS. BER (T1 SF MODE) ....................................140
FIGURE 33: TYPICAL DATA FRAME..............................................................147
FIGURE 34: EXAMPLE MULTI-PACKET OPERATIONAL SEQUENCE .........147
FIGURE 35: T1/E1 LINE LOOPBACK.............................................................152
FIGURE 36: T1/E1 DIAGNOSTIC DIGITAL LOOPBACK................................153
FIGURE 37: PER-CHANNEL LOOPBACK.....................................................154
FIGURE 38: DS3 DIAGNOSTIC LOOPBACK DIAGRAM ...............................155
FIGURE 39: DS3 LINE LOOPBACK DIAGRAM..............................................156
FIGURE 40: DS2 LOOPBACK DIAGRAM.......................................................156
FIGURE 41: PRGD PATTERN GENERATOR.................................................171
FIGURE 42: BOUNDARY SCAN ARCHITECTURE ........................................175
FIGURE 43: TAP CONTROLLER FINITE STATE MACHINE..........................177
FIGURE 44: INPUT OBSERVATION CELL (IN_CELL) ...................................180
FIGURE 45: OUTPUT CELL (OUT_CELL) .....................................................181
FIGURE 46: BIDIRECTIONAL CELL (IO_CELL).............................................181
FIGURE 47: LAYOUT OF OUTPUT ENABLE AND BIDIRECTIONAL CELLS 182
FIGURE 48: RECEIVE BIPOLAR DS3 STREAM............................................183
FIGURE 49: RECEIVE UNIPOLAR DS3 STREAM .........................................183
FIGURE 50: TRANSMIT BIPOLAR DS3 STREAM .........................................184
FIGURE 51: TRANSMIT UNIPOLAR DS3 STREAM.......................................184
FIGURE 52: FRAMER MODE DS3 TRANSMIT INPUT STREAM ..................185
PROPRIETARY AND CONFIDENTIAL vi
STANDARD PRODUCT
DATASHEET
PMC-2011596 ISSUE 1 HIGH DENSITY T1/E1 FRAMER
PM4328 TECT3
AND M13 MULTIPLEXER
FIGURE 53: FRAMER MODE DS3 TRANSMIT INPUT STREAM WITH
TGAPCLK ....................................................................................185
FIGURE 54: FRAMER MODE DS3 RECEIVE OUTPUT STREAM.................186
FIGURE 55: FRAMER MODE DS3 RECEIVE OUTPUT STREAM WITH
RGAPCLK....................................................................................186
FIGURE 56: SBI DROP BUS T1 FUNCTIONAL TIMING ................................187
FIGURE 57: SBI DROP BUS DS3 FUNCTIONAL TIMING .............................187
FIGURE 58: SBI ADD BUS JUSTIFICATION REQUEST FUNCTIONAL TIMING
.....................................................................................................188
FIGURE 59: EGRESS 8.192 MBPS H-MVIP LINK TIMING ............................189
FIGURE 60: INGRESS 8.192 MBPS H-MVIP LINK TIMING...........................189
FIGURE 61: T1 EGRESS INTERFACE CLOCK MASTER: NXCHANNEL MODE
.....................................................................................................190
FIGURE 62: E1 EGRESS INTERFACE CLOCK MASTER : NXCHANNEL MODE190
FIGURE 63: T1 AND E1 EGRESS INTERFACE CLOCK MASTER: CLEAR
CHANNEL MODE ........................................................................190
FIGURE 64: T1 EGRESS INTERFACE CLOCK SLAVE: EFP ENABLED MODE
.....................................................................................................191
FIGURE 65: E1 EGRESS INTERFACE CLOCK SLAVE : EFP ENABLED MODE
.....................................................................................................191
FIGURE 66: T1 EGRESS INTERFACE CLOCK SLAVE: EXTERNAL SIGNALING
MODE ..........................................................................................192
FIGURE 67: E1 EGRESS INTERFACE CLOCK SLAVE : EXTERNAL
SIGNALING MODE......................................................................192
FIGURE 68: T1 EGRESS INTERFACE 2.048 MHZ CLOCK SLAVE: EFP
ENABLED MODE ........................................................................193
FIGURE 69: T1 EGRESS INTERFACE 2.048 MHZ CLOCK SLAVE: EXTERNAL
SIGNALING MODE......................................................................194
PROPRIETARY AND CONFIDENTIAL vii
STANDARD PRODUCT
DATASHEET
PMC-2011596 ISSUE 1 HIGH DENSITY T1/E1 FRAMER
PM4328 TECT3
AND M13 MULTIPLEXER
FIGURE 70: T1 AND E1 EGRESS INTERFACE CLOCK SLAVE: CLEAR
CHANNEL MODE ........................................................................194
FIGURE 71: T1 INGRESS INTERFACE CLOCK MASTER : FULL CHANNEL
MODE ..........................................................................................195
FIGURE 72: E1 INGRESS INTERFACE CLOCK MASTER : FULL CHANNEL
MODE ..........................................................................................195
FIGURE 73: T1 INGRESS INTERFACE CLOCK MASTER: NXCHANNEL MODE196
FIGURE 74: E1 INGRESS INTERFACE CLOCK MASTER: NXCHANNEL MODE196
FIGURE 75: T1 AND E1 INGRESS INTERFACE CLOCK MASTER: CLEAR
CHANNEL MODE ........................................................................196
FIGURE 76: T1 INGRESS INTERFACE CLOCK SLAVE: EXTERNAL
SIGNALING MODE......................................................................197
FIGURE 77: E1 INGRESS INTERFACE CLOCK SLAVE: EXTERNAL
SIGNALING MODE......................................................................197
FIGURE 78: T1 INGRESS INTERFACE 2.048 MHZ CLOCK SLAVE: EXTERNAL
SIGNALING MODE......................................................................198
FIGURE 79: MICROPROCESSOR INTERFACE READ TIMING....................203
FIGURE 80: MICROPROCESSOR INTERFACE WRITE TIMING..................205
FIGURE 81: RSTB TIMING.............................................................................206
FIGURE 82: DS3 TRANSMIT INTERFACE TIMING .......................................208
FIGURE 83: DS3 RECEIVE INTERFACE TIMING.......................................... 211
FIGURE 84: SBI ADD BUS TIMING ................................................................214
FIGURE 85: SBI DROP BUS TIMING.............................................................216
FIGURE 86: SBI DROP BUS COLLISION AVOIDANCE TIMING ...................216
FIGURE 87: H-MVIP EGRESS DATA & FRAME PULSE TIMING...................218
FIGURE 88: H-MVIP INGRESS DATA TIMING ...............................................219
FIGURE 89: XCLK INPUT TIMING .................................................................220
PROPRIETARY AND CONFIDENTIAL viii
STANDARD PRODUCT
DATASHEET
PMC-2011596 ISSUE 1 HIGH DENSITY T1/E1 FRAMER
PM4328 TECT3
AND M13 MULTIPLEXER
FIGURE 90: EGRESS INTERFACE TIMING - CLOCK SLAVE: EFP ENABLED
MODE ..........................................................................................221
FIGURE 91: EGRESS INTERFACE TIMING - CLOCK SLAVE: EXTERNAL
SIGNALING MODE......................................................................222
FIGURE 92: EGRESS INTERFACE INPUT TIMING - CLOCK MASTER :
NXCHANNEL MODE ...................................................................223
FIGURE 93: EGRESS INTERFACE INPUT TIMING - CLOCK MASTER : CLEAR
CHANNEL MODE ........................................................................224
FIGURE 94: EGRESS INTERFACE INPUT TIMING - CLOCK MASTER :
SERIAL DATA AND H-MVIP CCS MODE ....................................225
FIGURE 95: EGRESS INTERFACE INPUT TIMING - CLOCK SLAVE : CLEAR
CHANNEL MODE ........................................................................226
FIGURE 96: INGRESS INTERFACE TIMING - CLOCK SLAVE MODES .......228
FIGURE 97: INGRESS INTERFACE TIMING - CLOCK MASTER MODES....229
FIGURE 98: TRANSMIT LINE INTERFACE TIMING ......................................230
FIGURE 99: JTAG PORT INTERFACE TIMING..............................................233
FIGURE 100: 324 PIN PBGA 23X23MM BODY..............................................235
LIST OF TABLES
TABLE 1: E1-FRMR FRAMING STATES ..........................................................60
TABLE 2: REGISTER MEMORY MAP ..............................................................99
TABLE 3: INSTRUCTION REGISTER ............................................................121
TABLE 4: IDENTIFICATION REGISTER.........................................................122
TABLE 5: BOUNDARY SCAN CHAIN .............................................................122
TABLE 6: PMON COUNTER SATURATION LIMITS (E1 MODE) ...................137
TABLE 7: PMON COUNTER SATURATION LIMITS (T1 MODE) ...................137
PROPRIETARY AND CONFIDENTIAL ix
STANDARD PRODUCT
DATASHEET
PMC-2011596 ISSUE 1 HIGH DENSITY T1/E1 FRAMER
PM4328 TECT3
AND M13 MULTIPLEXER
TABLE 8: PERFORMANCE REPORT MESSAGE STRUCTURE AND
CONTENTS .................................................................................148
TABLE 9: PERFORMANCE REPORT MESSAGE STRUCTURE NOTES......149
TABLE 10: PERFORMANCE REPORT MESSAGE CONTENTS ...................149
TABLE 11: STRUCTURE FOR CARRYING MULTIPLEXED LINKS ...............158
TABLE 12: T1 TRIBUTARY COLUMN NUMBERING......................................158
TABLE 13: SBI T1 LINK RATE INFORMATION ..............................................160
TABLE 14: SBI T1 CLOCK RATE ENCODING ...............................................160
TABLE 15: DS3 LINK RATE INFORMATION ..................................................161
TABLE 16: DS3 CLOCK RATE ENCODING ...................................................161
TABLE 17: T1 FRAMING FORMAT.................................................................162
TABLE 18: T1 CHANNEL ASSOCIATED SIGNALING BITS ...........................164
TABLE 19: DS3 FRAMING FORMAT ..............................................................165
TABLE 20: DS3 BLOCK FORMAT ..................................................................166
TABLE 21: DS3 MULTI-FRAME STUFFING FORMAT ...................................166
TABLE 22: DATA AND CAS T1 H-MVIP FORMAT ..........................................166
TABLE 23: DATA AND CAS E1 H-MVIP FORMAT IN G.747 MODE ...............167
TABLE 24: CCS T1 H-MVIP FORMAT ............................................................168
TABLE 25: CCS E1 H-MVIP FORMAT IN G.747 MODE .................................168
TABLE 26: PSEUDO RANDOM PATTERN GENERATION (PS BIT = 0)........173
TABLE 27: REPETITIVE PATTERN GENERATION (PS BIT = 1)...................174
TABLE 28: ABSOLUTE MAXIMUM RATINGS ................................................199
TABLE 29: D.C. CHARACTERISTICS ............................................................200
TABLE 30: MICROPROCESSOR INTERFACE READ ACCESS ....................202
PROPRIETARY AND CONFIDENTIAL x
STANDARD PRODUCT
DATASHEET
PMC-2011596 ISSUE 1 HIGH DENSITY T1/E1 FRAMER
PM4328 TECT3
AND M13 MULTIPLEXER
TABLE 31: MICROPROCESSOR INTERFACE WRITE ACCESS ..................204
TABLE 32: RTSB TIMING ...............................................................................206
TABLE 33: DS3 TRANSMIT INTERFACE TIMING..........................................206
TABLE 34: DS3 RECEIVE INTERFACE TIMING............................................210
TABLE 35: SBI ADD BUS TIMING (FIGURE 84) ............................................213
TABLE 36: SBI DROP BUS TIMING (FIGURE 85 TO FIGURE 86) ................214
TABLE 37: H-MVIP EGRESS TIMING (FIGURE 87).......................................217
TABLE 38: H-MVIP INGRESS TIMING (FIGURE 88) .....................................218
TABLE 39: XCLK INPUT (FIGURE 89) ...........................................................220
TABLE 40: EGRESS INTERFACE TIMING - CLOCK SLAVE: EFP ENABLED
MODE (FIGURE 90) ....................................................................221
TABLE 41: EGRESS INTERFACE TIMING - CLOCK SLAVE: EXTERNAL
SIGNALING (FIGURE 91) ...........................................................222
TABLE 42: EGRESS INTERFACE INPUT TIMING - CLOCK MASTER :
NXCHANNEL MODE (FIGURE 92) .............................................223
TABLE 43: EGRESS INTERFACE INPUT TIMING - CLOCK MASTER : CLEAR
CHANNEL MODE (FIGURE 92) ..................................................224
TABLE 44: EGRESS INTERFACE INPUT TIMING - CLOCK MASTER : SERIAL
DATA AND H-MVIP CCS MODE (FIGURE 92)............................225
TABLE 45: EGRESS INTERFACE INPUT TIMING - CLOCK SLAVE : CLEAR
CHANNEL MODE (FIGURE 92) ..................................................226
TABLE 46: INGRESS INTERFACE TIMING - CLOCK SLAVE MODES (FIGURE
96)................................................................................................227
TABLE 47: INGRESS INTERFACE TIMING - CLOCK MASTER MODES
(FIGURE 97)................................................................................229
TABLE 48: TRANSMIT LINE INTERFACE TIMING (FIGURE 98)...................230
TABLE 49: JTAG PORT INTERFACE .............................................................232
PROPRIETARY AND CONFIDENTIAL xi
STANDARD PRODUCT
DATASHEET
PMC-2011596 ISSUE 1 HIGH DENSITY T1/E1 FRAMER
PM4328 TECT3
AND M13 MULTIPLEXER
TABLE 50: ORDERING AND THERMAL INFORMATION ...............................234
TABLE 51: THERMAL INFORMATION – THETA JA VS. AIRFLOW ...............234
PROPRIETARY AND CONFIDENTIAL xii
STANDARD PRODUCT
DATASHEET
PMC-2011596 ISSUE 1 HIGH DENSITY T1/E1 FRAMER
PM4328 TECT3
AND M13 MULTIPLEXER
1 FEATURES
· Integrates 28 T1 framers, 21 E1 framers and a full featured M13 multiplexer
with DS3 framer in a single monolithic device for terminating DS3 multiplexed
T1 or E1 streams.
· Four fundamental modes of operation:
· Up to 28 T1 streams M13 multiplexed into a serial DS3.
· Up to 21 E1 streams multiplexed into a DS3 following the ITU-T G.747
recommendation. This E1 mode of operation is restricted to using the
serial clock and data or H-MVIP system interfaces.
· DS3 M13 Multiplexer with ingress or egress per link monitoring.
· Unchannelized DS3 framer mode for access to the entire DS3 payload.
· Supports transfer of PCM data to/from 1.544MHz and 2.048MHz serial
interface system-side devices. Also supports a fractional T1 or E1 system
interface with independent ingress/egress Nx64Kb/s rates. Supports a 2.048
MHz system-side interface for T1 mode without external clock gapping.
· Supports 8Mb/s H-MVIP on the system interface for all T1 or E1 links, a
separate 8Mb/s H-MVIP system interface for all T1 or E1 CAS channels and
a separate 8Mb/s H-MVIP system interface for all T1 or E1 CCS and
V5.1/V5.2 channels.
· Supports a byte serial Scaleable Bandwidth Interconnect (SBI) bus interface
for high density system side device interconnection of up to 84 T1 streams or
3 DS3 streams.
· Provides jitter attenuation in the T1 or E1 receive and transmit directions.
· Provides two independent de-jittered T1 or E1 recovered clocks for system
timing and redundancy.
· Provides per-DS0 line loopback and per link diagnostic and line loopbacks.
· Provides an on-board programmable binary sequence generator and detector
for error testing at DS3 rates. Includes support for patterns recommended in
ITU-T O.151.
PROPRIETARY AND CONFIDENTIAL 1
STANDARD PRODUCT
DATASHEET
PMC-2011596 ISSUE 1 HIGH DENSITY T1/E1 FRAMER
PM4328 TECT3
AND M13 MULTIPLEXER
· Also provides PRBS generators and detectors on each tributary for error
testing at DS1, E1 and NxDS0 rates as recommended in ITU-T O.151 and
O.152.
· Provides robbed bit signaling extraction and insertion on a per-DS0 basis.
· Provides programmable idle code substitution, data and sign inversion, and
digital milliwatt code insertion on a per-DS0 basis.
· Supports the M23 and C-bit parity DS3 formats.
· Standalone unchannelized DS3 framer mode for access to the entire DS3
payload.
· When configured to operate as a DS3 Framer, gapped transmit and receive
clocks can be optionally generated for interface to link layer devices which
only need access to payload data bits.
· DS3 Transmit clock source can be selected from either an external oscillator
or from the receive side clock (loop-timed).
· Register level compatibility with the PM4388 TOCTL Octal T1 Framer, the
PM6388 EOCTL Octal E1 Framer, the PM4351 COMET E1/T1 transceiver
and the PM8313 D3MX M13 Multiplexer/Demultiplexer.
· Provides a generic 8-bit microprocessor bus interface for configuration,
control and status monitoring.
· Provides a standard 5 signal P1149.1 JTAG test port for boundary scan board
test purposes.
· Low power 2.5V/3.3V CMOS technology. All pins are 5V tolerant.
· 324-pin fine pitch PBGA package (23mm x 23mm). Supports industrial
temperature range (-40oC to 85oC) operation.
Each one of 28 T1 receiver sections:
· Frames to DS-1 signals in SF and ESF formats.
· Frames to TTC JT-G.704 multiframe formatted J1 signals. Supports the
alternate CRC-6 calculation for Japanese applications.
· Accepts gapped data streams to support higher rate demultiplexing.
PROPRIETARY AND CONFIDENTIAL 2
STANDARD PRODUCT
DATASHEET
PMC-2011596 ISSUE 1 HIGH DENSITY T1/E1 FRAMER
PM4328 TECT3
AND M13 MULTIPLEXER
· Provides Red, Yellow, and AIS alarm integration.
· Provides ESF bit-oriented code detection and an HDLC/LAPD interface for
terminating the ESF facility data link.
· Indicates signaling state change, and two superframes of signaling debounce
on a per-DS0 basis.
· Provides an HDLC interface with 128 bytes of buffering for terminating the
facility data link.
· Provides performance monitoring counters sufficiently large as to allow
performance monitor counter polling at a minimum rate of once per second.
Optionally, updates the performance monitoring counters and interrupts the
microprocessor once per second, timed to the receive line.
· Provides an optional elastic store which may be used to time the ingress
streams to a common clock and frame alignment, or to facilitate per-DS0
loopbacks.
· Provides DS-1 robbed bit signaling extraction, with optional data inversion,
programmable idle code substitution, digital milliwatt code substitution, bit
fixing, and two superframes of signaling debounce on a per-channel basis.
· A pseudo-random sequence user selectable from 211 –1, 215 –1 or220 –1, may
be detected in the T1 stream in either the ingress or egress directions. The
detector counts pattern errors using a 24-bit non-saturating PRBS error
counter. The pseudo-random sequence can be the entire T1 or any
combination of DS0s within a framed T1.
· Line side interface is the DS3 interface via the M13 multiplex.
· System side interface is either serial clock and data, H-MVIP or SBI bus.
· Frames in the presence of and detects the “Japanese Yellow” alarm.
· Provides external access for up to two de-jittered recovered T1 clocks.
Each one of 21 E1 receiver sections:
· Frames to ITU-T G.704 basic and CRC-4 multiframe formatted E1 signals.
The framing procedures are consistent ITU-T G.706 specifications.
· Provides an HDLC interface with 128 bytes of buffering for terminating the
national use bit data link.
PROPRIETARY AND CONFIDENTIAL 3
STANDARD PRODUCT
DATASHEET
PMC-2011596 ISSUE 1 HIGH DENSITY T1/E1 FRAMER
PM4328 TECT3
AND M13 MULTIPLEXER
· Extracts 4-bit codewords from the E1 national use bits as specified in
ETS 300 233.
· V5.2 link indication signal detection.
· Provides performance monitoring counters sufficiently large as to allow
performance monitor counter polling at a minimum rate of once per second.
Optionally, updates the performance monitoring counters and interrupts the
microprocessor once per second, timed to the receive line.
· Provides a two-frame elastic store buffer for backplane rate adaptation that
performs controlled slips and indicates slip occurrence and direction.
· Frames to the E1 signaling multiframe alignment when enabled and extracts
channel associated signaling. Alternatively, a common channel signaling data
link may be extracted from timeslot 16.
· Can be programmed to generate an interrupt on change of signaling state.
· Provides trunk conditioning which forces programmable trouble code
substitution and signaling conditioning on all channels or on selected
channels.
· A pseudo-random sequence user selectable from 211 –1, 215 –1 or220 –1, may
be detected in the E1 stream in either the ingress or egress directions. The
detector counts pattern errors using a 24-bit non-saturating PRBS error
counter. The pseudo-random sequence can be the entire E1 or any
combination of timeslots within the framed E1.
· Line side interface is the DS3 interface mutiplexed as per the G.747
recommendation.
· System side interface is either serial clock and data or H-MVIP.
· Provides external access for up to two de-jittered recovered E1 clocks.
Each one of 28 T1 transmitter sections:
· May be timed to its associated receive clock (loop timing) or may derive its
timing from a common egress clock or a common transmit clock; the transmit
line clock may be synthesized from an N*8kHz reference.
· Provides minimum ones density through Bell (bit 7), GTE or “jammed bit 8”
zero code suppression on a per-DS0 basis.
PROPRIETARY AND CONFIDENTIAL 4
STANDARD PRODUCT
DATASHEET
PMC-2011596 ISSUE 1 HIGH DENSITY T1/E1 FRAMER
PM4328 TECT3
AND M13 MULTIPLEXER
· Provides a 128 byte buffer to allow insertion of the facility data link using the
host interface.
· Supports transmission of the alarm indication signal (AIS) or the Yellow alarm
signal in both SF and ESF formats.
· Provides a digital phase locked loop for generation of a low jitter transmit
clock.
· Provides a FIFO buffer for jitter attenuation and rate conversion in the
transmitter.
· Automatically generates and transmits DS-1 performance report messages to
ANSI T1.231and ANSI T1.408 specifications.
· Supports the alternate ESF CRC-6 calculation for Japanese applications.
· A pseudo-random sequence user selectable from 211 –1, 215 –1 or 220 –1,
may be inserted into the T1 stream in either the ingress or egress directions.
The pseudo-random sequence can be inserted into the entire T1 or any
combination of DS0s within the framed T1.
· Line side interface is through the DS3 Interface via the M13 multiplex.
· System side interface is either serial clock and data, H-MVIP or SBI bus.
Each one of 21 E1 transmitter sections:
· Provides a FIFO buffer for jitter attenuation and rate conversion in the
transmit path.
· Transmits G.704 basic and CRC-4 multiframe formatted E1.
· Supports unframed mode and framing bit, CRC, or data link by-pass.
· Provides signaling insertion, programmable idle code substitution, digital
milliwatt code substitution, and data inversion on a per channel basis.
· Provides trunk conditioning which forces programmable trouble code
substitution and signaling conditioning on all channels or on selected
channels.
· Provides a digital phase locked loop for generation of a low jitter transmit
clock.
PROPRIETARY AND CONFIDENTIAL 5
STANDARD PRODUCT
DATASHEET
PMC-2011596 ISSUE 1 HIGH DENSITY T1/E1 FRAMER
PM4328 TECT3
AND M13 MULTIPLEXER
· A pseudo-random sequence user selectable from 211 –1, 215 –1 or 220 –1,
may be inserted into the E1 stream in either the ingress or egress directions.
The pseudo-random sequence can be inserted into the entire E1 or any
combination of timeslots within the framed E1.
· Optionally inserts a datalink in the E1 national use bits.
· Supports 4-bit codeword insertion in the E1 national use bits as specified in
ETS 300 233
· Supports transmission of the alarm indication signal (AIS) and the Yellow
alarm signal.
· Line side interface is the DS3 interface mutiplexed as per the G.747
recommendation.
· System side interface is either serial clock and data or H-MVIP
DS3 Receiver Section:
· Frames to a DS3 signal with a maximum average reframe time of less than
1.5 ms (as required by TR-TSY-000009 Section 4.1.2 and TR-TSY-000191
Section 5.2).
· Decodes a B3ZS-encoded signal and indicates line code violations. The
definition of line code violation is software selectable.
· Provides indication of M-frame boundaries from which M-subframe
boundaries and overhead bit positions in the DS3 stream can be determined
by external processing.
· Detects the DS3 alarm indication signal (AIS) and idle signal. Detection
-3
algorithms operate correctly in the presence of a 10
bit error rate.
· Extracts valid X-bits and indicates far end receive failure (FERF).
· Accumulates up to 65,535 line code violation (LCV) events per second,
65,535 P-bit parity error events per second, 1023 F-bit or M-bit (framing bit)
events per second, 65,535 excessive zero (EXZ) events per second, and
when enabled for C-bit parity mode operation, up to 16,383 C-bit parity error
events per second, and 16,383 far end block error (FEBE) events per
second.
PROPRIETARY AND CONFIDENTIAL 6
STANDARD PRODUCT
DATASHEET
PMC-2011596 ISSUE 1 HIGH DENSITY T1/E1 FRAMER
PM4328 TECT3
AND M13 MULTIPLEXER
· Detects and validates bit-oriented codes in the C-bit parity far end alarm and
control channel.
· Terminates the C-bit parity path maintenance data link with an integral HDLC
receiver having a 128-byte deep FIFO buffer with programmable interrupt
threshold. Supports polled or interrupt-driven operation. Selectable none,
one or two address match detection on first byte of received packet.
· Programmable pseudo-random test-sequence detection–(up to 2
32
-1 bit
length patterns conforming to ITU-T O.151 standards) and analysis features.
DS3 Transmit Section:
· Provides the overhead bit insertion for a DS3 stream.
· Provides a bit serial clock and data interface, and allows the M-frame
boundary and/or the overhead bit positions to be located via an external
interface
· Provides B3ZS encoding.
· Generates an B3Zs encoded 100… repeating pattern to aid in pulse mask
testing.
· Inserts far end receive failure (FERF), the DS3 alarm indication signal (AIS)
and the idle signal when enabled by internal register bits.
· Provides optional automatic insertion of far end receive failure (FERF) on
detection of loss of signal (LOS), out of frame (OOF), alarm indication signal
(AIS) or red alarm condition.
· Provides diagnostic features to allow the generation of line code violation
error events, parity error events, framing bit error events, and when enabled
for the C-bit parity application, C-bit parity error events, and far end block
error (FEBE) events.
· Supports insertion of bit-oriented codes in the C-bit parity far end alarm and
control channel.
· Optionally inserts the C-bit parity path maintenance data link with an integral
HDLC transmitter. Supports polled and interrupt-driven operation.
· Provides programmable pseudo-random test sequence generation (up to
232-1 bit length sequences conforming to ITU-T O.151 standards) or any
PROPRIETARY AND CONFIDENTIAL 7
STANDARD PRODUCT
DATASHEET
PMC-2011596 ISSUE 1 HIGH DENSITY T1/E1 FRAMER
PM4328 TECT3
AND M13 MULTIPLEXER
repeating pattern up to 32 bits. The test pattern can be framed or unframed.
Diagnostic abilities include single bit error insertion or error insertion at bit
error rates ranging from 10-1 to 10-7.
M23 Multiplexer Section:
· Multiplexes 7 DS2 bit streams into a single M23 format DS3 bit stream.
· Performs required bit stuffing/destuffing including generation and
interpretation of C-bits.
· Includes required FIFO buffers for rate adaptation in the multiplex path.
· Allows insertion and detection of per DS2 payload loopback requests
encoded in the C-bits to be activated under microprocessor control.
· Internally generates DS2 clock for use in integrated M13 or C-bit parity
multiplex applications. Alternatively accepts external DS2 clock reference.
· Allows per DS2 alarm indication signal (AIS) to be activated or cleared for
either direction under microprocessor control.
· Allows DS2 alarm indication signal (AIS) to be activated or cleared in the
demultiplex direction automatically upon loss of DS3 frame alignment or
signal.
· Supports C-bit parity DS3 format.
DS2 Framer Section:
· Frames to a DS2 (ANSI T1.107 section 8) signal with a maximum average
reframe time of less than 7 ms (as required by TR-TSY-000009 Section 4.1.2
and TR-TSY-000191 Section 5.2).
· Detects the DS2 alarm indication signal (AIS) in 9.9 ms in the presence of a
10-3 bit error rate.
· Extracts the DS2 X-bit remote alarm indication (RAI) bit and indicates far end
receive failure (FERF).
· Accumulates up to 255 DS2 M-bit or F-bit error events per second.
PROPRIETARY AND CONFIDENTIAL 8
STANDARD PRODUCT
DATASHEET
PMC-2011596 ISSUE 1 HIGH DENSITY T1/E1 FRAMER
PM4328 TECT3
AND M13 MULTIPLEXER
DS2 Transmitter Section:
· Generates the required X, F, and M bits into the transmitted DS2 bit stream.
Allows inversion of inserted F or M bits for diagnostic purposes.
· Provides for transmission of far end receive failure (FERF) and alarm
indication signal (AIS) under microprocessor control.
· Provides optional automatic insertion of far end receive failure (FERF) on
detection of out of frame (OOF), alarm indication signal (AIS) or red alarm
condition.
M12 Multiplexer Section:
· Multiplexes four DS1 bit streams into a single M12 format DS2 bit stream.
· Performs required bit stuffing including generation and interpretation of C-
bits.
· Includes required FIFO buffers for rate adaptation in the multiplex path.
· Performs required inversion of second and fourth multiplexed DS1 streams
as required by ANSI T1.107 Section 7.2.
· Allows insertion and detection of per DS1 payload loopback requests
encoded in the C-bits to be activated under microprocessor control.
· Allows per tributary alarm indication signal (AIS) to be activated or cleared for
either direction under microprocessor control.
· Allows automatic tributary AIS to be activated upon DS2 out of frame.
Synchronous System Interfaces:
· Provides seven 8Mb/s H-MVIP data interfaces for synchronous access to all
the DS0s of all 28 T1 links or all timeslots of all 21 E1s. T1 DS0s are bundled
from four T1 links in sequential order (i.e. 1-4, 5-8, 9-12, 13-16, 17-20, 21-24,
25-28). In normal mode, E1 timeslots are bundled from 4 E1 links in
sequential order (i.e. 1-4, 5-8, 9-12, 13-16, 17-20 and 21 by itself). In G.747
mode, E1 timeslots are bundled from 3 E1 links in sequential order, spaced
by a reserved timeslot on every 4th frame (i.e. 1-3/X, 4-6/X, 7-9/X, 10-12/X,
13-15/X, 16-18/X, 19-21/X).
PROPRIETARY AND CONFIDENTIAL 9
STANDARD PRODUCT
DATASHEET
PMC-2011596 ISSUE 1 HIGH DENSITY T1/E1 FRAMER
PM4328 TECT3
AND M13 MULTIPLEXER
· Provides seven 8Mb/s H-MVIP interfaces for synchronous access to all
channel associated signaling (CAS) bits for all T1 DS0s or E1 timeslots. The
CAS bits occupy one nibble of every byte on the H-MVIP interfaces and are
repeated over the entire T1 or E1 multi-frame.
· Provides a single 8Mb/s H-MVIP interface for common channel signaling
(CCS) channels as well as V5.1 and V5.2 channels. In T1 mode DS0 24 is
available through this interface. In E1 mode timeslots 15, 16 and 31 are
available through this interface.
· All links accessed via the H-MVIP interface will be synchronously timed to the
common H-MVIP clock and frame alignment signals, CMV8MCLK, CMVFP,
CMVFPC.
· H-MVIP access for Channel Associated Signaling is available with the
Scaleable Bandwidth Interconnect bus as an optional replacement for CAS
access over the SBI bus as well as with the H-MVIP data interface. Common
Channel Signaling H-MVIP access is available with the SBI bus, serial PCM
and H-MVIP data interfaces.
· Compatible with H-MVIP PCM backplanes supporting 8.192 Mbit/s.
Scaleable Bandwidth Interconnect (SBI) Bus:
· Provides a high density byte serial interconnect for all framed and unframed
TECT3 links. Utilizes an Add/Drop configuration to asynchronously mutliplex
up to 84 T1s or 3 DS3s, equivalent to three TECT3s, with multiple payload or
link layer processors.
· External devices can access unframed DS3, framed unchannelized DS3,
unframed (clear channel) T1s or framed T1s over this interface.
· Framed and unframed T1 access can be selected on a per T1 basis.
· Synchronous access for T1 DS0 channels is supported in a locked format
mode.
· Channel associated signaling bits for channelized T1 are explicitly identified
across bus.
· Transmit timing is mastered either by the TECT3 or a layer 2 device
connecting to the SBI bus. Timing mastership is selectable on a per tributary
basis, where a tributary is either an individual T1 or a DS3.
PROPRIETARY AND CONFIDENTIAL 10
STANDARD PRODUCT
DATASHEET
PMC-2011596 ISSUE 1 HIGH DENSITY T1/E1 FRAMER
PM4328 TECT3
AND M13 MULTIPLEXER
2 APPLICATIONS
· High density T1 interfaces for multiplexers, multi-service switches, routers
and digital modems.
· High density E1 interfaces for multiplexers, multi-service switches, routers
and digital modems.
· Frame Relay switches and access devices (FRADS)
· M23 Based M13 Multiplexer
· C-Bit Parity Based M13 Multiplexer
· Channelized and Unchannelized DS3 Frame Relay Interfaces
PROPRIETARY AND CONFIDENTIAL 11
STANDARD PRODUCT
DATASHEET
PMC-2011596 ISSUE 1 HIGH DENSITY T1/E1 FRAMER
PM4328 TECT3
AND M13 MULTIPLEXER
3 REFERENCES
· American National Standard for Telecommunications - Digital Hierarchy Synchronous DS3 Format Specifications, ANSI T1.103-1993
· American National Standard for Telecommunications - Digital Hierarchy Formats Specification, ANSI T1.107-1995
· American National Standard for Telecommunications - Digital Hierarchy - Layer 1
In-Service Digital Transmission Performance Monitoring, ANSI T1.231-1997
· American National Standard for Telecommunications - Carrier to Customer
Installation - DS-1 Metallic Interface Specification, ANSI T1.403-1995
· American National Standard for Telecommunications - Customer Installation–toNetwork - DS3 Metallic Interface Specification, ANSI T1.404-1994
· American National Standard for Telecom–unications - Integrated Services Digital
Network (ISDN) Primary Rate- Customer Installation Metallic Interfaces Layer 1
Specification, ANSI T1.408-1990
· Bell Communications Research, TR–TSY-000009 - Asynchronous Digital
Multiplexes Requirements and Objectives, Issue 1, May 1986
· Bell Communications Research - DS-1 Rate Digital Service Monitoring Unit
Functional Specification, TA-TSY-000147, Issue 1, October, 1987
· Bell Communications Research - Alarm Indication Signal Requirements and
Objectives, TR-TSY-000191 Issue 1, May 1986
· Bell Communications Research - Wideband and Broadband Digital CrossConnect Systems Generic Criteria, TR-NWT-000233, Issue 3, November 1993
· Bell Communications Research - Integrated Digital Loop Carrier Generic
Requirements, Objectives, and Interface, TR-NWT-000303, Issue 2, December,
1992
· Bell Communications Research - Transport Systems Generic Requirements
(TSGR): Common Requirement, TR-TSY-000499, Issue 5, December, 1993
· Bell Communications Research - OTGR: Network Maintenance Transport
Surveillance - Generic Digital Transmission Surveillance, TR-TSY-000820,
Section 5.1, Issue 1, June 1990
PROPRIETARY AND CONFIDENTIAL 12
STANDARD PRODUCT
DATASHEET
PMC-2011596 ISSUE 1 HIGH DENSITY T1/E1 FRAMER
PM4328 TECT3
AND M13 MULTIPLEXER
· AT&T - Requirements For Interfacing Digital Terminal Equipment To Services
Employing The Extended Superframe Format, TR 54016, September, 1989.
· AT&T - Accunet T1.5 - Service Description and Interface Specification, TR 62411,
December, 1990
· ITU Study Group XVIII – Report R 105, Geneva, 9-19 June 1992
· ETSI - ETS 300 011 - ISDN Primary Rate User-Network Interface Specification
and Test Principles, 1992.
· ETSI - ETS 300 233 - Access Digital Section for ISDN Primary Rates, May 1994
· ETSI - ETS 300 324-1 - Signaling Protocols and Switching (SPS); V interfaces at
the Digital Local Exchange (LE) V5.1 Interface for the Support of Access
Network (AN) Part 1: V5.1 Interface Specification, February, 1994.
· ETSI - ETS 300 347-1 - Signaling Protocols and Switching (SPS); V Interfaces at
the Digital Local Exchange (LE) V5.2 Interface for the Support of Access
Network (AN) Part 1: V5.2 Interface Specification, September 1994.
· ITU-T - Recommendation G.704 - Synchronous Frame Structures Used at
Primary Hierarchical Levels, July 1995.
· ITU-T - Recommendation G.706 - Frame Alignment and CRC Procedures
Relating to G.704 Frame Structures, 1991.
· ITU-T - Recommendation G.732 – Characteristics of Primary PCM Multiplex
Equipment Operating at 2048 kbit/s, 1993.
· ITU-T Recommendation G.747 – Second Order Digital Multiplex Equipment
Operating at 6312kbit/s and Multiplexing Three Tributaries at 2048 kbit/s, 1988
· ITU-T Recommendation G.775, - Loss of Signal (LOS) and Alarm Indication
Signal (AIS) Defect Detection and Clearance Criteria, 11/94
· ITU-T Recommendation G.823, - The Control of Jitter and Wander within Digital
Networks which are Based on the 2048 kbit/s Hierarchy, 03/94
· ITU-T Recommendation G.964, - V-Interfaces at the Digital Local Ex–hange (LE)
- V5.1 Interface (Based on 2048 kbit/s) for the Support of Access Network (AN),
June 1994.
PROPRIETARY AND CONFIDENTIAL 13
STANDARD PRODUCT
DATASHEET
PMC-2011596 ISSUE 1 HIGH DENSITY T1/E1 FRAMER
PM4328 TECT3
AND M13 MULTIPLEXER
· ITU-T Recommendation G.965, - V-Interfaces at the Digital Local Ex–hange (LE)
- V5.2 Interface (Based on 2048 kbit/s) for the Support of Access Network (AN),
March –995.
· ITU-T - Recommend–tion I.431 - Primary Rate User-Network Interface – Layer 1
Specification, 1993.
· ITU-T Recommendation O.151 – Error Performance Measuring Equipment
Operating at the Primary Rate and Above, October 1992
· ITU-T Recommendation O.152 – Error Performance Measuring Equipment for
Bit Rates of 64 kbit/s and N x 64 kbit/s, October 1992
· ITU-T Recommendation O.153 - Basic Parameters for the Measurement of Error
Performance at Bit Rates below the Primary Rate, October 1992.
· ITU-T Recommendation Q.921 - ISDN User-Network Interface Data Link Layer
Specification, March 1993
· International Organization for Standardization, ISO 3309:1984 - High-Level Data
Link Control procedures - Frame Structure
· PMC-Sierra Inc., PMC-1980577 – Saturn Compatible Scaleable Bandwidth
Interface (SBI) Specification, Issue 3, 1998
· TTC Standard JT-G704 - Frame Structures on Primary and Secondary
Hierarchical Digital Interfaces, 1995.
· TTC Standard JT-G706 - Frame Synchronization and CRC Procedure
· TTC Standard JT-I431 - ISDN Primary Rate User-Network Interface Layer 1 -
Specification, 1995.
· Nippon Telegraph and Telephone Corporation - Technical Reference for HighSpeed Digital Leased Circuit Services, Third Edition, 1990.
· GO-MVIP, Multi-Vendor Integration Protocol, MVIP-90, Release 1.1, 1994
· GO-MVIP, H-MVIP Standard, Release1.1a, 1997
PROPRIETARY AND CONFIDENTIAL 14
STANDARD PRODUCT
DATASHEET
PMC-2011596 ISSUE 1 HIGH DENSITY T1/E1 FRAMER
PM4328 TECT3
AND M13 MULTIPLEXER
4 APPLICATION EXAMPLES
Figure 1: Channelized DS3 Circuit Emulation Application
PM4328
DS3 LIU
DS3 LIU
DS3 LIU
TECT3
28 T1/21 E1 Framer
M13 Mux, DS3 framer
PM4328
TECT3
28 T1/21 E1 Framer
M13 Mux, DS3 framer
PM4328
TECT3
28 T1/21 E1 Framer
M13 Mux, DS3 framer
SBI
Bus
Figure 2: High Density Frame Relay Application
PM4328
DS3 LIU
DS3 LIU
DS3 LIU
High Density T1/E1 Frame Relay Port Card
TECT3
28 T1/21 E1 Framer
M13 Mux, DS3 framer
PM4328
TECT3
28 T1/21 E1 Framer
M13 Mux, DS3 framer
PM4328
TECT3
28 T1/21 E1 Framer
M13 Mux, DS3 framer
PM73122
AAL1gator-32
ATM SAR
PM73122
AAL1gator-32
ATM SAR
PM73122
AAL1gator-32
ATM SAR
SBI
Bus
Utopia
Bus
PM7384
FREEDM
84P672
High Density
HDLC
Controller
PCI
Bus
PROPRIETARY AND CONFIDENTIAL 15
STANDARD PRODUCT
DATASHEET
PMC-2011596 ISSUE 1 HIGH DENSITY T1/E1 FRAMER
PM4328 TECT3
AND M13 MULTIPLEXER
5 BLOCK DIAGRAM
5.1 Top Level Block Diagram
The diagram below shows the complete TECT3. T1 or E1 links can be
multiplexed into a DS3 (E1s following the ITU-T G.747 recommendation).
System side access to the T1s is available via the serial clock and data, H-MVIP
or SBI bus interfaces. System side access to the E1s is available via the serial
clock and data or H-MVIP interfaces. DS3 line side access is via the clock and
data interface for line interface units. Unchannelized DS3 system side access is
available through a serial clock and data interface or the SBI bus, both shown at
the top of the diagram.
PROPRIETARY AND CONFIDENTIAL 16
STANDARD PRODUCT
DATASHEET
PMC-2011596 ISSUE 1 HIGH DENSITY T1/E1 FRAMER
PM4328 TECT3
AND M13 MULTIPLEXER
Figure 3: TECT3 Block Diagram
K
L
C
B
M
8
P
]
/
]
F
V
/
8
]
]
8
2
V
M
M
C
/
C
K
/
K
L
L
P
K
L
F
C
C
E
E
T
C
X
C
C
C
]
7
8
:
2
:
:
7
2
1
:
]
8
2
:
1
[
D
E
1
1
:
[
[
[
1
1
G
[
P
I
K
F
S
L
E
E
C
E
M
[
D
D
2
D
E
E
5
E
S
S
K
V
C
L
A
M
C
C
C
Q
]
0
:
7
[
A
T
P
A
D
D
A
A
S
S
]
]
0
E
:
R
7
[
_
K
A
L
T
S
C
5
L
F
U
J
V
P
E
A
A
A
R
S
S
S
S
T
T
P
C
P
A
5
L
F
A
V
P
D
D
I
1
B
D
D
D
D
C
S
S
S
S
S
S
]
/
0
]
:
8
8
1
2
]
[
:
2
]
:
8
T
1
8
1
[
2
[
:
E
2
G
:
1
K
I
D
[
I
1
L
[
S
P
I
B
C
D
F
I
I
S
I
C
P
F
]
V
2
]
7
:
7
:
1
[
1
[
D
I
D
I
S
V
A
M
C
1
K
K
M
L
L
C
/
C
C
D
K
I
S
C
C
V
V
L
P
C
C
F
C
E
E
I
I
C
C
R
R
K
L
/
C
O
O
S
P
P
I
R
F
/
F
P
M
K
K
F
M
T
/
O
P
F
T
D
L
L
M
R
H
C
/
O
C
I
T
/
R
P
T
P
O
T
I
V
A
A
A
A
P
P
D
F
O
G
G
D
F
T
T
R
R
R
R
T
e
s
c
m
s
F
a
e
I
f
e
t
r
r
S
s
e
g
E
y
t
E
S
n
I
r
0
e
l
l
S
C
o
D
S
r
-
t
P
r
n
e
T
o
P
C
,
,
:
N
g
r
n
n
,
n
A
i
e
o
o
n
i
i
t
n
t
R
t
t
o
i
r
i
o
a
T
t
i
e
r
-
t
m
r
i
s
e
1
s
e
d
n
n
n
s
E
I
n
/
e
a
n
o
I
r
g
S
G
n
T
C
i
A
m
l
c
e
i
r
k
B
a
s
a
m
n
n
l
X
a
a
u
-
g
A
r
i
r
B
1
F
T
S
T
s
n
r
o
r
e
i
t
t
o
t
t
i
S
p
T
a
J
P
O
u
A
l
n
O
J
a
g
t
e
T
i
T
n
t
i
t
g
i
A
m
i
D
T
I
I
B
B
S
S
X
E
l
O
e
l
S
l
I
a
P
r
I
a
B
P
S
r
e
t
t
i
C
R
L
m
P
s
D
D
n
T
H
a
r
T
d
r
e
o
t
t
n
C
e
a
e
r
d
i
O
r
e
o
B
n
O
C
X
e
t
i
G
B
s
s
I
s
I
s
e
r
g
E
o
t
S
B
R
P
s
s
B
e
B
u
u
r
S
S
g
B
B
N
I
n
I
l
O
l
e
l
l
P
a
l
I
i
a
i
r
o
a
S
r
t
r
I
e
e
a
B
S
S
P
S
r
n
-
o
r
/
r
t
r
e
e
c
t
o
n
e
t
t
t
e
a
a
e
G
P
D
e
c
e
M
r
n
s
R
o
a
n
o
t
i
t
o
P
m
n
u
r
p
A
o
s
A
o
-
f
e
r
M
1
e
R
T
P
r
r
o
e
I
C
L
D
R
N
O
M
P
t
C
v
m
i
a
L
r
M
r
e
a
L
D
g
c
l
e
e
A
H
A
t
R
n
I
e
c
d
s
r
n
a
m
r
o
f
r
e
P
r
e
r
t
o
o
e
C
t
t
e
n
t
i
c
e
d
n
i
O
n
e
r
o
u
o
t
B
o
e
O
C
M
R
t
C
D
i
B
e
s
c
m
s
a
F
e
e
f
I
t
r
r
s
S
e
I
g
y
t
n
I
S
n
I
r
0
e
l
l
S
C
o
D
S
r
-
t
P
r
n
e
R
o
P
C
r
g
o
n
t
i
X
l
c
a
a
G
I
r
n
t
S
g
x
i
E
S
c
i
T
e
t
r
S
s
o
t
a
L
l
S
E
E
R
,
M
t
n
M
n
o
e
R
m
F
-
a
r
1
F
E
/
1
T
2
1
X
M
R
M
R
F
1
#
A
i
e
t
m
R
M
r
c
m
r
A
a
a
l
n
e
r
R
t
g
A
i
m
x
F
l
a
E
A
r
F
r
o
s
r
r
r
e
1
e
t
o
t
t
T
i
T
a
m
J
u
8
A
J
R
2
1
M
2
S
D
3
2
X
M
a
l
r
n
2
a
t
e
i
F
f
t
t
g
i
o
1
A
D
E
e
n
1
2
O
X
/
U
n
X
e
s
M
U
v
2
E
e
M
1
D
S
M
r
/
f
e
o
R
m
e
M
a
r
n
R
F
F
O
X
/
3
U
X
2
U
M
M
E
M
D
r
e
o
-
c
s
F
o
a
s
I
r
f
e
r
P
c
i
c
e
t
M
o
M
r
n
I
P
]
]
B
B
B
B
B
E
0
0
:
:
L
T
T
S
D
R
3
7
A
S
N
[
C
R
1
I
W
[
D
R
A
PROPRIETARY AND CONFIDENTIAL 17
C
L
R
D
P
H
D
T
t
x
i
r
T
C
C
A
E
O
F
B
X
x
T
R
e
N
m
3
s
A
M
m
S
n
a
R
R
D
a
r
T
r
F
F
T
e
S
S
d
Z
Z
o
c
3
3
n
B
B
E
T
K
P
K
L
A
F
L
C
D
C
M
I
T
T
T
/
T
/
S
G
O
E
P
N
T
T
r
.
N
o
f
t
i
r
O
n
e
e
r
M
o
P
v
e
i
3
P
M
e
m
S
c
a
D
e
r
F
R
C
C
x
L
L
R
D
D
H
R
e
C
C
d
x
O
A
o
R
c
E
B
e
F
R
D
T
K
V
L
A
C
C
L
D
R
R
R
/
/
S
G
E
O
N
P
R
R
s
s
e
c
t
G
r
c
A
o
A
T
P
t
J
s
e
T
I
B
S
K
O
D
T
L
D
M
T
S
C
T
T
T
R
T
Loading...