• Provides on-chip data recovery and clock synthesis.
• Supports dual IEEE 802.3 -1998 GMII interfaces for connection to copper Gigabit
Ethernet physical layer devices.
• Provides dual standard IEEE 802.3 Gigabit Ethernet MACs for frame verification.
• Enables frame filtering on 8 unicast or 64 multicast entries.
• Internal 16k byte egress and 64k byte ingress FIFOs per channel to accommodate
system latencies.
• Incorporates SATURN POS-PHY Level 3 32-bit System Interface clocked up to
104 MHz (32 bit mode only).
• Line side loopback capability for system level diagnostic capability.
• Includes 16 bit generic microprocessor interface for device initialization, control,
register and per port statistics access.
• Provides a standard 5 signal P1149.1 JTAG test port for boundary scan board test
purposes.
• Low power 1.8V CMOS device with 3.3V TTL compatible digital inputs (5V TTL
compatible microprocessor inputs) and 3.3V CMOS/TTL compatible digital outputs
within a 352 pin 27mm by 27mm UBGA package.
• Industrial temperature range (-40°C to +85°C).
2.2 Line Side Interface
• SERDES interface provides 2 differential pairs at 1250 MHz for connection to
electrical optical modules.
• GMII interface provides 8 bit wide TX & RX data interfaces at 125 MHz with control
signals for connection to copper Gigabit Ethernet physical layer devices.
• Allows selection between SERDES and GMII interface on a per channel basis.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
The PM3386 S/UNI-2xGE is applicable to equipment implementing high density
Gigabit Ethernet interfaces. The PM3386 is a dual channel SERDES and GMAC
with embedded FIFOs that provides a high density and low power Gigabit
Ethernet solution for direct connection to electrical optical modules. Alternatively,
a GMII interface is provided for connection to copper Gigabit Ethernet physical
layer devices.
On the system side, the POS-PHY Level 3 (32 bit synchronous FIFO style
interface clocked up to 104 MHz) allows a common connection to higher layer
devices. A common system interface simplifies multi-service equipment utilizing
some or all of the following physical layer options:
• OC-48 POS/ATM
• 4xOC-12 POS/ATM
• 16xOC-3 POS/ATM
• Channelized POS/ATM
• High density DS3
• Gigabit Ethernet
The PM3386 is particularly suited for the following applications:
• Core Routers
• Edge Routers
• Enterprise Edge Routers
• Multi-Service Switches/Routers
• SONET/SDH Transport Muxes
These applications require various interfaces (Gigabit Ethernet, ATM, POS, DS3)
which use the POS-PHY Level 3 interface. Service cards for various physical
layer options can re-use upper layer devices and board design to improve timeto market. The use of Gigabit Ethernet within Internet points of presence
(POPs), Super POPs and Transport POPs is increasing due to the requirement
of inexpensive high-speed Layer 2 interconnect. Thus, connections between
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
Edge Routers and Core Routers within a POP are provided via Gigabit Ethernet.
Co-located server clusters are also connected via Gigabit Ethernet to POP
routers. Similarly, Gigabit Ethernet is becoming the choice for connection
between Enterprise Routers and Multi-Service switches. Transport equipment is
looking to provide Ethernet directly over SONET/SDH for wide area transparent
bridging.
In a typical application the S/UNI-2xGE performs data recovery on the Gigabit
Ethernet stream, MAC level frame checks and sends the frame to an upper layer
device (such as an IP processor) for forwarding via the POS-PHY level 3
interface. The S/UNI-2xGE maintains extensive statistics for SNMP and RMON
applications. On egress, frames are formatted into physical frames with the
proper inter-frame gap, preamble and start of frame delimiter. The physical
packet is then serialized for transmission over an external electrical optical
module. The initial configuration and ongoing control and monitoring of the
S/UNI-2xGE are provided via a generic microprocessor interface. The following
diagram shows a typical multi-service card application for the PM3386 S/UNI2xGE with similar cards for OC48 and Quad OC-12 ports.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
The PM3386 is a monolithic integrated circuit that implements a two port full
duplex 1000 Mbit/s Gigabit Ethernet MAC data transport device. The PM3386
provides line interface connectivity provided by an on-chip SERDES and GMII
functions and data transport to the up stream device via the industry standard
POS-PHY Level 3 interface.
Serializer-Deserializer (SERDES)
The PM3386 has two internal serializer-deserializer transceivers. The SERDES
are IEEE 802.3-1998 Gigabit Ethernet compatible supporting gigabit data
transfer flows. The SERDES is based on the X3T11 10 Bit specification. The
PM3386 receives and transmits Gigabit Ethernet streams using a bit serial
interface for direct connection to optical transceiver devices. The SERDES
performs data recovery and serial to parallel conversion for connection to the
Enhanced Gigabit Media Access Control block.
Gigabit Media Independent Interface (GMII)
For Gigabit Ethernet over copper support, the PM3386 provides dual standard
GMII interfaces. A copper Gigabit Ethernet physical layer device can be
connected to the PM3386 via this interface.
Enhanced Gigabit Media Access Control (EGMAC)
The Enhanced Gigabit Media Access Control (EGMAC) block provides an
integrated IEEE 802.3-1998 Gigabit Ethernet Media Access Control (MAC)
supporting high performance 1000Base capability. The EGMAC has line side
interfaces for connection to internal (SERDES) and external Gigabit PHY via
GMII on each Gigabit Ethernet port. The Enhanced Gigabit MAC (EGMAC)
incorporates all of the Gigabit Ethernet MAC functions including AutoNegotiation, statistics, and the MAC Control Sub-layer that adheres to IEEE
802.3-1998 providing support for PAUSE control frames. The EGMAC provides
basic frame integrity checks to validate incoming frames. The EGMAC also
provides simple line rate ingress address filtering support via 8 exact-match MAC
address and VID unicast filters, one 64-bin hash-based multicast filter, and the
ability to filter or accept matched frames on a per instance programmable
fashion. All inquires for filtering are done at line rate with no system latency
introduced for look up cycles.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
The PM3386 also incorporates a rich set of per port RMON, SNMP, and Etherlike
Management Information Base counters. Deep statistical counters are used for
management counts providing a minimum rollover time of greater than 58
minutes. All counts are easily managed via the Management Statistics (MSTAT)
block.
POS-PHY Level 3 Interface (PL3)
The PM3386 can connect to a single upper layer device through a POS-PHY
Level 3 Interface. The POS-PHY Level 3 interface is a 32-bit wide interface with
a clock rate from 60 to 104 MHz. POS-PHY Level 3 was developed with the
cooperation of the SATURN Development Group to cover all application bit rates
up to and including 3.2 Gbit/s. This interface provides standards support for
interoperation between the PM3386, a multiple PHY layer device, connecting to
one Link Layer device. The interface stresses simplicity of operation to allow
forward migration to more elaborate PHY and Link Layer devices. The POSPHY interface contains 64KB receive and 16KB transmit FIFOs per channel.
These FIFOs contain programmable thresholds specifying full and empty
conditions.
Receive Direction
In the receive direction, the PM3386 can be configured to use the internal
SERDES or the GMII interface on a per channel basis. For SERDES operation,
a Gigabit Ethernet bit stream is received from an external optical transceiver.
The data is recovered and converted from serial to parallel data for connection to
the EGMAC block. The EGMAC terminates the 8B/10B line codes and performs
frame integrity checks (frame length, FCS etc). For GMII operation, the physical
packet is sourced from an external copper physical layer device to the PM3386
via the GMII interface (8 bits clocked at 125 MHz). The EGMAC accepts the 8 bit
data and performs frame integrity checks once the complete frame is received.
The EGMAC can optionally filter erred frames.
Statistics are updated and the frame is sent to the POS-PHY Level 3 interface.
The FIFO’s in the POS-PHY interface accommodate system latencies and allows
for loss-less flow control up to 9.6k bytes. The received frames are then read
through the POS-PHY Level 3 (32 bits clocked from 60-104 MHz) system side
interface.
Transmit Direction
In the transmit direction, packets to be transmitted are written into the POS-PHY
TX FIFO through the POS-PHY Level 3 interface (32 bits clocked from 60-104
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
MHz) from the upper layer device. The channel is selected by the upper layer
device and is indicated in-band on the POS-PHY interface. The EGMAC builds a
properly formatted Ethernet physical packet (padding to minimum size and
inserting the preamble, start of frame delimiter (SFD) and the inter-packet gap
(IPG)). Statistics are updated and the physical packet is sent to the SERDES or
the GMII interface.
For SERDES operation, the EGMAC encodes the physical packet using 8B/10B
encoding and passes the physical packet to the SERDES block. The SERDES
performs parallel to serial conversion using an internally synthesized 1250 MHz
clock. The bit stream is sent to an external optical transceiver for transmission
over fiber cable. For GMII operation, the EGMAC sends the physical packet byte
by byte across the GMII interface (8 bits clocked at 125 MHz) to an external
copper Gigabit Ethernet physical layer device. The copper Gigabit Ethernet
physical layer device then transmits the physical packet over copper cable.
Flow Control
Flow control is handled in the EGMAC block. When a PAUSE control frame is
received, the PM3386 will optionally terminate transmission (after the current
frame is sent) and assert the appropriate channel side band flow control output
to indicate the paused condition. The received PAUSE control frame can be
optionally filtered or passed to the link layer device via the POS-PHY Level 3
interface.
PAUSE control frames are transmitted either under link layer control using
channel side band flow control inputs, under link layer control transparent to the
PM3386, host based PAUSE frame control or under internal control based on
receive FIFO levels. All four methods can provide for loss-less flow control.
General
The PM3386 is configured, controlled and monitored via a generic 16-bit
microprocessor bus interface. The PM3386 also provides a standard 5 signal
IEEE 1149.1 JTAG test port for boundary scan board test purposes.
The PM3386 is implemented in low power, +1.8 Volt, CMOS technology with 5V
TTL compatible digital inputs and 3.3V TTL/CMOS compatible digital outputs.
The PM3386 is packaged in a 352-pin UBGA package.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
125 MHz reference clock used to generate
GTX_CLK0 or GTX_CLK1 during GMII
mode. The Clock Synthesis Unit uses this
clock as it’s input reference during
SERDES mode.
Please refer to the Operations section for a
discussion of clock mode selection
interfacing issues.
Receive Differential Data (Port 0)
These PECL inputs (RXD0+/-) contain the
8B/10B bit serial receive stream. The
receive data is recovered from the RXD0+/bit stream.
Receive Signal Detect (Port 0)
RXSD0 indicates the presence of valid
receive signal power from the Optical
Physical Medium Dependent Device. A
logic level high indicates the presence of
valid data. A logic low indicates a loss of
signal.
RXD1+
RXD1-
Differential
PECL
Input
K26
K25
Receive Differential Data (Port 1)
The PECL inputs RXD1+/- contain the
8B/10B bit serial receive stream. The
receive data is recovered from the RXD1+/bit stream.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
RXSD1 indicates the presence of valid
receive signal power from the Optical
Physical Medium Dependent Device. A
logic level high indicates the presence of
valid data. A logic low indicates a loss of
signal.
Transmit Differential Data (Port 0)
The PECL outputs TXD0+/- contain the
1.25 Gbit/s transmit stream. The TXD0+/outputs are driven using the CSU clock.
Transmit Differential Data (Port 1)
The PECL outputs TXD1+/- contain the
1.25 Gbit/s transmit stream. The TXD1+/outputs are driven using the CSU clock.
Receive and Transmit Analog Test Ports
The ATP[1:0] pins are used for
manufacturing testing only and should be
tied to analog ground.
Table 3-Gigabit Media Independent Interface (GMII)
Signal NameDirectionPin No.Function
GTX_CLK0OutputAD22
GMII Transmit Clock (Port 0)
125 MHz reference clock supplied by the
PM3386.
TXD0[0]
TXD0[1]
TXD0[2]
TXD0[3]
TXD0[4]
TXD0[5]
TXD0[6]
TXD0[7]
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
OutputW24
W23
W25
W26
Y24
Y25
AA24
AA25
GMII Transmit Data (Port 0)
Byte-wide transmit data is output on these
pins synchronously to the PHY device.
The least significant bit, TXD0[0] is the first
bit transferred on the line.
This signal is updated on the rising edge of
GTX_CLK0.
When in GMII mode this signal is an active
high signal asserted when valid data is
present on the TXD0[7:0] and TX_ER0
pins. This signal is updated on the rising
edge of GTX_CLK0.
When in SERDES mode this signal
enables operation of the external
transmitter. When asserted (default active
low) it indicates the potential presence of
valid transmit data. When de-asserted
indicates the absence of valid transmit
data. Note that while in SERDES mode
the polarity of this signal is programmable
to support interoperability with differing
optical transmitters.
GMII Transmit Coding Error (Port 0)
Active high signal asserted when an error
is detected during transmission. Please
refer to the Operations section for a full
listing of error conditions reported by the
PM3386 using the TX_ER0 output.
This signal is updated on the rising edge of
GTX_CLK0.
RX_CLK0Schmitt
Input
AC21
GMII Receive Clock (Port 0)
125 MHz GMII reference clock received
from the PHY device.
RXD0[0]
RXD0[1]
RXD0[2]
RXD0[3]
RXD0[4]
RXD0[5]
RXD0[6]
RXD0[7]
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
InputAF20
AD19
AE20
AF21
AD20
AE21
AF22
AD21
GMII Receive Data (Port 0)
Byte-wide receive data is input on these
pins synchronously from the PHY device.
The least significant bit, RXD0[0] is
expected to contain the first bit received on
the line.
When in GMII mode this signal is an active
high signal asserted when valid data is
present on the TXD1[7:0] and TX_ER1
pins. This signal is updated on the rising
edge of GTX_CLK1.
When in SERDES mode this signal
enables operation of the external
transmitter. When asserted (default active
low) it indicates the potential presence of
valid transmit data. When de-asserted
indicates the absence of valid transmit
data. Note that while in SERDES mode
the polarity of this signal is programmable
to support interoperability with differing
optical transmitters.
GMII Transmit Coding Error (Port 1)
Active high signal asserted when an error
is detected during transmission. Please
refer to the Operations section for a full
listing of error conditions reported by the
PM3386 using the TX_ER1 output. This
signal is updated on the rising edge of
GTX_CLK1.
RX_CLK1Schmitt
Input
B20
GMII Receive Clock (Port 1)
125 MHz GMII reference clock received
from the PHY device.
RXD1[0]
RXD1[1]
RXD1[2]
RXD1[3]
RXD1[4]
RXD1[5]
RXD1[6]
RXD1[7]
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
InputC22
D21
A23
B22
C21
D20
A22
B21
GMII Receive Data (Port 1)
Byte-wide receive data is input on these
pins synchronously from the PHY device.
The least significant bit, RXD1[0] is
expected to contain the first bit received on
the line.
Active high signal asserted when valid data
is present on the RXD1[7:0] and RX_ER1
pins.
This signal is synchronized to RX_CLK1
GMII Receive Error (Port 1)
Active high signal asserted when there has
been an error during the received physical
packet.
This signal is synchronized to RX_CLK1.
MII Management Data Clock
MDC provides the MII reference clock for
communication between the PM3386 and
other transceivers.
MII Management Data
When configured as an input, the external
PHY supplies status during MII
Management read cycles. When
configured as an output, the PM3386
supplies control during MII Management
write/read cycles and data during MII
Management write cycles.
Data values on the MDIO pin are updated
and sampled on the rising edge of MDC.
Table 4-POS-PHY Level 3 Transmit Interface
Signal NameDirectionPin No.Function
TFCLKSchmitt
Input
AF7
POS-PHY Transmit FIFO Write Clock
TFCLK is used to synchronize data transfer
transactions between the higher layer
device and the PM3386. TFCLK cycles at
a 60 to 104 MHz rate.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
This bus carries the packet octets that are
written to the selected transmit FIFO and
the in-band port address to select the
desired transmit FIFO. The TDAT bus is
considered valid only when TENB is
simultaneously asserted.
When a 32-bit interface is used, data must
be transmitted in big endian order on
TDAT[31:0].
TDAT[31:0] is sampled on the rising edge
of TFCLK.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
Active high signal used to indicate that the
current packet must be aborted. TERR
should only be considered valid when
TENB and TEOP are simultaneously
asserted.
TERR is sampled on the rising edge of
TFCLK.
POS-PHY Transmit Write Enable
Active low signal used to control the flow of
data to the transmit FIFOs.
When TENB is high, the TDAT[31:0],
TMOD, TSOP, TEOP, TPRTY and TERR
signals are invalid and are ignored by the
PM3386. However, the TSX signal if
asserted is valid and is processed by the
PM3386 only when TENB is high.
When TENB is low, the TDAT[31:0], TMOD,
TSOP, TEOP, TPRTY and TERR signals
are valid and are processed by the
PM3386. The TSX signal is ignored by the
PM3386 when TENB is low.
TENB is sampled on the rising edge of
TFCLK.
TPRTYInputAE6
POS-PHY Transmit bus parity
The transmit parity (TPRTY) signal
indicates the parity calculated over the
TDAT bus. TPRTY is considered valid only
when TENB or TSX are asserted.
By default the PM3386 uses odd parity.
The PM3386 supports both even and odd
parity. The PM3386 reports any parity error
to the host processor via a maskable
interrupt, but does not interfere with the
transferred data.
TPRTY is sampled on the rising edge of
TFCLK.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
23
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