PMC PM3351-RC, PM3351-SW Datasheet
PM3351 ELAN 1X100
DATA SHEET
PMC-970113 ISSUE 3 SINGLE PORT FAST ETHERNET SWITCH
PM3351
ELAN 1X100
SINGLE PORT FAST ETHERNET
SWITCH
DATA SHEET
ISSUE 3: FEBRUARY 1998
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
PM3351 ELAN 1X100
DATA SHEET
PMC-970113 ISSUE 3 SINGLE PORT FAST ETHERNET SWITCH
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
PM3351 ELAN 1X100
DATA SHEET
PMC-970113 ISSUE 3 SINGLE PORT FAST ETHERNET SWITCH
CONTENTS
FEATURES............................................................................................................1
BLOCK DIAGRAM.................................................................................................3
DESCRIPTION ......................................................................................................4
Introduction....................................................................................................5
Switch Processor...........................................................................................5
Multi-channel DMA Processor........................................................................6
Ethernet/IEEE 802.3 MAC Interface..............................................................6
Expansion Port...............................................................................................6
Local Memory Controller................................................................................7
Clocking and Test..........................................................................................7
TYPICAL SYSTEM APPLICATION........................................................................8
Low-cost 10/100 Mbit/s Switching Hub..........................................................8
PRIMARY FEATURES AND BENEFITS ...............................................................9
Wire-speed frame switching...........................................................................9
Combined Input- and Output-buffered switch................................................9
Modular design. .............................................................................................9
Advanced switching features.........................................................................9
Spanning tree bridging capabilities..............................................................10
Management and monitoring support..........................................................10
Autoconfiguration via Local PROM/EEPROM..............................................10
PIN DIAGRAM.....................................................................................................12
208-Pin Quad Flat Pack Pin Diagram..........................................................12
PIN DESCRIPTION .............................................................................................13
Functional Grouping.....................................................................................15
PCI Expansion Bus Interface.......................................................................16
MII Interface Pins.........................................................................................17
Local Memory Interface ...............................................................................18
Clock Inputs and Outputs.............................................................................19
Miscellanous Inputs and Outputs.................................................................20
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PM3351 ELAN 1X100
DATA SHEET
PMC-970113 ISSUE 3 SINGLE PORT FAST ETHERNET SWITCH
DC CHARACTERISTICS.....................................................................................21
Absolute Maximum Ratings.........................................................................21
Recommended Operating Conditions..........................................................21
D.C. Characteristics.....................................................................................22
AC CHARACTERISTICS.....................................................................................23
PCI Bus Interface.........................................................................................24
MII Interface.................................................................................................25
Memory Interface.........................................................................................27
15 nS SRAM AC Timing.........................................................................27
150 ns EEPROM/EPROM AC Timing ....................................................28
60 ns EDO DRAM AC Timing.................................................................29
Clocking.......................................................................................................31
Miscellaneous..............................................................................................31
FUNCTIONAL DESCRIPTION.............................................................................32
Overview......................................................................................................32
System Components....................................................................................32
System Block Diagram...........................................................................33
System Memory Map..............................................................................34
Device Internal Blocks .................................................................................37
Switch Processor....................................................................................37
100Mbit/s Ethernet MAC Interface .........................................................38
Multichannel DMA Controller .......................................................................43
Memory Controller .......................................................................................46
PCI Expansion Port......................................................................................47
Watchdog Timer Facility.........................................................................51
Device Configuration..............................................................................52
System Bootstrap Image........................................................................54
Configuration Parameters.......................................................................60
Self Test and Error Reporting.................................................................61
Data Structures............................................................................................63
Switch Processor Operating Environment..............................................64
Packet Buffers........................................................................................68
Data Descriptors.....................................................................................71
Transfer Rings........................................................................................74
Local Port Descriptor and Port Descriptor Counters...............................76
Expansion Port Descriptor Table............................................................84
Address Hash Table...............................................................................86
Free Pools..............................................................................................94
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PM3351 ELAN 1X100
DATA SHEET
PMC-970113 ISSUE 3 SINGLE PORT FAST ETHERNET SWITCH
Spanning Tree Support Data Structures.................................................96
RTOS Requirements..............................................................................97
UDP/IP Protocol Stack Requirements....................................................97
SNMP Requirements..............................................................................97
Storage Requirements............................................................................97
Switching System Initialization...................................................................100
Frame Switching Process..........................................................................101
Address Learning and Aging......................................................................115
Local Address Learning........................................................................116
Remote Learning Process....................................................................117
Default Hash Bucket.............................................................................118
Buffer and Queue Management.................................................................122
Buffer Management..............................................................................123
Transmit FIFO Management ................................................................124
Broadcast Rate Limiting .......................................................................125
Statistics Collection....................................................................................126
Messaging Protocol ...................................................................................128
Spanning Tree Operation...........................................................................129
RTOS Operation........................................................................................129
UDP/IP Protocol Stack Operation..............................................................129
SNMP Operation........................................................................................129
Device Interface via PCI ............................................................................129
Frame Transfer to Non-ELAN Devices.................................................129
Participation in Address Learning.........................................................129
Participation in the Messaging Protocol................................................129
Accessing Variables and Statistics.......................................................129
Byte Ordering .......................................................................................129
Default Byte Ordering...........................................................................130
Alternate Byte Ordering........................................................................131
ELAN 1x100 / ELAN 8x10 Expansion Bus Data Transfer Rates..........131
PCI REGISTER/MEMORY ACCESS.................................................................137
PCI Configuration Space ...........................................................................137
PCI Configuration Registers.................................................................138
PCI Memory Space....................................................................................147
Local Memory Access...........................................................................148
Device Control/Status Registers...........................................................148
Device Configuration Registers............................................................150
Device Debug Registers.......................................................................155
Request and Acknowledge Counter Registers.....................................155
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PM3351 ELAN 1X100
DATA SHEET
PMC-970113 ISSUE 3 SINGLE PORT FAST ETHERNET SWITCH
PROGRAMMER'S MODEL................................................................................157
Local Memory ............................................................................................158
Register Map..............................................................................................158
General-Purpose Registers..................................................................158
Special-Purpose Registers...................................................................158
Control Registers..................................................................................159
Register Descriptions.................................................................................163
CPU Special Registers.........................................................................163
Device Control Registers......................................................................164
RPCIM Functional Block (PCI access DMA channel)................................173
DEBUG Functional Block...........................................................................182
DPI Functional Block (DMA transmit channel)...........................................187
TX_FIFO functional block: .................................................................................191
Major components of the TX_FIFO datapath.......................................191
TX_FIFO interrupts to Switch Processor..............................................192
Disposition of Frames:..........................................................................192
DPO funtional block (DMA transfer handshake channel)...........................199
HASH functional block...............................................................................215
Interrupts to Swtich Processor...................................................................226
GPI (Switch Processor General Purpose Inputs).......................................230
GPO (Switch Processor General Purpose Outputs)..................................231
Coprocessor Test Conditions.....................................................................235
OPERATION......................................................................................................237
Power Supply Sequencing.........................................................................237
MECHANICAL INFORMATION .........................................................................238
ORDERING AND THERMAL INFORMATION...................................................240
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PM3351 ELAN 1X100
DATA SHEET
PMC-970113 ISSUE 3 SINGLE PORT FAST ETHERNET SWITCH
FEATURES
• Single-chip, 1-port, full duplex or half duplex, 10/100BaseT switching device for
low-cost unmanaged and managed networks.
• On-chip 50 MHz RISC CPU processor core, multi-channel DMA controller,
MAC-layer interface logic, FIFOs, PCI-based expansion port and a flexible
memory controller.
• CPU supports background applications running on local OS (e.g., SNMP or
RMON), and real-time data oriented applications (e.g., frame forwarding and
filtering decisions).
• Performs frame switching at a rate of 200 Mbit/s (full duplex), 100 Mbit/s (half
duplex).
• Fully compatible with the PM3350, 8-port 10 Mbit/s switch device; may be used
to create a compact and inexpensive mixed 10/100 Mbit/s switching hub.
• Store-and-forward operation with full error checking and filtering.
• Filtering and switching at wire rates (up to 148,800 packets per second),
supporting a mix of Ethernet and IEEE 802.3 protocols.
• Expansion port supports a peak system bandwidth of 1 Gbit/s, and is compatible
with industry-standard PCI bus (version 2.1).
• Performs all address learning, address table management and aging functions
for up to 32,768 MAC addresses (limited by external memory). Address
learning rate of up to 100,000 addresses per second.
• Maximum broadcast/multicast at wire rates with configurable broadcast storm
rate limiting.
• Low-latency operation in both unicast and broadcast modes.
• Implements the Link Partition function to isolate malfunctioning segments or
hosts.
• IEEE 802.1d compliant spanning-tree transparent bridging supported on-chip,
with configurable aging time and frame lifetime control.
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PM3351 ELAN 1X100
DATA SHEET
PMC-970113 ISSUE 3 SINGLE PORT FAST ETHERNET SWITCH
• Flow control supported for both full duplex and half duplex operation: supports
IEEE 802.3x PAUSE frame flow control in full-duplex mode, and supports userenabled backpressure flow control in half-duplex mode with configurable buffer
thresholds and limits.
• Configuration, management, MIB statistics and diagnostics available in-band or
out-of-band.
• Maintains and collects per-port and per-host statistics at wire rates, allowing a
network switch comprised of PM3351 and PM3350 chips to implement RMON
statistics (EtherStats and HostStats) using supplied on-chip firmware.
• Interfaces directly to industry-standard 100 Mbit/s transceivers with no glue logic
via the built-in Medium Independent Interface (MII) port with full support for the
autonegotiation function implemented by the PHY devices.
• Fully static CMOS operation at 50 MHz clock rates.
• 3.3 Volt core, 5 Volt compatible I/O
• 208 pin PQFP package.
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PM3351 ELAN 1X100
DATA SHEET
PMC-970113 ISSUE 3 SINGLE PORT FAST ETHERNET SWITCH
BLOCK DIAGRAM
50 MHz
Embedded CPU
PCI
Expansion
Bus
PCI
Bus
Interface
Expansion
Registers
I
Cache
D
Cache
Transmit
Channel Logic
Receive
DMA Controller
External
memory
Interface
SRAM / EPROM
Tx
FIFO
Rx
FIFO
100BaseT
Transmit MAC
100BaseT
Transmit MAC
100BaseT
MII I/F
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PM3351 ELAN 1X100
DATA SHEET
PMC-970113 ISSUE 3 SINGLE PORT FAST ETHERNET SWITCH
DESCRIPTION
The PM3351 is a low-cost, highly integrated stand-alone single-chip switching device
for 10/100 Mbit/s Ethernet (IEEE 802.3u, IEEE 802.12) switching and bridging
applications. The device supports all processing required for switching Ethernet
packets between the on-chip Medium Independent Interface (MII) port and the built-in 1
Gbit/s expansion port, to which other PM3351 (ELAN 1x100) or PM3350 (ELAN 8x10)
devices may be attached.
The PM3351 is directly compatible with the PM3350, 8-port 10Mbit/s Ethernet switch
chip. The PM3351 can be used with the PM3350 to create non-blocking switches of the
configurations shown in the table below, with each 100 Mbit/s port configured for fullduplex and each 10 Mbit/s port configured for half-duplex
Switch Configuration # PM3350
Chips
# PM3351
Chips
4 x 100 Mbit/s 0 4
3 x 100 Mbit/s + 16 x 10Mbit/s 2 3
2 x 100 Mbit/s + 40 x 10 Mbit/s 5 2
1 x 100 Mbit/s + 56 x 10 Mbit/s 7 1
0 x 100 Mbit/s + 64 x 10 Mbit/s 8 0
A switch built using the PM3351 can be expanded to use up to 7 additional devices on
the PCI expansion bus; the limitation to 8 devices is a result of using dedicated internal
counters for implementing the ELAN switch protocol over the expansion bus. For details
on the expected expansion bus data traffic requirements for different combinations of
PM3350 and PM3351 chips please refer to section Expansion Bus Data Transfer
Rates.
All of the initialization, switching, interfacing, management and statistics gathering
functions are performed by the PM3351, minimizing the size and cost of a switching
hub with one or more 100 Mbit/s ports.
Switch configuration and management can be performed either remotely (in-band), via
the on-chip SNMP MIB, agent and integrated TCP/UDP/IP stack, or from a local CPU
interfaced to the expansion port. The ELAN 1x100 also collects per-port and per-host
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PM3351 ELAN 1X100
DATA SHEET
PMC-970113 ISSUE 3 SINGLE PORT FAST ETHERNET SWITCH
RMON statistics at wire rates on all ports. The PM3351 chip contains all the required
elements of a high-performance Ethernet switch: an MII interface for connection to
physical-layer transceivers, MAC-layer processing logic, buffer FIFOs, a high-speed
DMA engine for fast frame transfers, a local memory interface for up to 4 Mbytes of
external buffer memory, a compatible PCI bus master and slave unit for modular
expansion, and a switch processing unit that implements the switching and bridging
functions. The only additional components required for each 100 Mbit/s switch port are
an MII compliant transceiver (supports 100BaseTX/FX, 100BaseT4,100BaseT2, and
any future 802.3-compliant 100Mbit MII PHYs), passive line interface devices, a bank of
external memory and a system clock. The amount of external memory may range up to
4 Mbytes, depending on the amount of frame buffering required and the number of
MAC addresses to be supported, and may be implemented using standard
asynchronous SRAM devices with 15 nsec access times. Switch configuration
information is provided to the PM3351 using a single EPROM or EEPROM; only one
EPROM is required in a multiple PM3351/PM3350 system.
The ELAN 1x100 device is implemented in a high-density, low-voltage CMOS
technology for low cost and high performance. It is available in a 208-pin Quad Flat
Pack, and is ideally suited for compact, low-cost desktop, workgroup and departmental
Ethernet switching applications.
DEVICE DATA
Introduction
The ELAN 1x100 (PM3351) offers a complete system-level solution, integrating all
required elements (except frame/address memory and transceiver logic) in a single
high-density VLSI chip. It is a true single-chip switch; all the required functions,
including management, RMON-level statistics collection, spanning tree support and
self-configuration, are performed by the ELAN 1x100 without need for external CPUs or
logic. In addition, the functions required for expandability are also integrated into the
device.
The ELAN 1x100 is built around a RISC CPU based switching processor core which is
closely coupled with a multi-channel DMA controller, MAC-layer interface logic, FIFOs,
a PCI-based expansion port and a flexible memory controller.
Switch Processor
An on-chip Switch Processor is primarily responsible for performing the Ethernet / IEEE
802.3 frame routing functions, and can switch packets arriving simultaneously from the
single100BaseT port and the expansion port at full wire rates using address tables that
it creates and maintains in external local memory. Store-and-forward switching is
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PM3351 ELAN 1X100
DATA SHEET
PMC-970113 ISSUE 3 SINGLE PORT FAST ETHERNET SWITCH
performed, allowing the Switch Processor to detect CRC, length and alignment errors
and reject bad packets. The Switch Processor also supports IEEE 802.3
group/functional address handling. Address aging, topology change updates, and
statistics collection are performed by the Switch Processor as well.
The Switch Processor unit allows the device to support high-level capabilities. It
implements the full IEEE 802.1d spanning-tree transparent bridging protocol, which
allows the ELAN 1x100 to act as an expandable learning bridge, performing learning,
filtering and redirection at full speed. RMON statistics collection, plus a messaging
system to support master/slave communications in a multi-device switch, are also
implemented by the Switch Processor. When additional switch devices are connected
to the ELAN 1x100 expansion port, the Switch Processors in all PM3350 and PM3351
ELAN chips intercommunicate to transfer frames to each other and also transparently
support a distributed SNMP/RMON MIB.
Multi-channel DMA Processor
The on-chip DMA Controller contains four independent and concurrently operating
channels: one for receiving frames over the 100BaseT port; another for transmitting
frames over the same port; and two that are dedicated to the expansion port. The DMA
Controller operates under the control of the Switch Processor to transfer packets and
data at high speed between the 100BaseT port, the local memory and the expansion
port. It also computes 32-bit IEEE Frame Check Sequence (FCS) CRC remainders over
the transferred packets, allowing the Switch Processor to filter packets with errors and
generate CRCs for transmitted packets as required. Control logic is provided to support
full and half-duplex operation, as well as the handling of management traffic.
Ethernet/IEEE 802.3 MAC Interface
One Ethernet/IEEE 802.3u MAC-layer interface based on the Media Independent
Interface (MII) is built into the ELAN 1x100 chip. It connects directly to the external
100BaseT compatible PHY devices via the industry-standard MII interface, and
performs all of the MAC-layer processing tasks required for CSMA/CD networks. Both
full-duplex and half-duplex modes of operation are supported at 10 and 100 Mbit/s data
rates. The MAC interface includes independent receive and transmit FIFO buffers to
support sustained full wire rate operation.
Configuration and initialization of the attached 100Mbit/s PHY devices can be
performed using the MII management interface. This is accomplished by using the MII
pins MDIO and MDCLK to read, write and poll the management registers built into an
MII-compliant PHY device. This allows the PM3351 to support auto-negotiation, link
status, and other management operations on the attached PHY device(s), including the
Next Page functions. Serial management functions are implemented by the Switch
Processor for maximum flexibility and "standards-proofing".
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PM3351 ELAN 1X100
DATA SHEET
PMC-970113 ISSUE 3 SINGLE PORT FAST ETHERNET SWITCH
Expansion Port
A 32-bit parity-checked PCI-based expansion port is provided to allow the ELAN 1x100
to communicate transparently with other PCI bus devices to implement switches that
have multiple 100Mbit/s and 10Mbit/s ports. The expansion port supports a maximum
throughput of over 1 Gbit/s, and requires only a single PAL or similar device serving as
a bus arbiter. A common protocol is used for inter-chip communication between the
ELAN 1x100 (PM3351) and ELAN 8x10 (PM3350). Packets received on an ELAN
1x100 MAC port that are destined for an external ELAN switch chip are transferred over
the expansion bus prior to transmission on the designated destination port. Broadcast
and multicast packets are handled using a two-level replication scheme, in which the
broadcast/multicast frame is first transferred to all of the external ELAN switch chips,
after which it is transmitted out the required destination ports without any further use of
the expansion bus. (In the case of an ELAN 1x100, only one port is present in each
destination device, and hence only one level of replication takes place.) In addition,
ELAN switch chips interconnected via the PCI bus exchange information to maintain the
distributed MIB.
The expansion port is compatible with the industry-standard Peripheral Component
Interconnect (PCI) specification version 2.1, which allows the ELAN 1x100 chip to be
directly interfaced to any host computer supporting the PCI bus. The host CPU can
then communicate with the ELAN 1x100 and control its functions, greatly expanding the
range of potential applications. The maximum PCI clock of 40 MHz is supported.
Local Memory Controller
The local memory is used for holding configuration information, MAC address tables
and statistics tables, node management data, packet buffers, and host communication
queues if a local host CPU is present. The ELAN 1x100 integrates a memory controller
that is capable of addressing and directly driving up to 16 MBytes of external memory,
divided into four banks of 4 MBytes each, with decoded selects for each bank.
1
Independent, software programmable access times may be set for each bank, allowing
a glueless interface to a mix of SRAM, , EEPROM, and EPROM in the same system.
An external memory timing generator may also be used if desired. The memory
controller accepts simultaneous requests from the Switch Processor, the DMA
processor, and the expansion port, and efficiently partitions the 100 MByte-per-second
memory port bandwidth among them.
The ELAN 1x100 is capable of auto-configuring after power-up via an 8-bit EPROM or
EEPROM connected to the memory port. Parameters (such as the MAC address, IP
1
When accessing SRAM and EEPROM devices, however, the actual limit is 1 Mbyte per bank, as the
upper bits of the internal address bus are not brought out to physical pins. The entire 4 Mbytes per bank is
only accessible when using DRAM memory types.
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PM3351 ELAN 1X100
DATA SHEET
PMC-970113 ISSUE 3 SINGLE PORT FAST ETHERNET SWITCH
address, configuration options, etc.) may be placed in this EPROM or EEPROM, and
will be loaded automatically by the ELAN 1x100.
1
Clocking and Test
The PM3351 is implemented in fully-static CMOS technology, and can operate at any
device clock frequency between 45 and 50 MHz (25 to 40 MHz for the expansion port
bus). The Switch Processor performs a comprehensive power on self test (POST), and
can report failure conditions and device status in a variety of ways (an 8-bit LED
interface register connected to local memory, writing to a host over the PCI bus, writing
to a serial port interface connected to local memory, etc).
1
The ELAN 1x100 follows the same configuration process as the ELAN 8x10 chip.
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PM3351 ELAN 1X100
M
DATA SHEET
PMC-970113 ISSUE 3 SINGLE PORT FAST ETHERNET SWITCH
TYPICAL SYSTEM APPLICATION
Low-cost 10/100 Mbit/s Switching Hub
The PM3351 chip can act as a high-speed server or backbone port in low-cost,
compact Ethernet switching hub applications. Such a hub can be created from one or
more PM3351 devices (one for every 100 Mbit/s port required), 1 to 7 PM3350 chips
(one for every eight 10 Mbit/s ports required), a bank of memory per device (60 nsec
DRAM for each PM3350, 15 ns SRAM for each PM3351) for holding frame buffers and
switching tables, a single 32k x 8-bit EEPROM device for configuration information, two
LXT944 10BaseT interface adapters per PM3350 chip, one LXT 970 100 Mbit/s PHY
device per PM3351, and suitable passive components (filters, transformers, crystal
oscillators, etc.). A block diagram of a typical 32-port 10BaseT stackable switching hub
with two 100 Mbit/s server/backbone ports is given in the following diagram. The
stacking connectors allow multiple switch assemblies to be seamlessly stacked.
8 x 10BaseT 10/100BaseT8 x 10BaseT
Quad
PHY
ELA N 8x10
8x10BaseT
Quad
PHY
PM 3350
EDO
DRAM
Quad
PHY
ELA N 8x10
8x10BaseT
PM 3350
PC I Backplane
ELA N 8x10
EEPRO
8x10BaseT
PM 3350
Quad
PHY
Quad
PHY
EDO
DRAM
8 x 10B aseT 8 x 10B aseT
Expandable 10/100 Mbit/s Ethernet Switch
Quad
PHY
ELA N 8x10
8 x 10BaseT
PM 3350
Quad
PHY
Quad
PHY
EDO
DRAM
10/100
PHY
ELA N 1x100
1x10/100
BaseT
PM 3351
EDO
DRAM
SRAM
ELA N 1x100
1x10/100
BaseT
PM 3351
10/100
PHY
10/100BaseT
SRAM
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PM3351 ELAN 1X100
DATA SHEET
PMC-970113 ISSUE 3 SINGLE PORT FAST ETHERNET SWITCH
PRIMARY FEATURES AND BENEFITS
As an Ethernet switching/bridging solution, the PM3351 offers a number of benefits in a
low-cost switching hub:
Wire-speed frame switching.
Each PM3351 chip performs all of the functions required to implement a 10/100 Mbit/s
full/half duplex switch port at wire rates (ranging from 148,808 frames/sec for a frame
size of 64 bytes to 8130 frames/sec for a frame size of 1518 bytes). No additional logic,
microprocessors, etc. are necessary. In addition, the low cost and compact size
permitted by the single-chip PM3351 solution permits high-speed server or backbone
ports to be added to even entry-level switching hubs very simply.
Combined Input- and Output-buffered switch
The ELAN 1x100 implements a hybrid input-buffered/output-queued switching algorithm
which minimizes the possibility of frame lo ss, allows buffers to be allocate d on a
demand basis, and permits limits to be established to prevent any one memory
consumer from acquiring all system buffer memory. Frame buffer storage is allocated
within the external memory by the ELAN 1x100 from a central pool using an on-demand
method, employing linked lists of small, fixed-length buffers to hold variable sized
packets in order to maximize memory utilization.
Modular design.
Multiple PM3351 chips interconnect with no external glue logic (beyond a simple PCI
arbiter device), allowing a family of scalable switches to be built without redesign. When
used in conjunction with the PM3350 single-chip 8-port 10 Mbit/s Ethernet switch, a
10/100 Mbit/s switching hub can be realized at low cost. The 1 Gbit/s expansion port
bandwidth ensures that network capacity grows linearly as more chips from the ELAN
switch family are added.
Advanced switching features
The ELAN 1x100 implements per-frame lifetime control to ensure that transmit queues
are flushed properly in the event of bottlenecks at the output ports. Address aging is
handled on-chip, as is purging of the address table in the event of a network
reconfiguration. Broadcast storm rate limiting is implemented (with configurable rate
limits) to reduce the effects of high broadcast rates on the traffic flowing through the
switch. Two different methods of flow control are supported: backpressure for a halfduplex link and 802.3x Pause MAC Control frames for a full-duplex link. Flow control is
a user-selectable feature, with the thresholds and limits capable of being userconfigured in order to minimize frame loss in heavily loaded networks. Backpressure is
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performed by jamming (colliding with) incoming packets on the 100Mb port when the
port has no free receive buffers.
Spanning tree bridging capabilities
The ELAN 1x100 is capable of supporting the 802.1d spanning tree protocol, allowing it
to interoperate with IEEE-standard transparent bridges. The spanning tree protocol is
supported by the on-chip Switch Processor unit, and does not require an external CPU
for implementation, as the actual agent may be supported on the Switch Processor on
one of the PM3350 chips.
Management and monitoring support
The ELAN 1x100 (PM3351) maintains and collects RMON port and host statistics for all
learned MAC addresses at wire rates. These statistics may be retrieved either in-band
(via SNMP agent) or out-of-band (via the expansion bus). When multiple ELAN 1x100
and ELAN 8x10 chips are present in a system, they may be configured to
intercommunicate and create a distributed MIB in a transparent manner.
1
Status codes may be displayed on a set of LEDs (Light Emitting Diodes) during self-test
and operation at the system implementer's discretion. These status codes are output to
a register mapped into the ELAN 1x100 memory data bus at a specific address
location. Device failure during self-test, or specific operating conditions, may be
displayed using front-panel LEDs connected to the register.
An optional on-chip watchdog timer is provided by the ERST* output of the ELAN
1x100. The ERST* output of the device can be tied directly to the RST* input to provide
an optional system-wide watchdog reset. This facility permits the ELAN 1x100 to force
an automatic system restart whenever a fatal error is encountered during operation.
Autoconfiguration via Local PROM/EEPROM
The ELAN 1x100 automatically self-configures upon power-up using user-defined
parameters supplied in an external EPROM or EEPROM. The EPROM/EEPROM may
be connected to the memory bus and mapped to any address range; the ELAN 1x100
will automatically locate the EPROM or EEPROM and load the configuration
parameters from it. The ELAN 1x100 also contains hardware that enables it to write to
standard 3.3-volt EEPROM devices, thus permitting configuration information to be
changed dynamically.
1
The ELAN 8x10, if present in the system, can directly implement an optional on-chip SNMP agent on top
of an integral TCP/UDP/IP protocol stack, supporting SNMP and the RFC1493 bridge MIB, and supplying
SNMP access to the statistics gathered by the ELAN 1x100 (as well as the other devices in the system).
Alternatively, the system vendor may elect to disable the SNMP agent and access all chip statistics and
configuration variables directly from the expansion port.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 11
PM3351 ELAN 1X100
DATA SHEET
PMC-970113 ISSUE 3 SINGLE PORT FAST ETHERNET SWITCH
In a system with multiple ELAN devices, the master device (whether ELAN 1x100 or
ELAN 8x10) can load its configuration information and then configure the other ELAN
devices over the expansion bus, allowing configuration of the entire system with one
EPROM.
•
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 12
PM3351 ELAN 1X100
DATA SHEET
PMC-970113 ISSUE 3 SINGLE PORT FAST ETHERNET SWITCH
PIN DIAGRAM
The PM3351 is packaged in a 208-pin PQFP, with 135 signal pins, 36 VSS (gnd) pins,
31 VDD (3.3V) pins, and two 5V supply pins. The VSS and VDD pins are split between
internal (core) & i/o buffer pins (8 VSSI, 8 VDDI, 28 VSSO, & 23 VDDO pins). All pins
must be connected properly. Attention should be given to the 4 no-connect pins.
208-Pin Quad Flat Pack Pin Diagram
VSSI
VSSIncTST*
nc
VDDI
MINTR*
MDATA0
nc
MDATA1
VDDO
VSSO
MDATA3
MDATA2
MDATA4
VSSO
MDATA5
MDATA6
MDATA7
MDATA8
MDATA9
VDDO
VDDI
VSSO
MDATA10
MDATA11
MDATA12
VDDO
MDATA13
MDATA14
MDATA15
MDATA16
MDATA17
MDATA18
MDATA20
MDATA19
VSSO
VDDO
MDATA21
MDATA22
MDATA23
VSSO
MDATA24
MDATA25
MDATA26
MDATA27
MDATA28
VDDI
VSSI
MDATA29
MDATA30
MDATA31
BIAS5
VSSO
AD31
AD30
AD29
AD28
VDDO
VSSO
AD27
AD26
AD25
AD24
CBE3
VDDO
VSSO
FRAME*
DEVSEL*
IDSEL
TRDY*
IRDY*
VDDO
VSSO
AD23
AD22
AD21
AD20
AD19
AD18
VSSO
VDDO
VSSI
VDDI
AD17
AD16
CBE2
VSSO
REQ*
GNT*
INT*
VDDO
VSSO
AD15
AD14
AD13
AD12
AD11
VSSO
VDDO
AD10
AD9
AD8
CBE1
208
1
10
20
30
40
50
200
60
190
180
ELAN 1x100
PM3351
208 PQFP
70
80
100
160
150
140
130
120
110
VDDO
VSSO
MRAS*
MGWE
MWR0
MWR1
VDDO
VSSO
MWR2
MWR3
MRD*
MRDY*
MCS0*
VDDO
VSSO
MCS1*
MCS2*
MCS3*
MADDR0
MADDR1
MADDR2
MADDR3
VDDO
VDDI
VSSI
VSSO
MADDR4
MADDR5
MADDR6
MADDR7
MADDR8
MADDR9
VDDO
VSSO
MADDR10
MADDR11
MADDR12
MADDR13
VSSO
MADDR14
MADDR15
MADDR16
MADDR17
VDDO
VSSO
CRS
COL
TXD3
TXD2
TXD1
VSSI
VDDI
170
90
VSSO
VDDO
STOP*
PERR*
SERR*
PAR
AD7
AD6
AD5
AD4
AD3
AD1
AD0
AD2
VSSI
VSSO
VDDO
VDDI
VSSO
VDDO
CBE0
MEMCLK
VSSO
RST*
PCICLK
SYSCLK
VSSO
VDDO
nc
VSSI
MDC
VDDI
MDIO
VSSO
VDDO
CLK25
ERST*
VSSO
VDDO
RXD3
RXD2
RXD1
RXD0
RX_DV
RX_CLK
RX_ER
VDDO
TX_CLK
TXD0
TX_EN
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 13
BIAS5
VSSO
PM3351 ELAN 1X100
DATA SHEET
PMC-970113 ISSUE 3 SINGLE PORT FAST ETHERNET SWITCH
PIN DESCRIPTION
Pin Signal Pin Signal Pin Signal Pin Signal
1 BIAS5V 53 VDDO 105 VDDI 157 VDDI
2 VSSO 54 VSSO 106 VSSI 158 VSSI
3 AD31 55
4 AD30 56
5 AD29 57
6 AD28 58 PAR 110 COL 162 MDATA28
7 VDDO 59
8 VSSO 60 PCICLK 112 VSSO 164 MDATA27
9 AD27 61 VDDO 113 VDDO 165 MDATA26
10 AD26 62 VSSO 114 MADDR17 166 MDATA25
11 AD25 63 AD7 115 MADDR16 167 MDATA24
12 AD24 64 AD6 116 MADDR15 168 VSSO
13 CBE3 65 VDDI 117 MADDR14 169 VDDO
14 VDDO 66 VSSI 118 VSSO 170 MDATA23
15 VSSO 67 AD5 119 MADDR13 171 MDATA22
16
17
18 IDSEL 70 AD2 122 MADDR10 174 MDATA19
FRAME
DEVSEL
68 AD4 120 MADDR12 172 MDATA21
*
69 AD3 121 MADDR11 173 MDATA20
*
STOP
PERR
SERR
RST
*
*
*
*
107 TXD1 159 MDATA31
108 TXD2 160 MDATA30
109 TXD3 161 MDATA29
111 CRS 163 VSSO
19
20
21 VDDO 73 AD1 125 MADDR9 177 MDATA16
22 VSSO 74 AD0 126 MADDR8 178 MDATA15
23 AD23 75 CBE0 127 MADDR7 179 VSSO
24 AD22 76 MEMCLK 128 MADDR6 180 VDDO
25 AD21 77 VSSO 129 MADDR5 181 MDATA14
26 AD20 78 SYSCLK 130 MADDR4 182 MDATA13
27 AD19 79 VSSO 131 VSSO 183 VDDI
28 AD18 80 VDDO 132 VSSI 184 VSSI
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 14
TRDY
IRDY
*
*
71 VDDO 123 VSSO 175 MDATA18
72 VSSO 124 VDDO 176 MDATA17
PM3351 ELAN 1X100
DATA SHEET
PMC-970113 ISSUE 3 SINGLE PORT FAST ETHERNET SWITCH
Pin Signal Pin Signal Pin Signal Pin Signal
29 VSSO 81 CLK25 133 VDDI 185 MDATA12
30 VDDO 82 nc 134 VDDO 186 MDATA11
31 VSSI 83 MDIO 135 MADDR3 187 MDATA10
32 VDDI 84 VDDO 136 MADDR2 188 MDATA9
33 AD17 85 VSSO 137 MADDR1 189 MDATA8
34 AD16 86 VSSI 138 MADDR0 190 VSSO
35 CBE2 87 VDDI 139
36 VSSO 88 MDC 140
37
38
39
40 VDDO 92 RXD3 144
41 VSSO 93 RXD2 145 MRDY* 197 MDATA2
42 AD15 94 RXD1 146 MRD* 198 VSSO
43 AD14 95 RXD0 147
44 AD13 96 RX_DV 148
45 AD12 97 RX_CLK 149 VSSO 201 MDATA0
46 AD11 98 RX_ER 150 VDDO 202
47 VSSO 99 VDDO 151
48 VDDO 100 TX_CLK 152
49 AD10 101 TX_EN 153 MGWE* 205 nc
50 AD9 102 TXD0 154
REQ
GNT
INT
*
*
*
89 ERST* 141
90 VSSO 142 VSSO 194 MDATA5
91 VDDO 143 VDDO 195 MDATA4
MCS3
MCS2
MCS1
MCS0
MWR3
MWR2
MWR1
MWR0
MRAS
*
*
*
*
*
191 VDDO
192 MDATA7
193 MDATA6
196 MDATA3
199 VDDO
*
200 MDATA1
*
203 TST*
*
204 nc
*
206 nc
MINTR
*
51 AD8 103 BIAS5V 155 VSSO 207 VSSI
52 CBE1 104 VSSO 156 VDDO 208 VDDI
All VDD and VSS lines
•
be connected to the 3.3V supply and ground
must
respectively.
Standard decoupling practices should be followed for proper device operation.
•
The 4 pins marked as "nc" should be left as no-connects. They are intended
•
solely for factory use. Do not connect pins marked "nc" directly to either VDD or
VSS. If need be, the pins can be connected to either VDD or VSS through a
terminating resistor of value 1 k-ohm or greater.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 15
PM3351 ELAN 1X100
DATA SHEET
PMC-970113 ISSUE 3 SINGLE PORT FAST ETHERNET SWITCH
Functional Grouping
The following diagram shows the functional grouping of the PM3351 signal pins.
AD[31:0]
C/BE[3:0]*
PAR
FRAME*
TRDY*
IRDY*
STOP*
DEVSEL*
IDSEL
REQ*
GNT*
INT*
PERR*
SERR*
PCICLK
RST*
PM3351
PCI
ELAN 1x100
Local Memory Interface
ERST*
MD[31:0]
MA[17:0]
MCS[3:0]*
TXD[3:0]
TX_EN
TX_CLK
RXD[3:0]
RX_DV
MII
MRd*
MGWE*
MMWr[3:0]*
MRAS*
MRdy*
RX_CLK
RX_ER
CRS
COL
MDC
MDIO
SysClk
MemClk
Clk25
Mintr*
TST*
Pin description nomenclature:
• I input only
• O output only
• I/O bidirectional pin
• OD output only, open drain (requires external pull-up resistor to VDD).
The recommended pull-up resistance value for the open drain outputs is 2.7 k-ohm (this
is the recommended pull-up value suggested for PCI bus signals in the 5V signalling
environment).
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 16
PM3351 ELAN 1X100
DATA SHEET
PMC-970113 ISSUE 3 SINGLE PORT FAST ETHERNET SWITCH
PCI Expansion Bus Interface
Signal Name Size Type Description
AD[31:0] 32 I/O
CBE[3:0] 3 I/O
PAR 1 I/O
FRAME
DEVSEL
*
*
IRDY
*
TRDY
*
STOP
*
IDSEL 1 I
*
REQ
*
GNT
*
INT
*
PERR
*
SERR
PCICLK 1 I
1 I/O
1 I/O
1 I/O
1 I/O
1 I/O
1O
1I
1OD
1 I/O
1OD
Multiplexed PCI address/data bus, used by the PCI host or the PM3351 to
transfer addresses or data.
Command/Byte-Enable lines. These lines supply a command (during PCI
address phases) or byte enables (during data phases) for each bus transaction.
Address/data/command parity, supplies the even parity computed over the
AD[31:0] and CBE[3:0] lines during valid data phases; it is sampled (when the
PM3351 is acting as a target) or driven (when the PM3351 acts as an initiator)
one clock edge after the respective data phase.
Bus transaction delimiter (framing signal); a HIGH-to-LOW transition on this
signal indicates that a new transaction is beginning (with an address phase); a
LOW-to-HIGH transition indicates that the next valid data phase will end the
currently ongoing transaction.
Transaction Initiator (master) ready, used by the transaction initiator or bus
master to indicate that it is ready for a data transfer. A valid data phase ends
*
with data transfer when both IRDY
same clock edge.
Transaction Target ready, used by the transaction target or bus slave to indicate
that it is ready for a data transfer. A valid data phase ends with data transfer
*
when both IRDY
Transaction termination request, driven by the current target or slave to abort,
disconnect or retry the current transfer.
Device acknowledge: driven by a target to indicate to the initiator that the
address placed on the AD[31:0] lines (together with the command on the
CBE[3:0] lines) has been decoded and accepted as a valid reference to the
target's address space. Once asserted, it is held asserted until FRAME
deasserted; otherwise, it indicates (in conjunction with STOP
target-abort.
Device identification (slot) select. Assertion of IDSEL signals the PM3351 that it
is being selected for a configuration space access.
Bus request (to bus arbiter), asserted by the PM3351 to request control of the
PCI bus.
Bus grant (from bus arbiter); this indicates to the PM3351 that it has been
granted control of the PCI bus, and may begin driving the address/data and
control lines after the current transaction has ended (indicated by FRAME
*
and TRDY* all deasserted simultaneously).
IRDY
Interrupt request. This pin signals an interrupt request to the PCI host. The INT
pin should be tied to the INTA* line on the PCI bus.
Bus parity error signal, asserted by the PM3351 as a bus slave, or sampled by
the PM3351 as a bus master, to indicate a parity error on the AD[31:0] and
CBE[3:0] lines.
System error, used by the PM3351 to indicate to the PCI central resource that
there was a parity error on the AD[31:0] and CBE[3:0] lines during an address
phase.
PCI bus clock; supplies the PCI bus clock signal to the PM3351.
and TRDY* are sampled asserted on the same clock edge.
and TRDY* are sampled asserted on the
*
is
*
and TRDY*) a
*
,
*
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 17
PM3351 ELAN 1X100
DATA SHEET
PMC-970113 ISSUE 3 SINGLE PORT FAST ETHERNET SWITCH
RST
*
1I
PCI bus reset (system reset). Performs a hardware reset of the ELAN 1x100
and associated peripherals when asserted. The RST* input uses a Schmitt
trigger to accommodate slow rise and fall times, allowing a simple RC network
to be used to provide power-on reset capability.
MII Interface Pins
Signal Name Size Type Description
TXD[3:0] 4 O
TX_EN 1 O
TX_CLK 1 I
RX_DV 1 I
RXD[3:0] 4 I
RX_CLK 1 I
RX_ER 1 I
CRS 1 I
MII transmit data. TXD[3:0] is the nibble-wide MII transmit data bus. TXD[3:0]
transitions synchronously to the rising edge of TX_CLK. If TX_EN is asserted
then the TXD[3:0] bus has valid data which is to be accepted for transmission
by the PHY device.
MII transmit enable. Asserted by the PM3351 to indicate to the PHY device that
the TXD[3:0] bus has valid data. TX_EN is asserted with the first nibble of
preamble and remains continuously asserted throughout the frame. TX_EN is
negated prior to the first TX_CLK following the final nibble of the frame. TX_EN
is synchronous with respect to TX_CLK.
MII transmit clock. TX_CLK is a continuous clock that provides the timing
reference for the TX_EN and TXD[3:0] signals output from the PM3351.
TX_CLK is a nibble rate clock; an MII transceiver operating at 100Mbit/s must
provide a TX_CLK frequency of 25 Mhz.
For improved noise immunity this input buffer uses a Schmitt trigger.
MII receive data valid. RX_DV is an input that indicates that the PHY is
presenting recovered and decoded nibbles on the RXD[3:0] pins. In order for a
received frame to be accepted by the PM3351, RX_DV must be asserted prior
to or coincident to the first nibble of the Start of Frame Delimiter being driven on
RXD[3:0]; it must remain continuously asserted until after the rising edge of
RX_CLK when the last nibble fo the CRC is driven on RXD[3:0]. RX_DV is
synchronous with respect to RX_CLK.
MII receive data bus. RXD[3:0] is the nibble-wide MII receive data bus.
RXD[3:0] transitions synchronously to the rising edge of RX_CLK. The PM3351
samples RXD[3:0] on every rising edge of RX_CLK that RX_DV is asserted.
RXD[3:0] is ignored if RX_DV is deasserted.
MII receive clock. RX_CLK is a continuous clock that provides the timing
reference for the RX_DV, RX_ER, and RXD[3:0] signals input to the PM3351.
RX_CLK is a nibble rate clock; an MII transceiver operating at 100Mbit/s must
provide an RX_CLK frequency of 25 MHz during frame reception.
For improved noise immunity this input buffer uses a Schmitt trigger.
MII receive error. RX_ER is driven by the PHY for one or more RX_CLK periods
to indicate to the PM3351 that an error has occurred in the frame being
received. The PM3351 samples RX_ER on the rising edge of RX_CLK only if
RX_DV is asserted; all special code groups generated on RXD while RX_DV is
deasserted are ignored. RX_ER is synchronous with respect to RX_CLK.
MII carrier sense. CRS is an input that indicates that the physical media is nonidle, either because of transmit or receive activity. In full-duplex mode CRS is
ignored. The PHY is not required to have CRS transition synchronously to
either TX_CLK or RX_CLK.
The PM3351 samples CRS only on the rising edge of
the carrierSense variable in the MAC Deference process (see 802.3 spec
clauses 4.2.8 and 22.1.3.2).
TX_CLK
. It is used as
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 18
PM3351 ELAN 1X100
DATA SHEET
PMC-970113 ISSUE 3 SINGLE PORT FAST ETHERNET SWITCH
COL 8 I
MDIO 1 I/O
MDC 1 O
MII collision detect. COL is an input that indicates that a collision has occurred
on the physical media. In full-duplex mode COL is ignored. The PHY is not
required to have COL transition synchronously to either TX_CLK or RX_CLK.
The PM3351 only samples COL on the rising edge of TX_CLK.
MII management data input/output.MDIO is the bidirectional MII management
port data pin. MDIO is driven synchronously to MDCLK and is sampled on the
rising edge of MDCLK. When a management frame is not being transferred,
MDIO is not driven.
In order to implement the PHY detection feature via the MII mechanical
interface the MDIO pin should be externally pulled down to VSS through a 2.0kohm +/-5% resistor.
MII management data clock. MDC is an aperiodic signal that is used as a
timing reference for the MDIO pin. MDC is continuously driven by the PM3351;
it is asserted only during management frame activity. MDC uses the SYSCLK
input as a timing reference.
Local Memory Interface
Although the on-chip local memory interface is designed to operate with various
memory types the memories intended to be used with the PM3351 are -15ns SRAM
and -150ns PROM/EPROM/EEPROM. EDO DRAM is supported for management and
custom applications, but is not intended to be used for standard switching.
Signal Name Size Type Description
MDATA[31:0] 32 I/O
MADDR[17:0] 18 O
MCS[3:0]
MRAS
*
*
4O
1O
Memory data bus. MDATA[31:0] carries the data driven to the external local
memory by the PM3351 during local memory writes, and the data sent back to
the PM3351 by the memory devices during local memory reads.
In addition, configuration information is latched from the MDATA[31:0] lines
during ELAN 1x100 reset and loaded into an internal configuration register;
either pullup-pulldown resistors or tristate buffers (enabled by the RST
drive configuration data on to the MDATA[31:0] lines during reset.
All MDATA[31:0] pins have internal pullups.
Memory address bus; supplies a word-aligned address to the external memory
devices (i.e., address bits 19 through 2 of the 24-bit byte address generated by
the internal PM3351 logic), and thus select a single 32-bit word to be read or
written. Up to 1 MB of memory may be directly addressed in each bank using
these address lines.
Memory bank chip selects. The MCS[3:0]
banks (each bank has maximum depth of 4 megabyte). They are decoded
directly from the most significant 2 bits (bits 23 and 22) of the 24-bit physical
byte address generated by the internal PM3351 logic, and are synchronous to
MEMCLK.
DRAM Row Address Strobe output; supplies the Row Address Strobe (RAS)
signal to one or more external DRAM banks. It is asserted to latch the row
address (supplied on the MADDR lines) into the DRAM array, and allow the
column address to be output one cycle later.
NOTE- can be left as a no-connect output if not using DRAM.
*
input)
*
outputs select one of four memory
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 19
PM3351 ELAN 1X100
DATA SHEET
PMC-970113 ISSUE 3 SINGLE PORT FAST ETHERNET SWITCH
*
MRD
MWR[3:0]
MGWE* 1 O
MRDY
MINTR
*
*
*
1O
4O
1I
1I
Memory read enable. This output signals the external memory banks that a
read is being performed and data should be output on the MDATA[31:0] lines
from the specified address. The MRD* output may be tied to the OE* inputs of
standard memory devices.
Memory write enables, used by the PM3351 to enable the data presented on
individual byte lanes of MDATA[31:0] to be individually written to memory.
*
MWR[0]
and so on. The MWR[3:0]* outputs should be connected to the appropriate
byte write enables.
Gobal memory write enable. This signal is used to signal that a write access is
occurring, and should be connected to the WE* inputs of dual CAS
asynchronous DRAM devices.
NOTE- can be left as a no-connect output if not using DRAM
Memory ready input. If an external memory timing generator is used, it can be
connected to the MRDY* input to force the PM3351 to insert wait states into
memory accesses. If the MRDY
MADDR[15:0], MCS[3:0]
(as well as MDATA[31:0] for memory writes).The MRDY* input is only sampled
by the PM3351 when performing an SRAM-type access; it is ignored for all
other memory types.
This feature is not tested as part of the fuctional test program of the device.
Therefore, MRDY* must be tied low (to logic 0) to ensure correct operation.
Local interrupt input. The MINTR* may be used to provide an interrupt input to
the ELAN 1x100 in special applications. If the MINTR* input is not used it
should be tied HIGH.
For improved noise immunity this input buffer uses a Schmitt trigger.
corresponds to MDATA[7:0], MWR[1]* corresponds to MDATA[15:8],
*
line is deasserted, the PM3351 will hold the
*
, MRD* and MWR[3:0]* lines at their present values
Clock Inputs and Outputs
Signal Name Size Type Description
SYSCLK 1 I
MEMCLK 1 O
CLK25 1 O
50 MHz master device clock input, This should be driven by a 50 MHz
symmetrical clock source with a duty cycle between 40% and 60%. It is re-timed
and driven out on the MEMCLK line, and is also used in the internal device
logic.
For improved noise immunity this input buffer uses a Schmitt trigger.
50 MHz clock derived from SYSCLK; supplies the re-timed 50 MHz clock (input
on the SYSCLK pin) to external devices.
25 MHz clock output. The 50 MHz input clock is internally divided by two and
output as a symmetrical 25 MHz clock on the CLK25 output; this clock may be
used as a clock reference input to an external PHY device.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 20
PM3351 ELAN 1X100
DATA SHEET
PMC-970113 ISSUE 3 SINGLE PORT FAST ETHERNET SWITCH
Miscellanous Inputs and Outputs
Signal Name Size Type Description
BIAS5V 1 I
TST* 1 I
ERST* 1 OD
The 5 volt bias pin must be connected to 5.0 volts for the input and bi-directional
pins to be 5 volt tolerant. This pin may be tied to VDD provided the maximum
static signal level is below VDD + 0.3V.
During power-up, the voltage on the BIAS5V pin must be kept equal to or
greater then the voltage on all input pins to avoid damage to the device. In
addition, the voltage on the BIAS5V pin is to be kept greater than or equal to
the voltage on the VDD pins.
Test select signal used for production testing. It must be tied HIGH for correct
operation.
External reset output. The ERST* pin is driven low by the ELAN 1x100 to reset
other components in the system. This output is asserted for a pre-set duration
(10 milliseconds) upon the detection of a falling edge on the RST* input, or
when the ELAN 1x100 senses a condition requiring a system hardware reset. It
is an open-drain output, and should be pulled up using a 2.7k-ohm resistor. The
ERST* output may be tied directly to the RST* input to implement a debounce
function in pushbutton reset applications. (Note that the ERST* output should be
left unconnected in host-based applications where the ELAN 1x100 must not be
allowed to reset the host CPU.)
Notes on Pin Description:
1. All inputs and bi-directionals present minimal capacitive loading and operate at
TTL logic levels.
2. All digital outputs and bi-directionals have 2 mA D.C. drive capability.
3. Pins MDATA[31:0], MINTR*, TST*, GNT*, and RST* have internal pull-up
resistors.
4. The VSSI and VSSO ground pins are not internally connected together. Failure
to connect these pins externally may cause malfunction or damage the part.
5. The VDDI and VDDO power pins are not internally connected together. Failure
to connect these pins externally may cause malfunction or damage the part.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 21
PM3351 ELAN 1X100
DATA SHEET
PMC-970113 ISSUE 3 SINGLE PORT FAST ETHERNET SWITCH
DC CHARACTERISTICS
Absolute Maximum Ratings
Maximum rating are the worst case limits that the device can withstand without
sustaining permanent damage. They are not indicative of normal mode operation
conditions.
Parameter Symbol Value Units
Supply Voltage Vdd -0.3 to +7.0 Vdc
BIAS5V pin voltage
with respect to Vss
Input Voltage Vin V
Input Current Iin +/-10 mAdc
Static Discharge
Voltage
Latch-Up Current ±80 mA
Lead Temperature +220 °C
Storage Temperature Tst -45 to +125 °C
Junction Temperature Tj +125 °C
Vbias5V Minimum: VDD – 0.3V
Maximum: 5.5V
+0.3 Vdc
bias5v
±1000 V
Vdc
Recommended Operating Conditions
Parameter Symbol Value Unit
s
Min Nom Max
Supply Voltage Vdd +3.13 +3.30 +3.47 Vdc
BIAS5V Voltage Vbias5v +4.75 +5.0 +5.25 Vdc
Operating Ambient Temp. Ta 0 +70 °C
NOTE: the PM3351 has been characterized over the industrial temperature range (Ta =
-40°C to +85°C). All DC and AC parametrics met the limits presented in the following
tables. In addition the package thermal characteristics of the 208 pin PQFP package
and power consumption of the device are such that the device can be operated without
any forced air (i.e. still air) over the full commercial tem perature range; however, if
operating over the industrial temperature range (which has a maximum ambient
temperature of +85 °C) a minimum airflow of 100 linear feet per minute is required.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 22
PM3351 ELAN 1X100
DATA SHEET
PMC-970113 ISSUE 3 SINGLE PORT FAST ETHERNET SWITCH
D.C. Characteristics
DC characteristics are specified over recommended operating conditions (TA = 0°C to
+70°C, VDD = 3.3 V ±5%, V
Parameter Description TTL I/Os PCI I/Os Units
Vih Input High Voltage 2.0 Vdd+0.52.0 Vdd+0.5Vdc
Vil Input Low Voltage -0.5 0.8 -0.5 0.8 Vdc
Voh Output High Voltage (Vdd = min, IOH =
Vol Output Low Voltage (Vdd = min, IOL =
lil Input Low Leakage Current, Note 3 -10 10 -10 10 µA
lih Input High Leakage Current, Note 3 -10 10 -10 10 µA
lilpu Input Low Current (Pull ups, VIL =
lihpu Input High Current (Pull ups, VIH = Vdd,
lddop Supply Current, Vdd = 3.47 MHz,
Outputs Unloaded, SYSCLK = 50MHz
= 5.0V ±5%).
BIAS
-2 mA, Note 2)
-2 mA, Note 2)
GND, Note 4)
Note 4)
Min Max Min Max
2.4 Vdd 2.4 Vdd Vdc
00.400.4Vdc
+100 +20 µA
-10 +10 µA
450 mA
Notes on D.C. Characteristics:
1. Negative currents flow into the device (sinking), positive currents flow out of the
device (sourcing).
2. Output pin or bidirectional pin. Voh not measured on Open Drain outputs.
3. Input pin or bidirectional pin without internal pull-up resistor.
4. Input pin or bidirectional pin with internal pull-up resistor.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 23
PM3351 ELAN 1X100
DATA SHEET
PMC-970113 ISSUE 3 SINGLE PORT FAST ETHERNET SWITCH
AC CHARACTERISTICS
AC characteristics are specified over recommended operating conditions (TA = 0°C to
+70°C, VDD = 3.3 V ±5%, V
= 5.0V ±5%).
BIAS
The PM3351 only supports a 5V signalling environment.
Notes on Input Timing:
1. When a set-up time is specified between an input and a clock, the set-up time is
the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point
of the clock.
2. When a hold time is specified between an input and a clock, the hold time is the
time in nanoseconds from the 1.4 Volt point of the clock to the 1.4 Volt point of
the input.
Notes on Output Timing:
1. Output propagation delay time is the time in nanoseconds from the 1.4 Volt
point of the reference signal to the 1.4 Volt point of the output.
2. Maximum and minimum output propagation delays are specified with a 50 pF
load on the outputs, unless otherwise noted.
3. Output tristate delay is the time in nanoseconds from the 1.4 Volt point of the
reference signal to ±300mV of the termination voltage on the output. The test
load is 50Ω to 1.4V in parallel with 10 pf to GND.
Notes on Typical Values
AC parameters shown as Typical in the following tables are tested for functionality
under typical conditions. No guarantees are implied for maximum or minumum
performance.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 24
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