PMC Pm29F002 Technical data

PMC

FEATURES

ADVANCE INFORMATION

Pm29F002

2 Megabit (256K X 8) 5.0 Volt-only CMOS Flash Memory

Single Power Supply Operation

•

- 5.0 V ± 10% Read/Program/Erase

• High Performance Read

- 55/70/90 ns access time

• Cost Effective Block Architecture

- One 16 Kbytes top or bottom Boot Block with
software lockout

- Two 8 Kbytes Parameter Blocks

- One 96 Kbytes Main Block

- One 128 Kbytes Main Block

• Automatic Erase and Program

- Typical 15 µs/byte programming

- Typical 40 ms block or chip erase

• Hardware Data Protection

• Data# Polling and Toggle Bit Features

• Low Power Consumption

- Typical 10 mA active read current

- Typical 40 mA program/erase current

- Typical <0.1

• High Product Endurance

- Guarantee 10,000 program/erase cycles

- Typical 50,000 program/erase cycles

- Minimum 10 years data retention

• Industrial Standard Pin-out and Packaging

- 32-pin Plastic DIP

- 32-pin PLCC

• Manufactured on 0.30 µm process

- Fully compatible with previous 0.35 µm version

µ

A CMOS standby current

GENERAL DESCRIPTION

The Pm29F002 is a 2 Megabit, 5.0 Volt-only Flash Memory organized as 262,144 bytes of 8 bits each.
This device is designed to use a 5.0 Volt power supply to perform in-system programming, 12.0 Volt V
supply for program and erase operation is not required. The device can be programmed in standard EPROM
programmers as well.

The 2 Megabit memory array is divided into five blocks of one 16 Kbytes, two 8 Kbytes, one 96 Kbytes, and
one 128 Kbytes for BIOS and parameters storage. The five blocks allow users to flexibly make chip erase or
block erase operation flexible. The block erase feature allows a particular block to be erased and reprogrammed
without affecting the data in other blocks. After the device performed chip erase or block erase operation, it can
be reprogrammed on a byte-by-byte basis.

The device has a standard microprocessor interface as well as JEDEC single-power-supply Flash compatible
pin-out and command set. The program operation of Pm29F002 is executed by issuing the program command
code into command register. The internal control logic automatically handles the programming voltage ramp-up
and timing. The erase operation of Pm29F002 is executed by issuing the chip erase or block erase command
code into command register. The internal control logic automatically handles the erase voltage ramp-up and
timing. The preprogramming on the array which has not been programmed is not required before the erase
operation. The device also features Data# Polling and Toggle Bit function, the end of program or erase operation
can be detected by Data# Polling of I/O7 or Toggle Bit of I/O6.

The device has an optional 16 Kbytes top or bottom boot block with a software lockout feature for data
security. The boot block can be used to store user secure code. When the lockout feature is enabled, the boot
block is permanently protected from being reprogrammed.

The Pm29F002 is manufactured on PMC’s 0.30 µm advanced nonvolatile technology, P-FLASH™. The
device is packaged in a 32-pin DIP and PLCC with access time of 55, 70 and 90 ns.

power

PP

Programmable Microelectronics Corp. Issue Date: March, 2001 Rev:1.0

1

PMC

CONNECTION DIAGRAMS

NC

A16
A15
A12

A7
A6

A5
A4
A3

A2
A1

A0
I/O0
I/O1

I/O2

GND

1
2
3
4
5

6
7

8
9

10
11

12
13
14
15

16

32
31
30
29
28
27
26
25
24
23
22
21
20

19
18

17

CC

V

WE#
A17
A14
A13

A8
A9
A11
OE#
A10
CE#
I/O7
I/O6
I/O5
I/O4
I/O3

A7
A6

A5
A4

A3
A2
A1

A0

I/O0

5
6

7
8

9
10

11
12

13

14

A12

15

A15

Pm29F002

CC

A16

V

WE#

20

A17

29
28

27
26
25
24
23
22
21

A14
A13

A8
A9
A11

OE#
A10

CE#
I/O7

NC

1234323130

18

1716

19

LOGIC SYMBOL

18

A0-A17

CE#
OE#
WE#

32-Pin PDIP

I/O0-I/O7

I/O1

I/O2

GND

I/O3

I/O4

I/O5

I/O6

32-Pin PLCC

8

Programmable Microelectronics Corp.

Issue Date: March, 2001 Rev: 1.0

2

PMC

PRODUCT ORDERING INFORMATION

Pm29F002 T -55 P C

Pm29F002

Temperature Range

C = Commercial (0°C to +70°C)

Package Type

P = 32-pin Plastic DIP (32P)
J = 32-pin Plastic J-Leaded Chip Carrier (32J)

Speed Option
Boot Block Location

T = Top Boot Block
B = Bottom Boot Block

PMC Device Number

t

rebmuNtraP

CJ55-T200F92mP

CP55-T200F92mP
CJ55-B200F92mP

CP55-B200F92mP

CJ07-T200F92mP

CP07-T200F92mP
CJ07-B200F92mP

CP07-B200F92mP

CJ09-T200F92mP

CP09-T200F92mP
CJ09-B200F92mP

CP09-B200F92mP

CCA

)sn(

55

07

09

tooB

noitacoL

poT

mottoB

poT

mottoB

poT

mottoB

egakcaP

J23

P23

J23

P23

J23

P23

J23

P23

J23

P23

J23

P23

erutarepmeT

egnaR

laicremmoC

)C°07+otC°0(

laicremmoC

)C°07+otC°0(

laicremmoC

)C°07+otC°0(

Note: Valid combination list for the Pm29F002. Please consult the local PMC sales office, sales representa­tives or distributors to confirm the availability of specific valid combination and delivery schedule.

Programmable Microelectronics Corp.

Issue Date: March, 2001 Rev: 1.0

3

PMC

PIN DESCRIPTIONS

LOBMYSEPYTNOITPIRCSED

Pm29F002

71A-0ATUPNI

#ECTUPNI

#EWTUPNI

#EOTUPNI

7O/I-0O/I

V

CC

DNGdnuorG

.retsigerdnammocdnasesserddayromemroF:stupnIsserddA

.elcycetirwagniruddehctalyllanretnierasesserddA

seirtiucriclanretnis'ecivedehtsetavitcawol#EC:elbanEpihC

dnaecivedehtstcelesedhgih#EC.noitarepoecivedrof

.noitpmusnocrewopehtecuderotedomybdnatsotnisehctiws

.elbatscitsiretcarahcCDotreferesaelP

si#EW.noitarepoetirwrofecivedehtetavitcA:elbanEetirW

.wolevitca

daeragnirudsreffubatads'ecivedehtlortnoC:elbanEtuptuO

.wolevitcasi#EO.elcyc

,noitarepomargorpgnirudatadyarrastupnI:stuptuO/stupnIataD

gniruddehctalyllanretnisiataD.evitcaera#EWdna#ECnehw

/TUPNI

TUPTUO

.delbasiderastuptuo

ylppuSrewoPeciveD

,evitcaera#EOdna#ECnehW.selcycmargorpdnaetirweht

.edocecivedroedocrerutcafunam,atadyarrasdnestuptuoeht

ehtrodetcelesedsipihcehtnehwetats-irtottaolfsnipatadehT

CNnoitcennoCoN

Programmable Microelectronics Corp.

Issue Date: March, 2001 Rev: 1.0

4

PMC

BLOCK DIAGRAM

Pm29F002

ERASE/PROGRAM

VOLTAGE

GENERATOR

HIGH VOLTAGE

SWITCH

WE#

CE#
OE#

COMMAND
REGISTER

A0-A17

LATCH

ADDRESS

DEVICE OPERATION

READ OPERATION

The access of Pm29F002 is similar as that of
EPROM. To obtain data at the outputs, three control
functions must be satisfied:

• CE# is the chip enable and should be pulled low

( VIL ).

• OE# is the output enable and should be pulled

low ( VIL).

• WE# is the write enable and should remains high

( V

).

IH

BOOT BLOCK LOCKOUT

The device has a software lockout feature to pre­vent the data in the boot block from being erased or
reprogrammed. The boot block can be located at the
top or bottom of the address location. The block size is
16 Kbytes. Once the lockout feature is enable, the boot
block can not be erased or reprogrammed. Data in the
main memory block can still be updated through the
regular programming method. The boot block lockout
feature can be turned on by issuing a six-bus-cycle com­mand sequence. Please refer to Table 4 and Chart 4.

I/O0-I/O7

I/O BUFFERS

CE,OE LOGIC

Y-DECODER

X-DECODER

BOOT BLOCK LOCKOUT DETECTION

The state of the Boot Block lockout can be de­tected by software product identification entry. After
entry, selects Boot Block address with A0 = “0” and A1
= “1” and then read I/O0. A data of “0” means the lock­out feature is disabled and the Boot Block can be erased
or programmed. A data of “1” means the lockout fea­ture is enabled and the Boot Block is protected. Prod­uct identification exit must be executed before the de­vice returns to read mode.

PRODUCT IDENTIFICATION

The product identification mode can be used to identify
the device and the manufacturer by hardware or soft­ware operation. The hardware operation mode is acti­vated by applying a 12.0 Volt on A9 pin, typically used
by an external programmer to select the right program­ming algorithm for the device. For detail, please see
Bus Operation Modes in Table 3. The software opera­tion mode is activated by three-bus-cycle command.
Please see Software Command Definition in Table 4.

DATA

LATCH

Y-GATING

MEMORY

SENSE

AMP

ARRAY

Programmable Microelectronics Corp.

Issue Date: March, 2001 Rev: 1.0

5

PMC

DEVICE OPERATION (CONTINUED)

Pm29F002

BYTE PROGRAMMING

The programming is a four-bus-cycle operation
and the data is programmed into the device (to a logical
“0”) on a byte-by-byte basis. Please see Software Com­mand Definition in Table 4. A program operation is ac­tivated by writing the three-byte command sequence
followed by one byte of data into the device. The ad­dress are latched on the falling edge of WE# or CE#
whichever occurs later, and the data is latched on the
rising edge of WE# or CE#, whichever occurs first. The
internal control logic automatically handles the internal
programming voltages and timing.

A data “0” can not be programmed back to a “1”.
Only erase operation can convert “0”s to “1”s. The Data#
Polling of I/O7 or Toggle Bit of I/O6 can be used to de­tect when the programming operation is completed.

CHIP ERASE

The entire memory array can be erased through
a chip erase operation. Pre-programs the device is not
required prior to chip erase operation. Chip erase starts
after a six-bus-cycle chip erase command sequence.
All commands will be ignored once the chip erase
operation has started. The device will return back to
read mode after the completion of chip erase. When
the boot block lockout feature is enabled, the boot block
will not be erased during a chip erase operation. Only
the parameter blocks and the main blocks will be erased.

BLOCK ERASE

The memory array is organized into five blocks:
one 16 Kbytes boot block, two 8 Kbytes parameter
blocks, one 96 Kbytes and one 128 Kbytes main blocks.
A block erase operation allows to erase any individual
block. Pre-programs the block is not required prior to
block erase operation. If the boot block lockout feature
is enable, the block erase command attempts to erase
the boot block will be ignored. The block erase com­mand is similar to chip erase command except for the
last bus cycle command where the block addresses
are used to select the block for erasure and the input
data to the I/Os is 30h. Each block erase operation
erases one block. Block erase and chip erase are both
internally controlled and timed.

I/O7 DATA# POLLING

The Pm29F002 provides Data# Polling feature to
indicate the process or the completion of a program or
erase cycle. During a program cycle, an attempt to read
the device will result in the complement of the last loaded
data on I/O7. Once the program cycle is completed,
the true data of the last loaded data is valid on all out­puts. During a block or chip erase operation, an attempt
to read the device will result a “0” on I/O7. After the
erase cycle is completed, an attempt to read the device
will result a “1” on I/O7.

I/O6 TOGGLE BIT

The Pm29F002 also provides Toggle Bit feature
as a method to detect the process or the end of a pro­gram or erase cycle. During a program or erase opera­tion, an attempt to read data from the device will result
in I/O6 toggling between “1” and “0”. When the program
or erase operation is complete, I/O6 will stop toggling
and valid data will be read. Toggle bit may be accessed
at any time during a program or erase cycle.

HARDWARE DATA PROTECTION

Hardware data protection protects the device from
unintentional erase or program operation. It is performed
in the following ways: (a) VCC sense: if VCC is below 3.8
V (typical), the program function is inhibited. (b) Write
inhibit: holding any of the signal OE# low, CE# high or
WE# high inhibits a write cycle. (c) Noise filter: pulses
of less than 20 ns (typical) on the WE# or CE# inputs
will not initiate a write cycle.

Programmable Microelectronics Corp.

Issue Date: March, 2001 Rev: 1.0

6

PMC

MEMORY BLOCKS AND ADDRESSES

Table 1. Top Boot Block Address Table (Pm29F002T)

kcolBeziSkcolBegnaRsserddA

2kcolBniaMsetybK821hFFFF1-h00000

1kcolBniaMsetybK69hFFF73-h00002

2kcolBretemaraPsetybK8hFFF93-h00083

1kcolBretemaraPsetybK8hFFFB3-h000A3

kcolBtooBsetybK61hFFFF3-h000C3

Table 2. Bottom Boot Block Address Table ( Pm29F002B)

kcolBeziSkcolBegnaRsserddA

Pm29F002

kcolBtooBsetybK61hFFF30-h00000

1kcolBretemaraPsetybK8hFFF50-h00040

2kcolBretemaraPsetybK8hFFF70-h00060

1kcolBniaMsetybK69hFFFF1-h00080

2kcolBniaMsetybK821hFFFF3-h00002

OPERATING MODES

Table 3. Bus Operation Modes

edoM#EC#EO#EWSSERDDAO/I

daeRV
etirWV

ybdnatSV

LI

LI

HI

elbasiDtuptuOXV

noitacifitnedItcudorP

erawdraH

V

LI

Notes:

1. X can be VIL, VIH or addresses.

2. VH = 12.0 V ± 0.5 V.

Programmable Microelectronics Corp.

V

LI

V

HI

XX X ZhgiH

HI

V

LI

V

HI

V

LI

)1(

X

XD

XX ZhgiH

=71A-2AV=9A,X

V=1A

V

HI

LI

V=1A

LI

V=0A,

LI

V=0A,

HI

)2(

,

H

)2(

V=9A,X=71A-2A

,

H

3. Manufacturer Code: 9Dh;

Device Code: 1Dh (top boot), 2Dh (bottom boot)

Issue Date: March, 2001 Rev: 1.0

7

D

TUO

NI

)3(

edoCrerutcafunaM

)3(

edoCeciveD