PLX Technology PEX 8615A, PEX 8619BA Hardware Reference Manual

PEX 8615BA Base Board RDK

Hardware Reference Manual

Version 1.0

April 2009

Website: www.plxtech.com

Technical Support: www.plxtech.com/support

April 15, 2009

variations to this publication, known as errata. PLX assumes no liability whatsoever, including infri ngement of any patent or copyright, for sale and use of PLX products.

PLX Technology and the PLX logo are registered trademarks of PLX Technology, Inc. Other brands and names are the property of their respective owners. Document Number: PEX8615BA-Base Board RDK-HRM-1.0 April 15, 2009

PREFACE

NOTICE

This document contains PLX Confidential and Proprietary information. The contents of this document may not be copied nor duplicated in any form, in whole or in part, without prior written consent from PLX Technology, Inc.

PLX provides the information and data included in this document for your benefit, but it is not possible to entirely verify and test all the information, in all circumstances, particularly information relating to non-PLX manufactured products. PLX makes neither warranty nor representation relating to the quality, content, or adequacy of this information. The information in this document is subject to change without notice. Although every effort has been made to ensure the accuracy of this manual, PLX shall not be liable for any errors, incidental, or consequential damages in connection with the furnishing, performance, or use of this manual or examples herein. PLX assumes no responsibility for damage or loss resulting from the use of this manual, for loss or claims by third parties, which may arise through the use of the RDK, or for any damage or loss caused by deletion of data as a result of malfunction or repair.

ABOUT THIS MANUAL

This document describes the PLX PEX 8615BA-Base Board RDK, a Rapid Development Kit, from a hardware perspective. It contains a description of all major functional circuit blocks on the board and also is a reference for the creation of software for this product. This manual also includes complete schematics and bill of materials.

REVISION HISTORY

Date Version Comments

April 2009 1.0 Initial Release

CONTENTS

NOTICE ......................................................................................................................................................................... i

ABOUT THIS MANUAL ..................................................................................................................................................... i

REVISION HISTORY .................................................................................................................................................... i

1. General Information ........................................................................................................................................... 1

1.1 PEX 8615 Features ................................................................................................................................... 1

1.2 PEX 8615BA-BB RDK Features ................................................................................................................ 3

2. System Architecture ........................................................................................................................................... 4

3. Hardware Architecture ....................................................................................................................................... 4

3.1 PEX 8615 ................................................................................................................................................... 5

3.2 PCI Express Interfaces .............................................................................................................................. 5

3.2.1 RDK Configuration Modules and Their Receptacles ......................................................................... 5

3.2.2 PCI Express Lane 0 to Lane 3 ........................................................................................................... 5

3.2.3 PCI Express Lane 4 to Lane 7 ........................................................................................................... 6

3.2.4 PCI Express Lane 8 to Lane 11 ......................................................................................................... 7

3.3 Reference Clock Circuits ........................................................................................................................... 8

3.4 Reset Circuits ............................................................................................................................................ 8

3.5 Serial Hot-Plug (SHP) Controller Circuits .................................................................................................. 9

3.6 Serial EEPROM ....................................................................................................................................... 10

3.7 I2C Interface ............................................................................................................................................. 10

3.8 Power Distribution Circuits ....................................................................................................................... 11

3.9 FPGA Interface ........................................................................................................................................ 12

3.10 LED and 7-Segment Displays ................................................................................................................. 13

3.10.1 LED Indicators ................................................................................................................................. 13

3.10.2 7-Segment Displays ......................................................................................................................... 14

3.11 GPIO Pins ................................................................................................................................................ 15

3.12 Reserved Pins ......................................................................................................................................... 15

4. On-Board Connectors, Switches, and Jumpers ............................................................................................... 16

4.1 DIP Switches ........................................................................................................................................... 16

4.1.1 Dip Switch Group 1 .......................................................................................................................... 16

4.1.2 Dip Switch Group 2 .......................................................................................................................... 17

4.1.3 Dip Switch Group 3 .......................................................................................................................... 19

4.2 Push-Button Switches .............................................................................................................................. 20

4.2.1 Manual Reset# (S1) ......................................................................................................................... 20

4.2.2 FPGA Manual Reset# (S2) .............................................................................................................. 20

4.2.3 Serial Hot-Plug Controller Attention Button (S3) ............................................................................. 21

4.3 Connectors and Headers ......................................................................................................................... 21

4.3.1 ATX Peripheral Power Connectors (J1-J4 & J7-J8) ........................................................................ 21

4.3.2 x4 PCI Express External Cable Connectors (J5 & J6) .................................................................... 21

4.3.3 ATX Main Power Connector (J9) ..................................................................................................... 22

4.3.4 ATX +12V Power Connector(J10) ................................................................................................... 22

4.3.5 Xilinx JTAG Connector (J12) ........................................................................................................... 22

4.3.6 Xilinx Mode Setting Header (J13) .................................................................................................... 23

4.3.7 PEX 8615 JTAG Header (JP3) ........................................................................................................ 23

4.3.8 SMBus Header (JP5) ....................................................................................................................... 23

4.3.9 PCI Express x8 Midbus Probe Footprint (JP6) ................................................................................ 23

4.3.10 PEX 8615 I2C Port (JP8) ................................................................................................................. 24

4.3.11 Debug Signal Header (JP9 & JP11) ................................................................................................ 24

4.3.12 Debug Input Header (JP10) ............................................................................................................. 26

4.3.13 Reference Clock Header (JP100) .................................................................................................... 26

5. RDK Port Configurations .................................................................................................................................. 27

6. Bill of Materials/ Schematics ............................................................................................................................ 30

FIGURES

Figure 1. PEX 8615BA Base Board RDK Front View ................................................................................................ 2

Figure 2. Connecting The RDK to a PC with x1 or x4 link ......................................................................................... 4

Figure 3. Lanes 0-3 Hardware Connections on the RDK .......................................................................................... 6

Figure 4. Lanes 4-7 Hardware Connections on the RDK .......................................................................................... 7

Figure 5. Lanes 8-11 Hardware Connections on the RDK ........................................................................................ 7

Figure 6. RDK Reference Clock Circuits ................................................................................................................... 8

Figure 7. RDK Reset Circuits .................................................................................................................................... 9

Figure 8. SERIAL HOT-PLUG Circuits .................................................................................................................... 10

Figure 9. RDK ATX Power Connectors ................................................................................................................... 11

Figure 10. RDK Power Distribution Circuits ............................................................................................................ 12

Figure 11. FPGA Interface on RDK ......................................................................................................................... 13

Figure 12. RDK Dip Switch Groups ......................................................................................................................... 16

Figure 13. Group1 of Switches ................................................................................................................................ 16

Figure 14. Group 2 of Dipswitches .......................................................................................................................... 17

Figure 15. Group 3 of Dip Switches ......................................................................................................................... 19

Figure 16. x1 upstream and 11x1 downstream (PCFG=0000) ............................................................................... 27

Figure 17. x4 upstream 8x1 downstream (PCFG=0001) ........................................................................................ 28

Figure 18. x4 upstream, 1x4 and 4x1 downstream (PCFG=0010) .......................................................................... 29

TABLES

Table 1. Port Configurations Supported by the RDK ................................................................................................. 5

Table 2. RDK LED Indicator descriptions ................................................................................................................ 13

Table 3. RDK 7-Segment Display Functions ........................................................................................................... 14

Table 4. Strap_Reserved Pin Connections ............................................................................................................. 15

Table 5. Functional Description of Group 1 Dip Switches ....................................................................................... 17

Table 6. Functional Description of Group 2 Dip Switches ....................................................................................... 18

Table 7. Port Configurations use Dipswitch SW2 .................................................................................................... 19

Table 8. Functional Descriptions of SW3, SW6, SW13-SW14 ............................................................................... 20

Table 9. Signal Names of J1-J4 & J7-J8 ................................................................................................................. 21

Table 10. Signal Names of J5 and J6 ...................................................................................................................... 21

Table 11. Signal Names of J9 ................................................................................................................................. 22

Table 12. Signal Names of J10 ............................................................................................................................... 22

Table 13. Signal Names of J12 ............................................................................................................................... 22

Table 14. Signal Names of J13 ............................................................................................................................... 23

Table 15. Pin assignment of JP3 ............................................................................................................................. 23

Table 16. Signal Names of JP5 ............................................................................................................................... 23

Table 17. Signal Names of JP6 ............................................................................................................................... 23

Table 18. Pin assignment of JP8 ............................................................................................................................. 24

Table 19. Pin assignment of JP9 & JP11 ................................................................................................................ 24

Table 20. Pin assignment of JP10 ........................................................................................................................... 26

Table 21. Pin assignment of JP100 ......................................................................................................................... 26

1. General Information

The PLX PEX 8615BA Base Board RDK is a Rapid Development Kit based on the PEX 8615, a 12-lane, 12-port PCI Express switch based in the PCI Express Specification rev 2.0 with SerDes capable of running at 5 GT/s. The PEX 8615BA Base Board RDK provides a complete hardware and software development platform that facilitates getting designs up and running quickly, lowering risk and reducing time-to-market. This RDK consists a base board containing three hardware configuration Modules, a PCI Express cable adapter board that plugs into the host system, and up to two x4 PCI Express cables that used to connect the RDK to the cable adapter. This manual primarily focuses on the PEX 8615BA Base Board RDK, and its use with other parts to demonstrate the various functions of PEX 8615 chip. Figure 1 provides a top view (component side) of the PEX 8615BA Base Board RDK.

1.1 PEX 8615 Features

• 12-lane, 12-port PCI Express Gen 2 switch with integrated on-chip SerDes

• 120 GT/s aggregate bandwidth (5.0GT/s/Lane x 16 Lanes x 2 (full duplex))

• 19mm

• Typical Power – 1.7W

• Cut-Thru packet latency of less than 160ns

• Low power SerDes (under 90mW per lane)

• Fully non-blocking switch architecture

• Flexible port configuration

• Flexible device configuration

• Maximum packet payload size of 2,048 bytes

• Designate any Port as the Upstream Port (Port 0 is recommended)

• Dynamic Buffer Pool Architecture

• Read Pacing (allows user to throttle Read requests from Downstream Ports to allow for more efficient

• Dual-Cast (enhances performance by sending date from one ingress port to two egress ports)

• Integrated Direct Memory Access (DMA) engine

• Dynamic speed (2.5 GT/s or 5.0 GT/s) negotiation

• Dynamic link-width negotiation (automatically negotiates down to optimal link-width based on traffic

• Lane and polarity reversal

• Non-Transparent Bridging support

• Conventional PCI-compatible Link Power Management states – L0, L0s, L1, L2/L3 Ready, and L3 (with

• Conventional PCI-compatible Device Power Management states – D0 and D3hot

• Active State Power Management

• Spread-Spectrum Clock Isolation

• Quality of Service (QoS)

• Reliability, Availability, Serviceability (RAS) features

2

324-ball Plastic Ball Grid Array (PBGA) package

o 12 flexible and configurable ports (x1, or x4 ), x2 is also supported

2

o Configurable via serial EEPROM, I

C, hardware strapping, or by the host

performance)

density)

o Enables Dual-Host, Host-Failover applications

Vaux not supported)

o Dual-clock Domain o Two Virtual Channels (VC0 and VC1) and Eight Traffic classes (TC)

o Weighted Round-Robin Port and Virtual Channel arbitration

2

o All ports are Hot-Plug capable through I

C (Serial Hot-Plug Controller on every port)

o Advanced Error Reporting capability o Performance Monitoring

 Per-Port Payload and Header Counters  Per-traffic type (write, Read, Completion) Counters

o JTAG AC/DC boundary scan o 12 Lane status balls (PEX_LANE_GOOD[11:0]#)

o 32 GPIO balls (GPIO[31:0]

ON

SW5

BJ9

GND

BJ10

2.5VCC

SW7

SW4

SLOT1

ON

SW3

ON

SW2

SW6

Port #

D16D20D24D13D17D21D25D14D18D2 2D26

ON

SW14ONSW13

Link Width

J5

J6

PEX8615-BB RDK

Port #

cable

4x PCIE

connector

D12

cable

4x PCIE

connector

Port #

SLOT2

D6

1.0VCC_A

SLOT3

Link Width

0108

Module

Configuration

Link Width

Module

0108

Configuration

2.5VCC_A

Module

0108

SLOT4

D4

D8

D10

U100

PEX

8615

JP100

JP6

3

4

JP8

I2C Port

1

2

JP10

Mictor

Connectors

JP9 JP10

1.0VCC_A

JP3

1

JTAG Port

1

Footprint

Midbus Probe

1.0VCC

BJ6

BJ5

GND

Header

Debug Input

U115

Xilinx

FPGA

BJ3

BJ4

GND

Port #

S1

1.0VCC

Manual Reset

D7

D5

2.5VCC

Port

J12

FPGA JTAG

1

S2

FPGA Reset

3

4

JP5

I2C Port for

1

2

Thermal Sensor

J13

1

FPGA Mode

Link Width

SLOT5

SLOT6

SLOT7

SLOT8

SLOT9

SLOT10

SLOT11

SLOT12

D15D27 D23 D19

SLOT13

SLOT14

SLOT15

SW10

J1J7J3

J8

1

J9

J4

J2

J10

D9 3.3VCC1

D28 PWRLED#_S

D3 3.3VCC

D31 ATNLED#_S

D1 12V_A

D2 5V_A

D32 Interlock_S

D29 12V_SLT_8_HP

D30 3.3VCC_SLT_8_HP

24

User debug

SW11 S2

ON ONON

SW15

Figure 1. PEX 8615BA Base Board RDK Front View

• INTA# (PEX_INTA#) and FATAL ERROR (FATAL_ERR#) (Conventional PCI SERR# equivalent) ball support

• Compliant to the following specifications:

o PCI Local Bus Specification, Revision 3.0 (PCI r3.0) o PCI Bus Power Management Interface Specification, Revision 1.2 (PCI Power Mgmt. r1.2) o PCI to PCI Bridge Architecture Specification, Revision 1.2 (PCI-to-PCI Bridge r1.2) o PCI Express Base Specification, Revision 1.1 (PCI Express Base r1.1) o PCI Express Base Specification, Revision 2.0 (PCI Express Base r2.0) o IEEE Standard 1149.1-1990, IEEE Standard Test Access Port and Boundary-Scan Architecture,

1990 (IEEE Standard 1149.1-1990)

o IEEE Standard 1149.1a-1993, IEEE Standard Test Access Port and Boundary-Scan Architecture o IEEE Standard 1149.1-1994, Specifications for Vendor-Specific Extensions o IEEE Standard 1149.6-2003, IEEE Standard Test Access Port and Boundary-Scan Architecture

Extensions (IEEE Standard 1149.6-2003)

2

o The I

C-Bus Specification, Version 2.1 (I2C Bus v2.1)

1.2 PEX 8615BA-BB RDK Features

• PLX PEX 8615 PCI Express switch in a 324-ball Plastic BGA package

• Based on PCI Express Card Electromechanical (CEM) Specification 2.0 and PCI Express External

Cabling Specification 1.0

• Supports up to 3 different port configurations with 4x PCI Express cable connection(s) to the upstream PC

• Non-Transparent Bridging support

• One x8 Gen 2 Midbus probe footprint for upper 4 lanes of PCI Express signal probing for the chip

• PCI Express RefClk Circuits supports Spread-Spectrum Clock Isolation

• Serial Hot-Plug circuits on one PCI Express card edge connector

• In system programmable Serial EEPROM (2.5V)

• A standard 2x2 header provides the I

• DIP switches for port configuration, upstream port or NT port select and I

• Manual push-button PERST# capability

• Up to sixteen dual color LEDs for visual inspection of link speed and status

• 7-Segment displays for port numbers and link width

• Up to 3-digit display for junction temperature of PEX 8615

• Voltage level monitoring circuit for 1.0V and 2.5V power to the PEX 8615

2

C interface to an I2C master

2

C address settings

2. System Architecture

The PEX 8615BA-Base Board RDK is a 21” x 10” bench top board for silicon evaluation and design reference for the PEX 8615 PCI Express Gen 2 switch. This RDK consists of three main hardware components: the base board, the PCI Express External Cable Adapter and PCI Express Cable assembly. Figure 1 represents the placement of major component blocks on the RDK base board. Figure 2 and Figure 3 provide diagrams of the RDK being used in a PC. The RDK provides up to 11 PCI Express slots for add-in cards and visual indicators for port, link status and speed information. The RDK is designed to be powered up with an ATX power supply.

Figure 2. Connecting The RDK to a PC with x1 or x4 link

3. Hardware Architecture

The PEX 8615BA Base Board RDK is de based on the PCI Express CEM 2.0 Specification. The RDK offers PCI Express interfaces to 11 PCI Express Edge Card Connectors, two x4 PCI Express External cable connectors, and three configuration modules. The RDK is designed to support 3 different port configurations (see Table 1 for details) and to connect to its upstrea PC through its PCI Express Cable Connectors. The RDK relies on the PC connected to its PCI Express Cable Connector J5 to obtain it primary PCI Express reference clock and reset to support the RDK normal functions. Also, the RDK provides visual indications for power, link speed, port status, port number, and link width.

signed around the PEX 8615, a 12-port, 12-lane Gen 2 switch, and

m

3.1 PEX 8615

The PEX 8615 is a 12-lane, 12-port PCI Express Gen 2 (5.0GT/s) switch. It is in 19mmx19mm package. It supports 4 different types of port configurations with any port can be upstream or NT port. It supports SpreadSpectrum Clocking Isolation function. It also provides 12 lane status drivers and 32 GPIOs.

3.2 PCI Express Interfaces

The RDK provides 11 PCI Express connectors and one x4 PCI Express External Cable Connectors for PCI Express connections of PEX 8615. The RDK supports 3 different port configurations of PEX 8615. With the correct port configuration STRAP pin settings and the right Configuration Modules are installed, the RDK can demonstrate up to 12 ports and a up to x4 link upstream connection PCI Express Gen 2 switch. Table 1 shows all port configurations supported by the RDK while sections 3.2.1 to 3.2.5 describe the Configuration Modules and hardware configurations of grouped of each four PCI Express lanes in details.

Table 1. Port Configurations Supported by the RDK

Strap pin Settings

STRAP_PORTCFG[3:0]

0000 x1x1x1x1x1x1x1x1x1x1x1x1 0108 at U74;0108 at U75; and 0108 at U76 0001 x4x1x1x1x1x1x1x1x1 0107 at U74;0108 at U75; and 0108 at U76 0010 x4x4x1x1x1x1 0107 at U74;0108 at U75; and 0107 at U76

Port Configurations

Configuration Modules Used*

Note: * Three Configuration Modules may use for the RDK. They are “configuration Module 01 07-0109”; U74, U75 and U76 are receptacles on the RDK for Configuration Modules to be installed

3.2.1 RDK Configuration Modules and Their Receptacles

Each Configuration Module is a plug of a 200-pin board-to-board Mezzanine Connector assembled on a PCB. For the RDK, it is used to connect x4 link of PCI Express signals from PEX 8615 to one particular hardware connections. Only three Configuration Modules may be used on the PEX 8615BA base board RDK. These modules are labeled on their PCB silk screen as:

• Configuration Module 0107

• Configuration Module 0108

• Configuration Module 0109

On the RDK side, three receptacles of same Mezzanine Connectors are placed at U74, U75 and U76 where the Configuration Modules can be manually plugged in to complete the RDK PCI Express hardware configurations.

3.2.2 PCI Express Lane 0 to Lane 3

PCI Express lanes 0 - 3 of PEX 8615 are routed to the receptacle U74 as shown in Figure 4. When Configuration Module 0108 is plugged into U74 at Case (a), lanes 0-3 will be separately connected with a single line going to the following: PCI Express cable connector J5, PCI Express SLOT 1, PCI Express SLOT 2 and PCI Express SLOT 3. This results in x1 links to form port 0, 4, 6, and 8. When Configuration Module 0107 is plugged into U74 at Case (b), all four lanes will be connected to x4 PCI Express cable connector J5 to form a x4 link at port 0. Note that the PCIe signals to PCIe Cable Connector J5 can be an independent x4 port or the lower lanes of a x8 port.

Port 0

x1link to upstream

4x PCIe

Cable

Connector

J5

Lane 0

Lane 1

Lane 2

Lane 3

Port 0

x4 link to

upstream

4x PCIe

Cable

Connector

J5

Lane 0-3

Configuration Module

0108

Lane 0-3

Lane 3-0

Lane 4-7

PEX 8615

(U100)

Lane 8-11

x16 PCI Express Connectors

A1

SLT3

SL2 SLT1

Port 8 Port 6 Port 4

(a) (b)

Configuration Module

0107

Lane 0-3

Lane 3-0

Lane 4-7

PEX 8615

(U100)

Lane 8-11

U74U74

x16 PCI Express Connectors

A1

SLT3

SL2 SLT1

Figure 3. Lanes 0-3 Hardware Connections on the RDK

3.2.3 PCI Express Lane 4 to Lane 7

PCI Express lanes 4-7 of PEX 8615 are routed to the receptacle U75 as shown in Figure 5. When Configuration Module 0108 is plugged into U75 at Case (a), lanes 4-7 will be separately connected to PCI Express SLOT 4 to SLOT 7 with x1 link each to form ports 2, 10, 12, and 14. When Configuration Module 0107 is plugged into U75 at Case (b), four lanes will be connected to SLOT 4 to form a x4 link (port 4).

Figure 4. Lanes 4-7 Hardware Connections on the RDK

3.2.4 PCI Express Lane 8 to Lane 11

PCI Express lanes 8-11 of PEX 8615 are routed to the receptacle U76 as shown in Figure 6. When Configuration Module 0108 is plugged into U76 at Case (a), lanes 8-11 will be separately connected to PCI Express SLOT 8 to SLOT 11 with x1 link each to form ports 1, 5, 7, and 9. When Configuration Module 0107 is plugged into U76 at Case (b), four lanes will be connected to SLOT 8 to form a x4 link (port 1).

Figure 5. Lanes 8-11 Hardware Connections on the RDK

3.3 Reference Clock Circuits

The RDK reference clock circuits contain one crystal-to HCSL clock generator ( U108) from On Semiconductor (NB3N5573), two one-to-four differential clock fan out buffer (U28 and U61) from SpectraLinear (CY2840 0-2), two 1-to-10 differential clock drivers (U113-U114) from On Semiconductor (MC100LVEP111), AC coupling capacitors, and resistors for source terminations and voltage dividers. The clock circuits are designed to perform two major clock functions: reference clock fan out and Spread-Spectrum Clock Isolation. Refer to Figure 8, the PCI Express clock (CREFCLKp and CREFCLKn) from x4 PCI Express External Cable Connector J5 feeds into 1-to-4 fan out buffer U28. The outputs from U28 support the primary REFCLK of the PEX 8615 and connect to the inputs of clock drivers U113 and U114. The Constant frequency output from the clock generator (U108) is connected to a 1-to-4 fan out buffer U61. The outputs from U61 support the input to CFC_REFCK on the PEX 8615 as well as inputs to U113 and U114. When Spread Spectrum Clocking Crossing is enabled, the PEX 8615 can be made part of two clock domains. Port 0 is part of the SSC domain while all on-board PCI Express SLOT 1 to SLOT 11 are part of the constant frequency domain. Add-in cards connected to SLOT1 – SLOT11 will operate in a constant frequency clock. The SSC isolation feature can be enabled with a pull-down resistor on STRAP_SSC_ISO_ENABLE# pin. On the RDK, this can be done in Dipswitch SW6 position 1 set to ‘ON’. This feature is disabled on the RDK by default.

Figure 6. RDK Reference Clock Circuits

3.4 Reset Circuits

Refer to Figure 9, the RDK reset circuits include two National NC7S08 2-input AND gate (U17&U21), two Maxim MAX6420 reset controllers (U18 and U20), one Xilinx FPGA (U115), a Serial Hot-Plug controller, momentary switches (S1 and S3), resistors and capacitors.

CPERST_n from 4x

PCIe Cable

Connector J5

PS_PWR_GOOD

from ATX 24-P

Mainboard Power

Connector J9

PCI Express Connectors

PERST_n_SL1

Xilinx

3.3V

R

3.3V NC7S08

NC7S08

R

S1

3.3V

R

3.3V NC7S08

NC7S08

(U21)

R

S3

(U17)

MAX6420

(U18)

C88

MAX6420

(U20)

C153

3.3V

R

FPGA_PEX_RE

SET_n

3.3V

R

FPGA_RESET

FPGA

PERST_n_SL2

PERST_n_SL3

PERST_n_SL4

PERST_n_SL5 PERST_n_SL6

PERST_n_SL7

PERST_n_SL9 PERST_n_SL10

PERST_n_SL11

PEX_PERST_n

PEX8615

(U100)

7_Segmen

SHP

Controller

Slot 1 Slot 2

Slot 3 Slot 4

Slot 5 Slot 6

Slot 7 Slot 9

Slot 10 Slot 11

Displays

U115

Lane Status

PERST_n_SL8

LEDs

Slot 8

Figure 7. RDK Reset Circuits

The Reset Circuits contains two independent circuits: (a) the circuits reset the FPGA; (b) the circuits reset PEX 8615 and sends resets to 11 PCI Express connectors. The first one detect the power good signal, PS_PWR_GOOD, from the ATX 24-pin Main Power Connector and reset from momentary switch S3 to generate reset, FPGA_RESET, to the FPGA U115. The second detect the reset input, CPERST_n from the PCI Express Cable Connector J5 and the reset from momentary switch S1 input them to the FPGA that fans out the resets, PERST_n_SL[15:9, 7:1] , to 10 PCI Express slots, PEX_PERST_n to reset the PEX 8615, and PERST_n_SL8 to reset the PIC Express SLOT 8 through the Serial Hot-Plug Controller (see Figure 9 an Figure 10 for details)

3.5 Serial Hot-Plug (SHP) Controller Circuits

With external IO expenders and Hot-Plug controllers, PEX 8615 supports up to 12 PCI Express Serial Hot-Plug ports/ SLOTs. The RDK implements a serial Hot-Plug controller circuitry to PCI Express SLOT 8 for the SHP function demonstration. By default, the serial Hot-Plug circuit is enabled.

Figure 8. SERIAL HOT-PLUG Circuits

Refer to Figure 10 above, the serial Hot-Plug controller consists of MAX7311 I/O expander (U71), a TI TPS2311 dual hot–swap power controller (U70), a quad TI SN74LVC157 2-to-1 multiplexer (U72), two power MOSFET IRF7470 (Q1 and Q2), LEDs, manual switch, dipswitches and resistors. The PEX 8615 master I designed for the specific control use of the serial Hot-Plug controller. The maste r I I/O expander and the interrupt output from the I/O expander connects to the SHP_INT# of the PEX 8615. When power is applied to the PEX 8615, the master I of the I/O expander. If an I/O expander is detected, the I

2

C interface will scan the bus and attempts to detect the presence

2

C master will program it as a “remote parallel Hot-Plug

2

C interface connected to the

2

C interface is

controller” and assign an available serial Hot-Plug port to the I/O expander. The IO expender then generates PWREN, CLKEN#, and PERST# outputs to control the power enable, clock enable# and reset# of the SHP SLOT8 and drives the LEDs at PWRLED#, ATNLED# and INTERLOCK# outputs. Also, it accepts BUTTON#, PWRFLT#, PWRGOOD, PRSNT# and MRL# inputs and generates interrupts to PEX 8615 for SHP status changes.

The RDK also provides dip switch (SW10) for setting the SLOTID [3:0]for the SLOT 8, and another dipswitch (SW11) to control the Serial Hot-Plug controller functions (enable/disable it), a test point for access the GPIO pin, and three pull-down resistors to set ADD [2:0] of the I/O expander U71. The LEDs D29 and D32 a re 12V and 3.3V power indicators when power reaches PCI Express con nector SLOT 82.

3.6 Serial EEPROM

The PEX 8615BA Base Board RDK contains a blank surface mount Atmel AT25256A 32-Kbit serial EEPROM (U19) which is directly interfaced to the PEX 8615. When programmed correctly, the serial EEPROM can be used to change the default configuration and internal register values of the PEX 8615. A blank EEPROM results in the default register values set in the PEX 8615. Refer to the Software Development Kit (SDK) documentation for more information of how to program the serial EEPROM.

3.7 I2C Interface

The PEX 8615 implements an I2C slave interface (I2C port 0), which allows an external I2C master to read and write device registers through an out-of-band mechanism. The PEX 8615 I address, at data rates from 100 Kbps up to 3.4 Mbps. The RDK provides a 2x2, 0.1” pitch header (JP8), which interface to the PEX 8615’s I such as Total Phase Aardvark I

2

C port. This allows using standard ribbon cable, and/or connecting to an I2C master

2

C controller. (See 4.3.10 for pin assignment of JP8.)

2

C interface is accessible via a 7-bit

3.8 Power Distribution Circuits

To support the power of the RDK and the power of the PCI Express add-in cards plug into up to 15 PCI Express Edge Card connectors, an external ATX power supply is required. Refer to Figure 11, the RDK has 8 different ATX power connectors for power connections. These include one 24-pin ATX Main Power Connector J9, six 4-pin Peripheral Power Connectors J1- J4 & J7 - J8, and one 8-pin +12 V Power Connector.

J1

J9

24

D1 12V_A D2 5V_A D29 12V_SLT_8_HP D30 3.3VCC_SLT_8_HP D32 Interlock_S D31 ATNLED#_S D28 PWRLED#_S D3 3.3VCC D9 3.3VCC1

1

J3

J8

J2

SLOT11

J4

J7

J10

Figure 9. RDK ATX Power Connectors

The 24-pin ATX Power Connector should be connected to J9 an d two or three 4-pin ATX Peripheral Power Connectors should be connected to either J1-J4 or J7-J8 depending on the power co nsumption requirements of the PCI Express add-in cards plugging into the PCI Express slots of the RDK.

Note Some 600 watt power supplies in the market such as the NSpire model PSH600V-D 600 Watt powe r supply requires a minimum power consumption at +12V output to stabilize its +5V outputs. Without 0.8A loading at +12V outputs, the NSpire 600 watt power supply will drop its +5V output to near 3.9V-4.2V levels. The RDK only uses +5V output from the ATX power supply to generated lower DC voltages to support the PEX 8615 chip and the on board FPGA and other circuits. This particular power supply does not operate correctly unless there i s eno ugh loading on the +12V supply. An Nvidia Geforce 8800GT high power graphic card can be plugged into one of PCI Express slots on the RDK in order to provide enough loading on the +12V supply.

Figure 10. RDK Power Distribution Circuits

Refer to Figure 12, 11 PCI Express slots including the Serial Hot-Plug controlled SLOT 8 get 3.3 volt and 12 volt power from 24-pin ATX Main Power Connector, 4-pin ATX Peripheral Power Connectors and the +1 2V Power Connector. The RDK on board circuits and the PEX 8615 get their power from the +5V input from the ATX power supply. DC/DC converter U4 uses 5V input generates 3.3VCC1 to the on board circuit. The 3.3VCC1 further steps down by voltage regulator U117 to generate 2.5V and 1.2V for Xilinx FPGA (U115). Three DC/DC converters U2, U3 and U5 use 5V input to generate 1.0VCC, 1.0VCC_A and 2.5VCC for PEX 8615. Dip switch SW15 can be set to turn off these dc/dc converters for external power margin tests for PLX use only.

3.9 FPGA Interface

The RDK contains a Xilinx Spartan-3 FPGA which is used to perform 6 major functions (see Figure 13 for details):

• Connects to GPIOs, lane and chip status and spare pins of PEX 8615 ( for PLX use only)

• Controls the 7-segment displays for port numbers and link width for PCI Express Cable Connectors J5

and J6 and PCI Express connectors SLOT 1 to SLOT11

• Decodes lane status and converts them to link speed and status LED display

• Communicates with the thermal sensor and displays the junction temperature of PEX 8615 in 4 digits

• Connects to users defined Dipswitches

• Fans out reset signals to PEX 8615 and PCI Express slots

Figure 11. FPGA Interface on RDK

3.10 LED and 7-Segment Displays

The RDK provides 31 LEDs and forty 7-segment displays for power indicators, Hot-Plug output indicators, link speed/status, port numbers and link width of each port.

3.10.1 LED Indicators

All LED indicators and their associated functions are described in the Table 2 below.

Table 2. RDK LED Indicator descriptions

Indicator Type Locations LED Functions

D1 On: 12V_A is applied to the RDK from the ATX power supply

Power LEDs/green color

D2 On: 5V_A is applied to the RDK from the ATX power supply D3 On: 3.3VCC is applied to the RDK from the ATX power supply

Indicator Type Locations LED Functions

D9 On: 3.3VCC1 from dc/dc converter U4 D4 On: 2.5VCC_A is applied to PEX 8615 D5 On: 2.5VCC is applied to PEX 8615

Green LED on: 2.5VCC to PEX 8615 is within 10% range Red LED on: 2.5VCC to PEX 8615 is out of 10% range

Green LED on: 1.0VCC to PEX 8615 is within 10% range Red LED on: 1.0VCC to PEX 8615 is out of 10% range

Green LED on: port 0 link up with GEN 2 speed (5Gbps) at connector J5 Yellow LED on: port 0 link up with GEN 1 speed (2.5Gbps) at connector J5 Both LED off: port 0 link down or no connected or no configured

Power LEDs/dual color: green

and red

SERIAL HOT-PLUG (SHP)

LEDs/green color

Port Link Status and Speed

LEDs / Dual color: green and

yellow

D8

D10 D28 On: SHP power LED output active at SLOT 8

D29 On: 12V is applied to PCI Express SLOT 8 D30 On: 3.3V is applied to PCI Express SLOT 8 D31 On: SHP Attention LED output active at SLOT 8 D32 On: SHP Interlock LED output active at SLOT 8

D12

D16 Same function as D12 for port 4 at SLOT1 D20 Same function as D12 for port 6 at SLOT2 D24 Same function as D12 for port 8 at SLOT3 D13 Same function as D12 for port 2 at SLOT4 D17 Same function as D12 for port 10 at SLOT5 D21 Same function as D12 for port 12 at SLOT6 D25 Same function as D12 for port 14 at SLOT7 D14 Same function as D12 for port 1 at SLOT8 D18 Same function as D12 for port 5 at SLOT9 D22 Same function as D12 for port 7 at SLOT10 D26 Same function as D12 for port 9 at SLOT11

3.10.2 7-Segment Displays

The RDK has forty 7-segment displays. Thrity-four of them are used for port number and link width indicators of each PCI Express SLOTs, two are user defined 7-segment displays, and four of them are used for junction temperature display. (See

Table 3. RDK 7-Segment Display Functions

Location of Display 7-Segment Display Functions

DS37 For port 0 at cable connector J5, When enabled, LED display is 0 DS39 Link Width of port0, LED display is 1 or 4 depending on the port configuration DS33 Copy DS37 if cable connector J6 is used. Otherwise it would be off DS35 Copy DS39 if cable connector J6 is used. Otherwise it would be off

DS2 For port 4 at SLOT1, When enabled, LED display is 4 DS6 Link Width of port 4, When enabled, LED display is 1 DS9 For port 6 at SLOT2, When enabled, LED display is 6

DS13 Link Width of port 6, When enabled, LED display is 1

DS1 For port 8 at SLOT3, When enabled, LED display is 8 DS5 Link Width of port 8, When enabled, LED display is 1

DS12 For port 2 at SLOT4, When enabled, LED display is 2

Table 3 for details).

Location of Display 7-Segment Display Functions

DS16 Link Width of port 2, it can be 1 or 4 depends the port configuration

DS4 For port 10 at SLOT5, When it is on, it would be A

DS8 Link Width of port 10, When it is on, it would be 1 DS11 For port 12 at SLOT6, When it is on, it would be C DS15 Link Width of port 12, When it is on, it would be 1

DS3 For port 14 at SLOT7, When it is on, it would be E

DS7 Link Width of port 14, When it is on, it would be 1 DS26 For port 1 at SLOT8, When it is on, it would be 1 DS30 Link Width of port 1, it can be 1 or 4 depends the port configuration DS18 For port 5 at SLOT9, When it is on, it would be 5 DS22 Link Width of port 5, When it is on, it would be 1 DS25 For port 7 at SLOT10, When it is on, it would be 7 DS29 Link Width of port 7, When it is on, it would be 1 DS17 For port 9 at SLOT11, When it is on, it would be 9 DS21 Link Width of port 9, When it is on, it would be 1

DS10 and DS14 Users’ defined 7-segment displays

DS34, DS36, DS38,

DS40

They are used to display junction temperature of PEX 8615 in degree C

3.11 GPIO Pins

The PEX 8615 has thirty-two GPIO pins. Depends on the TEST MODE pin settings, 16 of them, GPIO[15:0], can be configured to perform Serial Hot-Plug reset output functions (PERSTx#).

3.12 Reserved Pins

The PEX 8615 has 2 STRAP_RESERVED pins. They are factory use only and should be set to know logic states. Table 4 shows the list of these reserved pins and their connections in the RDK.

Table 4. Strap_Reserved Pin Connections

Name Pin Location Connections on PEX 8615BA Base Board RDK

STRAP_RESERVED16 D14 Pull-down with a 1K ohm resistor

STRAP_RESERVED17# F1 Pull-up with a 4.7K ohm resistor

4. On-Board Connectors, Switches, and Jumpers

4.1 DIP Switches

The PEX 8615BA Base Board RDK contains eleven DIP switches for various functions. Refer to Figure 14; they can be divided into three groups. The Group1 contains three dip switches and is located at the lower left corner of the RDK, Group2 contains three dip switches and is located at the middle of right edge, and the last group contains five dip switches and is located at the lower right hand corner of the RDK

Figure 12. RDK Dip Switch Groups

4.1.1 Dip Switch Group 1

This group includes three dipswitches, SW10, SW11 and SW15. Figure 15 shows the default settings of these dipswitches and Table 5 describes the functions of each dipswitches

4. Debug_Normal#

3. PLX use only

2. PLX use only

1. PLX use only

2. HP_SL8_CTL

1. MRLI#_S

Figure 13. Group1 of Switches

4. SLOT3

3. SLOT2

2. SLOT1

1. SLOT0

Table 5. Functional Description of Group 1 Dip Switches

Name

Function

SW10 Slot number of Serial Hot-Plug port

PCIe connectro SPLT8

Default: on, on, on, on (0000) 4: SLOT 3

Settings

3: SLOT 2 2: SLOT 1 1: SLOT 0

SW11 Serial Hot-Plug Port input and

control

2. HP_SL8_CTL : on: enable Serial Hot-Plug (SHP) control outputs— PWREN_S, PERST#_S and CLKEN#_S; off: bypass above SHP control ouputs

1. MRLI#_S: on: enable SHP MRL# input; off: disable it Default: on,on (enable SHP functions at SLOT 8)

SW15 Debug function and dc/dc converter

controls

4: Debug_normal_#: on : for normal operation; off: for debug us 3-1: for PLX use only

Default: on, off,off,off

4.1.2 Dip Switch Group 2

This group includes three dipswitches, SW4, SW5 and SW7. Figure 16 shows the default settings of these dipswitches and Table 6 describes the functions of each dipswitches

SW7

1. TESTMODE3

ON

2. TESTMODE2 3: TESTMODE1

SW5

SW4

4: TESTMODE0

1. NT_ENABLE_n

ON

2. DEBUG_SEL0 3: PROBE_MODE_n 4: SERDES_MODE_EN_n

1. NT_UPSTR_PSEL3

2. NT_UPSTR_PSEL2

ON

3: NT_UPSTR_PSEL1 4: NT_UPSTR_PSEL0

Figure 14. Group 2 of Dipswitches

Table 6. Functional Description of Group 2 Dip Switches

Name

Function

SW4 NT Upstream Port Selects

NT_UPSTR_PSEL[3:0] Port #

Settings

on,on,on,on 0 on,on,on,off 1 on,on,off,on 2 on,off,on,on 4 on,off,on,off 5 on,off,off,on 6 on,off,off,off 7 off,on,on,on 8 off,on,on,off 9 off,on,off,on 10 off,off,on,on 12 off,off,off,on 14

SW5 NT port and debug mode enables 1. NT_ENABLE_n : on: enable NT mode, off: disable NT

mode, default disable NT mode

2. DEBUG_SEL0: for PLX use only 3: PROBE_MODE_n: for PLX use only

4. SERDES_MODE_EN_n: for PLX use only Default: 1-4: off,off,off,off

SW7 Test Mode selects 1. TESTMODE3: for PLX use only

2: TESTMODE2: for PLX use only

3. TESTMODE1: for PLX use only 4: TESTMODE0: for PLX use only

Default: 1-4: off,off,off,off

4.1.3 Dip Switch Group 3

This group includes five dipswitches, SW2, SW3, SW6, SW13 and SW14. Figure 17 shows the default settings of these dipswitches. Table 7 and Table 8 describe the functions of them.

SW3

1. UPSTR_PSEL3

2. UPSTR_PSEL2 3: UPSTR_PSEL1 4: UPSTR_PSEL0

SW6

SW2

SW14

SW13

Figure 15. Group 3 of Dip Switches

1. SSC_ISO_EN_n

2. PP_PYPASS_n 3: GEN1_n 4: FAST_BRINGUP_n

1. PORT_CFG3

2. PORT_CFG2 3: PORT_CFG1 4: PORT_CFG0

1. UMODE7

2. UMODE6 3: UMODE5 4: UMODE4

1. UMODE3

2. UMODE2 3: UMODE1 4: UMODE0

Table 7. Port Configurations use Dipswitch SW2

Dipswitch Settings for

STRAP_PORTCFG[3:0]

ON,ON,ON,ON (0000) x1x 1x1x1x1x1x1x1x1x1x1x1x1x1x1x1 ON,ON,ON,OFF (0001) x4x1x1x1x1x1x1x1x1x1x1x1x1 ON,ON,OFF,ON (0010) x4x4x1x1x1x1x1x1x1x1

Port Configurations

Table 8. Functional Descriptions of SW3, SW6, SW13-SW14

Name

SW3 Upstream Port Selects

SW6 Other Mode Selects 1. SSC_ISO_EN_n : on: enable the Spread Spectrum

Function

UPSTR_PSEL[3:0] Port #

on,on,on,on 0 on,on,on,off 1 on,on,off,on 2 on,off,on,on 4 on,off,on,off 5 on,off,off,on 6 on,off,off,off 7 off,on,on,on 8 off,on,on,off 9 off,on,off,on 10 off,off,on,on 12 off,off,off,on 14

Clocking (SSC) crossing, off: disable it, default is disable SSC crossing function

2. PP_PYPASS_n: for PLX use only 3: GEN 1_N: for PLX use only

4. FAST_BRINGUP_n: for PLX use only Default: 1-4: off,off,off,off

Settings

SW13 Users Define Mode Switches 1. UMODE3

2: UMODE2

3. UMODE1 4: UMODE0

Default: 1-4: off,off,off,off

SW14 Users Define Mode Switches 1. UMODE7

2: UMODE6

3. UMODE5 4: UMODE4

Default: 1-4: off,off,off,off

4.2 Push-Button Switches

4.2.1 Manual Reset# (S1)

The RDK provides a manual switch (S1) for manual PERST# capability. Note that manual PERST# will only apply warm reset to the PEX 8615 as well as PCI Express SLOT 1 to SLOT 11.

4.2.2 FPGA Manual Reset# (S2)

This momentary switch (S2) provides manual reset to the FPGA (U115) on the RDK.

4.2.3 Serial Hot-Plug Controller Attention Button (S3)

The RDK provides a manual switch (S3) for attention button to the Serial Hot-Plug circuit. When pushed and released, the switch generates an active low pulse to the Attention Button Input to the IO Expender U71 which will generate interrupt signal, INT#, to the PEX 8615 for attention (see section 3.5 for details).

4.3 Connectors and Headers

4.3.1 ATX Peripheral Power Connectors (J1-J4 & J7-J8)

The RDK has six ATX Peripheral Power Connectors.

Table 9. Signal Names of J1-J4 & J7-J8

Pin # Signal Name

1 12V 2 GND 3 GND 4 5V

4.3.2 x4 PCI Express External Cable Connectors (J5 & J6)

The RDK has two x4 PCI Express External Cable Connectors.

Table 10. Signal Names of J5 and J6

Pin # Signal Name Pin # Signal Name

A1 GND B1 GND A2 PETp0 B2 PERp0 A3 PETn0 B3 PERn0 A4 GND B4 GND A5 GND B5 PERp1 A6 PETp1 B6 PERn1 A7 PETn1 B7 GND A8 GND B8 PERp2

A9 PETp2 B9 PERn2 A10 PETn2 B10 GND A11 GND B11 PERp3 A12 PETp3 B12 PERn3 A13 PETn3 B13 GND A14 GND B14 PWR A15 CREFCLKp B15 PWR A16 CREFCLKn B16 PWR_RTN A17 GND B17 PWR_RTN A18 SB_RTN B18 CWAKE# A19 CPWRON B19 CPERST#

4.3.3 ATX Main Power Connector (J9)

Table 11. Signal Names of J9

Pin # Signal Name Pin # Signal Name

1 +3.3VDC 13 +3.3VDC 2 +3.3VDC 14 -12VDC 3 COM 15 COM 4 +5VDC 16 PS_ON# 5 COM 17 COM 6 +5VDC 18 COM 7 COM 19 COM 8 PWR_OK 20 -5VDC

9 +5VSB 21 +5VDC 10 +12VDC 22 +5VDC 11 +12VDC 23 +5VDC 12 +3.3VDC 24 COM

4.3.4 ATX +12V Power Connector(J10)

Table 12. Signal Names of J10

Pin # Signal Name Pin # Signal Name

1 COM 13 +12VDC

2 COM 14 +12VDC

3 COM 15 +12VDC

4 COM 16 +12VDC

4.3.5 Xilinx JTAG Connector (J12)

Table 13. Signal Names of J12

Pin # Signal Name Pin # Signal Name

1 VREF to 2.5V 2 GND

3 SS_PROG_TMS 4 GND

5 SCLK_CCLK_TCK 6 GND

7 MISO_DONE_TDO 8 GND

9 MOSI_DIN_TDI 10 GND 11 NC 12 GND 13 NC_INIT_NC 14 DNG

4.3.6 Xilinx Mode Setting Header (J13)

Table 14. Signal Names of J13

Pin # Signal Name Pin # Signal Name

1 GND 2 M0

3 GND 4 M1

5 GND 6 M2

4.3.7 PEX 8615 JTAG Header (JP3)

The 2x5 header JP3 provides a direct connection to the PEX 8615 JTAG interface. The 10-pin connector is designed to allow a direct interface to 3rd party JTAG controllers, such as the Corelis USB-1149.1/E controller. The pin assignment for the JTAG header (JP3) is listed at Table 15.

Table 15. Pin assignment of JP3

Pin # Signal Name Pin # Signal Name

1

3

5

7

9

JTAG_TRST

JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TCK

2 GND 4 GND 6 GND 8 GND

10 GND

4.3.8 SMBus Header (JP5)

This header is for PLX use only

Table 16. Signal Names of JP5

Pin # Signal Name Pin # Signal Name

1 SMBCLK 2 GND 3 SMBDATA 4 NC

4.3.9 PCI Express x8 Midbus Probe Footprint (JP6)

Table 17. Signal Names of JP6

Pin # Signal Name Pin # Signal Name

G1 GND 2 GND 1 C0p-Upstream 4 C0p-Downstream 3 C0n-Upstream 6 C0n-Downstream 5 GND 8 GND 7 C1p-Upstream

10 C1p-Downstream 9 C1n-Upstream 12 C1n-Downstream 11 GND 14 GND 13 C2p-Upstream 16 C2p-Downstream 15 C2n-Upstream 18 C2n-Downstream 17 GND

Pin # Signal Name Pin # Signal Name

20 GND 19 C3p-Upstream 22 C3p-Downstream 21 C3n-Upstream 24 C3n-Downstream 23 GND 26 GND 25 C4p-Upstream 28 C4p-Downstream 27 C4n-Upstream 30 C4n-Downstream 29 GND 32 GND 31 C5p-Upstream 34 C5p-Downstream 33 C5n-Upstream 36 C5n-Downstream 35 GND 38 GND 37 C6p-Upstream 40 C6p-Downstream 39 C6n-Upstream 42 C6n-Downstream 41 GND 44 GND 43 C7p-Upstream 46 C7p-Downstream 45 C7n-Upstream 48 C7n-Downstream 47

G2 GND

4.3.10 PEX 8615 I2C Port (JP8)

Table 18. Pin assignment of JP8

Pin Number Signal Name

1 I2C_SCL0 2 GND 3 I2C_SDA0 4 NC

4.3.11 Debug Signal Header (JP9 & JP11)

This is for PLX use only.

Table 19. Pin assignment of JP9 & JP11

Pin # Signal Name at JP9 Signal Name at JP11

1 - 3 GND GND 5 - NC 7 GPIO16 DEBUG_SEL0 9 GPIO17 STRAP_UPCFG_TIMER_EN#

11 GPIO18 STRAP_SMBUS_EN# 13 GPIO19 STRAP_SPARE0# 15 GPIO20 UPSTRM_PSEL3 17 GPIO21 GPIO29 19 GPIO22 GPIO30 21 GPIO23 I2C_ADDR2

Pin # Signal Name at JP9 Signal Name at JP11

23 GPIO24 STRAP_SPARE5# 25 GPIO25 GPIO6 27 GND GPIO7 29 - GPIO8 31 - GPIO26 33 - GPIO27 35 - STRAP_NT_P2P_EN# 37 - GND 39 GND GND 40 GND GND 41 GND GND 42 GND GND 43 GND GND

2 - 4 - 6 - 8 LN_GOOD_00_n GPIO0

10 LN_GOOD_01_n GPIO1 12 LN_GOOD_02_n GPIO2 14 LN_GOOD_03_n GPIO3 16 LN_GOOD_04_n GPIO4 18 LN_GOOD_05_n GPIO5 20 LN_GOOD_06_n I2C_ADDR0 22 LN_GOOD_07_n I2C_ADDR1 24 LN_GOOD_08_n STRAP_SPARE1# 26 LN_GOOD_09_n GPIO9 28 LN_GOOD_10_n GPIO10 30 LN_GOOD_11_n GPIO11 32 LN_GOOD_12_n GPIO12 34 LN_GOOD_13_n GPIO13 36 LN_GOOD_14_n GPIO14 38 LN_GOOD_15_n GPIO15

4.3.12 Debug Input Header (JP10)

This is for PLX use only.

Table 20. Pin assignment of JP10

Pin # Signal Name Pin # Signal Name

1 GND 2 STRAP_SPARE1# 3 I2C_ADDR2 4 I2C_ADDR1 5 GPIO30 6 I2C_ADDR0 7 GPIO29 8 GND 9 UPSTRM_PSEL3 10 GPIO5

11 STRAP_SPARE0# 12 GPIO4 13 GND 14 GPIO3 15 STRAP_SMBUS_EN# 16 GPIO2 17 STRAP_UPCFG_TIMER_EN# 18 GPIO1 19 DEBUG_SEL0 20 GPIO0

4.3.13 Reference Clock Header (JP100)

Table 21. Pin assignment of JP100

Pin Number Signal Name

1 LAI_Refclk_p 2 GND 3 LAI_Refclk_n

5. RDK Port Configurations

GND

BJ10

2.5VCC

ON

SW5

BJ9

SW7

SW4

SLOT1

ON

SW3

ON

SW2

SW6

Port #

D16D20D24D13D17D21D25D14D18D22D26

ON

SW14ONSW13

Link Width

PEX8615-BB RDK

SLOT2

D6

1.0VCC_A

SLOT3

Port #

Link Width

J5

cable

4x PCIE

connector

D12

J6

cable

4x PCIE

connector

Port #

0108

Module

Configuration

Link Width

Module

0108

D4

2.5VCC_A

Configuration

Module

0108

SLOT4

D8

D10

U100

PEX

8615

JP100

JP6

3

4

JP8

I2C Port

1

2

JP10

Mictor

Connectors

JP9 JP10

1.0VCC_A

BJ6

BJ5

GND

JP3

1

JTAG Port

1

Header

Debug Input

U115

Xilinx

FPGA

Footprint

Midbus Probe

BJ3

BJ4

GND

1.0VCC Port #

S1

1.0VCC

Manual Reset

D7

D5

2.5VCC

Port

J12

FPGA JTAG

1

S2

FPGA Reset

3

4

JP5

I2C Port for

1

2

Thermal Sensor

J13

1

FPGA Mode

Link Width

SLOT5

SLOT6

SLOT7

SLOT8

SLOT9

SLOT10

SLOT11

SLOT12

D15D19D23D27

SLOT13

SLOT14

SLOT15

SW10

J1J7J3

J8J4J2

J10

1

J9

24

D9 3.3VCC1

D3 3.3VCC

D28 PWRLED#_S

D31 ATNLED#_S

D1 12V_A

D2 5V_A

D32 Interlock_S

D29 12V_SLT_8_HP

D30 3.3VCC_SLT_8_HP

User debug

SW11 S2

ON ONON

SW15

Figure 16. x1 upstream and 11x1 downstream (PCFG=0000)

Figure 17. x4 upstream 8x1 downstream (PCFG=0001)

Figure 18. x4 upstream, 1x4 and 4x1 downstream (PCFG=0010)

6. Bill of Materials/ Schematics

Item

SURFACE MOUNT COMPONENTS

Qty Man. Man. Part # Description Package Type Component Designator(s)

#

1 1 PLX

2 4 BEL 3 1 Intersil ISL6132IR IC, multiple voltage monitor SMT, QFN-24 U16

4 2 National NC7S08M5X IC, 2-input AND gate SMT, SOT23-5 U17, U21 5 2 MAXIM

6 1 ATMEL 7 2

8 36 Fairchild MM74HC164MX

9 1 MAXIM MAX7311AUG

10 1 Texas TPS2311IPW 11 1 Texas 12 1 MAXIM MAX6658MSA

13 5 NXP SEMI SN74LVC04AD IC, hex inverter SMT, SO-14 U80, U85, U87, U91, U92 14 1

15 2

16 1 Xilinx

17 1 Xilinx 18 1 Maxim MAX8833ETJ+ 19 2 20 11 Lumex 21 2 22 12 23 1 Citizen 24 1 ECS Inc

25 2 Panasonic ELL-6SH1R0M Inductor, 1.0UH 20% 3.4A, SMT L2, L3 26

27 3 FCI 84517-101LF

28 2 Molex 75586-0011

30 15 CTS 742C083472JTR

SpectralLinear/C

ypress

On

Semiconductor

On

Semiconductor

International

Rectifier

CML Innovative

Technologies

CML Innovative

Technologies

PEX8615-

BA50BC G

S7AH-08E1A0 . Non-iso DC/DC converter,

MAX6420UK16-T IC, Reset controller, Adj.

AT25256AN-

10SU-2.7

CY28400OXC-2

SN74LVC157AP

W

NB3N5573DTG

MC100LVEP111

FAG

XC3S200-

4FTG256C

XCF01SVOG20C IC, 1Mbit platform flash

IRF7470PBF

SML-

LXT0805GW-TR

7016X1/5 LED, dual color, green/red SMT, 4-pin D8, D10 7016X5/7

HCM49

25.000MABJ-UT ECS-3953M-

1000-AU

IC, 16 lane 16 port PCIe

gen2 switch with DMA,

19x19mm

5Vin/0.9-3.3Vout @8A

reset timeout

IC, SPI Serial EEPROM SMT, SO-8 U19

IC, 100MHz Differential

Clock Buffer

IC, 8-bit serial in/parallel-

out shift register

IC, 2-wire-interface 16-bit

I/O Port Expander with

Interrupt

IC, dual hot-swap power

controller

IC, Quad 2-to-1 data

selector/multiplexer

IC, SMBus-compatible

temperature sensor

IC, crystal to HCSL clock

generator, 3.3V

IC, 1:10 differential

ECL/PECL/HSTL clock

driver, 2.5/3.3V

IC, Spartan-3 FPGA, 4ns,

173 I/Os, 256-pin, 1mm

pitch,

PROM

IC, dual 3A step-down

regulator

IC, N-channel MOSFET,

40V/10A 13mohm

LED, green color SMT, 0805

LED, dual color,

genn/yelow

CRYSTAL, 25.000 MHz,

18pF load capacitor

OSC, 100.000 MHZ 3.3V

SMD

Connector, 10x20,

Receptacle

Connector, receptacle,

right angle receptacle,

0.8mm pitch for PCIE 4x cable,

Resistor Network, 4.7K

ohm 4R isolated

BGA, 324-pin,

full matrix, 1mm

ball pitch

SMT, 7-pin U2, U3, U4, U5

SMT, SOT23-5 U18, U20

SMT, SSOP-28 U28, U61

U29, U30, U31, U32, U33, U34, U35, U36, U37, U38, U39, U40,

SMT, SO14

SMT, TSSOP-24 U71

SMT, TSSOP-20 U70 SMT, TSSOP-16 U72

SMT, SO-8 U78

SMT TSSOP-16 U108

SMT, QFP-32 U113, U114

SMT, 256-pin

BGA

SMT, TSSOP-20 U116

SMT, QFN-32 U117

SMT, SO-8 Q1, Q2

SMT, 4-pin

SMT Y2 SMT Y4

SMT U74, U75, U76

SMT 38-pin

connector

SMT, 8-pin

U41, U42, U43, U44, U45, U46, U49, U50, U53, U54, U57, U58, U62, U63, U64, U65, U66, U67, U68, U69, U83, U84, U88, U89

D1, D2, D3, D4, D5, D9, D28,

D12, D13, D14, D16, D17, D18, D20, D21, D22, D24, D25, D26,

RN1, RN4, RN5, RN6, RN7, RN8,

RN9, RN10, RN11, RN13, RN54,

RN55, RN58, RN59, RN60

U100

U115

D29, D30, D31, D32

J5, J6

Item

Qty Man. Man. Part # Description Package Type Component Designator(s)

#

31 32 Panasonic EXB-2HV221JV

32 1 CTS 742C083103JTR 33 1 CTS 742C083102JTR

34 5 ROHM MCR10EZHJ000 RES. 0.0 OHM 5% SMT, 0805 R10, R59, R61, R62, R269 35 2 Panasonic

36 1 Panasonic 37 3 Yageo 38 1 Panasonic

39 12 Panosonic

40 32 Panasonic

42 32 Panasonic

43 2 Panasonic

44 12 Panasonic

45 40 Panasonic

46 4 Panasonic ERJ-3EKF1431V RES 1.43K OHM 1% SMT, 0603 R281, R282, R283, R284 47 1 Panasonic ERJ-3EKF2000V RES 200 OHM 1% SMT, 0603 R278 48 2 Panasonic ERJ-3EKF2261V RES 2.26K OHM 1% SMT, 0603 R42, R44 49 3 Panasonic ERJ-3EKF4750V RES 475 OHM 1% SMT, 0603 R79, R292, R319 50 1 Panasonic ERJ-3EKF4990V RES 499 OHM 1% SMT, 0603 R28

51 9 Yageo 52 8 Panasonic ERJ-3EKF7321V RES 7.32K OHM 1% SMT, 0603

53 28 Panasonic ERJ-S02F3900X RES 390 OHM 5% SMT, 0402

ERJ-

6ENF2001V

ERJ6ENF2002V RC0805FR-

07374RL

ERJ6ENF4701V

ERJ-

3GEY0R00V

ERJ3GEYJ102V

ERJ3GEYJ121V

ERJ-

3GEYJ4R7V

ERJ3GEYJ512V

ERJ3GEYJ103V

RC0603FR-

075K1L

Resistor Network, 220 ohm

8R isolated

Resistor Network 10K ohm

4R isolated

Resistor Network, 1K ohm

4R isolated

RES. 2.00K OHM 1% SMT, 0805 R262, R263 RES. 20.0K OHM 1% SMT, 0805 R251

RES. 374 OHM 1% SMT, 0805 R29, R30, R34

RES. 4.70K OHM 1% SMT, 0805 R268

RES. ZERO OHM 5% SMT, 0603

RES. 1K OHM 5% SMT, 0603

RES. 120 OHM 5% SMT, 0805

RES. 4.7 OHM 5% SMT, 0603 R293, R320

RES. 5.1K OHM 5% SMT, 0603

RES 10K OHM 1% SMT, 0603

RES 5.10K OHM 1% SMT, 0603

SMT, 16-pin

SMT, 8-pin RN56 SMT, 8-pin RN3

RN14, RN15, RN16, RN17, RN18, RN19, RN20, RN21, RN22, RN23, RN24, RN25, RN26, RN27, RN28, RN29, RN30, RN31, RN34, RN35, RN38, RN39, RN42, RN43, RN46, RN47, RN48, RN49,

RN50, RN51, RN52, RN53

R277, R285, R286, R287, R311, R314, R315, R339, R340, R344,

R407, R408 R434, R435, R436, R437, R438, R439, R440, R441, R442, R443, R444, R445, R446, R447, R448, R505, R506, R507, R508, R509, R511, R512, R513, R514, R515, R516, R517, R518, R519, R520,

R521, R510 R530, R531, R532, R533, R534, R535, R540, R541, R542, R543, R544, R545, R550, R551, R552, R553, R554, R555, R556, R557, R558, R559, R560, R561, R562, R563, R564, R565, R566, R567,

R568, R569

R307, R308, R309, R310, R312, R313, R334, R335, R336, R337,

R338, R374 R449, R454, R455, R456, R457, R458, R459, R460, R465, R466, R467, R468, R469, R470, R471, R472, R473, R474, R475, R476, R485, R486, R487, R488, R489, R490, R491, R492, R493, R494, R495, R496, R497, R498, R499, R500, R501, R502, R503, R504

R60, R64, R70, R71, R72, R77,

R78, R80, R81

R450, R451, R452, R453, R461,

R462, R463, R464

R49, R50, R53, R54, R216, R217, R218, R219, R220, R221, R224, R225, R226, R227, R228, R229, R232, R233, R234, R235, R236, R237, R240, R241, R242,

R243, R244, R245,

Item

Qty Man. Man. Part # Description Package Type Component Designator(s)

#

54 23 Panasonic ERJ-2GEJ472X RES 4.7K OHM 5% SMT, 0402

55 3 Panasonic 56 1 Yageo 57 3 Panasonic 58 3 Yageo 59 1 Panasonic 60 1 Yageo 61 1 Panasonic 62 3 Panasonic 63 1 Panasonic 64 1 Panasonic 65 3 Panasonic 66 1 Yageo 67 1 Yageo 68 4 Yageo 69 1 Panasonic 70 1 Panasonic 71 1 Panasonic

72 21 Yageo

73 1 Yageo 74 2 Panasonic 75 1 Panasonic 76 1 Yageo

77 18 Panasonic

78 2 Panasonic ERJ-2GEJ513X RES 51K OHM 1% SMT, 0402 R57, R66 79 1 Yageo

80 1 Panasonic 81 1 Panasonic 82 2 Panasonic 83 1 Yageo 84 1 Yageo

ERJ-

2RKF1001X

RM04F1001CTL

F

ERJ-

2RKF1002X

RM04F1002CTL

F

ERJ-

2RKF1003X

RM04F10R0CTL

F

ERJ-

2RKF1181X

ERJ-

2RKF1201X

ERJ-

2RKF1242X

ERJ-

2RKF1372X

ERJ-

2RKF1500X

RM04F2000CTL

F

RM04F2001CTL

F

RM04F2002CTL

F

ERJ-

2RKF2321X

ERJ-

2RKF3091X

ERJ-

2RKF3161X

RC0402FR-

0733RL

RT0402FRE073

60RL ERJ-

2RKF3652X

ERJ-

2RKF4640X

ERJ-

2RKF4991X

ERJ-

2RKF49R9X

RT0402FRE075

1RL

ERJ-

2RKF5761X

ERJ-

2RKF7321X

ERJ-

M1WSF20MU

9C06031A7321F

KHFT

9C06031A1001F

KHFT

RES 1.00K OHM 1% SMT, 0402 R254, R257, R258

RES 1K 1% SMT, 0402 R350

RES 10.0K OHM 1% SMT, 0402 R58, R67, R351

RES 10K 1% SMT, 0402 R348, R349, R359 RES 100K OHM 1% SMT, 0402 R248 RES 10.0 OHM 1% SMT, 0402 R346

RES 1.18K OHM 1% SMT, 0402 R41 RES 1.21K OHM 1% SMT, 0402 R1, R12, R252 RES 12.4K OHM 1% SMT, 0402 R249 RES 13.7K OHM 1% SMT, 0402 R250

RES 150 OHM 1% SMT, 0402 R253, R255, R256

RES 200 OHM 1% SMT, 0402 R347

RES 2K OHM 1% SMT, 0402 R14

RES 20K 1% SMT, 0402 R352, R355, R356, R357

RES 2.32K OHM 1% SMT, 0402 R47 RES 3.09K OHM 1% SMT, 0402 R37 RES 3.16K OHM 1% SMT, 0402 R358

RES 33.0 OHM 1% SMT, 0402

RES 360 OHM 1% SMT, 0402 R2

RES 36.5K OHM 1% SMT, 0402 R7, R11

RES 464 OHM 1% SMT, 0402 R43

RES 4.99K 1% SMT, 0402 R354

RES 49.9 OHM 1% SMT, 0402

RES 51.1 OHM 1% SMT, 0402 R267 RES 5.76K OHM 1% SMT, 0402 R45 RES 7.32K OHM 1% SMT, 0402 R38

RES 0.02 OHM 1W 1% SMT, 2512 R261, R264

Res. 7.32K ohm, 1/10W

1%

Res. 1.0K ohm 1/10W 1% SMT, 0603 R345

SMT, 0603 R343

R9, R33, R35, R201, R202, R203, R204, R205, R206, R207, R208, R209, R210, R211, R259, R260, R265, R266, R270, R271,

R272, R273, R274

R63, R65, R289, R291, R297, R299, R300, R301, R302, R306, R316, R318, R324, R326, R327, R328, R329, R333, R341, R342,

R353

R73, R74, R290, R294, R295, R296, R298, R303, R304, R305, R317, R321, R322, R323, R325,

R330, R331, R332

Item

Qty Man. Man. Part # Description Package Type Component Designator(s)

#

85 2 Panasonic ERJ-2GEJ203X Res. 20K ohm 1/16W 5% SMT, 0402 R360-R361 90 11 Panasonic ECJ3YB1C106M CAP 10uF 16V 20% X5R SMT, 1206 91 1 CALCHIP ECJ-2VC1H151J CAP 150pf 50V 5% NPO SMT, 0805 C160

92 1 CALCHIP ECJ-2VC1H331J CAP 330pf 50V 5% NPO SMT, 0805 C80 93 2 Panasonic

94 8 Kemet

95 32 CALCHIP

96 2 Kemet 97 1 CALCHIP 98 1 CALCHIP 99 1 AVX

100 1 AVX

101 24 Kemet

102 47 AVX

103 64 Panasonic

104 81 Kemet

ECJ-

2VB1H102K

GMC21X7R104

K50NT

GMC21X7R105

K16NT-LF

GMC21X5R106

M6R3NT

08055C223KAT

2A

GMC21X5R226

M6R3NT

06033A180GAT

2A

0603YA220JAT2

A

C0603C105K8P

ACTU

04026C102KAT

2A

ECJ-

0EB1C103K

C0402C104K8P

ACTU

CAP 1000pf 50V 10% X7R SMT, 0805 C79, C82

CAP 0.1 uf 50V 10% X7R SMT, 0805

CAP 1UF10% 16V X5R SMT, 0805

CAP 10uf 6.3V 20% X5R SMT, 0805 C75, C84

CAP 0.022uf 50V 10%

X7R

CAP 22uf 6.3V 20% X5R SMT, 0805 C156

CAP 18PF 25V NP0 SMT, 0603 C327 CAP 22PF 16V NP0 SMT, 0603 C328

CAP 1.0UF 10V 10% X5R SMT, 0603

CAP 1000PF 50V X7R SMT, 0402

CAP 0.01uf 16V 10% X7R SMT, 0402

CAP 0.1UF 10V X5R SMT, 0402

SMT, 0805 C163

C42, C45, C47, C64, C67, C315,

C319, C320, C326, C336, C339

C72, C73, C74, C76, C78, C83,

C86, C157

C1, C2, C6, C8, C10, C12, C13,

C16, C19, C20, C21, C24, C25, C26, C27, C28, C44, C46, C48,

C63, C65, C71, C161, C257,

C296, C298, C301, C302, C305,

C306, C308, C310

C89, C90, C91, C92, C93, C94,

C95, C98, C121, C122, C123, C124, C125, C126, C127, C128, C389, C391, C392, C393, C395,

C396, C412, C423

C88, C153, C105, C108, C109, C110, C116, C117, C118, C120, C141, C145, C146, C148, C151, C259, C260, C334, C378, C379, C380, C381, C382, C383, C394, C397, C398, C399, C400, C401, C402, C403, C404, C405, C406, C407, C408, C409, C410, C415, C416, C417, C418, C419, C420,

C421, C422 C101, C102, C106, C107, C133, C137, C158, C159, C316, C317, C318, C321, C324, C325, C337, C338, C340, C341, C211, C212, C213, C214, C215, C216, C217, C218, C219, C220, C221, C222, C223, C224, C225, C226, C227, C228, C229, C230, C231, C232, C233, C234, C243, C244, C245, C246, C247, C248, C249, C250, C311, C312, C313, C314, C384, C385, C386, C387, C388, C390,

C411, C413, C414, C424

C85, C87, C154, C251, C252, C255, C256, C258, C261, C263, C264, C265, C266, C267, C268, C269, C270, C271, C272, C273, C274, C275, C276, C277, C278, C279, C280, C281, C282, C283, C284, C285, C286, C444, C445, C446, C447, C448, C449, C450, C451, C452, C453, C454, C455, C456, C457, C458, C459, C460, C461, C462, C463, C464, C465, C466, C467, C468, C469, C470, C471, C472, C473, C474, C475, C476, C477, C478, C479, C480, C481, C482, C483, C484, C485, C486, C487, C488, C489, C490,

C491,

Item

Qty Man. Man. Part # Description Package Type Component Designator(s)

#

105 1 AVX

106 46 AVX TAJC226K020R

107 10 AVX

108 20 Panasonic

109 3 Vishay 110 1 Taiyo Yuden

04023C222JAT2

A

0201ZD103KAT

2A

ECJ-

ZEB1E102K

594D187X0016

R2T

JMK212BJ476M

G-T

CAP 2200PF 25V X7R SMT, 0402 C262

C3, C4, C5, C7, C9, C11, C14,

C15, C17, C18, C22, C23, C29,

C30, C31, C32, C181, C182,

CAP 22UF 20V 10%

Tantalum

CAP 0.01UF 10% 10V

X5R

CAP 1000PF 25V X7R SMT, 0201

CAP, 180UF 16V 20%

Tantalum

CAP 47uf 6.3V 20% X5R SMT, 0805 C77

SMT, C Case

SMT, 0201

SMT, D Case C34, C35, C36

C183, C184, C185, C186, C187, C188, C189, C190, C191, C192, C193, C194, C195, C196, C197, C198, C199, C200, C202, C204, C295, C297, C299, C300, C303,

C304, C307, C309

C96, C97, C99, C100, C129,

C130, C134, C135, C136, C138

C103, C104, C111, C112, C113, C114, C115, C119, C131, C132, C139, C140, C142, C143, C144,

C147, C149, C150, C152, C155

MANUALLY INSERTED COMPONENTS

300 3 Amp/Tyco 382811-6 Jumpers JP13 (1-2,3-4,5-6)

MISCELLANEOUS COMPONENTS

400 8 Olander .2C5PPMS 401 12 3M SJ5009(BLACK) 402 1 PLX Technology 90-0104-000A

Screw, M2 X 5MM PHIL

PAN SST

RUBBER BUMPER, .40 X

.88 BLACK

PCB, PEX8618 Base

Board RDK

XCAGE1, XCAGE2

Install at the bottom side of each

board

PART THAT SHOULD NOT BE ASSEMBLED

500 0 501 0 502 0 Agilent E5387-68701

503 0 TBD TBD RES. SMT, 2512

504 0 Maxium DS4100H+ IC, HCSL, OSC, 100MHz 505 0 TBD TBD RES. SMT, 0805 R4, R5, R13, R16

506 0 TBD TBD CAP. SMT 0603 C253, C254 507 0 TBD TBD RES. SMT, 0402 R75, R76

20 0 Lumex 65 0 Panasonic 22 0 53 0 Panasonic ERJ-S02F3900X RES 390 OHM 5% SMT, 0402

200 0 Lumex LDS-A516RI

31 0 Panasonic EXB-2HV221JV

8 0 Fairchild MM74HC164MX

103 0 Panasonic

40 0 Panasonic 45 0 Panasonic

Concord

Electronics

Concord

Electronics

CML Innovative

Technologies

09-9127-1-0210 09-9127-1-0212

SML-

LXT0805GW-TR

ERJ-

2RKF1500X

7016X5/7

ECJ-

0EB1C103K

ERJ-

3GEYJ102V

ERJ-

3GEYJ103V

CONN, banana jack, black

color

CONN, banana jack, red

color

Midbus LAI 48-pin header

shroud

LED, green color SMT, 0805 D6, D7

RES 150 OHM 1% SMT, 0402 R31, R32

LED, dual color,

genn/yelow

7-SEGMENT display, red,

common anode,

0.75"x0.48"

Resistor Network, 220 ohm

8R isolated

IC, 8-bit serial in/parallel-

out shift register

CAP 0.01uf 16V 10% X7R SMT, 0402

RES. 1K OHM 5% SMT, 0603

RES 10K OHM 1% SMT, 0603

TH BJ3, BJ6, BJ9 TH BJ4, BJ5, BJ10 TH JP6

R15, R18, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R36, R39, R40, R46, R48, R51,

SMT, 10-pin

LCCC

SMT, 4-pin D15, D19, D23, D27

R222, R223, R230, R231, R238,

R239, R246.R247

10-pin DIP

SMT, 16-pin

SMT, SO14

DS19, DS20, DS23, DS24, DS27,

DS28, DS31, DS32,

RN32, RN33, RN36, RN3, RN40,

RN41, RN44, RN45,

U47, U48, U51, U52, U55, U56,

C235, C236, C237, C238, C239,

C240, C241, C242

R522, R523, R524, R525, R526,

R527, R528, R529

R477, R478, R479, R480, R481,

R482, R483, R484,

R52, R55

U98

U59, U60

Item

Qty Man. Man. Part # Description Package Type Component Designator(s)

#

104 0 Kemet

42 0 Panasonic

214 0 FCI

106 0 AVX TAJC226K020R

54 0 Panasonic ERJ-2GEJ472X RES 4.7K OHM 5% SMT, 0402 R212, R213, R214, R215, 26 0 AMP 767054-1

C0402C104K8P

ACTU

ERJ-

3GEYJ121V

10018783-

10003TLF

CAP 0.1UF 10V X5R SMT, 0402

RES. 120 OHM 5% SMT, 0805

Conn. X16 PCIe card edge

connector Vertical , 164-

pin 1mm pitch

CAP 22UF 20V 10%

Tantalum

Connector, 38-pin Mictor

connector, vertical

TH, 164-pin

SMT, C Case

SMT, vertical JP9, JP11

C287, C288, C289, C290, C291, C292, C293, C294, C492, C493, C494, C495, C496, C497, C498,

C499

R536, R537, R538, R539, R546,

R547, R548, R549,

SLOT12, SLOT13, SLOT14,

SLOT15

C201, C203, C205, C206, C207,

C208, C209, C210,

NOTES

A. R277, R314, R315, R407and R408 are placed at pad 1 and 3 B. Header JP13 jump 1-2,3-4 and 5-6 C. 2"x1/4" label with wording "PEX8615BA-BB4U1D RDK", place it at the upper right hand corner in the box E. R343, R345, R360 and R361 are used for rework the board (see assembly instructions for details)

5

D D

4

PORT ID

3

2

PORT ID

1

JTAG

I2C

POER WIDTH

SLOT11

PCIe[7:4]

SLOT8

SLOT7

SLOT9SLOT10

SLOT5SLOT6

SLOT4

PCIe[3:0]

SLOT1

SLOT2SLOT3

CONFIG RECEPTACLE CONFIG RECEPTACLE

C C

8615

x1

x1x1

x1

CONFIG RECEPTACLE

MidBus Connector

USER STATUS

x1

x1x1

x1

TEMPERATURE

B B

x1x1

PORT ID

XC3S200

POER WIDTH

EPROM

A A

PLX TECHNOLOGY, INC.

870 W Maude Ave, Sunnyvale, CA 94085

870 W Maude Ave, Sunnyvale, CA 94085 www.plxtech.com

www.plxtech.com

Title

Size Document Number Rev

Size Document Number Rev C

C

C Date: Sheet

Date: Sheet

5

4

3

2

Date: Sheet

www.plxtech.com

8615 Base Board RDK

91-0132-000-A 0

1

126Thursday, February 12, 2009

of

5

4

3

2

1

RELEASE NOTES:

Initial Release: Apr 18, 2008

Release 0.1: May 15, 2008

- changed the RefClock Fanout Buffer to MC100LVEP111

- Chnaged the Xilinx FPGA part from XCS40XL to XC3S200 and the associated prom

- Added the Multioutput Voltage regulator for the new Xilin FPGA

D D

- Updated the JTAG interface to USB to conform to latest Xilinx Tools

Release 0.2: March 9, 2009

- changed the R510 from 120 ohm to 1K ohm on page 6

C C

B B

A A

PLX TECHNOLOGY, INC.

870 W Maude Ave, Sunnyvale, CA 94085

870 W Maude Ave, Sunnyvale, CA 94085 www.plxtech.com

www.plxtech.com

Title

Size Document Number Rev

Size Document Number Rev C

C

C Date: Sheet

Date: Sheet

5

4

3

2

Date: Sheet

www.plxtech.com

8615 Base Board RDK

91-0132-000-A 0

1

226Monday, March 09, 2009

of

5

4

3

2

1

RELEASE NOTES:

D D

C C

B B

A A

PLX TECHNOLOGY, INC.

870 W Maude Ave, Sunnyvale, CA 94085

870 W Maude Ave, Sunnyvale, CA 94085 www.plxtech.com

www.plxtech.com

Title

Size Document Number Rev

Size Document Number Rev C

C

C Date: Sheet

Date: Sheet

5

4

3

2

Date: Sheet

www.plxtech.com

8615 Base Board RDK

91-0132-000-A 0

1

326Thursday, February 12, 2009

of

5

ATX HD POWER CONNECTORS

12V_A

TV1

J1

+12VDC

COM0

COM1

D D

+5VDC

15244449J115244449

J3

+12VDC

COM0

COM1

+5VDC

15244449J315244449

CPERST_n[16]

C C

DEBUG_NORMAL_n[26]

TV1

Prototyping Pad

1

2

3

4

1

2

3

4

3.3VCC

TV3

Prototyping Pad

TV5

Prototyping Pad

TV7

Prototyping Pad

R59 0R59 0

R9

4.7KR94.7K

8A

+

C2

C4

C3

C3 22uF

22uF

5V_A

4A

C9

C9 22uF

22uF

12V_A

8A

C17

C17 22uF

22uF

5V_A

4A

C29

C29 22uF

22uF

SW15 SW DIP-4SW15 SW DIP-4

5 6 7 8

C4

1uFC21uF

22uF

C11

+

C10

C10 1uF

1uF

22uF

+

C18

C20

C20 1uF

1uF

22uF

C30

C25

+

1uF

22uF

4

SW1 SETTINGS:

3

1: OFF

2

2: ON

1

J2

1

+12VDC

+

C1 1uFC11uF

2

COM0

3

COM1

4

C12

C12 1uF

1uF

C19

C19 1uF

1uF

C26

C26 1uF

1uF

+5VDC

15244449J215244449

J4

+12VDC

+5VDC

15244449J415244449

COM0

COM1

1

2

3

4

SW PUSHBUTTON

+

TV2

Prototyping Pad

TV4

Prototyping Pad

TV6

Prototyping Pad

TV8

Prototyping Pad

3.3VCC

S1

1 3

R57

R57 51K

51K

8A

4A

8A

4A

R58

R58 10K

10K

42

4

12V_A

C5

C5 22uF

22uF

5V_A

C14

C14 22uF

22uF

12V_A

C22

C22 22uF

22uF

5V_A

C31

C31 22uF

22uF

MAN_PST_S3

+

C6

C7

1uFC61uF

22uF

C13

C15

+

1uF

22uF

+

C23

C21

C21 1uF

1uF

22uF

+

C27

C32

1uF

22uF

3.3VCC

RESET CIRCUIT

U17

5

VCC

Y

1

A

2

GND

B

NC7S08

3

12V_A

TV45

1

2

3

4

1

2

3

4

U18

RST IN3VCC

RESET#

SRT4GND

MAX6420

TV45

Prototyping Pad

8A

TV46

Prototyping Pad

4A

TV43

Prototyping Pad

8A

TV44

Prototyping Pad

4A

5

PERST#_9

1

2

5V_A

12V_A

5V_A

3.3VCC

C299

C299 22uF

22uF

C300

C300 22uF

22uF

C303

C303 22uF

22uF

C304

C304 22uF

22uF

C87

0.1uF

+

R61 0R61 0

+

C302

C307

1uF

C301

C301 1uF

1uF

C306

C306 1uF

1uF

C305

C305 1uF

1uF

C307 22uF

22uF

C308

R15NLR15

1uF

NL

+

C309

+

C309 22uF

22uF

C295

C295 22uF

22uF

C297

C297 22uF

22uF

R60

5.1K

C310

C310 1uF

1uF

+

C296

C296 1uF

1uF

+

C298

C298 1uF

1uF

C37 IS USED TO SET THE RESET TIMEOUT PERIOD FOR U18. A VALUE OF 0.001UF RESULTS IS APPROXIMATELY 3MS. SEE MANUFACTURER DATASHEET FOR DETAILS.

FPGA_PEX_PERST_n [26]

R55NLR55

NL

J7

C8

1uFC81uF

1uF

0.001uF

+12VDC

COM0

COM1

+5VDC

C16

15244449J715244449

J8

+12VDC

C24

COM0

COM1

+5VDC

C28

15244449J815244449

RST_8

SRT_8

C88

+

4

3

2

3.3VCC 12V_A35V_A

R48NLR48

R52NLR52

R51NLR51

NL

TV57

Prototyping Pad

R18NLR18

R19NLR19

NL

PS_ON_n[26]

1 2 3 4 5 6 7 8

9 10 11 12

The Circuit on Board is Designed to provides Enough Load for all RAILS. These Resistor are there Just in Case the Power Supply Continues to Trip Because of Min Load Requirement

Place the shunt in position 1 and 3

12V_A212V_A1

J10

8

GND1

12V2_2

7

GND2

12V2_1

6

GND3

12V1_2

5

GND4

12V1_1

ATX 4plus4 Proc 12V Conn

+3.3V_1 +3.3V_2 COM_1 +5V_1 COM_2 +5V_2 COM_3 PG +5VSB +12V_1 +12V_2 +3.3V_3

J9

ATX-400P24J9ATX-400P24

1 2 3 4

+3.3V_4

COM_4 COM_5

COM_6 COM_7

COM_8

3

PS-ON

+5V_3 +5V_4 +5V_5

R277

0 Shunt

1

PS_Pwr_good [23,26]

13 14

-12V

15 16 17 18 19 20

-5V

21 22 23 24

12

TV50

Prototyping Pad

TV56

Prototyping Pad

PEX8615 VOLTAGE MONITOR CIRCUIT

ISL6132

D7 is green: 2.5VCCis within the 10%range D7 is red: 2.5VCC is out of range

12V_SLT_12

12V_SLT_13

Title

Size Document Number Rev

Size Document Number Rev C

C

C Date: Sheet

Date: Sheet

3.3VCC

R33 4.7KR33 4.7K R35 4.7KR35 4.7K

23

U16

20

UVMON_1

12

OVMON_1

17

UVMON_2

14

OVMON_2

1

EN1

11

EN2

3

NC9

4

NC8

D8

12V_SLT_14

8615 Base Board RDK

UVSTATUS_1

VDD

OVSTATUS_1 UVSTATUS_2 OVSTATUS_2

NC113NC215NC316NC418NC519NC621NC7

NC0

8

R49

R49 390

390

21

43

G

R

G

R

GREEN_RED_LED

12V_SLT_15

PLX TECHNOLOGY, INC.

870 W Maude Ave, Sunnyvale, CA 94085

870 W Maude Ave, Sunnyvale, CA 94085 www.plxtech.com

www.plxtech.com

91-0132-000-A 0

PGOOD2

22

PGOOD

GND

10

C85

0.1uF

3.3VCC

R50

R50 390

390

PWRGD_2p5

D10

1

2 5 6 7

24 9

R53

R53 390

390

43

R

RN1

6 7 8

4.7K

3.3VCC

21

G

GREEN_RED_LED

D8 is green: 1.0VCC is withinthe 10% range D8 is red: 1.0VCC is out of range

426Thursday, February 12, 2009

of

3.3VCC

45 3 2 1

R54

R54 390

390

PWRGD_1p0

C42

10uF

C45

10uF

Prototyping Pad

Prototyping Pad Prototyping Pad

Prototyping Pad

2 1

GREEND9GREEN

2 1

GREEND4GREEN

2 1

GREEND6GREEN

2 1

GREEND1GREEN

2 1

TV12

TV12 TV21

TV21 TV20

TV20 TV24

TV24

1.0VCC

1.0VCC_A

GREEND3GREEN

GREEND5GREEN

GREEND7GREEN

GREEND2GREEN

C44

1uF

C46

1uF

5V_A

5V-TO-1.0V DC/DC CONVERTER

U2

4

5

Trim

7

Trim up

V7AH-08B1A0

4

5

Trim

7

Trim up

V7AH-08B1A0

8A

R7

8A

R11

TV11

Prototyping Pad

TV16

Prototyping Pad

TV19

Prototyping Pad

TV25

Prototyping Pad

R34 374 1%R34 374 1% R28 499 1%R28 499 1% R29 374 1%R29 374 1% R30 374 1%R30 374 1% R31 150R31 150 R32 150R32 150

R1 1.2KR1 1.2K R2 360R2 360

R4 NLR4 NL

36.5K 1%R736.5K 1%

R5 NLR5 NL

36.5K 1%

C34 180uF

180uF

B B

C35

C35 180uF

180uF

Prototyping Pad

Prototyping Pad Prototyping Pad

Prototyping Pad

A A

POWER INDICATOR LEDS Place these next to appropriate voltage source. Silkscreen should lable these

POWER INDICATOR LEDS Place these next to appropriate Connectors

1

On/Off#

Gnd

NC06NC1

3

5V_A

5V-TO-1.0V_A DC/DC CONVERTER

U3

Vin2Vout

+

1

On/Off#

Gnd

NC06NC1

3

TV10

TV9

TV9 TV14

TV14 TV17

TV17 TV27

TV27

TV10

Prototyping Pad

TV15

Prototyping Pad

TV18

Prototyping Pad

TV28

Prototyping Pad

3.3VCC1

3.3VCC

2.5VCC_A

2.5VCC

1.0VCC_A

1.0VCC

12V_A 5V_A

5

Vin2Vout

+

C34

1.0v +F

1.0VCC1.0VCC_A3.3VCC 2.5VCC2.5VCC_A

D9

D4 D5 D6 D7

D1

1.0v +F

1.0VCC_A

BJ5

BJ5 red

red BJ6

BJ6 black

black

Prototyping Pad

Prototyping Pad Prototyping Pad

Prototyping Pad

D3

D2

1.0v -F

1

TV13

TV13 TV22

TV22 TV23

TV23 TV26

TV26

1.0VCC

BJ4

BJ4 red

red BJ3

BJ3 black

black

5V_A

1

+

C36

C36 180uF

180uF

1

C63

1uF

2.5V_A LDO

Prototyping Pad

Prototyping Pad Prototyping Pad

Prototyping Pad

5V-TO-3.3V DC/DC CONVERTER

U4

4

5

Trim

7

Trim up

V7AH-08B1A0

4

5

Trim

7

Trim up

V7AH-08B1A0

2.5VCC_A2.5VCC

C71

1uF

12V_A

3.3VCC

12V_A3

8A

R13 NLR13 NL

R12

1.21K 1%

8A

R16 NLR16 NL

R14

2K 1%

R23NLR23

NL

Vin2Vout

1

On/Off#

Gnd

NC06NC1

3

5V-TO-2.5V DC/DC CONVERTER

U5

Vin2Vout

1

On/Off#

Gnd

NC06NC1

3

0.0 Ohm

R10

TV55

TV55 TV54

TV54 TV51

TV51 TV53

TV53 TV52

TV52 TV33

TV33 TV34

TV34 TV49

TV49 TV48

TV48

R10

4

C67

10uF

NL

3.3VCC1

1.0VCC 2.5VCC

R38

R37

C47

C48

10uF

1uF

2.5VCC5V_A

2.5VCC

1

2.5v -F

C64

10uF

R21NLR21

R22NLR22

NL

BJ10

BJ10 red

red

C65

BJ9

BJ9 black

black

1uF

1

12V_A2

R20NLR20

NL

12V_SLT_1

3

R27NLR27

NL

12V_SLT_2

3.3VCC_SLT_2_3

R26NLR26

NL

12V_SLT_3

R25NLR25

NL

12V_SLT_4

R24NLR24

NL

12V_SLT_5

3.3VCC_SLT_6_7

12V_SLT_6

2 hotplug

3.3VCC_SLT_83.3VCC_SLT_1

12V_A1

R46NLR46

NL

12V_SLT_7

R40NLR40

NL

2 hotplug

12V_SLT_8

3.3VCC_SLT_9

R39NLR39

NL

12V_SLT_9

3.3VCC_SLT_10_113.3VCC_SLT_4_5

2

3.09K 1%

R36NLR36

NL

12V_SLT_10

R37

R411.18K 1% R411.18K 1%

R455.76K 1% R455.76K 1%

12V_SLT_11

3.3VCC_SLT_12_13

7.32K 1%

R43

464 1%

464 1% R47

R47

2.32K 1%

3.3VCC_SLT_14_15

5

3.3VCC

4

3

2

1

REFCLK CLOCK BUFFER CIRCUITS

R343

7.32K 1%

D D

C C

7.32K 1%

R345

R360

1.0K 1%

1.0K 1% 20K

20K

CREFCLKRECEPT0_p[16] CREFCLKRECEPT0_n[16]

R293 4.7R293 4.7

C319

C318

10uF

0.01uF

R312 5.1KR312 5.1K R309 5.1KR309 5.1K

R310 5.1KR310 5.1K R313 5.1KR313 5.1K

R308 5.1KR308 5.1K R307 5.1KR307 5.1K

0.01uF

U28

2 3

8

21 17

16 15 12 25

13 14

CY28400-2

28

VDD_A

SRC_IN SRC_IN#

OE_1 OE_6

HIGH_BW# SRC_STP PWRDWN PLL/BYPASS# OE_INV

SCLK SDATA

27

R361

20K

3.3VCC

R314

12

3

R315

R315 0 Shunt

0 Shunt

12

3

R311 0 Shunt

0 Shunt

12

3

0 Shunt

24

VDD01VDD15VDD211VDD318VDD4

VSS

VSS_A

4

DIFT1

DIFC1

DIFT2

DIFC2

DIFT5

DIFC5

DIFT6

DIFC6

IREF

C316

0.01uF

6 7

9 10

20 19

23 22

26

C317

0.01uF

R302 33R302 33 R306 33R306 33

R297 33R297 33 R301 33R301 33

R300 33R300 33 R299 33R299 33

R291 33R291 33 R289 33R289 33

R292

475 1%

R294

49.9

3.3VCC

R290

49.9

C315

C315 10uF

10uF

R296

49.9

R305

49.9

R304

49.9

R298

Place these CAPS as close to the destination as possible

C444

C445

C446

0.1uF

0.1uF C447

C447

0.1uF

C448

0.1uF

0.1uF C449

C449

0.1uF

C451

0.1uF

C450

0.1uF

R303

R295

49.9

RCKp_PEX8615 [7] RCKn_PEX8615 [7]

SSC_CK1p [6] SSC_CK1n [6]

SSC_CK2p [6] SSC_CK2n [6]

TPV27 Prototyping PadTPV27 Prototyping PadR311 TPV24 Prototyping PadTPV24 Prototyping Pad

3.3VCC

Y2 25MHzY2 25MHz

678

4 5

4R 4.7K

12

C327

C327 18pF

18pF

RN55

123

B B

A A

C328

C328 22pF

22pF

5

3.3VCC

U108

1

S0

2

S1

3

NC0

4

X1/CLK

5

X2

6

OE

7

GND0 NC18IREF

NB3N5573

U98NLU98

1

OE

2

RREF

3

GND

C159

0.01uF

VDD1

CLK0#

GND1 VDD0

CLK1#

VCC OUTP OUTN

NC07NC18NC29NC3

10

C158

0.01uF

16

R63 33R63 33

15

CLK0

14 13 12 11

CLK1

10 9

6 4 5

NL

No Load Components.

R6533R65

33

R79

R79 475 1%

475 1%

R75 NLR75 NL R76 NLR76 NL

CFC_Clk_p CFC_Clk_n

R73

R74

49.9

3.3VCC

R320 4.7R320 4.7

C325

C326

0.01uF

10uF

3.3VCC

R338 5.1KR338 5.1K R336 5.1KR336 5.1K

R407

12

R408

R408 0 Shunt

0 Shunt R344

R344 0 Shunt

0 Shunt

12

R337 5.1KR337 5.1K R374 5.1KR374 5.1K

R335 5.1KR335 5.1K R334 5.1KR334 5.1K

3

4

U61

2

SRC_IN

3

SRC_IN#

8

OE_1

21

OE_6

17

HIGH_BW#

16

SRC_STP

15

PWRDWN

12

PLL/BYPASS#

25

OE_INV

13

SCLK

14

SDATA

CY28400-2

28

VDD_A

27

24

VDD01VDD15VDD211VDD318VDD4

VSS

VSS_A

4

DIFT1

DIFC1

DIFT2

DIFC2

DIFT5

DIFC5

DIFT6

DIFC6

C321

0.01uF

6 7

9 10

20 19

23 22

26

IREF

C324

0.01uF

R329 33R329 33 R333 33R333 33

R324 33R324 33 R328 33R328 33

R327 33R327 33 R326 33R326 33

R318 33R318 33 R316 33R316 33

R319

475 1%

3

R321

49.9

3.3VCC

R317

49.9

C320

C320 10uF

10uF

R323

49.9

R332

49.9

R331

49.9

R325

Place these CAPS as close to the destination as possible

C462

C463

C464

0.1uF

0.1uF C465

C465

0.1uF

C466

0.1uF

0.1uF C467

C467

0.1uF

C468

C469

0.1uF

R330

R322

49.9

2

0.1uF

CFC_RCKp_PEX8614 [7] CFC_RCKn_PEX8614 [7]

CFC_CK1p [6] CFC_CK1n [6]

CFC_CK2p [6] CFC_CK2n [6]

TPV25

Prototyping Pad

TPV26 Prototyping PadTPV26 Prototyping Pad

PLX TECHNOLOGY, INC.

870 W Maude Ave, Sunnyvale, CA 94085

870 W Maude Ave, Sunnyvale, CA 94085 www.plxtech.com

www.plxtech.com

Title

Size Document Number Rev

Size Document Number Rev C

C

C Date: Sheet

Date: Sheet

www.plxtech.com

8615 Base Board RDK

91-0132-000-A 0

1

526Thursday, February 12, 2009

of

5

SSC_ISO_EN_n[8]

A LOW on SEL selects CLK0

4

3

2

1

3.3VCC

C339

C341

0.01uF

C340

0.01uF

C339 10uF

10uF

3.3VCC

D D

SSC_CK1p[5] SSC_CK1n[5]

CFC_CK1p[5] CFC_CK1n[5]

C C

B B

SSC_CK2p[5] SSC_CK2n[5]

CFC_CK2p[5] CFC_CK2n[5]

3.3VCC

R450

R464

7.32K

R449

R460

25

32

U113

C452

R557

R557 120

120

R568

R568 120

120

R558

R558 120

120

R569

R569 120

120

C452

C454

0.1uF

0.1uF C456

C456

0.1uF

0.1uF C458

C458

0.1uF

0.1uF C460

C460

0.1uF

0.1uF C470

C470

0.1uF

0.1uF C472

C472

0.1uF

0.1uF C474

C474

0.1uF

0.1uF C476

C476

0.1uF

0.1uF C478

C478

0.1uF

C480

C482

0.1uF

0.1uF C484

C484

0.1uF

0.1uF C486

C486

0.1uF

0.1uF C488

C488

0.1uF

0.1uF C490

C490

0.1uF

VCC_11VCC_29VCC_316VCC_4

MC100LVEP111

U114

VCC_11VCC_29VCC_316VCC_4

MC100LVEP111

C336

C336 10uF

10uF

VCC_5

31

Q0

30

Q0

29

Q1

28

Q1

27

Q2

26

Q2

24

Q3

23

Q3

22

Q4

21

Q4

20

Q5

19

Q5

18

Q6

17

Q6

15

Q7

14

Q7

13

Q8

12

Q8

11

Q9

10

Q9

5

VBB

R562

R550

R551

R552

R553

R561

R561 120

120

R533

R533 120

120

R563

R563 120

120

R553 120

120

R534

R534 120

120

R559

R560

120

25

32

VCC_5

31

Q0

30

Q0

29

Q1

28

Q1

27

Q2

26

Q2

24

Q3

23

Q3

22

Q4

21

Q4

20

Q5

19

Q5

18

Q6

17

Q6

15

Q7

14

Q7

13

Q8

12

Q8

11

Q9

10

Q9

5

VBB

R530

R530 120

120

R531

R531 120

120

R532

R532 120

120

R564

R564 120

120

R554

R554 120

120

R535

R535 120

120

R565

R565 120

120

R555

R555 120

120

R566

R566 120

120

R556

R556 120

120

R567

R567 120

120

R452

R451

10K

7.32K

R454

R453

7.32K

R455

R456

10K

2

SEL

6

CLK1

7

CLK1

3

CLK0

4

CLK0

8

VEE

3.3VCC

C337

C338

0.01uF

R461

R462

R463

7.32K

R457

R458

R459

10K

2

SEL

6

CLK1

7

CLK1

3

CLK0

4

CLK0

8

VEE

C453

C455

0.1uF

0.1uF C457

C457

0.1uF

0.1uF C459

C459

0.1uF

0.1uF C461

C461

0.1uF

0.1uF C471

C471

0.1uF

0.1uF C473

C473

0.1uF

0.1uF C475

C475

0.1uF

0.1uF C477

C477

0.1uF

0.1uF C479

C479

0.1uF

C481

C483

0.1uF

0.1uF C485

C485

0.1uF

0.1uF C487

C487

0.1uF

0.1uF C489

C489

0.1uF

0.1uF C491

C491

0.1uF

R5101KR510

R485

R486

R487

R488

R4351KR435 1K

R488

10K

R4371KR437

R4361KR436

1K

R4341KR434 1K

10K

3.3VCC

R468

R467

R466

R465

10K

1K

R5111KR511 1K

10K

R5121KR512

R5131KR513

1K

R4381KR438 1K

R5141KR514 1K

R494

R469

R490

R491

R492

R493

R495

R496

R4431KR443 1K

R5191KR519 1K

R474

R496

10K

R4441KR444

R4451KR445

1K

R475

R476

10K

R5201KR520

R5211KR521

1K

R489

10K

R4401KR440 1K

R5151KR515 1K

R471

10K

R4411KR441

R4421KR442

1K

R472

R473

10K

R5171KR517

R5181KR518

1K

10K

R4391KR439 1K

R470

10K

R5161KR516 1K

R4461KR446 1K

R497

R504

R498

R499

10K

R4471KR447

R4481KR448

R5051KR505

1K

R5061KR506 1K

R500

R502

R503

R501

10K

R5071KR507 1K

10K

LAI_RefClk_p [7] LAI_RefClk_n [7]

TPV28

Prototyping Pad

Prototyping Pad TPV29 Prototyping PadTPV29 Prototyping Pad TPV30

TPV30

Prototyping Pad

Prototyping Pad TPV31 Prototyping PadTPV31 Prototyping Pad TPV33

TPV33

Prototyping Pad

Prototyping Pad TPV32 Prototyping PadTPV32 Prototyping Pad TPV35

TPV35

Prototyping Pad

Prototyping Pad TPV34 Prototyping PadTPV34 Prototyping Pad

RCKp_SL1

RCKp_SL1 [9]

RCKn_SL1

RCKn_SL1 [9]

RCKp_SL2

RCKp_SL2 [9]

RCKn_SL2

RCKn_SL2 [9]

RCKp_SL3

RCKp_SL3 [10]

RCKn_SL3

RCKn_SL3 [10]

RCKp_SL4

RCKp_SL4 [10]

RCKn_SL4

RCKn_SL4 [10]

RCKp_SL5

RCKp_SL5 [11]

RCKn_SL5

RCKn_SL5 [11]

R5081KR508

R5091KR509

1K

RCKp_SL6

RCKp_SL6 [11]

RCKn_SL6

RCKn_SL6 [11]

RCKp_SL7

RCKp_SL7 [12]

RCKn_SL7

RCKn_SL7 [12]

RCKp_SL8

RCKp_SL8 [12]

RCKn_SL8

RCKn_SL8 [12]

RCKp_SL9

RCKp_SL9 [13]

RCKn_SL9

RCKn_SL9 [13]

RCKp_SL10

RCKp_SL10 [13]

RCKn_SL10

RCKn_SL10 [13]

RCKp_SL11

RCKp_SL11 [14]

RCKn_SL11

RCKn_SL11 [14]

10K

R542

R540 120

A A

5

4

120

R542

R541

R540

R543

R543 120

120

R544

R544 120

120

R545

R545 120

120

PLX TECHNOLOGY, INC.

870 W Maude Ave, Sunnyvale, CA 94085

870 W Maude Ave, Sunnyvale, CA 94085 www.plxtech.com

www.plxtech.com

Title

Size Document Number Rev

Size Document Number Rev C

C

C Date: Sheet

Date: Sheet

3

2

Date: Sheet

www.plxtech.com

8615 Base Board RDK

91-0132-000-A 0

1

626Monday, March 09, 2009

of

5

U100A

PEX 8615

R281

1.43K

1%

R282

1.43K

1%

R283

1.43K

1%

R284

1.43K

1%

U10

PEX_REFCLKp

V10

PEX_REFCLKn

P10

NC4

R10

REXT_A0

N11

REXT_B0

J17

NC0

J18

NC1

J14

NC5

J15

REXT_A1

H13

REXT_B1

B9

PEX_REFCLK_CFCp

A9

PEX_REFCLK_CFCn

E9

NC6

D9

REXT_A2

F8

REXT_B2

K1

NC2

K2

NC3

K5

NC7

K4

N/C

L6

N/C

PEX 8615

PEX_PETp0

PEX_PETn0 PEX_PERp0 PEX_PERn0

PEX_PETp1

PEX_PETn1 PEX_PERp1 PEX_PERn1

PEX_PETp2

PEX_PETn2 PEX_PERp2 PEX_PERn2

PEX_PETp3

PEX_PETn3 PEX_PERp3 PEX_PERn3

PEX_PETp4

PEX_PETn4 PEX_PERp4 PEX_PERn4

PEX_PETp5

PEX_PETn5 PEX_PERp5 PEX_PERn5

PEX_PETp6

PEX_PETn6 PEX_PERp6 PEX_PERn6

PEX_PETp7

PEX_PETn7 PEX_PERp7 PEX_PERn7

PEX_PETp8

PEX_PETn8 PEX_PERp8 PEX_PERn8

PEX_PETp9

PEX_PETn9 PEX_PERp9 PEX_PERn9

PEX_PETp10 PEX_PETn10 PEX_PERp10 PEX_PERn10

PEX_PETp11 PEX_PETn11 PEX_PERp11 PEX_PERn11

RCKp_PEX8615[5] RCKn_PEX8615[5]

D D

CFC_RCKp_PEX8614[5] CFC_RCKn_PEX8614[5]

C C

B B

TV35

Prototyping Pad

TV36

TV36 TV37

TV37 TV38

TV38

Prototyping Pad

Prototyping Pad Prototyping Pad

Prototyping Pad

TV39

Prototyping Pad

TV40

TV40 TV41

TV41 TV42

TV42

Prototyping Pad

Prototyping Pad Prototyping Pad

Prototyping Pad

PET_p0

U8

PET_n0

V8

PER_p0

P8

PER_n0

R8

PET_p1

U9

PET_n1

V9

PER_p1

P9

PER_n1

R9

PET_p2

U11

PET_n2

V11

PER_p2

P11

PER_n2

R11

PET_p3

U12

PET_n3

V12

PER_p3

P12

PER_n3

R12

PET_p4

L18

PET_n4

L17

PER_p4

L15

PER_n4

L14

PET_p5

K18

PET_n5

K17

PER_p5

K15

PER_n5

K14

PET_p6

H18

PET_n6

H17

PER_p6

H15

PER_n6

H14

PET_p7

G18

PET_n7

G17

PER_p7

G15

PER_n7

G14

PET_p8

B11

PET_n8

A11

PER_p8

E11

PER_n8

D11

PET_p9

B10

PET_n9

A10

PER_p9

E10

PER_n9

D10

PET_p10

B8

PET_n10

A8

PER_p10

E8

PER_n10

D8

PET_p11

B7

PET_n11

A7

PER_p11

E7

PER_n11

D7 H1

N/C

H2

N/C

H4

N/C

H5

N/C

J1

N/C

J2

N/C

J4

N/C

J5

N/C

L1

N/C

L2

N/C

L4

N/C

L5

N/C

M1

N/C

M2

N/C

M4

N/C

M5

N/C

4

C2630.1uF C2630.1uF

C2640.1uF C2640.1uF

C2650.1uF C2650.1uF

C2660.1uF C2660.1uF

C2670.1uF C2670.1uF

C2680.1uF C2680.1uF

C2690.1uF C2690.1uF

C2700.1uF C2700.1uF

C2710.1uF C2710.1uF

C2720.1uF C2720.1uF

C2730.1uF C2730.1uF

C2740.1uF C2740.1uF

C2750.1uF C2750.1uF

C2760.1uF C2760.1uF

C2770.1uF C2770.1uF

C2780.1uF C2780.1uF

C2790.1uF C2790.1uF

C2800.1uF C2800.1uF

C2810.1uF C2810.1uF

C2820.1uF C2820.1uF

C2830.1uF C2830.1uF

C2840.1uF C2840.1uF

C2850.1uF C2850.1uF

C2860.1uF C2860.1uF

3

MIDBUS PROBE IS PUT ON Lane[15:8] Only

JP6

1

TX0+ TX0-3RX0+

5

GND0

7

TX1+

9

TX1-

11

GND1

13

TX2+

15

TX2-

17

GND2

19

TX3+

21

TX3-

23

GND3

25

TX4+

27

TX4-

29

GND4

31

TX5+

33

TX5-

35

GND5

37

TX6+

39

TX6-

41

GND6

43

TX7+

45

TX7-

47

GND7 DGND1G1DGND2

Midbus LAI

GND8

GND9

RX1+

GND10

RX2+

GND11

RX3+

GND12

RX4+

GND13

RX5+

GND14

RX6+

GND15

RX7+

2 4 6

RX0-

8 10 12

RX1-

14 16 18

RX2-

20 22 24

RX3-

26 28 30

RX4-

32 34 36

RX5-

38 40 42

RX6-

44 46 48

RX7-

G2

2

TX0p_RECEPT1 [22]

TX0n_RECEPT1 [22] RX0p_RECEPT1 [22] RX0n_RECEPT1 [22]

TX1p_RECEPT1 [22]

TX1n_RECEPT1 [22] RX1p_RECEPT1 [22] RX1n_RECEPT1 [22]

TX2p_RECEPT1 [22]

TX2n_RECEPT1 [22] RX2p_RECEPT1 [22] RX2n_RECEPT1 [22]

TX3p_RECEPT1 [22]

TX3n_RECEPT1 [22] RX3p_RECEPT1 [22] RX3n_RECEPT1 [22]

TX0p_RECEPT2 [22]

TX0n_RECEPT2 [22] RX0p_RECEPT2 [22] RX0n_RECEPT2 [22]

TX1p_RECEPT2 [22]

TX1n_RECEPT2 [22] RX1p_RECEPT2 [22] RX1n_RECEPT2 [22]

TX2p_RECEPT2 [22]

TX2n_RECEPT2 [22] RX2p_RECEPT2 [22] RX2n_RECEPT2 [22]

TX3p_RECEPT2 [22]

TX3n_RECEPT2 [22] RX3p_RECEPT2 [22] RX3n_RECEPT2 [22]

TX0p_RECEPT3 [22]

TX0n_RECEPT3 [22] RX0p_RECEPT3 [22] RX0n_RECEPT3 [22]

TX1p_RECEPT3 [22]

TX1n_RECEPT3 [22] RX1p_RECEPT3 [22] RX1n_RECEPT3 [22]

TX2p_RECEPT3 [22]

TX2n_RECEPT3 [22] RX2p_RECEPT3 [22] RX2n_RECEPT3 [22]

TX3p_RECEPT3 [22]

TX3n_RECEPT3 [22] RX3p_RECEPT3 [22] RX3n_RECEPT3 [22]

1

The TWO Mechanical Pins on the MidBusProbe should be tied to digital Ground

TMS-103-02-S-S

A A

5

4

LAI_RefClk_p[6] LAI_RefClk_n[6]

TMS-103-02-S-S

1

REFCLK+

3

REFCLK-

3

2

GND

JP100

PLX TECHNOLOGY, INC.

870 W Maude Ave, Sunnyvale, CA 94085

870 W Maude Ave, Sunnyvale, CA 94085 www.plxtech.com

www.plxtech.com

Title

Size Document Number Rev

Size Document Number Rev C

C

C Date: Sheet

Date: Sheet

2

Date: Sheet

www.plxtech.com

8615 Base Board RDK

91-0132-000-A 0

1

726Thursday, February 12, 2009

of

5

PEX_PERST_n[17,18,19,21,26]

PEX8615 JTAG PORT

JP3

2

PEX_JTAG_TRST_n PEX_JTAG_TCK PEX_JTAG_TMS PEX_JTAG_TDI PEX_JTAG_TDO

45

123

RN8

RN8 4R 4.7K

4R 4.7K

678

3.3VCC

R44

2.26K

1%

678

112 334 556 778 9910

HDR 5X2

123

RN5

RN5 4R 4.7K

4R 4.7K

3.3VCC

4 6 8 10

123

45

RN6

RN6 4R 4.7K

4R 4.7K

678

123

45

RN9

RN9 4R 4.7K

4R 4.7K

678

R285

12

3

0 Shunt

0 Shunt R286

R286

12

3

0 Shunt

0 Shunt R287

R287

12

3

0 Shunt

123

45

678

3.3VCC

RN3

1

8

2

7

3

6

4 5

4R 1K

D D

3.3VCC

EEPROM

U19

8

CS#

VCC

7

SI

HOLD#

3

SO

WP#

4

SCLK

GND

AT25256A

C C

SW2 SW DIP-4SW2 SW DIP-4

PORT_CFG0

4

5 6 7 8

5

B B

6 7 8

5 6 7 8

SW3 SW DIP-4SW3 SW DIP-4

SW4 SW DIP-4SW4 SW DIP-4

SW5 SW DIP-4SW5 SW DIP-4

SW6 SW DIP-4SW6 SW DIP-4

SW7 SW DIP-4SW7 SW DIP-4

I2C_ADDR0[25] I2C_ADDR1[25] I2C_ADDR2[25]

I2C_SCL0[26] I2C_SDA0[26]

I2C_SCL1[21] I2C_SDA1[21]

PORT_CFG1

3

PORT_CFG2

2

PORT_CFG3

1

UPSTR_PSEL0

4

UPSTR_PSEL1

3

UPSTR_PSEL2

2

UPSTR_PSEL3

1

NT_UPSTR_PSEL0

4

NT_UPSTR_PSEL1

3

NT_UPSTR_PSEL2

2

NT_UPSTR_PSEL3

1

SERDES_MODE__EN_n

4

PROBE_MODE_n

3

DEBUG_SEL0

2

NT_ENABLE_n

1

FAST_BRINGUP_n

4

GEN1_n

3

PP_BYPASS_n

2

SSC_ISO_EN_n

1

TESTMODE0

4

TESTMODE1

3

TESTMODE2

2

TESTMODE3

1

I2C HEADERS

JP8

2 4

HEADER 2X2

SCL1GND SDA3NC

A A

PEX_EE_CS_n

1

PEX_EE_DI

5

PEX_EE_DO

2

PEX_EE_CK

6

3.3VCC1

45

R42

2.26K

1%

5

RN10

RN10 4R 4.7K

4R 4.7K

4

3.3VCC

678

RN4

RN4 4R 4.7K

4R 4.7K

123

4 5

123

45

RN7

TV47

4R 4.7K

Prototyping Pad

678

4

U100B

P17

PEX_PERST#

P16

PEX_NT_RESET#

D15

JTAG_TRST#

B15

JTAG_TCK

C14

JTAG_TMS

E14

JTAG_TDI

C15

JTAG_TDO

R18

EE_SK

R17

EE_CS

N15

EE_DI

N16

EE_DO

A5

STRAP_PORTCFG0

A4

STRAP_PORTCFG1

B2

STRAP_PORTCFG2

C13

STRAP_PORTCFG3

E2

STRAP_UPSTRM_PORTSEL0

F3

STRAP_UPSTRM_PORTSEL1

F2

STRAP_UPSTRM_PORTSEL2

E1

STRAP_UPSTRM_PORTSEL3

N18

STRAP_NT_ENABLE#

P1

STRAP_NT_UPSTRM_PORTSEL0

P2

STRAP_NT_UPSTRM_PORTSEL1

R1

STRAP_NT_UPSTRM_PORTSEL2

P6

STRAP_NT_UPSTRM_PORTSEL3

C4

STRAP_SERDES_MODE_EN#

T17

STRAP_PROBE_MODE#

N17

STRAP_DEBUG_SEL0

C2

STRAP_FAST_BRINGUP#

F1

STRAP_RESERVED17#

R15

STRAP_PLL_BYPASS#

U3

STRAP_SSC_ISO_ENABLE#

V14

STRAP_TESTMODE0

V15

STRAP_TESTMODE1

V16

STRAP_TESTMODE2

U17

STRAP_TESTMODE3

C18

I2C_ADDR0

E17

I2C_ADDR1

E18

I2C_ADDR2

C17

I2C_SCL0

A17

I2C_SDA0

B16

I2C_SCL1

C16

I2C_SDA1

VSS0A1VSS1A2VSS2A3VSS3A6VSS4

PEX 8615

A12

A18

VSS5

VSS6B1VSS7B6VSS8

B12

2.5VCC

F13

N13

VDD250F6VDD251

VDD252N6VDD253

VSS15D6VSS14

VSS11

VSS9

VSS10

VSS12C8VSS13

C6

C1

B18

D12

C12

C10

PROBE_MODE_n DEBUG_SEL0 [25] UPSTRM_PSEL3 [25] SSC_ISO_EN_n [6]

C89

1uF

C96

0.01uF

C103

C103 1000pF

1000pF

2.5VCC_A

VSS17E6VSS16

E12

3

C90

1uF

C97

0.01uF

C105

C104

C104 1000pF

1000pF

C121

1uF

C129

0.01uF

C131

C131 1000pF

1000pF

J13

N10

F11

VDD10_0F7VDD10_1

VDD25A0F9VDD25A1

VDD25A2K6VDD25A3

VSS24

VSS23

VSS22

VSS21

VSS20

VSS19F5VSS18

F18

F17

F16

F15

F14

F10

C122

1uF

C130

0.01uF

C132

C132 1000pF

1000pF

F12

3

VDD10_2

VDD10_3G6VDD10_4

1000pF

G13

C139

C139 1000pF

1000pF

L13

VDD10_5H6VDD10_6

VDD10_7M6VDD10_8

M13

C108

C108 1000pF

1000pF

N7

VDD10_9

VDD10_10N8VDD10_11

VSS34

VSS33G9VSS32G8VSS31G7VSS30G5VSS29G4VSS28G3VSS27G2VSS26G1VSS25

G10

N12

G11

C140

C140 1000pF

1000pF

VSS35

G12

VDD10A_0C7VDD10A_1C9VDD10A_2

VSS39H9VSS38H8VSS37H7VSS36

C11

G16

J16

VDD10A_3

VDD10A_4H3VDD10A_5

VSS41

VSS43

VSS40

H12

H11

H16

H10

1.0VCC

C91

C92

1uF

C100

C99

0.01uF

C109

C110

1000pF

1.0VCC_A

C123

1uF

C133

0.01uF

C141

C141 1000pF

1000pF

L16

T8

T10

T12

VDD10A_6K3VDD10A_7

VDD10A_8M3VDD10A_9

VDD10A_10

VDD10A_11

PEX 8615

VSS55

VSS54K9VSS53K8VSS52K7VSS51

VSS50

VSS49

VSS48J9VSS47J8VSS46J7VSS45J6VSS44J3VSS42

J12

J11

J10

K11

K10

C124

1uF

C134

0.01uF

C142

C142 1000pF

1000pF

VSS56

K12

VSS57

K13

2

C98

VSS67M7VSS68M8VSS70

C95

1uF

C106

0.01uF

C113

C113 1000pF

1000pF

VSS69M9VSS72

M10

C98

1uF

C107

0.01uF

C114

C114 1000pF

1000pF

C127

C128

1uF

C137

C138

0.01uF

C145

C146

1000pF

VSS71

VSS73

VSS74

VSS75

VSS76

M11

M12

M14

M15

M16

M17

M18

C93

C94

1uF

C101

C102

0.01uF

C111

C112

1000pF

C125

C126

1uF

C136

C135

0.01uF

C143

C144

1000pF

VSS60L3VSS59

VSS58

VSS61L7VSS63L9VSS65

VSS62L8VSS64

VSS66

L11

L10

L12

K16

2

Place 1000pf close to the pins. Sprinkle 0.01uf around the chip. Sprinkle 1uf around the chip

C115

C116

1000pF

C147

C148

1000pF

VSS77

VSS78N1VSS79N2VSS80N3VSS81N4VSS82N5VSS83N9VSS84

VSS85P7VSS86

VSS87R7VSS88

P13

N14

R13

C117

C118

1000pF

C150

C149

1000pF

PEX_LANE_GOOD10# PEX_LANE_GOOD11#

STRAP_RESERVED16

STRAP_UPCFG_TIMER_EN#

VSS89T7VSS90T9VSS91

VSS92

VSS93

VSS94U7VSS95

VSS96

VSS97V1VSS98V2VSS99V3VSS100V7VSS101

U1

T11

T13

U13

U18

PLX TECHNOLOGY, INC.

870 W Maude Ave, Sunnyvale, CA 94085

870 W Maude Ave, Sunnyvale, CA 94085 www.plxtech.com

www.plxtech.com

Title

Size Document Number Rev

Size Document Number Rev C

C

C Date: Sheet

Date: Sheet

www.plxtech.com

8615 Base Board RDK

91-0132-000-A 0

C119

C120

1000pF

C151

C151 1000pF

1000pF

GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8

GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21 GPIO22 GPIO23 GPIO24 GPIO25 GPIO26 GPIO27 GPIO28 GPIO29 GPIO30 GPIO31

PEX_LANE_GOOD0# PEX_LANE_GOOD1# PEX_LANE_GOOD2# PEX_LANE_GOOD3# PEX_LANE_GOOD4# PEX_LANE_GOOD5# PEX_LANE_GOOD6# PEX_LANE_GOOD7# PEX_LANE_GOOD8# PEX_LANE_GOOD9#

PEX_INTA#

FATAL_ERR#

THERMAL_DIODEp THERMAL_DIODEn

SHPC_INT#

SPARE0

SPARE1 STRAP_NT_P2P_EN# STRAP_SMBUS_EN#

SPARE5

VSS102

VSS103

VSS104

V13

V17

V18

D13

1

C152

C152 1000pF

1000pF

GPIO00

E4

GPIO01

D3

GPIO02

E3

GPIO03

D2

GPIO04

D1

GPIO05

F4

GPIO06

T3

GPIO07

R3

GPIO08

P4

GPIO09

P5

GPIO10

U2

GPIO11

U6

GPIO12

R6

GPIO13

V4

GPIO14

V5

GPIO15

V6

GPIO16

P14

GPIO17

T16

GPIO18

T15

GPIO19

R14

GPIO20

R16

GPIO21

P15

GPIO22

T18

GPIO23

D16

GPIO24

E15

GPIO25

B14

GPIO26

C3

GPIO27

C5

GPIO28

B5

GPIO29

B4

GPIO30

D5

GPIO31

D4

U14 T14 U16 U15 B17 D18 D17 E16 B3 A13 E13 E5 R2

N/C

P3

N/C

T1

N/C

T2

N/C

D14 T6

N/C

P18 B13

A14 A15 A16

R4 T4 R5

STRAP_NT_P2PEN# [25,26]

U4

STRAP_SMBUSEN# [25,26]

U5

STRAP_UPCFG_TR_EN# [25,26]

T5

1

GPIO00 [25,26] GPIO01 [25,26] GPIO02 [25,26] GPIO03 [25,26] GPIO04 [25,26] GPIO05 [25,26] GPIO06 [25,26] GPIO07 [25,26] GPIO08 [25,26] GPIO09 [25,26] GPIO10 [25,26] GPIO11 [25,26] GPIO12 [25,26] GPIO13 [25,26] GPIO14 [25,26] GPIO15 [25,26] GPIO16 [25,26] GPIO17 [25,26] GPIO18 [25,26] GPIO19 [25,26] GPIO20 [25,26] GPIO21 [25,26] GPIO22 [25,26] GPIO23 [25,26] GPIO24 [25,26] GPIO25 [25,26] GPIO26 [25,26] GPIO27 [25,26] GPIO28 [26] GPIO29 [25,26] GPIO30 [25,26] GPIO31 [26]

LN_GOOD_00_n [25,26] LN_GOOD_01_n [25,26] LN_GOOD_02_n [25,26] LN_GOOD_03_n [25,26] LN_GOOD_04_n [25,26] LN_GOOD_05_n [25,26] LN_GOOD_06_n [25,26] LN_GOOD_07_n [25,26] LN_GOOD_08_n [25,26] LN_GOOD_09_n [25,26] LN_GOOD_10_n [25,26] LN_GOOD_11_n [25,26]

NVM_VDDQ [23] PROCMON [25,26] PEX_INTA_n [26] FATAL_ERR_n [26]

TDIODE_p [23] TDIODE_n [23] SHPC_INT_n [21,26]

SPARE0 [25,26] SPARE1 [25,26]

SPARE5 [25,26]

826Thursday, February 12, 2009

of

5

12V_SLT_2

+

C181

22uF

3.3VCC_SLT_2_3 3.3VCC_SLT_2_3

3.3VCC

R201

4.7K

D D

PRSNT_n_SL2[26]

TX0p_SL2[22] TX0n_SL2[22]

PRSNT_n_SL2

TX0p_SL2 TX0n_SL2

4.7K

Wake_n[10,11,12,13,14,26] Wake_n[10,11,12,13,14,26]

C C

B B

4

SLOT 02 SLOT 01

SLOT2

PRSNT1#

+12V_3 +12V_4 GND34

TCLK

+3.3V_2 +3.3V_1

PERST#

GND35

REFCLK+

REFCLK-

GND36 PERp0 PERn0 GND37 RSVD3 GND38 PERp1 PERn1 GND39 GND40 PERp2 PERn2 GND41 GND42 PERp3 PERn3 GND43 RSVD4 RSVD5 GND44 PERp4 PERn4 GND45 GND46 PERp5 PERn5 GND47 GND48 PERp6 PERn6 GND49 GND50 PERp7 PERn7 GND51 RSVD6 GND52 PERp8 PERn8 GND53 GND54 PERp9 PERn9 GND55

GND56 PERp10 PERn10

GND57

GND58 PERp11 PERn11

GND59

GND60 PERp12 PERn12

GND61

GND62 PERp13 PERn13

GND63

GND64 PERp14 PERn14

GND65

GND66 PERp15 PERn15

GND67

A1 A2 A3 A4 A5 A6

TDI

A7

TDO TMS

+

C183

A8 A9 A10 A11

A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66 A67 A68 A69 A70 A71 A72 A73 A74 A75 A76 A77 A78 A79 A80 A81 A82

C183

22uF

PERST_n_SL2

RCKp_SL2 RCKn_SL2

RX0p_SL2 RX0n_SL2

PERST_n_SL2 [26]

RCKp_SL2 [6] RCKn_SL2 [6]

RX0p_SL2 [22] RX0n_SL2 [22]

B1

+12V_0

B2

+12V_1

B3

+12V_2

B4

GND0

B5

SMCLK

B6

SMDAT

B7

GND1

B8

+3.3V_0

B9

TRST#

B10

3.3VAUX

B11

WAKE#

B12

RSVD0

B13

GND2

B14

PETp0

B15

PETn0

B16

GND3

B17

PRSNT2#_0

B18

GND4

B19

PETp1

B20

PETn1

B21

GND5

B22

GND6

B23

PETp2

B24

PETn2

B25

GND7

B26

GND8

B27

PETp3

B28

PETn3

B29

GND9

B30

RSVD1

B31

PRSNT2#_1

B32

GND10

B33

PETp4

B34

PETn4

B35

GND11

B36

GND12

B37

PETp5

B38

PETn5

B39

GND13

B40

GND14

B41

PETp6

B42

PETn6

B43

GND15

B44

GND16

B45

PETp7

B46

PETn7

B47

GND17

B48

PRSNT2#_2

B49

GND18

B50

PETp8

B51

PETn8

B52

GND19

B53

GND20

B54

PETp9

B55

PETn9

B56

GND21

B57

GND22

B58

PETp10

B59

PETn10

B60

GND23

B61

GND24

B62

PETp11

B63

PETn11

B64

GND25

B65

GND26

B66

PETp12

B67

PETn12

B68

GND27

B69

GND28

B70

PETp13

B71

PETn13

B72

GND29

B73

GND30

B74

PETp14

B75

PETn14

B76

GND31

B77

GND32

B78

PETp15

B79

PETn15

B80

GND33

B81

PRSNT2#_4

B82

RSVD2

x16 PCI Express Contr

3

12V_SLT_1

+

C182

22uF

3.3VCC_SLT_1 3.3VCC_SLT_1

3.3VCC

TX0p_SL1[22] TX0n_SL1[22]

PRSNT_n_SL1

TX0p_SL1 TX0n_SL1

PRSNT_n_SL1[26]

R202

4.7K

B1 B2 B3 B4 B5 B6 B7 B8

B9 B10 B11

B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49 B50 B51 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 B63 B64 B65 B66 B67 B68 B69 B70 B71 B72 B73 B74 B75 B76 B77 B78 B79 B80 B81 B82

2

SLOT1

PRSNT1#

+12V_0

+12V_3

+12V_1

+12V_4

+12V_2

GND34

GND0

TCLK

SMCLK

TDI

SMDAT

TDO

GND1

TMS

+3.3V_0

+3.3V_2

TRST#

+3.3V_1

3.3VAUX PERST#

WAKE# RSVD0

GND35

REFCLK+

GND2 PETp0

REFCLK-

PETn0

GND36

GND3

PERp0

PRSNT2#_0

PERn0

GND4

GND37

PETp1

RSVD3

PETn1

GND38

GND5

PERp1

GND6

PERn1

PETp2

GND39

PETn2

GND40

GND7

PERp2

GND8

PERn2

PETp3

GND41

PETn3

GND42

GND9

PERp3

RSVD1

PERn3

GND43

PRSNT2#_1

RSVD4

GND10

RSVD5

PETp4

GND44

PETn4

PERp4

GND11

PERn4

GND12

GND45

PETp5

GND46

PETn5

PERp5

GND13

PERn5

GND14

GND47

PETp6

GND48

PETn6

PERp6

GND15

PERn6

GND16

GND49

PETp7

GND50

PETn7

PERp7

GND17

PERn7

PRSNT2#_2

GND51

GND18

RSVD6

PETp8

GND52

PETn8

PERp8

GND19

PERn8

GND20

GND53

PETp9

GND54

PETn9

PERp9

GND21

PERn9

GND22

GND55

PETp10

GND56

PETn10

PERp10

GND23

PERn10

GND24

GND57

PETp11

GND58

PETn11

PERp11

GND25

PERn11

GND26

GND59

PETp12

GND60

PETn12

PERp12

GND27

PERn12

GND28

GND61

PETp13

GND62

PETn13

PERp13

GND29

PERn13

GND30

GND63

PETp14

GND64

PETn14

PERp14

GND31

PERn14

GND32

GND65

PETp15

GND66

PETn15

PERp15

GND33

PERn15

PRSNT2#_4

GND67

RSVD2

x16 PCI Express Contr

1

A1 A2 A3 A4 A5 A6 A7

+

C184

A8 A9 A10 A11

A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66 A67 A68 A69 A70 A71 A72 A73 A74 A75 A76 A77 A78 A79 A80 A81 A82

C184

22uF

PERST_n_SL1

RCKp_SL1 RCKn_SL1

RX0p_SL1 RX0n_SL1

PERST_n_SL1 [26]

RCKp_SL1 [6] RCKn_SL1 [6]

RX0p_SL1 [22] RX0n_SL1 [22]

A A

PLX TECHNOLOGY, INC.

870 W Maude Ave, Sunnyvale, CA 94085

870 W Maude Ave, Sunnyvale, CA 94085 www.plxtech.com

www.plxtech.com

Title

Size Document Number Rev

Size Document Number Rev C

C

C Date: Sheet

Date: Sheet

5

4

3

2

Date: Sheet

www.plxtech.com

8615 Base Board RDK

91-0132-000-A 0

1

926Thursday, February 12, 2009

of

5

12V_SLT_4

+

C185

22uF

3.3VCC_SLT_4_5 3.3VCC_SLT_4_5

3.3VCC

R204

4.7K

D D

C C

B B

PRSNT_n_SL4[26]

PRSNT_n_SL4

TX0p_SL4

TX0p_SL4[22]

TX0n_SL4

TX0n_SL4[22]

Wake_n[9,11,12,13,14,26] Wake_n[9,11,12,13,14,26]

TX1p_SL4

TX1p_SL4[22]

TX1n_SL4

TX1n_SL4[22]

TX2p_SL4

TX2p_SL4[22]

TX2n_SL4

TX2n_SL4[22]

TX3p_SL4

TX3p_SL4[22]

TX3n_SL4

TX3n_SL4[22]

SLOT 04

SLOT4

B1

+12V_0

B2

+12V_1

B3

+12V_2

B4

GND0

B5

SMCLK

B6

SMDAT

B7

GND1

B8

+3.3V_0

B9

TRST#

B10

3.3VAUX

B11

WAKE#

B12

RSVD0

B13

GND2

B14

PETp0

B15

PETn0

B16

GND3

B17

PRSNT2#_0

B18

GND4

B19

PETp1

B20

PETn1

B21

GND5

B22

GND6

B23

PETp2

B24

PETn2

B25

GND7

B26

GND8

B27

PETp3

B28

PETn3

B29

GND9

B30

RSVD1

B31

PRSNT2#_1

B32

GND10

B33

PETp4

B34

PETn4

B35

GND11

B36

GND12

B37

PETp5

B38

PETn5

B39

GND13

B40

GND14

B41

PETp6

B42

PETn6

B43

GND15

B44

GND16

B45

PETp7

B46

PETn7

B47

GND17

B48

PRSNT2#_2

B49

GND18

B50

PETp8

B51

PETn8

B52

GND19

B53

GND20

B54

PETp9

B55

PETn9

B56

GND21

B57

GND22

B58

PETp10

B59

PETn10

B60

GND23

B61

GND24

B62

PETp11

B63

PETn11

B64

GND25

B65

GND26

B66

PETp12

B67

PETn12

B68

GND27

B69

GND28

B70

PETp13

B71

PETn13

B72

GND29

B73

GND30

B74

PETp14

B75

PETn14

B76

GND31

B77

GND32

B78

PETp15

B79

PETn15

B80

GND33

B81

PRSNT2#_4

B82

RSVD2

x16 PCI Express Contr

4

PRSNT1#

+12V_3 +12V_4 GND34

TCLK

+3.3V_2 +3.3V_1 PERST#

GND35 REFCLK+ REFCLK-

GND36

PERp0

PERn0 GND37 RSVD3 GND38

PERp1

PERn1 GND39 GND40

PERp2

PERn2 GND41 GND42

PERp3

PERn3 GND43 RSVD4 RSVD5 GND44

PERp4

PERn4 GND45 GND46

PERp5

PERn5 GND47 GND48

PERp6

PERn6 GND49 GND50

PERp7

PERn7 GND51 RSVD6 GND52

PERp8

PERn8 GND53 GND54

PERp9

PERn9 GND55 GND56

PERp10 PERn10

GND57 GND58

PERp11 PERn11

GND59 GND60

PERp12 PERn12

GND61 GND62

PERp13 PERn13

GND63 GND64

PERp14 PERn14

GND65 GND66

PERp15 PERn15

GND67

A1 A2 A3 A4 A5 A6

TDI

A7

TDO

A8

TMS

A9 A10 A11

A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66 A67 A68 A69 A70 A71 A72 A73 A74 A75 A76 A77 A78 A79 A80 A81 A82

Pin1&2 of J2 should be placed on the refclk traces and close to SLOT2 without stubs

+

C187

22uF

PERST_n_SL4

RCKp_SL4 RCKn_SL4

RX0p_SL4 RX0n_SL4

RX1p_SL4 RX1n_SL4

RX2p_SL4 RX2n_SL4

RX3p_SL4 RX3n_SL4

PERST_n_SL4 [26]

RCKp_SL4 [6] RCKn_SL4 [6]

RX0p_SL4 [22] RX0n_SL4 [22]

RX1p_SL4 [22] RX1n_SL4 [22]

RX2p_SL4 [22] RX2n_SL4 [22]

RX3p_SL4 [22] RX3n_SL4 [22]

3

12V_SLT_3

+

C186

22uF

3.3VCC_SLT_2_3 3.3VCC_SLT_2_3

3.3VCC

R203

4.7K

TX0p_SL3[22] TX0n_SL3[22]

PRSNT_n_SL3

TX0p_SL3 TX0n_SL3

PRSNT_n_SL3[26]

SLOT 03

SLOT3

B1

+12V_0

B2

+12V_1

B3

+12V_2

B4

GND0

B5

SMCLK

B6

SMDAT

B7

GND1

B8

+3.3V_0

B9

TRST#

B10

3.3VAUX

B11

WAKE#

B12

RSVD0

B13

GND2

B14

PETp0

B15

PETn0

B16

GND3

B17

PRSNT2#_0

B18

GND4

B19

PETp1

B20

PETn1

B21

GND5

B22

GND6

B23

PETp2

B24

PETn2

B25

GND7

B26

GND8

B27

PETp3

B28

PETn3

B29

GND9

B30

RSVD1

B31

PRSNT2#_1

B32

GND10

B33

PETp4

B34

PETn4

B35

GND11

B36

GND12

B37

PETp5

B38

PETn5

B39

GND13

B40

GND14

B41

PETp6

B42

PETn6

B43

GND15

B44

GND16

B45

PETp7

B46

PETn7

B47

GND17

B48

PRSNT2#_2

B49

GND18

B50

PETp8

B51

PETn8

B52

GND19

B53

GND20

B54

PETp9

B55

PETn9

B56

GND21

B57

GND22

B58

PETp10

B59

PETn10

B60

GND23

B61

GND24

B62

PETp11

B63

PETn11

B64

GND25

B65

GND26

B66

PETp12

B67

PETn12

B68

GND27

B69

GND28

B70

PETp13

B71

PETn13

B72

GND29

B73

GND30

B74

PETp14

B75

PETn14

B76

GND31

B77

GND32

B78

PETp15

B79

PETn15

B80

GND33

B81

PRSNT2#_4

B82

RSVD2

x16 PCI Express Contr

2

PRSNT1#

+12V_3 +12V_4

GND34

TCLK

+3.3V_2 +3.3V_1 PERST#

GND35

REFCLK+

REFCLK-

GND36 PERp0 PERn0 GND37 RSVD3 GND38 PERp1 PERn1 GND39 GND40 PERp2 PERn2 GND41 GND42 PERp3 PERn3 GND43 RSVD4 RSVD5 GND44 PERp4 PERn4 GND45 GND46 PERp5 PERn5 GND47 GND48 PERp6 PERn6 GND49 GND50 PERp7 PERn7 GND51 RSVD6 GND52 PERp8 PERn8 GND53 GND54 PERp9 PERn9 GND55

GND56 PERp10 PERn10

GND57

GND58 PERp11 PERn11

GND59

GND60 PERp12 PERn12

GND61

GND62 PERp13 PERn13

GND63

GND64 PERp14 PERn14

GND65

GND66 PERp15 PERn15

GND67

A1 A2 A3 A4 A5 A6

TDI

A7

TDO

A8

TMS

A9 A10 A11

A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66 A67 A68 A69 A70 A71 A72 A73 A74 A75 A76 A77 A78 A79 A80 A81 A82

Pin1&2 of J2 should be placed on the refclk traces and close to SLOT2 without stubs

+

C188

22uF

PERST_n_SL3

RCKp_SL3 RCKn_SL3

RX0p_SL3 RX0n_SL3

PERST_n_SL3 [26]

RCKp_SL3 [6] RCKn_SL3 [6]

RX0p_SL3 [22] RX0n_SL3 [22]

1

A A

PLX TECHNOLOGY, INC.

870 W Maude Ave, Sunnyvale, CA 94085

870 W Maude Ave, Sunnyvale, CA 94085 www.plxtech.com

www.plxtech.com

Title

Size Document Number Rev

Size Document Number Rev C

C

C Date: Sheet

Date: Sheet

5

4

3

2

Date: Sheet

www.plxtech.com

8615 Base Board RDK

91-0132-000-A 0

1

10 26Thursday, February 12, 2009

of

5

12V_SLT_6

+

C189

22uF

3.3VCC_SLT_6_7 3.3VCC_SLT_6_7

3.3VCC

R205

4.7K

D D

C C

B B

PRSNT_n_SL6[26]

PRSNT_n_SL6

TX0p_SL6

TX0p_SL6[22]

TX0n_SL6

TX0n_SL6[22]

Wake_n[9,10,12,13,14,26] Wake_n[9,10,12,13,14,26]

4

SLOT 06

SLOT6

B1

+12V_0

B2

+12V_1

B3

+12V_2

B4

GND0

B5

SMCLK

B6

SMDAT

B7

GND1

B8

+3.3V_0

B9

TRST#

B10

3.3VAUX

B11

WAKE#

B12

RSVD0

B13

GND2

B14

PETp0

B15

PETn0

B16

GND3

B17

PRSNT2#_0

B18

GND4

B19

PETp1

B20

PETn1

B21

GND5

B22

GND6

B23

PETp2

B24

PETn2

B25

GND7

B26

GND8

B27

PETp3

B28

PETn3

B29

GND9

B30

RSVD1

B31

PRSNT2#_1

B32

GND10

B33

PETp4

B34

PETn4

B35

GND11

B36

GND12

B37

PETp5

B38

PETn5

B39

GND13

B40

GND14

B41

PETp6

B42

PETn6

B43

GND15

B44

GND16

B45

PETp7

B46

PETn7

B47

GND17

B48

PRSNT2#_2

B49

GND18

B50

PETp8

B51

PETn8

B52

GND19

B53

GND20

B54

PETp9

B55

PETn9

B56

GND21

B57

GND22

B58

PETp10

B59

PETn10

B60

GND23

B61

GND24

B62

PETp11

B63

PETn11

B64

GND25

B65

GND26

B66

PETp12

B67

PETn12

B68

GND27

B69

GND28

B70

PETp13

B71

PETn13

B72

GND29

B73

GND30

B74

PETp14

B75

PETn14

B76

GND31

B77

GND32

B78

PETp15

B79

PETn15

B80

GND33

B81

PRSNT2#_4

B82

RSVD2

x16 PCI Express Contr

PRSNT1#

+12V_3 +12V_4

GND34

TCLK

+3.3V_2 +3.3V_1 PERST#

GND35

REFCLK+

REFCLK-

GND36 PERp0 PERn0 GND37 RSVD3 GND38 PERp1 PERn1 GND39 GND40 PERp2 PERn2 GND41 GND42 PERp3 PERn3 GND43 RSVD4 RSVD5 GND44 PERp4 PERn4 GND45 GND46 PERp5 PERn5 GND47 GND48 PERp6 PERn6 GND49 GND50 PERp7 PERn7 GND51 RSVD6 GND52 PERp8 PERn8 GND53 GND54 PERp9 PERn9 GND55

GND56 PERp10 PERn10

GND57

GND58 PERp11 PERn11

GND59

GND60 PERp12 PERn12

GND61

GND62 PERp13 PERn13

GND63

GND64 PERp14 PERn14

GND65

GND66 PERp15 PERn15

GND67

A1 A2 A3 A4 A5 A6

TDI

A7

TDO

A8

TMS

A9 A10 A11

A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66 A67 A68 A69 A70 A71 A72 A73 A74 A75 A76 A77 A78 A79 A80 A81 A82

Pin1&2 of J2 should be placed on the refclk traces and close to SLOT2 without stubs

+

C191

22uF

PERST_n_SL6

RCKp_SL6 RCKn_SL6

RX0p_SL6 RX0n_SL6

PERST_n_SL6 [26]

RCKp_SL6 [6] RCKn_SL6 [6]

RX0p_SL6 [22] RX0n_SL6 [22]

3

12V_SLT_5

+

C190

22uF

3.3VCC_SLT_4_5 3.3VCC_SLT_4_5

3.3VCC

R206

4.7K

TX0p_SL5[22] TX0n_SL5[22]

PRSNT_n_SL5

TX0p_SL5 TX0n_SL5

PRSNT_n_SL5[26]

SLOT 05

SLOT5

B1

+12V_0

B2

+12V_1

B3

+12V_2

B4

GND0

B5

SMCLK

B6

SMDAT

B7

GND1

B8

+3.3V_0

B9

TRST#

B10

3.3VAUX

B11

WAKE#

B12

RSVD0

B13

GND2

B14

PETp0

B15

PETn0

B16

GND3

B17

PRSNT2#_0

B18

GND4

B19

PETp1

B20

PETn1

B21

GND5

B22

GND6

B23

PETp2

B24

PETn2

B25

GND7

B26

GND8

B27

PETp3

B28

PETn3

B29

GND9

B30

RSVD1

B31

PRSNT2#_1

B32

GND10

B33

PETp4

B34

PETn4

B35

GND11

B36

GND12

B37

PETp5

B38

PETn5

B39

GND13

B40

GND14

B41

PETp6

B42

PETn6

B43

GND15

B44

GND16

B45

PETp7

B46

PETn7

B47

GND17

B48

PRSNT2#_2

B49

GND18

B50

PETp8

B51

PETn8

B52

GND19

B53

GND20

B54

PETp9

B55

PETn9

B56

GND21

B57

GND22

B58

PETp10

B59

PETn10

B60

GND23

B61

GND24

B62

PETp11

B63

PETn11

B64

GND25

B65

GND26

B66

PETp12

B67

PETn12

B68

GND27

B69

GND28

B70

PETp13

B71

PETn13

B72

GND29

B73

GND30

B74

PETp14

B75

PETn14

B76

GND31

B77

GND32

B78

PETp15

B79

PETn15

B80

GND33

B81

PRSNT2#_4

B82

RSVD2

x16 PCI Express Contr

2

PRSNT1#

+12V_3 +12V_4 GND34

TCLK

+3.3V_2 +3.3V_1 PERST#

GND35

REFCLK+

REFCLK-

GND36

PERp0

PERn0 GND37 RSVD3 GND38

PERp1

PERn1 GND39 GND40

PERp2

PERn2 GND41 GND42

PERp3

PERn3 GND43 RSVD4 RSVD5 GND44

PERp4

PERn4 GND45 GND46

PERp5

PERn5 GND47 GND48

PERp6

PERn6 GND49 GND50

PERp7

PERn7 GND51 RSVD6 GND52

PERp8

PERn8 GND53 GND54

PERp9

PERn9 GND55 GND56

PERp10 PERn10

GND57 GND58

PERp11 PERn11

GND59 GND60

PERp12 PERn12

GND61 GND62

PERp13 PERn13

GND63 GND64

PERp14 PERn14

GND65 GND66

PERp15 PERn15

GND67

A1 A2 A3 A4 A5 A6

TDI

A7

TDO

A8

TMS

A9 A10 A11

A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66 A67 A68 A69 A70 A71 A72 A73 A74 A75 A76 A77 A78 A79 A80 A81 A82

Pin1&2 of J2 should be placed on the refclk traces and close to SLOT2 without stubs

+

C192

22uF

PERST_n_SL5

RCKp_SL5 RCKn_SL5

RX0p_SL5 RX0n_SL5

PERST_n_SL5 [26]

RCKp_SL5 [6] RCKn_SL5 [6]

RX0p_SL5 [22] RX0n_SL5 [22]

1

A A

PLX TECHNOLOGY, INC.

870 W Maude Ave, Sunnyvale, CA 94085

870 W Maude Ave, Sunnyvale, CA 94085 www.plxtech.com

www.plxtech.com

Title

Size Document Number Rev

Size Document Number Rev C

C

C Date: Sheet

Date: Sheet

5

4

3

2

Date: Sheet

www.plxtech.com

8615 Base Board RDK

91-0132-000-A 0

1

11 26Thursday, February 12, 2009

of

5

12V_SLT_8_HP

+

C193

22uF

3.3VCC_SLT_8_HP 3.3VCC_SLT_8_HP

3.3VCC

R208

4.7K

D D

C C

B B

PRSNT_n_SL8[21,26]

TX0p_SL8[22] TX0n_SL8[22]

Wake_n[9,10,11,13,14,26] TX1p_SL8[22] TX1n_SL8[22]

TX2p_SL8[22] TX2n_SL8[22]

TX3p_SL8[22] TX3n_SL8[22]

PRSNT_n_SL8

TX0p_SL8 TX0n_SL8

TX1p_SL8 TX1n_SL8

TX2p_SL8 TX2n_SL8

TX3p_SL8 TX3n_SL8

4

SLOT 08 SLOT 07

SLOT8

B1

+12V_0

B2

+12V_1

B3

+12V_2

B4

GND0

B5

SMCLK

B6

SMDAT

B7

GND1

B8

+3.3V_0

B9

TRST#

B10

3.3VAUX

B11

WAKE#

B12

RSVD0

B13

GND2

B14

PETp0

B15

PETn0

B16

GND3

B17

PRSNT2#_0

B18

GND4

B19

PETp1

B20

PETn1

B21

GND5

B22

GND6

B23

PETp2

B24

PETn2

B25

GND7

B26

GND8

B27

PETp3

B28

PETn3

B29

GND9

B30

RSVD1

B31

PRSNT2#_1

B32

GND10

B33

PETp4

B34

PETn4

B35

GND11

B36

GND12

B37

PETp5

B38

PETn5

B39

GND13

B40

GND14

B41

PETp6

B42

PETn6

B43

GND15

B44

GND16

B45

PETp7

B46

PETn7

B47

GND17

B48

PRSNT2#_2

B49

GND18

B50

PETp8

B51

PETn8

B52

GND19

B53

GND20

B54

PETp9

B55

PETn9

B56

GND21

B57

GND22

B58

PETp10

B59

PETn10

B60

GND23

B61

GND24

B62

PETp11

B63

PETn11

B64

GND25

B65

GND26

B66

PETp12

B67

PETn12

B68

GND27

B69

GND28

B70

PETp13

B71

PETn13

B72

GND29

B73

GND30

B74

PETp14

B75

PETn14

B76

GND31

B77

GND32

B78

PETp15

B79

PETn15

B80

GND33

B81

PRSNT2#_4

B82

RSVD2

x16 PCI Express Contr

PRSNT1#

+12V_3 +12V_4 GND34

TCLK

TDO

TMS +3.3V_2 +3.3V_1 PERST#

GND35 REFCLK+ REFCLK-

GND36

PERp0

PERn0 GND37 RSVD3 GND38

PERp1

PERn1 GND39 GND40

PERp2

PERn2 GND41 GND42

PERp3

PERn3 GND43 RSVD4 RSVD5 GND44

PERp4

PERn4 GND45 GND46

PERp5

PERn5 GND47 GND48

PERp6

PERn6 GND49 GND50

PERp7

PERn7 GND51 RSVD6 GND52

PERp8

PERn8 GND53 GND54

PERp9

PERn9 GND55 GND56

PERp10 PERn10

GND57 GND58

PERp11 PERn11

GND59 GND60

PERp12 PERn12

GND61 GND62

PERp13 PERn13

GND63 GND64

PERp14 PERn14

GND65 GND66

PERp15 PERn15

GND67

A1 A2 A3 A4 A5 A6

TDI

A7

+

C195

A8 A9 A10 A11

A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66 A67 A68 A69 A70 A71 A72 A73 A74 A75 A76 A77 A78 A79 A80 A81 A82

C195

22uF

PERST_n_SL8

RCKp_SL8 RCKn_SL8

RX0p_SL8 RX0n_SL8

RX1p_SL8 RX1n_SL8

RX2p_SL8 RX2n_SL8

RX3p_SL8 RX3n_SL8

PERST_n_SL8 [21]

RCKp_SL8 [6] RCKn_SL8 [6]

RX0p_SL8 [22] RX0n_SL8 [22]

RX1p_SL8 [22] RX1n_SL8 [22]

RX2p_SL8 [22] RX2n_SL8 [22]

RX3p_SL8 [22] RX3n_SL8 [22]

3

12V_SLT_7

+

C194

22uF

3.3VCC_SLT_6_7 3.3VCC_SLT_6_7

3.3VCC

TX0p_SL7[22] TX0n_SL7[22]

PRSNT_n_SL7

TX0p_SL7 TX0n_SL7

PRSNT_n_SL7[26]

Wake_n[9,10,11,13,14,26]

R207

4.7K

B1 B2 B3 B4 B5 B6 B7 B8

B9 B10 B11

B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49 B50 B51 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 B63 B64 B65 B66 B67 B68 B69 B70 B71 B72 B73 B74 B75 B76 B77 B78 B79 B80 B81 B82

2

SLOT7

PRSNT1#

+12V_0

+12V_3

+12V_1

+12V_4

+12V_2

GND34

GND0

TCLK

SMCLK

TDI

SMDAT

TDO

GND1

TMS

+3.3V_0

+3.3V_2

TRST#

+3.3V_1

3.3VAUX PERST#

WAKE# RSVD0

GND35

REFCLK+

GND2 PETp0

REFCLK-

PETn0

GND36

GND3

PERp0

PRSNT2#_0

PERn0

GND4

GND37

PETp1

RSVD3

PETn1

GND38

GND5

PERp1

GND6

PERn1

PETp2

GND39

PETn2

GND40

GND7

PERp2

GND8

PERn2

PETp3

GND41

PETn3

GND42

GND9

PERp3

RSVD1

PERn3 GND43

PRSNT2#_1

RSVD4

GND10

RSVD5

PETp4

GND44

PETn4

PERp4

GND11

PERn4

GND12

GND45

PETp5

GND46

PETn5

PERp5

GND13

PERn5

GND14

GND47

PETp6

GND48

PETn6

PERp6

GND15

PERn6

GND16

GND49

PETp7

GND50

PETn7

PERp7

GND17

PERn7

PRSNT2#_2

GND51

GND18

RSVD6

PETp8

GND52

PETn8

PERp8

GND19

PERn8

GND20

GND53

PETp9

GND54

PETn9

PERp9

GND21

PERn9

GND22

GND55

PETp10

GND56

PETn10

PERp10

GND23

PERn10

GND24

GND57

PETp11

GND58

PETn11

PERp11

GND25

PERn11

GND26

GND59

PETp12

GND60

PETn12

PERp12

GND27

PERn12

GND28

GND61

PETp13

GND62

PETn13

PERp13

GND29

PERn13

GND30

GND63

PETp14

GND64

PETn14

PERp14

GND31

PERn14

GND32

GND65

PETp15

GND66

PETn15

PERp15

GND33

PERn15

PRSNT2#_4

GND67

RSVD2

x16 PCI Express Contr

1

A1 A2 A3 A4 A5 A6 A7

+

C196

A8 A9 A10 A11

A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66 A67 A68 A69 A70 A71 A72 A73 A74 A75 A76 A77 A78 A79 A80 A81 A82

C196

22uF

PERST_n_SL7

RCKp_SL7 RCKn_SL7

RX0p_SL7 RX0n_SL7

PERST_n_SL7 [26]

RCKp_SL7 [6] RCKn_SL7 [6]

RX0p_SL7 [22] RX0n_SL7 [22]

A A

PLX TECHNOLOGY, INC.

870 W Maude Ave, Sunnyvale, CA 94085

870 W Maude Ave, Sunnyvale, CA 94085 www.plxtech.com

www.plxtech.com

Title

Size Document Number Rev

Size Document Number Rev C

C

C Date: Sheet

Date: Sheet

5

4

3

2

Date: Sheet

www.plxtech.com

8615 Base Board RDK

91-0132-000-A 0

1

12 26Thursday, February 12, 2009

of

5

12V_SLT_10

+

C197

22uF

3.3VCC_SLT_10_11 3.3VCC_SLT_10_11

3.3VCC

R209

4.7K

D D

PRSNT_n_SL10[26]

TX0p_SL10[22] TX0n_SL10[22]

PRSNT_n_SL10

TX0p_SL10 TX0n_SL10

Wake_n[9,10,11,12,14,26] Wake_n[9,10,11,12,14,26]

C C

B B

4

SLOT 10 SLOT 09

SLOT10

B1

+12V_0

B2

+12V_1

B3

+12V_2

B4

GND0

B5

SMCLK

B6

SMDAT

B7

GND1

B8

+3.3V_0

B9

TRST#

B10

3.3VAUX

B11

WAKE#

B12

RSVD0

B13

GND2

B14

PETp0

B15

PETn0

B16

GND3

B17

PRSNT2#_0

B18

GND4

B19

PETp1

B20

PETn1

B21

GND5

B22

GND6

B23

PETp2

B24

PETn2

B25

GND7

B26

GND8

B27

PETp3

B28

PETn3

B29

GND9

B30

RSVD1

B31

PRSNT2#_1

B32

GND10

B33

PETp4

B34

PETn4

B35

GND11

B36

GND12

B37

PETp5

B38

PETn5

B39

GND13

B40

GND14

B41

PETp6

B42

PETn6

B43

GND15

B44

GND16

B45

PETp7

B46

PETn7

B47

GND17

B48

PRSNT2#_2

B49

GND18

B50

PETp8

B51

PETn8

B52

GND19

B53

GND20

B54

PETp9

B55

PETn9

B56

GND21

B57

GND22

B58

PETp10

B59

PETn10

B60

GND23

B61

GND24

B62

PETp11

B63

PETn11

B64

GND25

B65

GND26

B66

PETp12

B67

PETn12

B68

GND27

B69

GND28

B70

PETp13

B71

PETn13

B72

GND29

B73

GND30

B74

PETp14

B75

PETn14

B76

GND31

B77

GND32

B78

PETp15

B79

PETn15

B80

GND33

B81

PRSNT2#_4

B82

RSVD2

x16 PCI Express Contr

PRSNT1#

+12V_3 +12V_4 GND34

TCLK

TDO

TMS +3.3V_2 +3.3V_1 PERST#

GND35 REFCLK+ REFCLK-

GND36

PERp0

PERn0 GND37 RSVD3 GND38

PERp1

PERn1 GND39 GND40

PERp2

PERn2 GND41 GND42

PERp3

PERn3 GND43 RSVD4 RSVD5 GND44

PERp4

PERn4 GND45 GND46

PERp5

PERn5 GND47 GND48

PERp6

PERn6 GND49 GND50

PERp7

PERn7 GND51 RSVD6 GND52

PERp8

PERn8 GND53 GND54

PERp9

PERn9 GND55 GND56

PERp10 PERn10

GND57 GND58

PERp11 PERn11

GND59 GND60

PERp12 PERn12

GND61 GND62

PERp13 PERn13

GND63 GND64

PERp14 PERn14

GND65 GND66

PERp15 PERn15

GND67

A1 A2 A3 A4 A5 A6

TDI

A7

+

C199

A8 A9 A10 A11

A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66 A67 A68 A69 A70 A71 A72 A73 A74 A75 A76 A77 A78 A79 A80 A81 A82

C199

22uF

PERST_n_SL10

RCKp_SL10 RCKn_SL10

RX0p_SL10 RX0n_SL10

PERST_n_SL10 [26]

RCKp_SL10 [6] RCKn_SL10 [6]

RX0p_SL10 [22] RX0n_SL10 [22]

3

12V_SLT_9

+

C198

22uF

3.3VCC_SLT_9 3.3VCC_SLT_9

3.3VCC

TX0p_SL9[22] TX0n_SL9[22]

PRSNT_n_SL9

TX0p_SL9 TX0n_SL9

PRSNT_n_SL9[26]

R210

4.7K

B1 B2 B3 B4 B5 B6 B7 B8

B9 B10 B11

B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49 B50 B51 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 B63 B64 B65 B66 B67 B68 B69 B70 B71 B72 B73 B74 B75 B76 B77 B78 B79 B80 B81 B82

2

SLOT9

PRSNT1#

+12V_0

+12V_3

+12V_1

+12V_4

+12V_2

GND34

GND0

TCLK

SMCLK

TDI

SMDAT

TDO

GND1

TMS

+3.3V_0

+3.3V_2

TRST#

+3.3V_1

3.3VAUX PERST#

WAKE# RSVD0

GND35

REFCLK+

GND2 PETp0

REFCLK-

PETn0

GND36

GND3

PERp0

PRSNT2#_0

PERn0

GND4

GND37

PETp1

RSVD3

PETn1

GND38

GND5

PERp1

GND6

PERn1

PETp2

GND39

PETn2

GND40

GND7

PERp2

GND8

PERn2

PETp3

GND41

PETn3

GND42

GND9

PERp3

RSVD1

PERn3 GND43

PRSNT2#_1

RSVD4

GND10

RSVD5

PETp4

GND44

PETn4

PERp4

GND11

PERn4

GND12

GND45

PETp5

GND46

PETn5

PERp5

GND13

PERn5

GND14

GND47

PETp6

GND48

PETn6

PERp6

GND15

PERn6

GND16

GND49

PETp7

GND50

PETn7

PERp7

GND17

PERn7

PRSNT2#_2

GND51

GND18

RSVD6

PETp8

GND52

PETn8

PERp8

GND19

PERn8

GND20

GND53

PETp9

GND54

PETn9

PERp9

GND21

PERn9

GND22

GND55

PETp10

GND56

PETn10

PERp10

GND23

PERn10

GND24

GND57

PETp11

GND58

PETn11

PERp11

GND25

PERn11

GND26

GND59

PETp12

GND60

PETn12

PERp12

GND27

PERn12

GND28

GND61

PETp13

GND62

PETn13

PERp13

GND29

PERn13

GND30

GND63

PETp14

GND64

PETn14

PERp14

GND31

PERn14

GND32

GND65

PETp15

GND66

PETn15

PERp15

GND33

PERn15

PRSNT2#_4

GND67

RSVD2

x16 PCI Express Contr

1

A1 A2 A3 A4 A5 A6 A7

+

C200

A8 A9 A10 A11

A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66 A67 A68 A69 A70 A71 A72 A73 A74 A75 A76 A77 A78 A79 A80 A81 A82

C200

22uF

PERST_n_SL9

RCKp_SL9 RCKn_SL9

RX0p_SL9 RX0n_SL9

PERST_n_SL9 [26]

RCKp_SL9 [6] RCKn_SL9 [6]

RX0p_SL9 [22] RX0n_SL9 [22]

A A

PLX TECHNOLOGY, INC.

870 W Maude Ave, Sunnyvale, CA 94085

870 W Maude Ave, Sunnyvale, CA 94085 www.plxtech.com

www.plxtech.com

Title

Size Document Number Rev

Size Document Number Rev C

C

C Date: Sheet

Date: Sheet

5

4

3

2

Date: Sheet

www.plxtech.com

8615 Base Board RDK

91-0132-000-A 0

1

13 26Thursday, February 12, 2009

of

5

12V_SLT_12

+

C201

22uF

3.3VCC_SLT_12_13 3.3VCC_SLT_12_13

3.3VCC

R212

4.7K

D D

C C

B B

4.7K

4

SLOT 12 (Unsued) SLOT 11

SLOT12

B1

+12V_0

B2

+12V_1

B3

+12V_2

B4

GND0

B5

SMCLK

B6

SMDAT

B7

GND1

B8

+3.3V_0

B9

TRST#

B10

3.3VAUX

B11

WAKE#

B12

RSVD0

B13

GND2

B14

PETp0

B15

PETn0

B16

GND3

B17

PRSNT2#_0

B18

GND4

B19

PETp1

B20

PETn1

B21

GND5

B22

GND6

B23

PETp2

B24

PETn2

B25

GND7

B26

GND8

B27

PETp3

B28

PETn3

B29

GND9

B30

RSVD1

B31

PRSNT2#_1

B32

GND10

B33

PETp4

B34

PETn4

B35

GND11

B36

GND12

B37

PETp5

B38

PETn5

B39

GND13

B40

GND14

B41

PETp6

B42

PETn6

B43

GND15

B44

GND16

B45

PETp7

B46

PETn7

B47

GND17

B48

PRSNT2#_2

B49

GND18

B50

PETp8

B51

PETn8

B52

GND19

B53

GND20

B54

PETp9

B55

PETn9

B56

GND21

B57

GND22

B58

PETp10

B59

PETn10

B60

GND23

B61

GND24

B62

PETp11

B63

PETn11

B64

GND25

B65

GND26

B66

PETp12

B67

PETn12

B68

GND27

B69

GND28

B70

PETp13

B71

PETn13

B72

GND29

B73

GND30

B74

PETp14

B75

PETn14

B76

GND31

B77

GND32

B78

PETp15

B79

PETn15

B80

GND33

B81

PRSNT2#_4

B82

RSVD2

x16 PCI Express Contr

PRSNT1#

+12V_3 +12V_4

GND34

TCLK

+3.3V_2 +3.3V_1 PERST#

GND35

REFCLK+

REFCLK-

GND36 PERp0 PERn0 GND37 RSVD3 GND38 PERp1 PERn1 GND39 GND40 PERp2 PERn2 GND41 GND42 PERp3 PERn3 GND43 RSVD4 RSVD5 GND44 PERp4 PERn4 GND45 GND46 PERp5 PERn5 GND47 GND48 PERp6 PERn6 GND49 GND50 PERp7 PERn7 GND51 RSVD6 GND52 PERp8 PERn8 GND53 GND54 PERp9 PERn9 GND55

GND56 PERp10 PERn10

GND57

GND58 PERp11 PERn11

GND59

GND60 PERp12 PERn12

GND61

GND62 PERp13 PERn13

GND63

GND64 PERp14 PERn14

GND65

GND66 PERp15 PERn15

GND67

A1 A2 A3 A4 A5 A6

TDI

A7

TDO TMS

+

C203

A8 A9 A10 A11

A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66 A67 A68 A69 A70 A71 A72 A73 A74 A75 A76 A77 A78 A79 A80 A81 A82

C203

22uF

3

12V_SLT_11

+

C202

22uF

3.3VCC_SLT_10_11 3.3VCC_SLT_10_11

3.3VCC

TX0p_SL11[22] TX0n_SL11[22]

PRSNT_n_SL11

TX0p_SL11 TX0n_SL11

PRSNT_n_SL11[26]

Wake_n[9,10,11,12,13,26]

R211

4.7K

B1 B2 B3 B4 B5 B6 B7 B8

B9 B10 B11

B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49 B50 B51 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 B63 B64 B65 B66 B67 B68 B69 B70 B71 B72 B73 B74 B75 B76 B77 B78 B79 B80 B81 B82

2

SLOT11

PRSNT1#

+12V_0

+12V_3

+12V_1

+12V_4

+12V_2

GND34

GND0

TCLK

SMCLK

TDI

SMDAT

TDO

GND1

TMS

+3.3V_0

+3.3V_2

TRST#

+3.3V_1

3.3VAUX PERST#

WAKE# RSVD0

GND35

REFCLK+

GND2 PETp0

REFCLK-

PETn0

GND36

GND3

PERp0

PRSNT2#_0

PERn0

GND4

GND37

PETp1

RSVD3

PETn1

GND38

GND5

PERp1

GND6

PERn1

PETp2

GND39

PETn2

GND40

GND7

PERp2

GND8

PERn2

PETp3

GND41

PETn3

GND42

GND9

PERp3

RSVD1

PERn3

GND43

PRSNT2#_1

RSVD4

GND10

RSVD5

PETp4

GND44

PETn4

PERp4

GND11

PERn4

GND12

GND45

PETp5

GND46

PETn5

PERp5

GND13

PERn5

GND14

GND47

PETp6

GND48

PETn6

PERp6

GND15

PERn6

GND16

GND49

PETp7

GND50

PETn7

PERp7

GND17

PERn7

PRSNT2#_2

GND51

GND18

RSVD6

PETp8

GND52

PETn8

PERp8

GND19

PERn8

GND20

GND53

PETp9

GND54

PETn9

PERp9

GND21

PERn9

GND22

GND55

PETp10

GND56

PETn10

PERp10

GND23

PERn10

GND24

GND57

PETp11

GND58

PETn11

PERp11

GND25

PERn11

GND26

GND59

PETp12

GND60

PETn12

PERp12

GND27

PERn12

GND28

GND61

PETp13

GND62

PETn13

PERp13

GND29

PERn13

GND30

GND63

PETp14

GND64

PETn14

PERp14

GND31

PERn14

GND32

GND65

PETp15

GND66

PETn15

PERp15

GND33

PERn15

PRSNT2#_4

GND67

RSVD2

x16 PCI Express Contr

1

A1 A2 A3 A4 A5 A6 A7

+

C204

A8 A9 A10 A11

A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66 A67 A68 A69 A70 A71 A72 A73 A74 A75 A76 A77 A78 A79 A80 A81 A82

C204

22uF

PERST_n_SL11

RCKp_SL11 RCKn_SL11

RX0p_SL11 RX0n_SL11

PERST_n_SL11 [26]

RCKp_SL11 [6] RCKn_SL11 [6]

RX0p_SL11 [22] RX0n_SL11 [22]

A A

PLX TECHNOLOGY, INC.

870 W Maude Ave, Sunnyvale, CA 94085

870 W Maude Ave, Sunnyvale, CA 94085 www.plxtech.com

www.plxtech.com

Title

Size Document Number Rev

Size Document Number Rev C

C

C Date: Sheet

Date: Sheet

5

4

3

2

Date: Sheet

www.plxtech.com

8615 Base Board RDK

91-0132-000-A 0

1

14 26Thursday, February 12, 2009

of

5

12V_SLT_14

+

C205

22uF

3.3VCC_SLT_14_15 3.3VCC_SLT_14_15

3.3VCC

R213

4.7K

D D

C C

B B

4.7K

4

SLOT 14 (Unused) SLOT 13 (Unused)

SLOT14

PRSNT1#

+12V_3 +12V_4 GND34

TCLK

+3.3V_2 +3.3V_1 PERST#

GND35

REFCLK+

REFCLK-

GND36

PERp0

PERn0 GND37 RSVD3 GND38

PERp1

PERn1 GND39 GND40

PERp2

PERn2 GND41 GND42

PERp3

PERn3 GND43 RSVD4 RSVD5 GND44

PERp4

PERn4 GND45 GND46

PERp5

PERn5 GND47 GND48

PERp6

PERn6 GND49 GND50

PERp7

PERn7 GND51 RSVD6 GND52

PERp8

PERn8 GND53 GND54

PERp9

PERn9 GND55 GND56

PERp10 PERn10

GND57 GND58

PERp11 PERn11

GND59 GND60

PERp12 PERn12

GND61 GND62

PERp13 PERn13

GND63 GND64

PERp14 PERn14

GND65 GND66

PERp15 PERn15

GND67

A1 A2 A3 A4 A5 A6

TDI

A7

TDO TMS

+

C207

A8 A9 A10 A11

A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66 A67 A68 A69 A70 A71 A72 A73 A74 A75 A76 A77 A78 A79 A80 A81 A82

C207

22uF

B1

+12V_0

B2

+12V_1

B3

+12V_2

B4

GND0

B5

SMCLK

B6

SMDAT

B7

GND1

B8

+3.3V_0

B9

TRST#

B10

3.3VAUX

B11

WAKE#

B12

RSVD0

B13

GND2

B14

PETp0

B15

PETn0

B16

GND3

B17

PRSNT2#_0

B18

GND4

B19

PETp1

B20

PETn1

B21

GND5

B22

GND6

B23

PETp2

B24

PETn2

B25

GND7

B26

GND8

B27

PETp3

B28

PETn3

B29

GND9

B30

RSVD1

B31

PRSNT2#_1

B32

GND10

B33

PETp4

B34

PETn4

B35

GND11

B36

GND12

B37

PETp5

B38

PETn5

B39

GND13

B40

GND14

B41

PETp6

B42

PETn6

B43

GND15

B44

GND16

B45

PETp7

B46

PETn7

B47

GND17

B48

PRSNT2#_2

B49

GND18

B50

PETp8

B51

PETn8

B52

GND19

B53

GND20

B54

PETp9

B55

PETn9

B56

GND21

B57

GND22

B58

PETp10

B59

PETn10

B60

GND23

B61

GND24

B62

PETp11

B63

PETn11

B64

GND25

B65

GND26

B66

PETp12

B67

PETn12

B68

GND27

B69

GND28

B70

PETp13

B71

PETn13

B72

GND29

B73

GND30

B74

PETp14

B75

PETn14

B76

GND31

B77

GND32

B78

PETp15

B79

PETn15

B80

GND33

B81

PRSNT2#_4

B82

RSVD2

x16 PCI Express Contr

3

2

12V_SLT_13

SLOT13

+

C206

22uF

3.3VCC_SLT_12_13 3.3VCC_SLT_12_13

3.3VCC

R214

4.7K

SLOT13

B1

+12V_0

B2

+12V_1

B3

+12V_2

B4

GND0

B5

SMCLK

B6

SMDAT

B7

GND1

B8

+3.3V_0

B9

TRST#

B10

3.3VAUX

B11

WAKE#

B12

RSVD0

B13

GND2

B14

PETp0

B15

PETn0

B16

GND3

B17

PRSNT2#_0

B18

GND4

B19

PETp1

B20

PETn1

B21

GND5

B22

GND6

B23

PETp2

B24

PETn2

B25

GND7

B26

GND8

B27

PETp3

B28

PETn3

B29

GND9

B30

RSVD1

B31

PRSNT2#_1

B32

GND10

B33

PETp4

B34

PETn4

B35

GND11

B36

GND12

B37

PETp5

B38

PETn5

B39

GND13

B40

GND14

B41

PETp6

B42

PETn6

B43

GND15

B44

GND16

B45

PETp7

B46

PETn7

B47

GND17

B48

PRSNT2#_2

B49

GND18

B50

PETp8

B51

PETn8

B52

GND19

B53

GND20

B54

PETp9

B55

PETn9

B56

GND21

B57

GND22

B58

PETp10

B59

PETn10

B60

GND23

B61

GND24

B62

PETp11

B63

PETn11

B64

GND25

B65

GND26

B66

PETp12

B67

PETn12

B68

GND27

B69

GND28

B70

PETp13

B71

PETn13

B72

GND29

B73

GND30

B74

PETp14

B75

PETn14

B76

GND31

B77

GND32

B78

PETp15

B79

PETn15

B80

GND33

B81

PRSNT2#_4

B82

RSVD2

x16 PCI Express Contr

PRSNT1#

+12V_3 +12V_4 GND34

TCLK

+3.3V_2 +3.3V_1 PERST#

GND35

REFCLK+

REFCLK-

GND36

PERp0

PERn0 GND37 RSVD3 GND38

PERp1

PERn1 GND39 GND40

PERp2

PERn2 GND41 GND42

PERp3

PERn3 GND43 RSVD4 RSVD5 GND44

PERp4

PERn4 GND45 GND46

PERp5

PERn5 GND47 GND48

PERp6

PERn6 GND49 GND50

PERp7

PERn7 GND51 RSVD6 GND52

PERp8

PERn8 GND53 GND54

PERp9

PERn9 GND55 GND56

PERp10 PERn10

GND57 GND58

PERp11 PERn11

GND59 GND60

PERp12 PERn12

GND61 GND62

PERp13 PERn13

GND63 GND64

PERp14 PERn14

GND65 GND66

PERp15 PERn15

GND67

1

A1 A2 A3 A4 A5 A6

TDI

A7

TDO TMS

+

C208

A8 A9 A10 A11

A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66 A67 A68 A69 A70 A71 A72 A73 A74 A75 A76 A77 A78 A79 A80 A81 A82

C208

22uF

A A

PLX TECHNOLOGY, INC.

870 W Maude Ave, Sunnyvale, CA 94085

870 W Maude Ave, Sunnyvale, CA 94085 www.plxtech.com

www.plxtech.com

Title

Size Document Number Rev

Size Document Number Rev C

C

C Date: Sheet

Date: Sheet

5

4

3

2

Date: Sheet

www.plxtech.com

8615 Base Board RDK

91-0132-000-A 0

1

15 26Thursday, February 12, 2009

of

5

J5

CPWRON[26] CPRSNTN[26]

D D

C C

B B

CREFCLKRECEPT0_n[5] CREFCLKRECEPT0_p[5]

TX3n_PCIe_Cable[22] TX3p_PCIe_Cable[22]

TX2n_PCIe_Cable[22] TX2p_PCIe_Cable[22]

TX1n_PCIe_Cable[22] TX1p_PCIe_Cable[22]

TX0n_PCIe_Cable[22] TX0p_PCIe_Cable[22]

TV29

TV29 TV30

TV30

Prototyping Pad

TV31

Prototyping Pad

TV32

Prototyping Pad

TX7n_PCIe_Cable[22]

Prototyping Pad

TX7p_PCIe_Cable[22] TX6n_PCIe_Cable[22]

TX6p_PCIe_Cable[22] TX5n_PCIe_Cable[22]

TX5p_PCIe_Cable[22] TX4n_PCIe_Cable[22]

TX4p_PCIe_Cable[22]

A19 A18 A17 A16 A15 A14 A13 A12 A11 A10

A9 A8 A7 A6 A5 A4 A3 A2 A1

A19 A18 A17 A16 A15 A14 A13 A12 A11 A10

A9 A8 A7 A6 A5 A4 A3 A2 A1

1 2 3 4 5 6 7 8 9

CPWRON CPRSNT# SB_RTN GND0 CREFCLKn CREFCLKp GND1 PETn3 PETp3 GND3 PETn2 PETp2 GND4 PETn1 PETp1 GND5 PETn0 PETp0 GND6

PCIex4_Cab-Con

J6

CPWRON CPRSNT# SB_RTN GND0 CREFCLKn CREFCLKp GND1 PETn3 PETp3 GND3 PETn2 PETp2 GND4 PETn1 PETp1 GND5 PETn0 PETp0 GND6

PCIex4_Cab-Con

CAGE1

1 2 3 4 5 6 7 8 9

cage

CAGE2

1 2 3 4 5 6 7 8 9

cage

CPERST#

CWAKE# PWR_RTN1 PWR_RTN0

PWR1 PWR0

GND11

PERn3 PERp3

GND10

PERn2 PERp2

GND9 PERn1 PERp1

GND8 PERn0 PERp0

GND7

CPERST#

CWAKE# PWR_RTN1 PWR_RTN0

PWR1 PWR0

GND11

PERn3 PERp3

GND10

PERn2 PERp2

GND9 PERn1 PERp1

GND8 PERn0 PERp0

GND7

B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1

4

CPERST_n [4]

TPV22 Prototyping PadTPV22 Prototyping Pad

TPV1

Prototyping Pad

RX3n_PCIe_Cable [22] RX3p_PCIe_Cable [22]

RX2n_PCIe_Cable [22] RX2p_PCIe_Cable [22]

RX1n_PCIe_Cable [22] RX1p_PCIe_Cable [22]

RX0n_PCIe_Cable [22] RX0p_PCIe_Cable [22]

TPV2

TPV2 TPV4

TPV4

Prototyping Pad

TPV3

Prototyping Pad

RX7n_PCIe_Cable [22] RX7p_PCIe_Cable [22]

RX6n_PCIe_Cable [22] RX6p_PCIe_Cable [22]

RX5n_PCIe_Cable [22] RX5p_PCIe_Cable [22]

RX4n_PCIe_Cable [22] RX4p_PCIe_Cable [22]

3

12V_SLT_15

+

C209

22uF

3.3VCC_SLT_14_15 3.3VCC_SLT_14_15

3.3VCC

R215

4.7K

B1 B2 B3 B4 B5 B6 B7 B8

B9 B10 B11

B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49 B50 B51 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 B63 B64 B65 B66 B67 B68 B69 B70 B71 B72 B73 B74 B75 B76 B77 B78 B79 B80 B81 B82

2

SLOT 15 (Unused)

SLOT15

A1

PRSNT1#

+12V_0 +12V_1 +12V_2 GND0 SMCLK SMDAT GND1 +3.3V_0 TRST#

3.3VAUX WAKE#

RSVD0 GND2 PETp0 PETn0 GND3 PRSNT2#_0 GND4 PETp1 PETn1 GND5 GND6 PETp2 PETn2 GND7 GND8 PETp3 PETn3 GND9 RSVD1 PRSNT2#_1 GND10 PETp4 PETn4 GND11 GND12 PETp5 PETn5 GND13 GND14 PETp6 PETn6 GND15 GND16 PETp7 PETn7 GND17 PRSNT2#_2 GND18 PETp8 PETn8 GND19 GND20 PETp9 PETn9 GND21 GND22 PETp10 PETn10 GND23 GND24 PETp11 PETn11 GND25 GND26 PETp12 PETn12 GND27 GND28 PETp13 PETn13 GND29 GND30 PETp14 PETn14 GND31 GND32 PETp15 PETn15 GND33 PRSNT2#_4 RSVD2

x16 PCI Express Contr

+12V_3 +12V_4 GND34

TCLK

+3.3V_2 +3.3V_1 PERST#

GND35

REFCLK+

REFCLK-

GND36

PERp0

PERn0 GND37 RSVD3 GND38

PERp1

PERn1 GND39 GND40

PERp2

PERn2 GND41 GND42

PERp3

PERn3 GND43 RSVD4 RSVD5 GND44

PERp4

PERn4 GND45 GND46

PERp5

PERn5 GND47 GND48

PERp6

PERn6 GND49 GND50

PERp7

PERn7 GND51 RSVD6 GND52

PERp8

PERn8 GND53 GND54

PERp9

PERn9 GND55 GND56

PERp10 PERn10

GND57 GND58

PERp11 PERn11

GND59 GND60

PERp12 PERn12

GND61 GND62

PERp13 PERn13

GND63 GND64

PERp14 PERn14

GND65 GND66

PERp15 PERn15

GND67

A2 A3 A4 A5 A6

TDI

A7

TDO

A8

TMS

A9 A10 A11

A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66 A67 A68 A69 A70 A71 A72 A73 A74 A75 A76 A77 A78 A79 A80 A81 A82

1

+

C210

22uF

A A

PLX TECHNOLOGY, INC.

870 W Maude Ave, Sunnyvale, CA 94085

870 W Maude Ave, Sunnyvale, CA 94085 www.plxtech.com

www.plxtech.com

Title

Size Document Number Rev

Size Document Number Rev C

C

C Date: Sheet

Date: Sheet

5

4

3

2

Date: Sheet

www.plxtech.com

8615 Base Board RDK

91-0132-000-A 0

1

16 26Thursday, February 12, 2009

of

5

3.3VCC1

U80A

147

PEX_PERST_n[8,18,19,21,26]

D D

LEDSET1_DATA[26]

1 2

74LVC04/SO

LEDSET1_CLK[26]

LEDSET0_DATA[26]

LEDSET0_CLK[26]

U80B

U80B 74LVC04/SO

74LVC04/SO

3 4

U80C

U80C 74LVC04/SO

74LVC04/SO

5 6

U80D

U80D 74LVC04/SO

74LVC04/SO

9 8

U80E

U80E 74LVC04/SO

74LVC04/SO

11 10

subpart F not used

1 2

8 9

MM74HC164

C C

3.3VCC1

1 2

8 9

MM74HC164

LEDSET7_DATA[26]

LEDSET7_CLK[26]

U92E

U92E 74LVC04/SO

74LVC04/SO

11 10

MM74HC164

3.3VCC1

1

B B

2 8 9

MM74HC164

3.3VCC1

1 2

8 9

MM74HC164

3.3VCC1

4

3.3VCC1

U29

14

QA

A

VCC

QB

B

QC

CLK

QD

QE

CLR

QF QG QH

GND

7

RN14

3 4

10

5

11

6

12

10

13

11

14

12

15

13

16

220

Port ID3

7

89

A

6

7

B

4

6

C

2

5

D

1

4

E

9

3

F

10

2

G

5

1

DP

DS1

DS1 Red

Red

3.3VCC1

8

ANODE03ANODE1

1 2

8 9

MM74HC164

3.3VCC1

U33

14

QA

A

QB

B

VCC

QC

CLK

QD

QE

CLR

QF QG QH

GND

7

3.3VCC1

U37

14

QA

A

QB

B

VCC

QC

CLK

QD

QE

CLR

QF QG QH

GND

7

3.3VCC1 3.3VCC1

U41

14

QA

A

VCC

QB

B

QC

CLK

QD

QE

CLR

QF QG QH

GND

7

RN18

3 4

10

5

11

6

12

10

13

11

14

12

15 16

13

220

RN22

3 4

10

5

11

6

12

10

13

11

14

12

15

13

16

220

RN26

3 4

10

5

11

6

12

10

13

11

14

12

15

13

16

220

Port STS3

89

7

A

6

7

B

4

6

C

2

5

D

1

4

E

9

3

F

10

2

G

1

5

DP

DS5

DS5 Red

Red

Port ID2

7

89

A

6

7

B

4

6

C

2

5

D

1

4

E

9

3

F

10

2

G

5

1

DP

DS9

DS9 Red

Red

Port STS2 USERDEBUG0

7

89

A

6

7

B

4

6

C

2

5

D

1

4

E

9

3

F

10

2

G

5

1

DP

DS13

DS13 Red

Red

3.3VCC1

8

ANODE03ANODE1

3.3VCC1

1 2

8 9

MM74HC164

Place the USERDEBUG[1:0] related components close to the ATX power connector

3.3VCC1

8

ANODE03ANODE1

3.3VCC1 3.3VCC1 3.3VCC1 3.3VCC1

8

ANODE03ANODE1

1 2

8 9

MM74HC164

Place USERDEBUG0 and USERDEBUG1 at the top right of the Board. USERDEBUG0 is Unit Digit and USERDEBUG1 is tens digit. Place it close to the ATX24 power connector

3.3VCC1 3.3VCC1

1 2

8 9

MM74HC164

3.3VCC1

3

3.3VCC1

3.3VCC1 3.3VCC1

U30

14

QA

A

VCC

QB

B

QC

CLK

QD QE

CLR

QF QG QH

GND

7

RN15

3 4

10

5

11

6

12

10

13

11

14

12

15

13

16

220

Port ID1

7

89

6

7

4

6

2

5

1

4

9

3

10

2

5

1

DS2

DS2 Red

Red

3.3VCC1

8

A B C D E F G DP

1 2

8

ANODE03ANODE1

9

MM74HC164

3.3VCC1

U34

14

QA

A

QB

B

VCC

QC

CLK

QD QE

CLR

QF QG QH

GND

7

RN19

3 4

10

5

11

6

12

10

13

11

14

12

15 16

13

220

Port STS1

89

7 6

7

4

6

2

5

1

4

9

3

10

2 1

5

DS6

DS6 Red

Red

3.3VCC1

8

A B C D E F G DP

1 2

8

ANODE03ANODE1

9

MM74HC164

3.3VCC1

U38

14

3

QA

A

4

10

QB

B

VCC

5

11

QC

6

CLK CLR

GND

7

U42

14

A

VCC

B CLK CLR

GND

7

12

QD

10

13

QE

11

14

QF

12

15

QG

13

16

QH

3

QA

4

10

QB

5

11

QC

6

12

QD

10

13

QE

11

14

QF

12

15

QG

13

16

QH

USERDEBUG1 Port ID6 Port ID4

RN23

220

RN27

220

7

89

6

7

4

6

2

5

1

4

9

3

10

2

5

1

DS10

DS10 Red

Red

7

89

6

7

4

6

2

5

1

4

9

3

10

2

5

1

DS14

DS14 Red

Red

3.3VCC1

8

A B C D E F G DP

8

A B C D E F G DP

1 2

8

ANODE03ANODE1

9

MM74HC164

1 2

8

ANODE03ANODE1

9

MM74HC164

3.3VCC1

2

LEDSET1

U31

A B

CLK CLR

14

QA

VCC

QB QC QD

QE

QF QG QH

GND

7

RN16

3 4 5 6 10 11 12 13

89 7

10

6

11

5

12

4

13

3

14

2

15

1

16

220

3.3VCC1

Port ID7 Port ID5

7

A

6

B

4

C

2

D

1

E

9

F

10

G

5

DP

DS3

DS3 Red

Red

3.3VCC13.3VCC1

8

ANODE03ANODE1

1 2

8 9

MM74HC164

3.3VCC1

U35

14

QA

A

QB

B

VCC

QC

CLK

QD

QE

CLR

QF QG QH

GND

7

RN20

3 4

10

5

11

6

12

10

13

11

14

12

15 16

13

220

Port STS7

89

7

A

6

7

B

4

6

C

2

5

D

1

4

E

9

3

F

10

2

G

1

5

DP

DS7

DS7 Red

Red

3.3VCC1

8

ANODE03ANODE1

1 2

8 9

MM74HC164

3.3VCC1

U39

14

QA

A

QB

B

VCC

QC

CLK

QD

QE

CLR

QF QG QH

GND

7

3.3VCC1 3.3VCC1

U43

14

QA

A

VCC

QB

B

QC

CLK

QD

QE

CLR

QF QG QH

GND

7

RN24

3 4

10

5

11

6

12

10

13

11

14

12

15

13

16

220

7

89

A

6

7

B

4

6

C

2

5

D

1

4

E

9

3

F

10

2

G

5

1

DP

DS11

DS11 Red

Red

Port STS6 Port STS4

RN28

3 4

10

5

11

6

12

10

13

11

14

12

15

13

16

220

7

89

A

6

7

B

4

6

C

2

5

D

1

4

E

9

3

F

10

2

G

5

1

DP

DS15

DS15 Red

Red

3.3VCC1

8

ANODE03ANODE1

1 2

8 9

MM74HC164

3.3VCC1

8

ANODE03ANODE1

1 2

8 9

3.3VCC1

1

3.3VCC1

LEDSET1LEDSET0 LEDSET0

3.3VCC1

U32

14

QA

A

VCC

QB

B

QC

CLK

QD

QE

CLR

QF QG QH

GND

7

RN17

3 4 5 6 10 11 12 13

89 7

10

6

11

5

12

4

13

3

14

2

15

1

16

220

8

7

A

6

B

4

C

2

ANODE03ANODE1

D

1

E

9

F

10

G

5

DP

DS4

DS4 Red

Red

3.3VCC1

U36

14

QA

A

QB

B

VCC

QC

CLK

QD

QE

CLR

QF QG QH

GND

7

RN21

3 4

10

5

11

6

12

10

13

11

14

12

15 16

13

220

Port STS5

89 7 6 5 4 3 2 1

8

7

A

6

B

4

C

2

ANODE03ANODE1

D

1

E

9

F

10

G

5

DP

DS8

DS8 Red

Red

3.3VCC1

U40

14

QA

A

QB

B

VCC

QC

CLK

QD

QE

CLR

QF QG QH

GND

7

U44

14

QA

A

VCC

QB

B

QC

CLK

QD

QE

CLR

QF QG QH

GND

MM74HC164

7

RN25

3 4 5 6 10 11 12 13

89 7

10

6

11

5

12

4

13

3

14

2

15

1

16

220

RN29

89 7

10

6

11

5

12

4

13

3

14

2

15

1

16

220

8

7

A

6

B

4

C

2

ANODE03ANODE1

D

1

E

9

F

10

G

5

DP

DS12

DS12 Red

Red

8

7

A

6

B

4

C

2

ANODE03ANODE1

D

1

E

9

F

10

G

5

DP

DS16

DS16 Red

Red

C215

C212

C213

C214

C211

A A

5

C211

0.01uF

4

0.01uF

C214

0.01uF

C215

0.01uF

C216

0.01uF

C218

C217

0.01uF

3

C219

0.01uF

C220

0.01uF

C221

0.01uF

C222

0.01uF

2

C224

C225

C223

0.01uF

Title

Size Document Number Rev

Size Document Number Rev C

C

C Date: Sheet

Date: Sheet

C225

C226

0.01uF

8615 Base Board RDK

91-0132-000-A 0

C226

0.01uF

PLX TECHNOLOGY, INC.

870 W Maude Ave, Sunnyvale, CA 94085

870 W Maude Ave, Sunnyvale, CA 94085 www.plxtech.com

www.plxtech.com

1

17 26Thursday, February 12, 2009

of

5

3.3VCC1

U85A

74LVC04/SO

147

PEX_PERST_n[8,17,19,21,26]

D D

1 2

subpart F not used

U85C

74LVC04/SO

5 6

4

3

2

1

LEDSET2_DATA[26]

LEDSET2_CLK[26]

C C

U85E

U85E 74LVC04/SO

74LVC04/SO

11 10

3.3VCC1

LEDSET2 LEDSET2

3.3VCC1

U45

1 2

8 9

MM74HC164

14

QA

A

QB

B

VCC

QC

CLK

QD QE

CLR

QF QG QH

GND

7

RN30

3 4

10

5

11

6

12

10

13

11

14

12

15

13

16

220

Port ID11

8

7

89

A

6

7

B

4

6

C

2

5 4 3 2 1

ANODE03ANODE1

D

1

E

9

F

10

G

5

DP

DS17

DS17 Red

Red

3.3VCC1

U49

1

A

2

B

8

CLK

9

CLR

MM74HC164

3.3VCC1 14

VCC

GND

7

RN34

3

QA

10

4

QB

5

11

QC

6

12

QD

10

13

QE

11

14

QF

12

15

QG

13

16

QH

220

Port STS11

89 7 6 5 4 3 2 1

8

7

A

6

B

4

C

2

ANODE03ANODE1

D

1

E

9

F

10

G

5

DP

DS21

DS21 Red

Red

3.3VCC1

U46

1

A

2

B

8

CLK

9

CLR

MM74HC164

U50

1

A

2

B

8

CLK

9

CLR

MM74HC164

3.3VCC1 14

VCC

GND

7

3.3VCC1 14

VCC

GND

7

3.3VCC1

Port ID9

RN31

3

QA

4

QB

5

QC

6

QD

10

QE

11

QF

12

QG

13

QH

89 7

10

6

11

5

12

4

13

3

14

2

15

1

16

220

8

7

A

6

B

4

C

2

ANODE03ANODE1

D

1

E

9

F

10

G

5

DP

DS18

DS18 Red

Red

3.3VCC1

Port STS9

RN35

3

QA

4

QB

5

QC

6

QD

10

QE

11

QF

12

QG

13

QH

89 7

10

6

11

5

12

4

13

3

14

2

15

1

16

220

8

7

A

6

B

4

C

2

ANODE03ANODE1

D

1

E

9

F

10

G

5

DP

DS22

DS22 Red

Red

3.3VCC1 3.3VCC1

3.3VCC1

U53

14

1

QA

A

2

VCC

QB

B

QC

B B

8

CLK

9

CLR

MM74HC164

QD QE QF QG QH

GND

7

RN38

3 4

10

5

11

6

12

10

13

11

14

12

15

13

16

220

Port ID10

89

7

A

6

7

B

4

6

C

2

5

D

1

4

E

9

3

F

10

2

G

5

1

DP

DS25

DS25 Red

Red

3.3VCC1

U54

8

ANODE03ANODE1

U54

1

A

2

B

8

CLK

9

CLR

MM74HC164

14

QA

VCC

QB QC QD QE QF

QG

QH

GND

7

RN39

3 4

10

5

11

6

12

10

13

11

14

12

15

13

16

220

Port ID8

89 7 6 5 4 3 2 1

8

7

A

6

B

4

C

2

ANODE03ANODE1

D

1

E

9

F

10

G

5

DP

DS26

DS26 Red

Red

3.3VCC1 3.3VCC1

C230

0.01uF

Port STS10

7

89

A

6

7

B

4

6

C

2

5

D

1

4

E

9

3

F

10

2

G

5

1

DP

DS29

DS29 Red

Red

3.3VCC1

U58

8

ANODE03ANODE1

U58

1

A

2

B

8

CLK

9

CLR

MM74HC164

3.3VCC13.3VCC1

C231

0.01uF

14

QA

VCC

QB QC QD QE QF

QG

QH

GND

7

C232

0.01uF

RN43

3 4

10

5

11

6

12

10

13

11

14

12

15

13

16

220

C233

0.01uF

3

3.3VCC1

3.3VCC1 3.3VCC1

U57

14

1

QA

A

2

VCC

QB

B

QC

8

CLK

QD QE

9

CLR

QF QG QH

GND

7

MM74HC164

C227

A A

5

C227

0.01uF

C228

0.01uF

4

RN42

3 4

10

5

11

6

12

10

13

11

14

12

15

13

16

220

C229

0.01uF

C234

89 7 6 5 4 3 2 1

0.01uF

Port STS8

7

A

6

B

4

C

2

D

1

E

9

F

10

G

5

DP

DS30

DS30 Red

Red

8

ANODE03ANODE1

PLX TECHNOLOGY, INC.

870 W Maude Ave, Sunnyvale, CA 94085

870 W Maude Ave, Sunnyvale, CA 94085 www.plxtech.com

www.plxtech.com

Title

Size Document Number Rev

Size Document Number Rev C

C

C Date: Sheet

Date: Sheet

2

Date: Sheet

www.plxtech.com

8615 Base Board RDK

91-0132-000-A 0

1

18 26Thursday, February 12, 2009

of

5

3.3VCC1

U92A

147

PEX_PERST_n[8,17,18,21,26]

1 2

74LVC04/SO

LEDSET6_DATA[26]

D D

LEDSET6_CLK[26]

LEDSET5_DATA[26]

LEDSET5_CLK[26]

LEDSET4_DATA[26]

LEDSET4_CLK[26]

3.3VCC1

U87A

74LVC04/SO

147

U92F

U92F 74LVC04/SO

74LVC04/SO

13 12

3 4

74LVC04/SO

U87D

U87D 74LVC04/SO

74LVC04/SO

9 8

U91C

74LVC04/SO

5 6

U92D

U92D 74LVC04/SO

74LVC04/SO

9 8

U92B

3.3VCC1

1 2

MM74HC164

3.3VCC1

U91A

74LVC04/SO

147

C C

1 2

MM74HC164

3.3VCC1

LEDSET4

U62

1

A

2

B

8

CLK

9

CLR

U64

1

A

2

B

8

CLK

9

CLR

MM74HC164

3.3VCC1 14

VCC

GND

7

3.3VCC1 14

VCC

GND

7

4

3

2

1

3.3VCC1 3.3VCC1

LEDSET6

3.3VCC1

U83

1

A

2

B

8

CLK

9

CLR

MM74HC164

U84

1

A

2

B

8

CLK

9

CLR

MM74HC164

3.3VCC1 14

VCC

GND

7

3.3VCC1 14

VCC

GND

7

3

QA

4

QB

5

QC

6

QD

10

QE

11

QF

12

QG

13

QH

3

QA

4

QB

5

QC

6

QD

10

QE

11

QF

12

QG

13

QH

PEX_LN11_2p5G [20] PEX_LN11_5p0G [20] PEX_LN10_2p5G [20] PEX_LN10_5p0G [20] PEX_LN9_2p5G [20] PEX_LN9_5p0G [20] PEX_LN8_2p5G [20] PEX_LN8_5p0G [20]

Port RCPT1 ID

RN46

3

QA

4

10

QB

5

11

QC

6

12

QD

10

13

QE

11

14

QF

12

15

QG

13

16

QH

220

7

89

6

7

4

6

2

5

1

4

9

3

10

2

5

1

DS33

DS33 Red

Red

3.3VCC1

8

A B C

ANODE03ANODE1

D E F G DP

3.3VCC1

Port RCPT1 STS

RN48

3

QA

4

QB

5

QC

6

QD

10

QE

11

QF

12

QG

13

QH

89

7

10 11 12 13 14 15 16

220

6

4 2

5

1

4

9

3

10

2

5

1

DS35

DS35 Red

Red

3.3VCC1

8

A B C

ANODE03ANODE1

D E F G DP

U63

1

A

2

B

8

CLK

9

CLR

MM74HC164

U65

1

A

2

B

8

CLK

9

CLR

MM74HC164

LEDSET5

3.3VCC1 14

VCC

GND

7

3.3VCC1 14

VCC

GND

7

TEMPERATURE100

RN47

3

QA

4

QB

5

QC

6

QD

10

QE

11

QF

12

QG

13

QH

89 7

10

6

11

5

12

4

13

3

14

2

15

1

16

220

8

7

A

6

B

4

C

2

ANODE03ANODE1

D

1

E

9

F

10

G

5

DP

DS34

DS34 Red

Red

3.3VCC1

TEMPERATURE10

RN49

3

QA

4

QB

5

QC

6

QD

10

QE

11

QF

12

QG

13

QH

89 7

10

6

11

5

12

4

13

3

14

2

15

1

16

220

8

7

A

6

B

4

C

2

ANODE03ANODE1

D

1

E

9

F

10

G

5

DP

DS36

DS36 Red

Red

3.3VCC1 3.3VCC1

3.3VCC1

U88

1

A

2

B

8

CLK

9

CLR

MM74HC164

3.3VCC1 14

VCC

GND

7

3

QA

4

QB

5

QC

6

QD

10

QE

11

QF

12

QG

13

QH

PEX_LN7_2p5G [20] PEX_LN7_5p0G [20] PEX_LN6_2p5G [20] PEX_LN6_5p0G [20] PEX_LN5_2p5G [20] PEX_LN5_5p0G [20] PEX_LN4_2p5G [20] PEX_LN4_5p0G [20]

3.3VCC1

U66

14

A B

CLK CLR

7

MM74HC164

3

QA

10

4

VCC

QB

5

11

QC

6

12

QD

10

13

QE

11

14

QF

12

15

QG

13

16

QH

GND

1 2

B B

8 9

RN50

220

Port RCPT0 ID

89 7 6 5 4 3 2 1

3.3VCC1

U67

8

7

A

6

B

4

C

2

ANODE03ANODE1

D

1

E

9

F

10

G

5

DP

DS37

DS37 Red

Red

U67

1

A

2

B

8

CLK

9

CLR

MM74HC164

14

3

QA

4

VCC

QB

5

QC

6

QD

10

QE

11

QF

12

QG

13

QH

GND

7

TEMPERATURE1

RN51

89 7

10

6

11

5

12

4

13

3

14

2

15

1

16

220

8

7

A

6

B

4

C

2

ANODE03ANODE1

D

1

E

9

F

10

G

5

DP

DS38

DS38 Red

Red

3.3VCC1 3.3VCC1

3.3VCC1

U89

14

1 2

8 9

Title

8615 Base Board RDK

Size Document Number Rev

Size Document Number Rev C

C

C Date: Sheet

Date: Sheet

3

QA

A

4

QB

B

VCC

5

QC

6

CLK

QD

10

QE

11

CLR

QF

12

QG

13

QH

GND

7

MM74HC164

3.3VCC1

C312

C313

0.01uF

C313

0.01uF

1

C314

0.01uF

PLX TECHNOLOGY, INC.

870 W Maude Ave, Sunnyvale, CA 94085

870 W Maude Ave, Sunnyvale, CA 94085 www.plxtech.com

www.plxtech.com

91-0132-000-A 0

C311

0.01uF

PEX_LN3_2p5G [20] PEX_LN3_5p0G [20] PEX_LN2_2p5G [20] PEX_LN2_5p0G [20] PEX_LN1_2p5G [20] PEX_LN1_5p0G [20] PEX_LN0_2p5G [20] PEX_LN0_5p0G [20]

19 26Thursday, February 12, 2009

of

C249

0.01uF

TEMPERATURE0.1

RN53

89 7

10

6

11

5

12

4

13

3

14

2

15

1

16

220

C250

0.01uF

8

7

A

6

B

4

C

2

ANODE03ANODE1

D

1

E

9

F

10

G

5

DP

DS40

DS40 Red

Red

2

3.3VCC1 3.3VCC1

U68

14

1 2

8 9

A A

5

3

QA

A

4

VCC

B CLK CLR

GND

7

MM74HC164

3.3VCC1 3.3VCC1

C243

0.01uF

10

QB

5

11

QC

6

12

QD

10

13

QE

11

14

QF

12

15

QG

13

16

QH

C244

C245

0.01uF

4

RN52

220

C246

0.01uF

89 7 6 5 4 3 2 1

Port RCPT0 STS

7

A

6

B

4

C

2

D

1

E

9

F

10

G

5

DP

DS39

DS39 Red

Red

U69

8

ANODE03ANODE1

U69

14

1 2

8 9

3

QA

A

4

VCC

QB

B

5

QC

6

CLK

QD

10

QE

11

CLR

QF

12

QG

13

QH

GND

7

MM74HC164

C248

C247

0.01uF

The above FOUR 7Segs should Be placed in accordance with their Name. TEMPERATURE.01 is the LSD and TEMPERATURE100 is the MSD.

3

5

Except for PEX_LN0_xpxG LED all of the LEDs on this page are associated to slots. Place them accordingly with the Port IDx(x) and Port STSx(x). The PEX_LN0_XpxG should be placed with the close to Port ID/Port STS LED for the PCIe Receptacle

D D

PEX_LN0_2p5G[19] PEX_LN0_5p0G[19]

D12

R216

R216 390

390

3.3VCC1

43

R

21

R217

R217 390

390

G

GREEN_AMBER_LED

4

3.3VCC1

R219

R218

390

21

43

G

Y

G

Y

D13

GREEN_AMBER_LED

PEX_LN4_2p5G[19] PEX_LN4_5p0G[19]

GREEN_AMBER_LED

3

3.3VCC1

R221

R220

390

21

43

G

Y

G

Y

D14

GREEN_AMBER_LED

PEX_LN8_2p5G[19] PEX_LN8_5p0G[19]

GREEN_AMBER_LED

2

1

D17

D21

D25

R226

R226 390

390

R234

R234 390

390

R242

R242 390

390

3.3VCC1

43

Y

3.3VCC1

43

Y

3.3VCC1

43

Y

21

R227

R227 390

390

G

GREEN_AMBER_LED

R235

R235 390

390

G

GREEN_AMBER_LED

R243

R243 390

390

G

GREEN_AMBER_LED

PEX_LN9_2p5G[19] PEX_LN9_5p0G[19]

PEX_LN10_2p5G[19] PEX_LN10_5p0G[19]

PEX_LN11_2p5G[19] PEX_LN11_5p0G[19]

3.3VCC1

R225

R224

390

21

43

G

Y

G

Y

D16

GREEN_AMBER_LED

D20

D24

R232

R232 390

390

R240

R240 390

390

3.3VCC1

43

Y

3.3VCC1

43

Y

21

GREEN_AMBER_LED

R233

R233 390

390

G

GREEN_AMBER_LED

R241

R241 390

390

G

GREEN_AMBER_LED

PEX_LN1_2p5G[19] PEX_LN1_5p0G[19]

C C

PEX_LN2_2p5G[19] PEX_LN2_5p0G[19]

B B

PEX_LN3_2p5G[19] PEX_LN3_5p0G[19]

PEX_LN5_2p5G[19] PEX_LN5_5p0G[19]

PEX_LN6_2p5G[19] PEX_LN6_5p0G[19]

PEX_LN7_2p5G[19] PEX_LN7_5p0G[19]

D18

D22

D26

R228

R228 390

390

R236

R236 390

390

R244

R244 390

390

3.3VCC1

43

Y

3.3VCC1

43

Y

3.3VCC1

43

Y

21

G

21

G

21

G

R229

R229 390

390

GREEN_AMBER_LED

R237

R237 390

390

GREEN_AMBER_LED

R245

R245 390

390

GREEN_AMBER_LED

A A

PLX TECHNOLOGY, INC.

870 W Maude Ave, Sunnyvale, CA 94085

870 W Maude Ave, Sunnyvale, CA 94085 www.plxtech.com

www.plxtech.com

Title

Size Document Number Rev

Size Document Number Rev C

C

C Date: Sheet

Date: Sheet

5

4

3

2

Date: Sheet

www.plxtech.com

8615 Base Board RDK

91-0132-000-A 0

1

20 26Thursday, February 12, 2009

of

5

4

3

2

1

SERIAL HOT PLUG CIRCUIT FOR SLOT 8

To demonstrate the serial hot plug function of PEX 8614 requires the chip to boot with EEPROM and sets both

D D

3.3VCC

RN54

1

8

2

7

3

C255

0.1uF

24 21

2 3

22 23

1

12

6

U71

V+

IO0 IO1

AD0

IO2

AD1

IO3

AD2

IO4 IO5 IO6

SCL

IO7

SDA

IO8 IO9

IO10 IO11

INT#

IO12 IO13

GND

IO14 IO15

MAX7311AUG

4R 4.7K

45

4 5 6 7 8 9 10

SLOT0_3

11

SLOT1_3

13

SLOT2_3

14

SLOT3_3

15 16 17 18 19 20

AD0_3

R254 1KR254 1K

AD1_3

R257 1KR257 1K

AD2_3

R258 1KR258 1K

R259 4.7KR259 4.7K

3.3VCC

R260 4.7KR260 4.7K

I2C_SCL1

3.3VCC

I2C_SCL1 I2C_SDA1

R266 4.7KR266 4.7K

SHPC_INT_n

I2C_SCL1[8] I2C_SDA1[8]

SHPC_INT_n[8,26]

C C

1 2 3 4

PWRLED#_S ATNLED#_S PWREN_S CLKEN#_S PERST#_S INTERLOCK_S GPIO_S

PRSNT_n_SL8 MRLI#_S BUTTONI#_S PWRFLT#_S PWRGOOD_S

pos. 1 and 2 of SW3 to "on" position.

SW10

8 7 6 5

SW DIP-4

TP1

Prototyping Pad

PRSNT_n_SL8 [12,26]

D28 GREEND28 GREEN

D31 GREEND31 GREEN

D32

2 1

GREEN

3.3VCC

R255

150

D3_2

21

D4_2

21

D5_1

R270

4.7K

4.7K S2

S2

4 2

SW PUSHBUTTON

R256

150

R26751R267

51

13

SW11

3 4

ON

SW DIP-2

5 6 7 8

R261 0.02 1%R261 0.02 1%

12V_A

PEX_PERST_n[8,17,18,19,26]

3.3VCC

R273

4.7K

2 1

SW2 Default Settings 1: off (disable MRL#_S) 2: off (disable Serial HP)

12V_SLT_8_HP

R248

R249

100K 1%

12VG_4

IS1_4

PWREN_5

V_4

C256

R271 4.7KR271 4.7K

2 3 5

6 11 10 14 13

1

SN74LVC157APW

R249

12.4K 1%

U70

VS1_4

VSENSE17VSENSE2 DISCH120DISCH2 GATE11GATE2 ISENSE110ISENSE2

15

ISET1

11

IN1

18

ENABLE

5

VREG

3

DGND

8

AGND

TPS2311PW

3.3VCC

16

U72

1A

VCC

1B 2A 2B 3A 3B 4A 4B

A#/B

GND

8

R250

13.7K 1%

ISET2

IN2 PWRGD1# PWRGD2#

TIMER

FAULT#

C258

0.1uF

4

1Y

PERST_n_SL8

7

2Y

CLKEN_n_SL8

9

3Y

12

4Y

15

G#

C251 0.1uFC251 0.1uF

C253 NLC253 NL

Q1

1

D0

S0

2

D1

S1

3

D2

S2

D3

4

G

IRF7470PBF

12VSENSE_4

R262 2KR262 2K R263 2KR263 2K

0.1uF

PWREN_S PERST#_S

PEX_PERST_n CLKEN#_S

R274

4.7K

HP_SL8_CTL MRLI#_S

VS2_4

6 19 2 9

IS_4

14 12

17 13

T_4

4 16

C257

C257 1uF

1uF

R272 4.7KR272 4.7K

3.3VCC_SLT_8_HP

R251

20K 1%

3VG_4 3VSENSE_4

R265 4.7KR265 4.7K

PWRGOOD_S

FAULT#_4

PERST_n_SL8 [12]

C252 0.1uFC252 0.1uF

C254 NLC254 NL

R268 4.7KR268 4.7K R269 0R269 0

1

S0

2

S1

3

S2

4

G

IRF7470PBF

R264 0.02 1%R264 0.02 1%

Q2

5

D0

6

D1

7

D2

8

D3

3.3VCC_SLT_8

3.3VCC

PWRFLT#_S

U92C

74LVC04/SO

5 6

D1_2

21

R252

1.2K

D29

GREEN

3.3VCC_SLT_8_HP12V_SLT_8_HP

R253

R253 150

150

D2_2

21

D30

GREEN

CLKEN_SL8 [26]

B B

A A

PLX TECHNOLOGY, INC.

870 W Maude Ave, Sunnyvale, CA 94085

870 W Maude Ave, Sunnyvale, CA 94085 www.plxtech.com

www.plxtech.com

Title

Size Document Number Rev

Size Document Number Rev C

C

C Date: Sheet

Date: Sheet

5

4

3

2

Date: Sheet

www.plxtech.com

8615 Base Board RDK

91-0132-000-A 0

1

21 26Thursday, February 12, 2009

of

5

D D

U74A

123

A3

TX0_S_p

C3

TX0_S_n

A7

TX1_S_p

C7

TX1_S_n

A11

TX2_S_p

C11

TX2_S_n

A15

TX3_S_p

C15

TX3_S_n

A19

TX4_S_p

C19

TX4_S_n

H3

RX0_S0_p

G2

RX0_S1_p

H2

RX0_S2_p

J3

RX0_S0_n

I2

RX0_S1_n

J2

RX0_S2_n

H7

RX1_S0_p

G6

RX1_S1_p

H6

RX1_S2_p

J7

RX1_S0_n

I6

RX1_S1_n

J6

RX1_S2_n

H11

RX2_S0_p

G10

RX2_S1_p

H10

RX2_S2_p

J11

RX2_S0_n

I10

RX2_S1_n

J10

RX2_S2_n

H15

RX3_S0_p

G14

RX3_S1_p

H14

RX3_S2_p

J15

RX3_S0_n

I14

RX3_S1_n

J14

RX3_S2_n

H19

RX4_S0_p

G18

RX4_S1_p

H18

RX4_S2_p

J19

RX4_S0_n

I18

RX4_S1_n

J18

RX4_S2_n

F1

PRESENT

E1

CFGID0

E2

CFGID1

45

RN60

RN60 4R 4.7K

4R 4.7K

TX0p_RECEPT1[7]

TX0n_RECEPT1[7]

TX1p_RECEPT1[7]

TX1n_RECEPT1[7]

TX2p_RECEPT1[7]

TX2n_RECEPT1[7]

TX3p_RECEPT1[7]

C C

B B

TX3n_RECEPT1[7]

RX0p_PCIe_Cable[16] RX0p_PCIe_Cable[16]

RX0n_PCIe_Cable[16] RX0n_PCIe_Cable[16]

RX1p_PCIe_Cable[16] RX0p_SL1[9]

RX1n_PCIe_Cable[16] RX0n_SL1[9]

RX2p_PCIe_Cable[16] RX0p_SL2[9]

RX2n_PCIe_Cable[16] RX0n_SL2[9]

RX3p_PCIe_Cable[16] RX0p_SL3[10]

RX3n_PCIe_Cable[16] RX0n_SL3[10]

RECP0_PRES_n[26] RECP0_CFGID0[26] RECP0_CFGID1[26]

TXRX

TX0_D0_p TX0_D1_p TX0_D2_p

TX0_D0_n TX0_D1_n TX0_D2_n

TX1_D0_p TX1_D1_p TX1_D2_p

TX1_D0_n TX1_D1_n TX1_D2_n

TX2_D0_p TX2_D1_p TX2_D2_p

TX2_D0_n TX2_D1_n TX2_D2_n

TX3_D0_p TX3_D1_p TX3_D2_p

TX3_D0_n TX3_D1_n TX3_D2_n

TX4_D0_p TX4_D1_p TX4_D2_p

TX4_D0_n TX4_D1_n TX4_D2_n

RX0_D_p

RX0_D_n

RX1_D_p

RX1_D_n

RX2_D_p

RX2_D_n

RX3_D_p

RX3_D_n

RX4_D_p

RX4_D_n

B3 A2 B2

D3 C2 D2

B7 A6 B6

D7 C6 D6

B11 A10 B10

D11 C10 D10

B15 A14 B14

D15 C14 D14

B19 A18 B18

D19 C18 D18

G3

I3

G7

I7

G11

I11

G15

I15

G19

I19

Receptacle 10 x 20

TX0p_PCIe_Cable [16] TX0p_PCIe_Cable [16]

TX0n_PCIe_Cable [16] TX0n_PCIe_Cable [16]

TX1p_PCIe_Cable [16] TX0p_SL1 [9]

TX1n_PCIe_Cable [16] TX0n_SL1 [9]

TX2p_PCIe_Cable [16] TX0p_SL2 [9]

TX2n_PCIe_Cable [16] TX0n_SL2 [9]

TX3p_PCIe_Cable [16] TX0p_SL3 [10]

TX3n_PCIe_Cable [16] TX0n_SL3 [10]

RX0p_RECEPT1 [7]

RX0n_RECEPT1 [7]

RX1p_RECEPT1 [7]

RX1n_RECEPT1 [7]

RX2p_RECEPT1 [7]

RX2n_RECEPT1 [7]

RX3p_RECEPT1 [7]

RX3n_RECEPT1 [7]

4

123

A3

C3

A7

C7

A11

C11

A15

C15

A19

C19

H3 G2 H2

J3

I2

J2

H7 G6 H6

J7

I6

J6

H11 G10 H10

J11

I10

J10

H15 G14 H14

J15

I14

J14

H19 G18 H18

J19

I18

J18

F1 E1 E2

45

RN59

RN59 4R 4.7K

4R 4.7K

TX0p_RECEPT2[7]

TX0n_RECEPT2[7]

TX1p_RECEPT2[7]

TX1n_RECEPT2[7]

TX2p_RECEPT2[7]

TX2n_RECEPT2[7]

TX3p_RECEPT2[7]

TX3n_RECEPT2[7]

RX0p_SL4[10] RX0p_SL4[10] RX4p_PCIe_Cable[16]

RX0n_SL4[10] RX0n_SL4[10] RX4n_PCIe_Cable[16]

RX1p_SL4[10] RX0p_SL5[11] RX5p_PCIe_Cable[16]

RX1n_SL4[10] RX0n_SL5[11] RX5n_PCIe_Cable[16]

RX2p_SL4[10] RX0p_SL6[11] RX6p_PCIe_Cable[16]

RX2n_SL4[10] RX0n_SL6[11] RX6n_PCIe_Cable[16]

RX3p_SL4[10] RX0p_SL7[12] RX7p_PCIe_Cable[16]

RX3n_SL4[10] RX0n_SL7[12] RX7n_PCIe_Cable[16]

RECP1_PRES_n[26] RECP1_CFGID0[26] RECP1_CFGID1[26]

U75A

TX0_S_p

TX0_S_n

TX1_S_p

TX1_S_n

TX2_S_p

TX2_S_n

TX3_S_p

TX3_S_n

TX4_S_p

TX4_S_n

RX0_S0_p RX0_S1_p RX0_S2_p

RX0_S0_n RX0_S1_n RX0_S2_n

RX1_S0_p RX1_S1_p RX1_S2_p

RX1_S0_n RX1_S1_n RX1_S2_n

RX2_S0_p RX2_S1_p RX2_S2_p

RX2_S0_n RX2_S1_n RX2_S2_n

RX3_S0_p RX3_S1_p RX3_S2_p

RX3_S0_n RX3_S1_n RX3_S2_n

RX4_S0_p RX4_S1_p RX4_S2_p

RX4_S0_n RX4_S1_n RX4_S2_n

PRESENT CFGID0 CFGID1

3

TXRX

TX0_D0_p TX0_D1_p TX0_D2_p

TX0_D0_n TX0_D1_n TX0_D2_n

TX1_D0_p TX1_D1_p TX1_D2_p

TX1_D0_n TX1_D1_n TX1_D2_n

TX2_D0_p TX2_D1_p TX2_D2_p

TX2_D0_n TX2_D1_n TX2_D2_n

TX3_D0_p TX3_D1_p TX3_D2_p

TX3_D0_n TX3_D1_n TX3_D2_n

TX4_D0_p TX4_D1_p TX4_D2_p

TX4_D0_n TX4_D1_n TX4_D2_n

B3 A2 B2

D3 C2 D2

B7 A6 B6

D7 C6 D6

B11 A10 B10

D11 C10 D10

B15 A14 B14

D15 C14 D14

B19 A18 B18

D19 C18 D18

G3

RX0_D_p

I3

RX0_D_n

G7

RX1_D_p

I7

RX1_D_n

G11

RX2_D_p

I11

RX2_D_n

G15

RX3_D_p

I15

RX3_D_n

G19

RX4_D_p

I19

RX4_D_n

Receptacle 10 x 20

TX0p_SL4 [10] TX0p_SL4 [10] TX4p_PCIe_Cable [16]

TX0n_SL4 [10] TX0n_SL4 [10] TX4n_PCIe_Cable [16]

TX1p_SL4 [10] TX0p_SL5 [11] TX5p_PCIe_Cable [16]

TX1n_SL4 [10] TX0n_SL5 [11] TX5n_PCIe_Cable [16]

TX2p_SL4 [10] TX0p_SL6 [11] TX6p_PCIe_Cable [16]

TX2n_SL4 [10] TX0n_SL6 [11] TX6n_PCIe_Cable [16]

TX3p_SL4 [10] TX0p_SL7 [12] TX7p_PCIe_Cable [16]

TX3n_SL4 [10] TX0n_SL7 [12] TX7n_PCIe_Cable [16]

RX0p_RECEPT2 [7]

RX0n_RECEPT2 [7]

RX1p_RECEPT2 [7]

RX1n_RECEPT2 [7]

RX2p_RECEPT2 [7]

RX2n_RECEPT2 [7]

RX3p_RECEPT2 [7]

RX3n_RECEPT2 [7]

2

U76A

123

A3

TX0_S_p

C3

TX0_S_n

A7

TX1_S_p

C7

TX1_S_n

A11

TX2_S_p

C11

TX2_S_n

A15

TX3_S_p

C15

TX3_S_n

A19

TX4_S_p

C19

TX4_S_n

H3

RX0_S0_p

G2

RX0_S1_p

H2

RX0_S2_p

J3

RX0_S0_n

I2

RX0_S1_n

J2

RX0_S2_n

H7

RX1_S0_p

G6

RX1_S1_p

H6

RX1_S2_p

J7

RX1_S0_n

I6

RX1_S1_n

J6

RX1_S2_n

H11

RX2_S0_p

G10

RX2_S1_p

H10

RX2_S2_p

J11

RX2_S0_n

I10

RX2_S1_n

J10

RX2_S2_n

H15

RX3_S0_p

G14

RX3_S1_p

H14

RX3_S2_p

J15

RX3_S0_n

I14

RX3_S1_n

J14

RX3_S2_n

H19

RX4_S0_p

G18

RX4_S1_p

H18

RX4_S2_p

J19

RX4_S0_n

I18

RX4_S1_n

J18

RX4_S2_n

F1

PRESENT

E1

CFGID0

E2

CFGID1

45

RN58

RN58 4R 4.7K

4R 4.7K

TX0p_RECEPT3[7]

TX0n_RECEPT3[7]

TX1p_RECEPT3[7]

TX1n_RECEPT3[7]

TX2p_RECEPT3[7]

TX2n_RECEPT3[7]

TX3p_RECEPT3[7]

TX3n_RECEPT3[7]

RX0p_SL8[12] RX0p_SL8[12]

RX0n_SL8[12] RX0n_SL8[12]

RX1p_SL8[12] RX0p_SL9[13]

RX1n_SL8[12] RX0n_SL9[13]

RX2p_SL8[12] RX0p_SL10[13]

RX2n_SL8[12] RX0n_SL10[13]

RX3p_SL8[12] RX0p_SL11[14]

RX3n_SL8[12] RX0n_SL11[14]

RECP2_PRES_n[26] RECP2_CFGID0[26] RECP2_CFGID1[26]

TXRX

TX0_D0_p TX0_D1_p TX0_D2_p

TX0_D0_n TX0_D1_n TX0_D2_n

TX1_D0_p TX1_D1_p TX1_D2_p

TX1_D0_n TX1_D1_n TX1_D2_n

TX2_D0_p TX2_D1_p TX2_D2_p

TX2_D0_n TX2_D1_n TX2_D2_n

TX3_D0_p TX3_D1_p TX3_D2_p

TX3_D0_n TX3_D1_n TX3_D2_n

TX4_D0_p TX4_D1_p TX4_D2_p

TX4_D0_n TX4_D1_n TX4_D2_n

RX0_D_p

RX0_D_n

RX1_D_p

RX1_D_n

RX2_D_p

RX2_D_n

RX3_D_p

RX3_D_n

RX4_D_p

RX4_D_n

B3 A2 B2

D3 C2 D2

B7 A6 B6

D7 C6 D6

B11 A10 B10

D11 C10 D10

B15 A14 B14

D15 C14 D14

B19 A18 B18

D19 C18 D18

G3

I3

G7

I7

G11

I11

G15

I15

G19

I19

Receptacle 10 x 20

1

TX0p_SL8 [12] TX0p_SL8 [12]

TX0n_SL8 [12] TX0n_SL8 [12]

TX1p_SL8 [12] TX0p_SL9 [13]

TX1n_SL8 [12] TX0n_SL9 [13]

TX2p_SL8 [12] TX0p_SL10 [13]

TX2n_SL8 [12] TX0n_SL10 [13]

TX3p_SL8 [12] TX0p_SL11 [14]

TX3n_SL8 [12] TX0n_SL11 [14]

RX0p_RECEPT3 [7]

RX0n_RECEPT3 [7]

RX1p_RECEPT3 [7]

RX1n_RECEPT3 [7]

RX2p_RECEPT3 [7]

RX2n_RECEPT3 [7]

RX3p_RECEPT3 [7]

RX3n_RECEPT3 [7]

678

A A

5

4

678

3.3VCC13.3VCC13.3VCC1

3

678

PLX TECHNOLOGY, INC.

870 W Maude Ave, Sunnyvale, CA 94085

870 W Maude Ave, Sunnyvale, CA 94085 www.plxtech.com

www.plxtech.com

Title

Size Document Number Rev

Size Document Number Rev C

C

C Date: Sheet

Date: Sheet

2

Date: Sheet

www.plxtech.com

8615 Base Board RDK

91-0132-000-A 0

1

22 26Thursday, February 12, 2009

of

5

D D

PS_Pwr_Good[4,26]

C C

B B

3.3VCC1 3.3VCC1

R66

R67

51K

10K

S3

MAN_FPGA_RST

1 3

42

SW PUSHBUTTON

XILINX_VCC_CORE_1p2 XILINX_VCC_AUX_2p5

R348

R348 10K

10K

U21

5

4

VCC

Y

1

A

3

2

GND

B

NC7S08

C78

0.1uF

NC7S08

C79

1000pf

R347

R347 200

200

C77

47uF

C153

0.001uF

L2

1uHL21uH

Inductor/Bead Should be Rated Above 3Amps Inductor/Bead Should be Rated Above 3Amps

R349

C81

10K

1uF NL

C80

330pf

U20

RST IN3VCC

SRT4GND

MAX6420

C74

C75

0.1uF

10uF

C76

0.1uF

RESET#

C72

0.1uF

U117

27 28

24 25 26

21

22 23

30

4

5

1

2

REG_VDD

IN1_1 IN1_2

PGND1_1 PGND1_2 PGND1_3

BST1

LX1_1 LX1_2

COMP1

3.3VCC1

3

VDD

R34610R346

10

C154

0.1uF

3.3VCC1

R62 0R62 0

R64

This Net should go to FPGA GSR Capable Pin

5.1K

FPGA_RESET

C73

0.1uf

6

DUAL OUTPUT VOLTAGE REGULATOR

VDL

13

IN2_1

14

IN2_2

PGND2_1 PGND2_2 PGND2_3

BST2

LX2_1 LX2_2

COMP2

C83

0.1uF

15 16 17

20

C86

0.1uF

18 19

11

FPGA_RESET [26]

C84

10uF

L3

1uHL31uH

C161

C162

1uF

1uF NL

R35333R353

3

TP4

EXT_NVM_VDDQ

TP3

TP3 Prototyping Pad

Prototyping Pad

TP2

TP2 Prototyping Pad

Prototyping Pad

C156

R3501KR350

- Make the common trace on NVM_VDDQ thicker - Make the traces on pin 2 of both the Resistors Thicker - Populate 1 to 3 connection on Both of these shunts

EN_NVM_VDDQ[26]

SMBCLK_16[26] SMBDATA_16[26]

ALERT_n[26] OVERT_n[26]

C157

22uF

0.1uF

R351

1K

20K

C160

150pf

33

3.3VCC1

2 4

JP5

HDR 2X2

C389

1uF

C407

C407 1000pF

1000pF

C383

C383 1000pF

1000pF

2

C395

1uF

C399

C399 1000pF

1000pF

C259

C259 1000pF

1000pF

C261

C261 .1uF

.1uF

3.3VCC1

R278

R278 200

200

U78

1

VCC

8

SMBCLK

7

SMBDATA

6

ALTER#

4

OVERT1#

MAX6658

Decoupling Caps for FPGA. Place 1000pf close to the pins. Sprinkle 0.01uf around the chip. Sprinkle 1uf around the chip

C396

1uF

C400

C400 1000pF

1000pF

C260

C260 1000pF

1000pF

C401

C401 1000pF

1000pF

C334

C334 1000pF

1000pF

C387

0.01uF

C402

C402 1000pF

1000pF

C378

C378 1000pF

1000pF

R340

12

3

0 Shunt

0 Shunt R339

R339

12

3

0 Shunt

112 334

3.3VCC

C391

1uF

C408

C408 1000pF

1000pF

C394

C394 1000pF

1000pF

C392

1uF

C410

C410 1000pF

1000pF

C397

C397 1000pF

1000pF

RN56

RN56 10K

10K

123

C393

1uF

C409

C409 1000pF

1000pF

C398

C398 1000pF

1000pF

NVM_VDDQ [8]

678

4 5

1

2

DXP

C262

C262 2200pF

2200pF

3

DXN

5

GND

C384

0.01uF

C403

C403 1000pF

1000pF

C379

C379 1000pF

1000pF

C385

0.01uF

C404

C404 1000pF

1000pF

C380

C380 1000pF

1000pF

C386

0.01uF

C405

C405 1000pF

1000pF

C381

C381 1000pF

1000pF

TDIODE_p [8]

TDIODE_n [8]

C388

0.01uF

C406

C406 1000pF

1000pF

C382

C382 1000pF

1000pF

C390

0.01uF

XILINX_VCC_AUX_2p5

C418

C411

0.01uF

C413

0.01uF

C412

C415

C416

1000pF

1uF

1000pF

C417

C417 1000pF

1000pF

C418 1000pF

1000pF

31

FB1

R359

10K

2

REFIN

C82

REG_VDD

R357

A A

R357 20K

20K

REG_VDD

R352

R352 20K

20K

1000pf

EN1 EN2

5

32

SS1

5

NC

1

PWRGD1

29

EN1

GND

4

FSYNC

PWRGD2

EP

33

10

FB2

R358

20K

R3545KR354

7

20K

XILINX_VCC_CORE_1p2

5K

C422

C421

SS2

EN2

0.022uF

8 12

REG_VDD

R355

R355 20K

20K

REG_VDD

R356

R356 20K

20K

3

C163

9

C414

0.01uF

2

0.01uF

1uF

C423

C424

C414

C421

C419

1000pF

Title

Size Document Number Rev

Size Document Number Rev C

C

C Date: Sheet

Date: Sheet

C422

C420

1000pF

PLX TECHNOLOGY, INC.

870 W Maude Ave, Sunnyvale, CA 94085

870 W Maude Ave, Sunnyvale, CA 94085 www.plxtech.com

www.plxtech.com

8615 Base Board RDK

91-0132-000-A 0

1

23 26Thursday, February 12, 2009

of

5

U74B

D D

C C

B B

A1 A4 A5 A8

A9 A12 A13 A16 A17 A20

B1

B4

B5

B8

B9 B12 B13 B16 B17 B20

C1 C4 C5 C8

C9 C12 C13 C16 C17 C20

D1

D4

D5

D8

D9 D12 D13 D16 D17 D20

G1

G4

G5

G8

G9

G12 G13 G16 G17 G20

H1

H4

H5

H8

H9 H12 H13 H16 H17 H20

I1 I4 I5 I8

I9 I12 I13 I16 I17 I20

J1 J4 J5 J8

J9 J12 J13 J16 J17 J20

U74B

GND0 GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND10 GND11 GND12 GND13 GND14 GND15 GND16 GND17 GND18 GND19 GND20 GND21 GND22 GND23 GND24 GND25 GND26 GND27 GND28 GND29 GND30 GND31 GND32 GND33 GND34 GND35 GND36 GND37 GND38 GND39 GND40 GND41 GND42 GND43 GND44 GND45 GND46 GND47 GND48 GND49 GND50 GND51 GND52 GND53 GND54 GND55 GND56 GND57 GND58 GND59 GND60 GND61 GND62 GND63 GND64 GND65 GND66 GND67 GND68 GND69 GND70 GND71 GND72 GND73 GND74 GND75 GND76 GND77 GND78 GND79

Receptacle 10 x 20

NC10 NC11 NC12 NC13 NC14 NC15 NC16 NC17 NC18 NC19 NC20 NC21 NC22 NC23 NC24 NC25 NC26 NC27 NC28 NC29 NC30 NC31 NC32 NC33 NC34 NC35 NC36

NC0 NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9

4

E20 E11 E10 E9 E8 E7 E6 E5 E4 E3 E19 E18 E17 E16 E15 E14 E13 E12 F20 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F19 F18 F17 F16 F15 F14 F13 F12

A1 A4 A5 A8

A9 A12 A13 A16 A17 A20

B1

B4

B5

B8

B9 B12 B13 B16 B17 B20

C1

C4

C5

C8

C9

C12 C13 C16 C17 C20

D1

D4

D5

D8

D9

D12 D13 D16 D17 D20

G1

G4

G5

G8

G9

G12 G13 G16 G17 G20

H1

H4

H5

H8

H9

H12 H13 H16 H17 H20

I1 I4 I5 I8

I9 I12 I13 I16 I17 I20

J1

J4

J5

J8

J9

J12 J13 J16 J17 J20

3

U75B

GND0 GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND10 GND11 GND12 GND13 GND14 GND15 GND16 GND17 GND18 GND19 GND20 GND21 GND22 GND23 GND24 GND25 GND26 GND27 GND28 GND29 GND30 GND31 GND32 GND33 GND34 GND35 GND36 GND37 GND38 GND39 GND40 GND41 GND42 GND43 GND44 GND45 GND46 GND47 GND48 GND49 GND50 GND51 GND52 GND53 GND54 GND55 GND56 GND57 GND58 GND59 GND60 GND61 GND62 GND63 GND64 GND65 GND66 GND67 GND68 GND69 GND70 GND71 GND72 GND73 GND74 GND75 GND76 GND77 GND78 GND79

Receptacle 10 x 20

NC10 NC11 NC12 NC13 NC14 NC15 NC16 NC17 NC18 NC19 NC20 NC21 NC22 NC23 NC24 NC25 NC26 NC27 NC28 NC29 NC30 NC31 NC32 NC33 NC34 NC35 NC36

2

U76B

E20

NC0

E11

NC1

E10

NC2

E9

NC3

E8

NC4

E7

NC5

E6

NC6

E5

NC7

E4

NC8

E3

NC9

E19 E18 E17 E16 E15 E14 E13 E12 F20 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F19 F18 F17 F16 F15 F14 F13 F12

A1 A4 A5 A8

A9 A12 A13 A16 A17 A20

B1

B4

B5

B8

B9 B12 B13 B16 B17 B20

C1 C4 C5 C8

C9 C12 C13 C16 C17 C20

D1

D4

D5

D8

D9 D12 D13 D16 D17 D20

G1

G4

G5

G8

G9 G12 G13 G16 G17 G20

H1

H4

H5

H8

H9 H12 H13 H16 H17 H20

I1 I4 I5 I8

I9 I12 I13 I16 I17 I20

J1 J4 J5 J8

J9 J12 J13 J16 J17 J20

GND0 GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND10 GND11 GND12 GND13 GND14 GND15 GND16 GND17 GND18 GND19 GND20 GND21 GND22 GND23 GND24 GND25 GND26 GND27 GND28 GND29 GND30 GND31 GND32 GND33 GND34 GND35 GND36 GND37 GND38 GND39 GND40 GND41 GND42 GND43 GND44 GND45 GND46 GND47 GND48 GND49 GND50 GND51 GND52 GND53 GND54 GND55 GND56 GND57 GND58 GND59 GND60 GND61 GND62 GND63 GND64 GND65 GND66 GND67 GND68 GND69 GND70 GND71 GND72 GND73 GND74 GND75 GND76 GND77 GND78 GND79

Receptacle 10 x 20

NC10 NC11 NC12 NC13 NC14 NC15 NC16 NC17 NC18 NC19 NC20 NC21 NC22 NC23 NC24 NC25 NC26 NC27 NC28 NC29 NC30 NC31 NC32 NC33 NC34 NC35 NC36

E20

NC0

E11

NC1

E10

NC2

E9

NC3

E8

NC4

E7

NC5

E6

NC6

E5

NC7

E4

NC8

E3

NC9

E19 E18 E17 E16 E15 E14 E13 E12 F20 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F19 F18 F17 F16 F15 F14 F13 F12

1

A A

PLX TECHNOLOGY, INC.

870 W Maude Ave, Sunnyvale, CA 94085

870 W Maude Ave, Sunnyvale, CA 94085 www.plxtech.com

www.plxtech.com

Title

Size Document Number Rev

Size Document Number Rev C

C

C Date: Sheet

Date: Sheet

5

4

3

2

Date: Sheet

www.plxtech.com

8615 Base Board RDK

91-0132-000-A 0

1

24 26Thursday, February 12, 2009

of

5

Note: The debug Circuit on this page is for PLX use only

D D

PROCMON[8,26]

C C

SPARE5[8,26]

GPIO06[8,26] GPIO07[8,26] GPIO08[8,26]

GPIO26[8,26] GPIO27[8,26]

STRAP_NT_P2PEN#[8,26]

4

I2C_ADDR2[8] GPIO30[8,26] GPIO29[8,26] UPSTRM_PSEL3[8]

SPARE0[8,26]

STRAP_SMBUSEN#[8,26]

STRAP_UPCFG_TR_EN#[8,26]

DEBUG_SEL0[8]

TV58Prototyping Pad TV58Prototyping Pad TV59Prototyping Pad TV59Prototyping Pad TV60Prototyping Pad TV60Prototyping Pad TV61Prototyping Pad TV61Prototyping Pad TV62Prototyping Pad TV62Prototyping Pad TV63Prototyping Pad TV63Prototyping Pad TV64Prototyping Pad TV64Prototyping Pad TV65Prototyping Pad TV65Prototyping Pad

3

JP10

2

GND012

4

334

6

556

8

77GND2

10

9910

12

111112

14

GND11314

16

151516

18

171718

20

191920

PRB MODE INPUT HEADER

JP11

2

NC01NC1

4

GND03NC2

6

CLK/Q05CLK/Q1

8

L3:77R1:7

10

L3:69R1:6

12

L3:511R1:5

14

L3:413R1:4

16

L3:315R1:3

18

L3:217R1:2

20

L3:119R1:1

22

L3:021R1:0

24

L2:723R0:7

26

L2:625R0:6

28

L2:527R0:5

30

L2:429R0:4

32

L2:331R0:3

R0:2

L2:2

R0:1

L2:1

R0:0

L2:0

GND2

GND1

GND4

GND3 GND5

MICTOR 38 RECEPT

34 36 38 40 42

33 35 37 39 41 43

MICTOR CONNECTOR A

SPARE1 [8,26]

I2C_ADDR1 [8]

I2C_ADDR0 [8] GPIO05 [8,26] GPIO04 [8,26]

GPIO03 [8,26] GPIO02 [8,26] GPIO01 [8,26] GPIO00 [8,26]

GPIO09 [8,26] GPIO10 [8,26] GPIO11 [8,26] GPIO12 [8,26] GPIO13 [8,26] GPIO14 [8,26] GPIO15 [8,26]

TPV5 Prototyping PadTPV5 Prototyping Pad TPV16 Prototyping PadTPV16 Prototyping Pad TPV17 Prototyping PadTPV17 Prototyping Pad TPV18 Prototyping PadTPV18 Prototyping Pad TPV19 Prototyping PadTPV19 Prototyping Pad TPV20 Prototyping PadTPV20 Prototyping Pad TPV21 Prototyping PadTPV21 Prototyping Pad

2

1

B B

GPIO16[8,26] GPIO17[8,26] GPIO18[8,26] GPIO19[8,26] GPIO20[8,26] GPIO21[8,26] GPIO22[8,26] GPIO23[8,26] GPIO24[8,26] GPIO25[8,26]

A A

5

4

TV70Prototyping Pad TV70Prototyping Pad TV71Prototyping Pad TV71Prototyping Pad TV72Prototyping Pad TV72Prototyping Pad TV73Prototyping Pad TV73Prototyping Pad TV66Prototyping Pad TV66Prototyping Pad TV67Prototyping Pad TV67Prototyping Pad TV68Prototyping Pad TV68Prototyping Pad TV69Prototyping Pad TV69Prototyping Pad TV74Prototyping Pad TV74Prototyping Pad TV75Prototyping Pad TV75Prototyping Pad

JP9

NC01NC1 GND03NC2 CLK/Q05CLK/Q1 L3:77R1:7 L3:69R1:6 L3:511R1:5 L3:413R1:4 L3:315R1:3 L3:217R1:2 L3:119R1:1 L3:021R1:0 L2:723R0:7 L2:625R0:6 L2:527R0:5 L2:429R0:4 L2:331R0:3

33

L2:2

35

L2:1

37

L2:0

39

GND1

41

GND3

43

GND5

MICTOR 38 RECEPT

GND2 GND4

2 4 6 8 10 12 14 16

LN_GOOD_04_n [8,26]

18

LN_GOOD_05_n [8,26]

20

LN_GOOD_06_n [8,26]

22

LN_GOOD_07_n [8,26]

24 26 28 30 32

LN_GOOD_12_n

34

R0:2 R0:1 R0:0

LN_GOOD_13_n

36

LN_GOOD_14_n

38

LN_GOOD_15_n

40 42

LN_GOOD_00_n [8,26] LN_GOOD_01_n [8,26] LN_GOOD_02_n [8,26] LN_GOOD_03_n [8,26]

LN_GOOD_08_n [8,26]

LN_GOOD_09_n [8,26] LN_GOOD_10_n [8,26] LN_GOOD_11_n [8,26]

MICTOR CONNECTOR C

PLX TECHNOLOGY, INC.

870 W Maude Ave, Sunnyvale, CA 94085

870 W Maude Ave, Sunnyvale, CA 94085 www.plxtech.com

www.plxtech.com

Title

Size Document Number Rev

Size Document Number Rev C

C

C Date: Sheet

Date: Sheet

3

2

Date: Sheet

www.plxtech.com

8615 Base Board RDK

91-0132-000-A 0

1

25 26Thursday, February 12, 2009

of

5

U115A

XC3S200-4FTG256C

A5

IO_0

A7

IO_1

C5

IO_L25N_0

B5

IO_L25P_0

E6

IO_L27N_0

D6

IO_L27P_0

C6

IO_L28N_0

B6

IO_L28P_0

E7

IO_L29N_0

D7

IO_L29P_0

C7

IO_L30N_0

B7

IO_L30P_0

2 OF 12

U115C

G16

IO_5

B16

IO_L01N_2_VRP_2

C16

IO_L01P_2_VRN_2

C15

IO_L16N_2

D14

IO_L16P_2

D15

IO_L17N_2

D16

IO_L17P_2_VREF_2

E13

IO_L19N_2

E14

IO_L19P_2

E15

IO_L20N_2

E16

IO_L20P_2

F12

IO_L21N_2

F13

IO_L21P_2

U115D

K15

IO_6

P16

IO_L01N_3_VRP_3

R16

IO_L01P_3_VRN_3

P15

IO_L16N_3

P14

IO_L16P_3

N16

IO_L17N_3

N15

IO_L17P_3_VREF_3

M14

IO_L19N_3

N14

IO_L19P_3

M16

IO_L20N_3

M15

IO_L20P_3

L13

IO_L21N_3

M13

IO_L21P_3

U115E

T12

IO_7

T14

IO_8

N12

IO_VREF_4_0

P13

IO_VREF_4_1

T10

IO_VREF_4_2

R13

IO_L01N_4_VRP_4

T13

IO_L01P_4_VRN_4

P12

IO_L25N_4

R12

IO_L25P_4

M11

IO_L27N_4_DIN_D0

N11

IO_L27P_4_D1

P11

IO_L28N_4

R11

IO_L28P_4

45

678

XC3S200-4FTG256C

IO_L31P_0_VREF_0

1 OF 12

VCCO_1_2 VCCO_1_1 VCCO_1_0

IO_VREF_1

IO_L32P_1_GCLK4 IO_L32N_1_GCLK5

IO_L31P_1

IO_L31N_1_VREF_1

IO_L30P_1 IO_L30N_1

XC3S200-4FTG256C

IO_L40P_2_VREF_2

IO_L23N_2_VREF_2

3 OF 12

XC3S200-4FTG256C

IO_L40N_3_VREF_3

IO_L23P_3_VREF_3

4 OF 12

XC3S200-4FTG256C

IO_L31P_4_DOUT_BUSY

5 OF 12

123

45

RN13

4R 4.7K

678

IO_VREF_0_0 IO_VREF_0_1

IO_L01P_0_VRN_0 IO_L01N_0_VRP_0

VCCO_0_2 VCCO_0_1 VCCO_0_0

IO_L32P_0_GCLK6 IO_L32N_0_GCLK7

IO_L31N_0

XC3S200-4FTG256C

3.3VCC1

F10 F9 E9

D12

D9

SPARE0 [8,25]

C9

SPARE1 [8,25]

B10

STRAP_NT_P2PEN# [8,25]

A10

STRAP_SMBUSEN# [8,25]

E10

STRAP_UPCFG_TR_EN# [8,25]

D10

SPARE5 [8,25]

VCCO_2_2 VCCO_2_1 VCCO_2_0

IO_L40N_2 IO_L39P_2 IO_L39N_2 IO_L24P_2 IO_L24N_2 IO_L23P_2

IO_L22P_2 IO_L22N_2

XC3S200-4FTG256C

VCCO_3_2 VCCO_3_1 VCCO_3_0 IO_L40P_3

IO_L39P_3 IO_L39N_3 IO_L24P_3 IO_L24N_3

IO_L23N_3 IO_L22P_3 IO_L22N_3

VCCO_4_2 VCCO_4_1 VCCO_4_0

IO_L32P_4_GCLK0 IO_L32N_4_GCLK1

IO_L31N_4_INIT_B

IO_L30P_4_D3

IO_L30N_4_D2

IO_L29P_4

IO_L29N_4

XC3S200-4FTG256C

TP39TP39 TP40TP40 TP41TP41 TP42TP42

FPGA_RESET[23]

A3 D5

A4 B4

F8 F7 E8

A8 B8 C8 D8

H12 H11 G11 H16 H15 H14 H13 G15 G14 G13 G12 F15 F14

K11 J12 J11 K16 J16 J13 J14 K13 K14 L12 K12 L14 L15

TP7TP7

TP9TP9

RECP2_PRES_n[22] RECP2_CFGID0[22] RECP2_CFGID1[22] RECP1_PRES_n[22] RECP1_CFGID0[22] RECP1_CFGID1[22]

D D

RECP0_PRES_n[22] RECP0_CFGID0[22] RECP0_CFGID1[22]

GPIO13[8,25] GPIO14[8,25]

C C

GPIO15[8,25] GPIO16[8,25] GPIO17[8,25] GPIO18[8,25] GPIO19[8,25] GPIO20[8,25] GPIO21[8,25] GPIO22[8,25] GPIO23[8,25] GPIO24[8,25] GPIO25[8,25]

GPIO26[8,25] GPIO27[8,25] GPIO28[8] GPIO29[8,25] GPIO30[8,25] GPIO31[8] LN_GOOD_00_n[8,25] LN_GOOD_01_n[8,25] LN_GOOD_02_n[8,25] LN_GOOD_03_n[8,25] LN_GOOD_04_n[8,25] LN_GOOD_05_n[8,25] LN_GOOD_06_n[8,25]

B B

LN_GOOD_07_n[8,25] LN_GOOD_08_n[8,25] LN_GOOD_09_n[8,25] LN_GOOD_10_n[8,25] LN_GOOD_11_n[8,25]

A A

TP22TP22

U115B

XC3S200-4FTG256C

ROM_DOUT

TP25TP25

SW13 SW DIP-4SW13 SW DIP-4

5 6 7 8

SW14 SW DIP-4SW14 SW DIP-4

5 6 7 8

A9 A12 C10 A14 B14 A13 B13 B12 C12 D11 E11 B11 C11

4R 4.7K

UMODE0

4

UMODE1

3

UMODE2

2

UMODE3

1

UMODE4

4

UMODE5

3

UMODE6

2

UMODE7

1

5

IO_2 IO_3 IO_4 IO_L01N_1_VRP_1 IO_L01P_1_VRN_1 IO_L10N_1_VREF_1 IO_L10P_1 IO_L27N_1 IO_L27P_1 IO_L28N_1 IO_L28P_1 IO_L29N_1 IO_L29P_1

3.3VCC1

123

RN11

GPIO00[8,25] GPIO01[8,25] GPIO02[8,25] GPIO03[8,25] GPIO04[8,25] GPIO05[8,25] GPIO06[8,25] GPIO07[8,25] GPIO08[8,25] GPIO09[8,25] GPIO10[8,25] GPIO11[8,25] GPIO12[8,25]

TP23TP23

TP24TP24

TP19TP19

M9 L10 L9

T9 R9 P9 N9 R10 P10 N10 M10

4

3.3VCC1

R342 33R342 33

ROM_OE_RESET_n

4

PS_ON_n [4]

CLKEN_SL8 [21]

LEDSET0_DATA [17] LEDSET0_CLK [17] LEDSET1_DATA [17] LEDSET1_CLK [17] LEDSET2_DATA [18] LEDSET2_CLK [18]

TP26TP26 TP27TP27

LEDSET4_DATA [19] LEDSET4_CLK [19] LEDSET5_DATA [19] LEDSET5_CLK [19] LEDSET6_DATA [19] LEDSET6_CLK [19] LEDSET7_DATA [17] LEDSET7_CLK [17]

PEX_PERST_n [8,17,18,19,21] WAKE_n [9,10,11,12,13,14]

PROCMON [8,25] PEX_INTA_n [8] FATAL_ERR_n [8]

U115H

G2

IO_13

C1

IO_L01N_7_VRP_7

B1

IO_L01P_7_VRN_7

C2

IO_L16N_7

C3

IO_L16P_7_VREF_7

D1

IO_L17N_7

D2

IO_L17P_7

E3

IO_L19N_7_VREF_7

D3

IO_L19P_7

E1

IO_L20N_7

E2

IO_L20P_7

F4

IO_L21N_7

E4

IO_L21P_7

TP13TP13

TP14TP14

TP15TP15

TP16TP16

TP17TP17

TP18TP18

TP20TP20

TP21TP21

TP29TP29

XC3S200-4FTG256C

8 OF 12

FPGA_PEX_PERST_n[4] DEBUG_NORMAL_n[4] CPWRON[16]

PS_Pwr_Good[4,23]

TP28TP28

3.3VCC1

IO_L40N_7_VREF_7

XC3S200-4FTG256C

PRSNT_n_SL1[9] PRSNT_n_SL2[9] PRSNT_n_SL3[10] PRSNT_n_SL4[10] PRSNT_n_SL5[11] PRSNT_n_SL6[11] PRSNT_n_SL7[12] PRSNT_n_SL8[12,21] PRSNT_n_SL9[13] PRSNT_n_SL10[13] PRSNT_n_SL11[14]

Y4

1

EN

4

VCC

VCCO_7_2 VCCO_7_1 VCCO_7_0

IO_L40P_7 IO_L39P_7

IO_L39N_7 IO_L24P_7 IO_L24N_7 IO_L23P_7 IO_L23N_7 IO_L22P_7 IO_L22N_7

C155

1000pF

OUT

GND

100MHzY4100MHz

TP32TP32

TP33TP33

TP34TP34

TP35TP35

TP36TP36

TP37TP37

FPGA_CLK1 FPGA_CLKFPGA_CLK

3 2

3.3VCC1

H6 H5 G6 G1 H1 H4 H3 G4 G3 F5 G5 F3 F2

3

N5

P7 T5 T8 T3

R3

T4 R4 R5

P5 N6 M6

K1 R1

P1

P2 N3 N2 N1 M4 M3 M2 M1

L5

L4

R341 33R341 33

CPRSNTN [16]

SHPC_INT_n [8,21]

3

U115F

XC3S200-4FTG256C

IO_9 IO_10 IO_11 IO_VREF_5 IO_L01N_5_RDWR_B IO_L01P_5_CS_B IO_L10N_5_VRP_5 IO_L10P_5_VRN_5 IO_L27N_5_VREF_5 IO_L27P_5 IO_L28N_5_D6 IO_L28P_5_D7

U115G

XC3S200-4FTG256C

IO_12 IO_L01N_6_VRP_6 IO_L01P_6_VRN_6 IO_L16N_6 IO_L16P_6 IO_L17N_6 IO_L17P_6_VREF_6 IO_L19N_6 IO_L19P_6 IO_L20N_6 IO_L20P_6 IO_L21N_6 IO_L21P_6

FPGA CLK

TP5

ALERT_n [23] OVERT_n [23]

SMBDATA_16 [23] SMBCLK_16 [23] EN_NVM_VDDQ [23]

I2C_SCL0 [8] I2C_SDA0 [8]

6 OF 12

7 OF 12

TP38TP38

VCCO_5_2 VCCO_5_1 VCCO_5_0

IO_L32P_5_GCLK2 IO_L32N_5_GCLK3

IO_L31P_5_D5 IO_L31N_5_D4

IO_L30P_5

IO_L30N_5

IO_L29P_5_VREF_5

IO_L29N_5

XC3S200-4FTG256C

VCCO_6_2 VCCO_6_1 VCCO_6_0

IO_L40P_6_VREF_6

IO_L40N_6

IO_L39P_6

IO_L39N_6

IO_L24P_6

IO_L24N_6_VREF_6

IO_L23P_6

IO_L23N_6

IO_L22P_6

IO_L22N_6

XC3S200-4FTG256C

TP6HOT_SWAP_EN TP6HOT_SWAP_EN

XILINX_VCC_AUX_2p5

M8 L8 L7

N8 P8 R7 T7 M7 N7 P6 R6

R77

5.1K

TP11NC_INIT_NC TP11NC_INIT_NC

K6 J6 J5 J1 J2 J3 J4 K2 K3 K4 K5 L2 L3

FPGA_CLK

2

3.3VCC1

PERST_n_SL1 [9] PERST_n_SL2 [9] PERST_n_SL3 [10] PERST_n_SL4 [10] PERST_n_SL5 [11]

3.3VCC1

PERST_n_SL5 [11] PERST_n_SL6 [11] PERST_n_SL7 [12] PERST_n_SL9 [13] PERST_n_SL10 [13] PERST_n_SL11 [14]

XILINX_VCC_AUX_2p5

R78

5.1K

2

TP30TP30

TP31TP31

U115K

T15

CCLK

R14

DONE

C4

HSWAP_EN

U115L

XC3S200-4FTG256C

C14

TCK

A2

TDI

U116

3

CLK

4

TDI

5

TMS

6

TCK

10

CE

2

DNC0

9

DNC1

12

DNC2

14

DNC3

15

DNC4

16

DNC5

J12

2

VREF

4

SS_PROG_TMS

6

SCK_CCLK_TCK

8

MISO_DONE_TDO

10

MOSI_DIN_TDI

12

NC_NC_NC

14

NC_INIT_NC

A16

B15 F11

G10

H10

A6

A11

F1

F16

L1

L16

T6

T11

XC3S200-4FTG256C

XCF01SVOG20C

JTAG HEADER 7x2

11 OF 12

XC3S200-4FTG256C

12 OF 12

XC3S200-4FTG256C

OE_RESET

VCCO

VCCINT

XCF01SVOG20C

VCCJ

GND0 GND1 GND2 GND3 GND4 GND5 GND6

CEO TDO

GND

PROG_B

D0 CF

T16

GND31

T1

GND30

R15

GND29

R8

GND28

R2

GND27

L11

GND26

L6

GND25

K10

GND24

K9

GND23

K8

GND22

K7

GND21

J15

GND20

J10

GND19

J9

GND18

J8

GND17

J7

GND16

N13 N4 M12 M5 E12 E5 D13 D4

R72

5.1K

2

4

6

2

4

6

1

3

5

1

3

5

ROM_OE_RESET_n

1

XILINX_VCC_CORE_1p2XILINX_VCC_AUX_2p5

XILINX_VCC_AUX_2p5

R80

R81

5.1K

ROM_DOUT

1

U115I

XC3S200-4FTG256C

A1

GND0 GND1

B2

GND2

B9

GND3 GND4

F6

GND5 GND6

G7

GND7

G8

GND8

G9

GND9 GND10

H2

GND11

H7

GND12

H8

GND13

H9

GND14 GND15

9 OF 12

XC3S200-4FTG256C

U115J

XC3S200-4FTG256C

VCCAUX0 VCCAUX1 VCCAUX2 VCCAUX3 VCCAUX4 VCCAUX5 VCCAUX6 VCCAUX7

TMS TDO

1 7 13 17 8

20 19 18

11

1 3 5 7 9 11 13

M2 M1 M0

C13 A15

VCCINT7 VCCINT6 VCCINT5 VCCINT4 VCCINT3 VCCINT2 VCCINT1 VCCINT0

10 OF 12

XC3S200-4FTG256C

R70

R71

5.1K

B3 P4 T2 P3

J13

Header 3x2

XILINX_VCC_AUX_2p5

PLX TECHNOLOGY, INC.

870 W Maude Ave, Sunnyvale, CA 94085

870 W Maude Ave, Sunnyvale, CA 94085 www.plxtech.com

www.plxtech.com

Title

Size Document Number Rev

Size Document Number Rev C

C

C Date: Sheet

Date: Sheet

www.plxtech.com

8615 Base Board RDK

91-0132-000-A 0

TP8 ROM_DOUTTP8 ROM_DOUT TP10ROM_CEO_nTP10ROM_CEO_n TP12

TP12

ROM_OE_RESET_n

26 26Thursday, February 12, 2009

of

PLX Technology PEX 8615A, PEX 8619BA Hardware Reference Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

NOTICE

ABOUT THIS MANUAL

REVISION HISTORY

1. General Information

1.1 PEX 8615 Features

1.2 PEX 8615BA-BB RDK Features

2. System Architecture

3. Hardware Architecture

3.1 PEX 8615

3.2 PCI Express Interfaces

3.2.1 RDK Configuration Modules and Their Receptacles

3.2.2 PCI Express Lane 0 to Lane 3

3.2.3 PCI Express Lane 4 to Lane 7

3.2.4 PCI Express Lane 8 to Lane 11

3.3 Reference Clock Circuits

3.4 Reset Circuits

3.5 Serial Hot-Plug (SHP) Controller Circuits

3.6 Serial EEPROM

3.7 I2C Interface

3.8 Power Distribution Circuits

3.9 FPGA Interface

3.10 LED and 7-Segment Displays

3.10.1 LED Indicators

3.10.2 7-Segment Displays

3.11 GPIO Pins

3.12 Reserved Pins

4. On-Board Connectors, Switches, and Jumpers

4.1 DIP Switches

4.1.1 Dip Switch Group 1

4.1.2 Dip Switch Group 2

4.1.3 Dip Switch Group 3

4.2 Push-Button Switches

4.3 Connectors and Headers

4.3.1 ATX Peripheral Power Connectors (J1-J4 & J7-J8)

4.3.2 x4 PCI Express External Cable Connectors (J5 & J6)

4.3.3 ATX Main Power Connector (J9)

4.3.4 ATX +12V Power Connector(J10)

4.3.5 Xilinx JTAG Connector (J12)

4.3.6 Xilinx Mode Setting Header (J13)

4.3.7 PEX 8615 JTAG Header (JP3)

4.3.8 SMBus Header (JP5)

4.3.9 PCI Express x8 Midbus Probe Footprint (JP6)

4.3.10 PEX 8615 I2C Port (JP8)

4.3.11 Debug Signal Header (JP9 & JP11)

4.3.12 Debug Input Header (JP10)

4.3.13 Reference Clock Header (JP100)

5. RDK Port Configurations

6. Bill of Materials/ Schematics