PLX TECHNOLOGY PEX 8524V User Manual

Flexible & Versatile PCI Express™ Switch

Features

 PEX 8524V General Features

o 24-lane PCI Express switch

- Integrated SerDes
o Up to six configurable ports
o 35mm x35mm, 680 pin PBGA package
o Typical Power: 5.7 Watts

 PEX 8524V Key Features

o Standard Compliant

- PCI Express Base Specification, r1.1
o High Performance

- Non-blocking switch fabric

- Full line rate on all ports
o Non-Transparent Bridging

- Configurable Non-Transparent port

for Multi-Host or Intelligent I/O
Support

o Flexible Configuration

- Six highly flexible & configurable

ports (x1, x2, x4, x8, or x16)

- Configurable with strapping pins,

EEPROM, or Host software

- Lane and polarity reversal
o PCI Express Power Management

- Link power management states: L0,

L0s, L1, L2/L3 Ready, and L3

- Device states: D0 and D3hot
o Quality of Service (QoS)

- Two Virtual Channels per port

- Eight Traffic Classes per port

- Fixed and Round-Robin Virtual

Channel Port Arbitration

o Reliability, Availability,

Serviceability

- 6 Standard Hot-Plug Controllers

- Upstream port as hot-plug client

- Transaction Layer end-to-end CRC

- Poison bit

- Advanced Error Reporting

- Lane Status bits and GPO available

- Per port performance monitoring

• Average packet size

• Number of packets

• CRC errors and more

- JTAG boundary scan

Multi-purpose, Feature Rich ExpressLane™ PCI Express Switch

The ExpressLane PEX 8524V device offers PCI Express switching capability
enabling users to add scalable high bandwidt h, n on - bl oc ki n g interconnection to a
wide variety of applications including servers, storage systems, communications
platforms, blade servers, and embedded-control products. The PEX 8524V is
well suited for fan-out, aggregation, dual-graphics, peer-to-peer, and intelligent
I/O module applications.

Highly Flexible Port Configurations

The ExpressLane PEX 8524V offers highly configurable ports. There are a
maximum of 6 ports that can be configured to any legal width from x1 to x16, in any
combination to support your specific bandwidth needs. The ports can be configured
for symmetric (each port having the same lane width and traffic load) or
asymmetric (ports having different lane widths) traffic. In the event of asymmetric
traffic, the PEX 8524V features a flexible central packet memory that allocates a
memory buffer for each port as required by the application or endpoint. This buffer
allocation along with the device's flexible packet flow control minimizes
bottlenecks when the upstream and aggregated downstream bandwidths do not match
(are asymmetric). Any of the ports can be designated as the upstream port, which can
be changed dynamically.

End-to-end Packet Integrity

The PEX 8524V provides end-to-end CRC protection (ECRC) and Poison bit
support to enable designs that require end-to-en d data integrity. These features are
optional in the PCI Express specification, but PLX provides them across its entire
ExpressLane switch product line.

Non-Transparent “Bridging” in a PCI Express Switch

The ExpressLane PEX 8524V product supports full non-transparent bridging (NTB)
functionality to allow implementation of multi-host systems and intelligent I/O

modules in communications, storage, blade server, and graphics fan-out
applications. To ensure quick product migration, the non-transparency features are

implemented in the same fashion as in standard PCI applications.
Non-transparent bridges allow systems to isolate memory domains by presenting the

processor subsystem as an endpoint, rather than another memory system. Base
address registers are used to translate addresses; doorbell registers are used to send
interrupts between the address domains; and scratchpad registers are accessible from
both address domains to allow inter-processor communication.

Two Virtual Channels

The ExpressLane PEX 8524V switch supports 2 full-featured Virtual Channels
(VCs) and a full 8 Traffic Classes (TCs). The mapping of Traffic Classes to port­specific Virtual Channels allows for different mappings for different ports. In
addition, the devices offer user-selectable Virtual Channel arbitration algorithms to
enable users to fine tune the Quality of Service (QoS) required for a specific
application.

Low Power with Granular SerDes Control

The PEX 8524V provides low power capability that is fully compliant with the PCI
Express power management specification. In addition, the SerDes physical links can
be turned off when unused for even lower power.

PEX 8524V

Version 1.4 2007

Not Recommended

for New Designs

查询PEX8524V供应商

Flexible Port Width Configuration

The lane width for each port can be individually configured
through auto-negotiation, hardware strapping, upstream
software configuration, or through an optional EEPROM.

The PEX 8524V supports a large number of port
configurations. For example, if you are using the PEX 8524V
in a fan-out application, you may configure the upstream port
as x8 and the downstream ports as four x4 ports; two x8 ports
for dual-graphics fan-out; or other combinations, as long as
you don’t run out of lanes (24) or ports (6). In a peer-t o- peer
application you can configure all six ports as x4. Figure 1
shows the most common port configurations.

Figure 1. Common Port Configurations

Hot Plug for High Availability

Hot plug capability allows users to replace hardware modules
and perform maintenance without powering down the system.
The PEX 8524V hot plug capability and Advanced Error

Reporting features makes it suitable for High Availability
(HA) applications. Each downstream port includes a Standard

Hot Plug Controller. If the PEX 8524V is used in an
application where one or more of its downstream ports
connect to PCI Express slots, each port’s Hot Plug Controller
can be used to manage the hot-plug event of its associated slot.
Furthermore, its upstream port is a hot-plug client, allowing it
to be used on hot-pluggable adapter cards, backplanes, and
fabric modules.

Fully Compliant Power Management

For applications that require power management, the PEX
8524V device supports both link (L0, L0s, L 1, L2/L3 Ready,
and L3) and device (D0 and D3hot) power management states,
in compliance with the PCI Express power management
specification.

SerDes Power and Signal Management

The ExpressLane PEX 8524V supports software control of
the SerDes outputs to allow optimization of power and signal
strength in a system. The PLX SerDes implementation
supports four levels of power – off, low, typi cal , and hi g h. The
SerDes block also supports loop-back modes and advanced
reporting of error conditions, which enables efficient debug
and management of the entire system.

Flexible Virtual Channel Arbitration

The ExpressLane PEX 8524V switches support hardware
fixed and Round Robin arbitration schemes for two virtual

channels on each port. This allows for the fine tuning of
Quality of Service for efficient use of packet buffers and
system bandwidth.

Applications

Suitable for host-centric as well as peer-to-peer traffic
patterns, the PEX 8524V can be configured for a wide variety

of form factors and applications.

Host-Centric Fan-out

The PEX 8524V, with its symmetric or asymmetric lane
configuration capability, allows user specific tuning to a

variety of host-centric applications.

Figure 2. Fan-in/out Usage

Figure 2 shows a typical server-based design, where the root
complex provides a PCI Express link that needs to be fanned
into a larger number of smaller ports for a variety of I/O
functions, each with different bandwidth requirements.

In this example, the PEX 8524V would typically have an 8­lane upstream port, and as many as 5 downstream ports (4
shown here). The downstream ports can be of differi n g wi dths
if required. The figure also shows how some of the por ts can
be bridged to provide PCI or PCI-X slots through the use of
the ExpressLane PEX 8114 and PEX 8111 PCIe bridging
devices.

Not Recommended

for New Designs