PLEXUS ADSP-TS101S User Manual
ADSP-TS101S MP System Simulation and Analysis
Rev. 1.2 March 12, 2002
Copyright © 2002, Plexus Corp.
Signal Integrity Analysis Group
TABLE OF CONTENTS
1 OVERVIEW .....................................................................................................................................3
2 THEORETICAL FOUNDATION ......................................................................................................4
2.1 SIMULATION RESULTS .......................................................................................................5-8
3 TIMING ANALYSIS BACKGROUND ........................................................................................9-11
3.1 TIMING ANALYSIS DATA......................................................................................................12
4 TERMINATION STRATEGY ......................................................................................................... 17
5 PHYSICAL IMPLEMENTATION ...................................................................................................18
5.1 SYSTEM CLOCK DISTRIBUTION.........................................................................................19
6 PCB STACK-UP AND DESIGN REQUIREMENTS......................................................................20
6.1 PLACEMENT AND ROUTING ...............................................................................................22
7 CONCLUSION...............................................................................................................................24
Plexus Corp – Signal Integrity Analysis Group
400 Amherst St., Suite 301, Nashua, New Hampshire, 03063
Phone: (603) 864-1300 Internet: www.plexus.com
Copyright © 2002 Plexus Corp 2 of 24
1. Overview
This document details analysis and implementation of a reliable bus topology for 8 clustered
TigerSHARCs (ADSP-TS101S) plus a host processor and external SDRAM. The host processor
in this system is defined as an additional TS101S for simplicity.
SDRAM
Cluster of 8
TigerSHARC
Devices
Host
TigerSHARC
Figure 1. The TS101S external memory bus includes a 64-bit data bus, 32 bit address bus and
related control signals.
Signal integrity analysis and investigation is limited to the external memory signals only. The final
topology developed for the external memory bus however, is extended to other relevant signals.
Topology development of the external memory bus is based on the following four assumptions:
• Host and memory must communicate with each other.
• Each clustered TS101S must communicate with the host and memory.
• Clustered TS101S devices communicate with each other.
• Performance target for bus operation is 100 MHz.
In preparing this document, Plexus investigated several different system topologies to identify a
successful theoretical solution. Plexus then implemented the theoretical solution in a physical
PCB layout to determine placement and routing feasibility. Post route simulations confirmed
signal quality based on the four initial assumptions listed above. The recommend topology for the
cluster bus is discussed in further detail in the next section. Simulation results appear with
recommended termination requirements. System clock distribution, PCB stack-up, and layout
design constraints are summarized in the final section.
Conclusion: A cluster of 8 TS101S devices is a very realistic system, yielding excellent hardware
performance, using common manufacturing techniques and design practices as detailed in this
document.
Disclaimer: This document is not meant to endorse any device or company. Part selection for
memory devices and clock drivers are only an example.
Plexus Corp – Signal Integrity Analysis Group
400 Amherst St., Suite 301, Nashua, New Hampshire, 03063
Phone: (603) 864-1300 Internet: www.plexus.com
Copyright © 2002 Plexus Corp 3 of 24
2. Theoretical Foundation
The performance goal for the TS101S multiprocessor bus topology is 100 MHz, providing reliable
communication between all devices. The only topology that meets this stringent performance
goal is a star pattern topology as shown in Figure 2 below.
R
C
TigerSHARC
3
TigerSHARC
4
L3
SDRAM
2
Devices
L1
L1
TigerSHARC
1
L
2
L1
TigerSHARC
2
L1L1
L
1
L1
TigerSHARC
8
L1
L1
TigerSHARC
7
TigerSHARC
9 - HOST
TigerSHARC
5
Figure 2. Recommended topology for maximum TS101S cluster configuration with a host and
external SDRAM. L1, L2, and L3 represent maximum transmission line lengths of 3.0”, 2.0”, and
1.0” respectively.
Plexus Corp – Signal Integrity Analysis Group
400 Amherst St., Suite 301, Nashua, New Hampshire, 03063
Phone: (603) 864-1300 Internet: www.plexus.com
Copyright © 2002 Plexus Corp 4 of 24
TigerSHARC
6
PIN 1 INDICATOR
VIA CONNECTION
The ideal star topology has drivers and receivers attached to transmission lines with equal
lengths. This topology is usually implemented with a common tie point (generally a connector or
via) located in the middle of the transmission lines. Pre-route simulation results in section 2.1
show reliable communication between all devices at 100 MHz.
Figure 2 indicates the use of AC termination. The value of the resistor should match the
impedance of the transmission line to eliminate reflection. An appropriate capacitor value helps
the waveform at the loads approach an ideal square wave while simultaneously optimizing
overshoot and undershoot. For more information, see section 4 - Termination Strategy.
2.1 Simulation Results for the Star Topology
Simulation results are based on 50 and 100 MHz stimulus frequencies. TS101S drive strengths 5,
6, and 7 are applied in applicable simulation cases.
Simulation models used:
• TS101s27.ibs - Analog Devices IBIS model for ADSP-TS101S, file revision 2.1.
• Y95W.ibs - Micron IBIS model for MT48LC4M32B2TG (86 pin TSOP, 0.5mm pitch), file
revision 1.1.
• All simulation results based on Cadence SpecctraQuest and SigXplorer version 13.6.
SDRAM - Driver TS101s - Receivers
Figure 3a. Memory driving topology depicted in Figure 2 at 100 MHz with 50 Ohm and 330pF
termination. All TS101S's have the same wave shape because the star topology is symmetrical
from a driver/receiver point of view.
Plexus Corp – Signal Integrity Analysis Group
400 Amherst St., Suite 301, Nashua, New Hampshire, 03063
Phone: (603) 864-1300 Internet: www.plexus.com
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TS101s - Receivers
SDRAM - Driver
Figure 3b. Memory driving topology depicted in Figure 2 at 50 MHz with 50 Ohm and 330pF
termination. All TS101S's have the same wave shape because the star topology is symmetrical
from a driver/receiver point of view.
TS101S Driver
TS101S – Receivers (8 total)
SDRAM
Figure 4. Any TS101S device driving topology depicted in Figure 2 at 100 MHz with 50 Ohms and
330pF termination usingTS101S drive strength 5. The symmetrical geometry of the star topology
results in identical wave shapes for all TS101S devices regardless of which TS101S device drives.
Plexus Corp – Signal Integrity Analysis Group
400 Amherst St., Suite 301, Nashua, New Hampshire, 03063
Phone: (603) 864-1300 Internet: www.plexus.com
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TS101 TYP Varying Drive Strengths 4, 5, 6, and 7 – TS101 Receivers Shown, 50 MHz
Figure 5. TS101S device driving topology depicted in Figure 2 at 50 MHz with 50 Ohms and
330pF termination. Memory receiver shown with varying TS101S drive strengths 4, 5, 6 and 7.
, 50 MHz
Figure 6. TS101S device driving topology depicted in Figure 2 at 50 MHz with 50 Ohms and
330pF termination. All other TS101S receivers shown with varying TS101S drive strengths 4, 5, 6
and 7.
Plexus Corp – Signal Integrity Analysis Group
400 Amherst St., Suite 301, Nashua, New Hampshire, 03063
Phone: (603) 864-1300 Internet: www.plexus.com
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, 100 MHz
Figure 7. TS101S device driving topology depicted in Figure 2 at 100 MHz with 50 Ohms and
330pF termination. Memory receiver shown with varying TS101S drive strengths 5, 6 and 7.
, 100 MHz
Figure 8. TS101S device driving topology depicted in Figure 2 at 100 MHz with 50 Ohms and
330pF termination. All other TS101S receivers shown with varying TS101S drive strengths 5, 6 & 7.
The simulation results shown in Figures 3 - 8 show that the star topology theoretically meets the
performance requirements of a cluster bus with 8 clustered TS101S devices plus one host and two
SDRAM chips for 100 MHz operation. Additionally, the simulation results show some margin in
choosing the TS101S driver strength.
Plexus Corp – Signal Integrity Analysis Group
400 Amherst St., Suite 301, Nashua, New Hampshire, 03063
Phone: (603) 864-1300 Internet: www.plexus.com
Copyright © 2002 Plexus Corp 8 of 24
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