Planar EL640.400-CE User Manual

EL640.400-CE Series

640 x 400 Pixel Electroluminescent Displays

Product Profile

The EL640.400-CE is a high performance electroluminescent (EL) display designed to offer performance and features unequalled by any other monochrome flat panel display. The display features Integral Contrast Enhancement (ICE™) which provides dramatically improved contrast and overall viewability in a wide variety of lighting environments. The CE series displays also incorporate a dual scan drive scheme providing either superior brightness or low power consumption.

The EL640.400-CE is a 640 column by 400 row flat panel display with a dot pitch of 0.305mm (83 dots per inch). The pixel aspect ratio is 1:1. The display series eases system integration by offering an 8-bit Flat Panel Display (FPD) interface, a "Normal" EL interface, and a VGA interface for compatibility with the IBM Feature Connectors found on standard VGA cards.

The EL640.400-CE Series display requires +5 V and +10 to +15 V (VL, VH) power and five basic input signals to operate:

1. Video Data or pixel information (VID)

2. Video Clock, pixel clock, or dot clock (VCLK)

3. Horizontal Sync (HS)

4. Vertical Sync (VS)

5. Blanking (BLANK) in VGA Modes

EL Technology

Operations Manual

The EL glass panel is a solid-state device with a thinfilm electroluminescent layer sandwiched between transparent dielectric layers and a matrix of row and column electrodes. The row electrodes, in back, are aluminum; the column electrodes, in front, are transparent. The entire thin film device is deposited on a single glass substrate. The glass panel is mounted to a metal frame carrying the electronic circuit boards . The result is a flat, compact, reliable and rugged display device.

The display consists of an electroluminescent glass

panel and attached circuit boards with control electronics.

ALUMINUM ROW

ELECTRODE

DIELECTRIC

LAYERS

1 micron

LIGHT EMITTING LAYER

light emitting layer

The display has 640 column electrodes and 400 row electrodes arranged in an X-Y formation with the intersecting areas forming pixels. Voltage is applied to both the correct row electrode and the correct column electrode to cause a lit pixel. Operating voltages required are provided by an integral DC/DC converter. The display utilizes a frame buffer to capture video data and scan the display at high (bright) refresh rates in Normal, VGA, and buffered 8-bit FPD versions.

NOT FOR NEW DESIGNS

1 mm

TRANSPARENT

COLUMN ELECTRODE

GLASS SUBSTRATE

VIEW

V(t)

EL640.400-CE Series

Electrical Characteristics

■ Connector Layout

To p

J1 Data/Power

Connector

J2 Luminance/

Contrast Control

PS1

1234

PS1

Fig. 1 The input connectors and jumpers on the EL640.400-CE Series display

■ Signal Inputs

Power/Video Input Connector (J1)

Symbol Pin Pin Symbol

VH (+12V) 1 2 VH +12V) VL (+5V) 3 4 VL (+5V) BLANK 5 6 GND (TVID) VID VS (S) 9 10 GND HS 11 12 GND VCLK 1 3 14 GND (VID) VID VID VID VID VID VID

Video signals and DC power are connected to the display through a right angle, dual row header. The pin assignments are shown in the tables above.

U0 U2 L0 L1 L2 L3

7 8 8-BIT

15 16 GND 17 18 VID 19 20 GND 21 22 GND 23 24 GND 25 26 GND

J1 Input Signal Descriptions

Symbol Functional Description VCLK Video Clock. See timing diagrams for the definition of the active edge. VID

U0-U3

VID

L0-L3

VID For the CE5 , CE6 this signal provides odd and even video pixel data in Single-Line mode, or even pixel data in 2-Bit Data Mode TVID For the CE5 this signal provides odd column data in 2-Bit video mode. HS Horizontal sync. See the appropriate display timing diagrams for active edge details. VS Vertical sync. See the appropriate display timing diagrams. (S) VL (+5V) +5V Logic Supply voltage VH (+12V) +12V supply for DC-DC converter and display analog circuits GND Signal return for logic and power supplies 8- BIT This input is internally pulled to High state if not connected.

BLANK This input is internally pulled to High state if not connected.

For the CE4 display, these signals provide video pixel data to the upper half of the display. Pixel information is supplied from left to right and from top to bottom (see page 7); the first bit of data on VIDU3 at the beginning of a frame is displayed at the pixel in the upper left corner of the display. Bit number 160 of VIDU0 is at the upper right corner of the display. The data on VIDU0-3 are displayed on the upper 200 rows of the display. Same as VID

CE4 – This line must be High CE5/CE6 – This line must be Low

CE4/CE5 – This signal must be High CE6 – A low input level blanks the display. The trailing edge of blanking is used to position the display horizontally and sense the display mode.

(see above) but for the lower half of the display.

U0-U3

J2 Luminance/Contrast Control

LUM Input for external 50KΩ logarithmic pot to adjust the display luminance/contrast. GND Signal ground return for LUM, L0, L1, and ENABLE. L0 Digital refresh rate control LSB. L1 Digital refresh rate control MSB. ENABLE When the ENABLE line is pulled to a logic Low, the display stops scanning and emitting light. This gives a "sleep" mode for

minimum power, typically 1 Watt. This input is internally pulled to a high state if not connected.

Luminance/Contrast Control Connector (J2)

Pin Symbol

1 LUM 2GND 3L0 4L1 5 ENABLE

EL640.400-CE Series3

■ CE Series Overview

The EL640.400-CE display can be ordered with

three interface options. T h e s e t h r e e d i s p l a y s a r e mechanically and optically identical.

Display Video Interface

EL640.400-CE4 8-Bit Flat Panel Display (FPD)

Local frame buffer selected

by PS1 Jumper 4 EL640.400-CE5 EL Normal EL640.400-CE6 VGA Modes

■ Connectors

Video/Power Input J1 26-pin header T&B Ansley 609-2607 or

3M 2526-5002-UB, or equivalent

Mating

(customer supplied) T&B Ansley 609-2641CE or

3M 3399-6626, or equivalent

Luminance/Contrast Control J2 5-pin header Hirose DF1-5P-2.5DS, or

equivalent

Mating

(customer supplied) Hirose DF1-5S-2.5R28 and

Hirose DF1-5A1.05, or equiv.

■ Luminance Control

The Luminance/Contrast control connector (J2) provides analog control of display Luminance/ Contrast with a 50K ohm external potientiometer. This analog dimming is available in all video modes. Also, two bit digital dimming is available in all modes except the 8-Bit non-buffered FPD mode (see table).

■ 200 Rows Mode

Two hundred input data rows may be displayed by automatically doubling every row of data. This function is selected by installing Jumper PS1/2. This is available only on the CE5 version of the display. Contact Planar for more information on this mode.

■ Internal Frame Buffer

The CE display includes an internal frame buffer. The brightness of the display is directly proportional to the output frequency at the frame buffer. The frame buffer frequency is controlled by L0 and L1 on connector J2. When the frame buffer is in use, loss of image will not occur with loss of video input. The displayed image is not automatically cleared.

Approximate Refresh Rate L1 L0

160 H H 120 H L

75 L H 60 L L

(L1 and L0 are internally pulled high if not connected.)

The buffered, 8-Bit Flat Panel Display, VGA, and Normal interfaces utilize the internal frame buffer. The brightness of the display is independent of the input frame rate. The f rame buffer in the CE4 can be bypassed by removing Jumper 4 on PS1 to allow input timing to control the frame rate. This mode allows use of frame rate gray scale algorithms. For optimum operation in this mode, L1 and L0 should be high or left disconnected.

■ Selectable Features

PS1 Jumper Description

Pin Name Function Applicable to

CE4CE5 CE6 1 SELFTEST Patterns Displayed xxx 2 200DBL 200 line mode. Each x

line of data is repeated

on the subsequent row 3 2-BIT Two-Bits-Parallel Mode x 4 Buffered FPD Refresh rate x

independent of input

frame rate. Remove

jumper when using

The PS1 jumper allows selection of several modes. Factory default for CE5 and CE6 is no jumpers installed. Factory default for CE4 is jumpers 1 through 3 open and jumper 4 installed.

Caution

The EL640.400-CE displays include an internal frame buffer. The displayed image is not automatically cleared in the absence of input video signals. The ENABLE control input signal can be used to blank the display in the event of system malfunction.

EL640.400-CE Series

Input Specifications

Parameter Symbol Min. Max. Units

Video Input Signals:

Absolute Maximum Input Voltage V Low-level Input Voltage V High-level Input Voltage V Low-level Input Current I High-level Input Current I

All video signal inputs are CMOS compatible with 100Ω series resistors. A series resistor at the driven end of the video

cable will reduce overshoot and undershoot. Generally, the resistor value should be equivalent to the impedance of the

DC Input Requirements

Input Voltage (nom=12.0V) VH 10.0 15.0 Vdc Input Voltage Absolute Max. VH Input Current (VH=12.0) IH 0.250

Refresh Rate=60Hz 1.0 Adc

Refresh Rate=160Hz 2.1 Adc Logic Voltage (nom=5.0V) VL 4.75 5.25 Vdc Logic Voltage Absolute Max. VL Logic Current IL 25 185 mAdc Power Consumption Typical Max. Units

Refresh Rate=60Hz 6.5 12.5 Watts

Refresh Rate=160Hz 12.6 25 Watts

Imax

max

-0.3 5.5 V

-0.3 0.5 V

4.5 5.0 V — -0.4 mA — 10 µA

cable.

–– 15.0 Vdc

-0.5 6.0 Vdc

■ Video Interfaces

The CE series displays make it easy to interface to different display controllers. The interfaces are: 8-bit FPD (CE4), Normal (CE5), and VGA (CE6).

The EL640.400-CE4 with its 8-bit FPD interface is designed for easy interfacing to flat panel controller IC's. The falling edge of VCLK simultaneously latches four data bits into the top half of the display and four bits into the bottom half of the display. This low speed clock can be an asset in reducing EMI. The 8-bit FPD interface allows access to gray scale algorithms generated in video controller chips which can result in 4 to 5 levels of gray scale at 60 Hz. More levels are available at higher frame rates. For further information, contact factory.

The EL640.400-C5 is backward compatible with some earlier Planar displays. This interface is pin and timing compatible with the MD640.400 and EL640.400CB series displays. There are only four necessary input signals: serial video data (VID), video clock (VLCK), horizontal synchronizing control (HS) and vertical synchronizing signal (VS). The fifth signal, BLANK, is not used and should be high or left disconnected.

Horizontal data position is determined in the Normal mode by the relationship between the falling edge of HS and the input data VID. The first 640 pixels after the rising edge of HS are displayed.

Vertical position is determined by the relationship between VS and HS. The data displayed on the first or top row is determined by the location of the VS rising edge.

The first row of a new frame is marked by the rising edge of VS during the HS high time. Data clocked into the display during this HS period will be displayed on the first row. See timing diagram for detailed timing.

In the normal mode it is possible to feed the input data in two line parallel mode to reduce the input data and clock frequencies. The data for the odd columns, as numbered from left to the right from the viewers side, should be connected to the TVID input (J1/ pin 7) and the data for the even columns to the VID input (J1/ pin 15).

The EL640.400-CE6 display is compatible with the IBM VGA feature connector standard. The display can directly use the signals available via the feature connector on IBM compatible VGA cards. The display is compatible with most VGA modes. The display assumes VGA standard borders. In 720 column modes, every ninth pixel is skipped. The ninth pixel is either a redundant character pixel or an extra space pixel so no data is lost. In VGA modes requiring 480 rows, the first 400 lines of data will be displayed. The last 80 lines of data are ignored.

EL640.400-CE Series5

■ 8-Bit FPD Interface (CE4)

This diagram illustrates the pattern of displayed data while in the 8-Bit FPD video mode.

Key: [

Video Data Line: Row In Frame, Data Bit In Row

] The data bits for 8 pixels per clock are sent to the display. For instance, 4 pixels (U3:1,1-U0:1,1) are sent to row 1 at the same time as four pixels (L0:1,1-L3:1,1) are sent to row 201. At the next clock, (U3:1,2-U0:1,2) are sent at the same time

as (L3:1,2-L0:1,2).

Num. Description Symbol Minimum Maximum Units

1 HS High time tHS 2 HS Low time tHS 3 HS setup to VCLK tHS 4 VID setup to VCLK tVID 5 VID hold from VCLK tVID 6 Video clock period tVCLK 150 -- nsec

VCLK rise, fall time tVCLK 7 VCLK low width tVCLK 8 VCLK high width tVCLK 9 VS (S) high setup to HS¯ tVS 10 VS(S) hold after HS¯ tVS 11 VCLK to HS allowance 0 -- nsec

HSU

12 HS period tHS 30.6 + t 13 VS (S) period tVS 200 --

Frame rate tVS -- 160 Hz

Frame time tVS 6.25 14 HS rise to VCLK fall tHSrVf 890 -- nsec 15 HS rise to VSrise tHSrVSr -- 62 nsec Notes:

HSL > tHS - tVS

1) is less than number 1]

[in figure above number 12 - number 9], where tVS

HSU

2) In the Buffered mode of operation the first 160 valid video data nibbles (Upper and Lower) after thefalling edge of HS are displayed. In the Non-Buffered mode of operation, the last 160 nibbles of video data prior to the rising edge of HS are displayed.

3) No more than 255 pixel clocks per line.

20 -- nsec 160

VCLK 95 -- nsec 5 -- nsec 10 -- nsec

-- 30 nsec 20 -- nsec 20 nsec 50 nsec 40 -- nsec

-- usec

< tHSH [in figure above number 9

HSU

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