Planar EL4836HB276.128 User Manual
EL4836HB and EL4836HB-ICEEL4836HB and EL4836HB-ICE
A
EL4836HB and EL4836HB-ICE
EL4836HB and EL4836HB-ICEEL4836HB and EL4836HB-ICE
276 x 128 Pixel Electroluminescent Display276 x 128 Pixel Electroluminescent Display
276 x 128 Pixel Electroluminescent Display
276 x 128 Pixel Electroluminescent Display276 x 128 Pixel Electroluminescent Display
Product ProfileProduct Profile
Product Profile
Product ProfileProduct Profile
The EL4836HB and the EL4836HB-ICE displays are
low power, rugged, high-resolution electroluminescent
(TFEL) flat panel displays. They replace the LCD or bulky
CRT in instrument product designs. Their compact
dimensions save space that can allow addition of features
or reductions in overall size. They are designed to
function in extreme environments, and the crisp displays
are viewable under most lighting conditions at wide
viewing angles. Their ease of installation reduces system
integration costs.
The EL4836HB and the EL4836HB-ICE are 276
column by 128 row displays with a resolution of 48 dots
per inch. The pixel aspect ratio is 1:1. The LCD-type
interface is TTL-compatible and is designed for hardware
compatibility with the Hitachi HD61830B or equivalent
LCD controller. These displays may be driven at frame
rates up to 120 Hz for applications requiring extra
brightness.
The displays require +5V/+12VDC or +12VDC
only power and four basic signals to operate:
1. Video Data or pixel information (VID)
2. Video Clock, pixel clock, or dot clock (VCLK)
3. Horizontal Sync (HS)
4. Vertical Sync (VS)
EL TechnologyEL Technology
EL Technology
EL TechnologyEL Technology
A display consists of an electroluminescent glass
panel and a mounted circuit board with control electronics.
LUMINUM ROW
ELECTRODE
DIELECTRIC
LAYERS
1 micron
1 mm
LIGHT EMITTING LAYER
TRANSPARENT
COLUMN ELECTRODE
GLASS SUBSTRATE
VIEW
Operations ManualOperations Manual
Operations Manual
Operations ManualOperations Manual
The EL glass panel is a solid-state device with a thin
film luminescent layer sandwiched between transparent
dielectric layers and a matrix of row and column
electrodes. The row electrodes, in back, are aluminum;
the column electrodes, in front, are transparent. The
entire thin film device is deposited on a single glass
substrate. A circuit board is connected to the back of the
glass substrate. Components are mounted on this circuit
board within the same area as the electroluminescent
viewing area on the glass panel. The circuit board is
connected to the glass with metal-on-elastomer
interconnect technology. The result is a flat, compact,
reliable and rugged display device.
The EL4836HB-ICE display includes a light absorbing
Integral Contrast Enhancement (ICETM) construction of
the display glass. ICETM background significantly improves
the luminance contrast of the display in bright ambients,
and makes the display easier to read by increasing the
crispness of the pixels.
The 276 column electrodes and 128 row electrodes
are arranged in an X-Y formation with the
intersecting areas performing as pixels. Voltage
is applied to both the correct row electrode and
V(t)
the correct column electrode to cause a lit pixel.
Special operating voltages required are provided
by a DC/DC converter.
®
The Definition of Quality ®
2EL4836HB, EL4836HB-ICE
Electrical CharacteristicsElectrical Characteristics
Electrical Characteristics
Electrical CharacteristicsElectrical Characteristics
DisplayDisplay
Display
DisplayDisplay
The EL4836HB and EL4836HB-ICE products consist of a display, a DC/DC converter, and interconnecting cable
as shown below.
Back of DisplayBack of Display
Back of Display
Back of DisplayBack of Display
WARNINGWARNING
WARNING
WARNINGWARNING
The display generates potentially
dangerous voltages, up to 200 volts.
J1
Do not touch the display electronics
during operation!
P1
CAUTIONCAUTION
CAUTION
CAUTIONCAUTION
1
J1
19 20
2
Maximum
cable length is
24"
P3
J3
J0
P0
DC/DC ConverterDC/DC Converter
DC/DC Converter
DC/DC ConverterDC/DC Converter
2
1
J0
16
15
Connector J1 is not polarized.
Input to the Display at P0Input to the Display at P0
Input to the Display at P0
Input to the Display at P0Input to the Display at P0
PinsPins
Pins
PinsPins
1, 2 Voltage VH +12V. See also the descriptions of DC power requirements on page 4.
3, 4 Voltage VL +5V optional input, see page 4.
5 not connected
6 not connected
7, 8, 10
12, 14, 16 Ground GND Signal return.
9 Vertical Sync VS VS initiates a new frame scan. To properly position the displayed data, VS rising edge must
11 Horizontal Sync HS HS marks the last pixel of a horizontal scan line.
13 Video Clock VCLK VID and HS are referenced to VCLK. Data latching occurs on the falling edge of VCLK. This
15 Video Data VID VID contains the serial video data to be displayed. A logic high corresponds to a lit pixel. Pixel
SignalSignal
Signal
SignalSignal
SymbolSymbol
Symbol
SymbolSymbol
DescriptionDescription
Description
DescriptionDescription
be high at the end of the first horizontal scan line of the frame . This signal passes directly
from the video source to the display via the DC/DC converter. It is not buffered or terminated
within the DC/DC converter.
tVCLK. The last 276 pixels prior to the falling edge of HS will be visible on the display. This
signal passes directly from the video source to the display via the DC/DC converter. It is not
buffered or terminated within the DC/DC converter.
signal passes directly from the video source to the display via the DC/DC converter. It is not
buffered or terminated within the DC/DC converter.
information on VID is supplied from left to right and from top to bottom; the first bit of data
on VID following HS is displayed as the pixel at the upper left corner of the display. Bit number
240 is at the upper right corner. Bit number 276 is directly beneath pixel number 1 and so
on. This signal passes directly from the video source to the display via the DC/DC converter.
It is not buffered or terminated within the DC/DC converter.
HS period must be an even multiple of 4
Hitachi 61830B LCD ControllerHitachi 61830B LCD Controller
Hitachi 61830B LCD Controller
Hitachi 61830B LCD ControllerHitachi 61830B LCD Controller
Compatible Video Timing Input at POCompatible Video Timing Input at PO
Compatible Video Timing Input at PO
Compatible Video Timing Input at POCompatible Video Timing Input at PO
3 EL4836HB, EL4836HB-ICE
275
Video ParametersVideo Parameters
Video Parameters
Video ParametersVideo Parameters
ParameterParameter
Parameter
ParameterParameter
1 Video clock (CL2) period (tVCLK) 235 630 ns
2 VCLK lowtime (tWL) 100 — n s
VCLK high time (tWH) 100 — ns
3 VID setup to VCLK (tDS) 50 — n s
4 VID hold from VCLK (tDH) 50 — n s
5 HS (CL1) high time (tHS high) 100 tVCLK ns
(Symbol)(Symbol)
(Symbol)
(Symbol)(Symbol)
276
Min.Min.
Min.
Min.Min.
Max.Max.
Max.
Max.Max.
UnitsUnits
Units
UnitsUnits
ParameterParameter
Parameter
ParameterParameter
6 HS setup time (tHSS) 100 tWL n s
7 HS hold from VCLK (tHSH) 0 tWH ns
8 VS (FLM) setup to HS (tHSD) 400 — ns
9 VS hold from HS (tVSD) 1000 — ns
HS (CL1) period (tHS) 276 — tVCLK
VS period (tVS) 128 — tHS
Frame Rate (1/VS period) 120 H z
(Symbol)(Symbol)
(Symbol)
(Symbol)(Symbol)
Min.Min.
Min.
Min.Min.
Max.Max.
Max.
Max.Max.
UnitsUnits
Units
UnitsUnits
Video Electrical SpecificationsVideo Electrical Specifications
Video Electrical Specifications
Video Electrical SpecificationsVideo Electrical Specifications
SymbolSymbol
Symbol
SymbolSymbol
VIL low-level input voltage - 0.3 0.8 V
VIH high-level input voltage 2.4 5.0 V
IILlow-level input current — - 0.4 mA
IIH high-level input current — 10 µA
VOH output high voltage 2.0 V
VOL output low voltage 0.4 V
ParameterParameter
Parameter
ParameterParameter
maximum input voltage — 5.5 V
@ IOH= 0.4 mA
@ IOL = 2.1 mA
Min.Min.
Min.
Min.Min.
Max.Max.
Max.
Max.Max.
UnitsUnits
Units
UnitsUnits
Note: All inputs are TTL-compatible CMOS with
24KΩ pull-up resistors and 100Ω series resistors to
minimize under- and over-shoot of input signals.
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