This service manual is intended for qualified service technicians ; it is not meant for the casual do-ityourselfer. Qualified technicians have the necessary test equipment and tools, and have been trained
to properly and safely repair complex products such as those covered by this manual.
Improperly performed repairs can adversely affect the safety and reliability of the product and may
void the warranty. If you are not qualified to perform the repair of this product properly and safely, you
should not risk trying to do so and refer the repair to a qualified service technician.
WARNING
This product contains lead in solder and certain electrical parts contain chemicals which are known to the state of California to cause
cancer, birth defects or other reproductive harm.
Health & Safety Code Section 25249.6 – Proposition 65
NOTICE
(FOR CANADIAN MODEL ONLY)
Fuse symbols (fast operating fuse) and/or (slow operating fuse) on PCB indicate that replacement parts must
be of identical designation.
REMARQUE
(POUR MODÈLE CANADIEN SEULEMENT)
Les symboles de fusible (fusible de type rapide) et/ou (fusible de type lent) sur CCI indiquent que les pièces
de remplacement doivent avoir la même désignation.
(FOR USA MODEL ONLY)
1. SAFETY PRECAUTIONS
The following check should be performed for the
continued protection of the customer and service
technician.
LEAKAGE CURRENT CHECK
Measure leakage current to a known earth ground (water
pipe, conduit, etc.) by connecting a leakage current tester
such as Simpson Model 229-2 or equivalent between the
earth ground and all exposed metal parts of the appliance
(input/output terminals, screwheads, metal overlays, control
shaft, etc.). Plug the AC line cord of the appliance directly
into a 120V AC 60Hz outlet and turn the AC power switch
on. Any current measured must not exceed 0.5mA.
Reading should
not be above
0.5mA
Earth
ground
Device
under
test
Also test with
plug reversed
(Using AC adapter
plug as required)
Leakage
current
tester
Test all
exposed metal
surfaces
ANY MEASUREMENTS NOT WITHIN THE LIMITS
OUTLINED ABOVE ARE INDICATIVE OF A POTENTIAL
SHOCK HAZARD AND MUST BE CORRECTED BEFORE
RETURNING THE APPLIANCE TO THE CUSTOMER.
2. PRODUCT SAFETY NOTICE
Many electrical and mechanical parts in the appliance
have special safety related characteristics. These are
often not evident from visual inspection nor the protection
afforded by them necessarily can be obtained by using
replacement components rated for voltage, wattage, etc.
Replacement parts which have these special safety
characteristics are identified in this Service Manual.
Electrical components having such features are identified
by marking with a
in this Service Manual.
The use of a substitute replacement component which does
not have the same safety characteristics as the PIONEER
recommended replacement one, shown in the parts list in
this Service Manual, may create shock, fire, or other hazards.
Product Safety is continuously under review and new
instructions are issued from time to time. For the latest
information, always consult the current PIONEER Service
Manual. A subscription to, or additional copies of, PIONEER
Service Manual may be obtained at a nominal charge from
PIONEER.
on the schematics and on the parts list
AC Leakage Test
2
TS5, BCT-1510, BCT-1520,
BCT-1530
3
TS5, BCT-1510, BCT-1520,
BCT-1530
2. EXPLODED VIEWS AND PARTS LIST
NOTES:•Parts marked by "NSP" are generally unavailable because they are not in our Master Spare Parts List.
2.1 PACKING
TS5/NYXK/FR only
The mark found on some component parts indicates the importance of the safety factor of the part.
•
Therefore, when replacing, be sure to use parts of identical designation.
Screws adjacent to mark on the product are used for disassembly.
•
12
15
13
14
10
18
7
9
16
Except TS5/NYXK/FR
6
2
16(Except BCT-1520)
12
18
8
15
9
3
1
14(Except BCT-1530)
10
11(BCT-1530 only)
17(for BCT-1510)
17(for BCT-1530)
8
4
16 (BCT-1520 only)
1
7
5
4
(1) PACKING PARTS LIST
Mark No. Description Part No.
1 Packing CaseSee Contrast Table(2)
2 Pulp Mold Pad FSee Contrast Table(2)
3 Pulp Mold Pad RSee Contrast Table(2)
4 Side Pad LSee Contrast Table(2)
5 Side Pad RSee Contrast Table(2)
6 Sub Packing CaseSee Contrast Table(2)
7 Remote Control UnitSee Contrast Table(2)
8 SheetAHG1153
9 Battery (R03) 2PVEM1018
TS5/NYXK/FR, TS5/NYXK/FR1, TS5/NYXK/FR2, TS5/NYXK/FR3, BCT-1510/NYXK/SP, BCT-1520/NYXK/IT and
BCT-1530/NYWXKPL are constructed the same except for the following:
.oNtraP
kraM.oNnoitpircseDdnalobmyS
TS5
/NYXK/FR
1Packing CaseBHD1489BHD1369BHD1369BHD1369 BHD1375 BHD1480 BHD1442
2Pulp Mold Pad F
3
Pulp Mold Pad R
4Side Pad L
5
Side Pad R
6
Sub Packing CaseBHB1036
Remote Control UnitBXD1010 BXD1010 BXD1010 BXD10107BXD1016 BXD1018
TS5/NYXK/FR, TS5/NYXK/FR1, TS5/NYXK/FR2, TS5/NYXK/FR3, BCT-1510/NYXK/SP, BCT-1520/NYXK/IT and
BCT-1530/NYWXKPL are constructed the same except for the following:
Fuse 0109 (REK1102) : Only this part is supplied as a service part..
KA4
NOTE FOR FUSE REPLACEMENT
CAUTION
FOR CONTINUED PROTECTION AGAINST RISK OF FIRE.
REPLACE ONLY WITH SAME TYPE AND RATINGS ONLY.
2170
2n2
D
26
D
1234
5
3110
6127
61286126
2127
2109
678
TS5, BCT-1510, BCT-1520,
BCT-1530
6180
BAS216
4
100K
2
220p47p
1N4004
1N4004
1N4004
8
7
7170
CDT1103G
2170
5170
CT283D3
2n2
7180
TCDT1103G
7275
KA431LZTA
10
16
12
11
14
18
17
13
15
F222
F223
F220
F221
10K
3290
F234
BYW95C/20
BYW95C/20
BYV27-200
6210
BYV27-200
BYD33D
3273
1
3
2
100n
2290
6220
BYD33J
6252
6250
6202
6225
6230
SB340
100R
2275
33n
+5V Return
AC_CLK
2200
22502222
2205
2210
2223
2230
+8Va
3274
4K7
3275
10K
4.7
100u
22u
100u100u
220u
+8Va
220u
2m2
+5Va+8Va
3278
3277
3276
3221
680R
9251
+5Va
5200
22u
5220
100u
470R
4K7
4K7
F201F202
BZX79-B27
6221
1N414B
6222
3202
BZX79
-B6V2
62046222
F209 F210
5210
3u3
F218
F217
6226
BZX79-C4V7
3230
+24V/19V
270R
+12V
BZX79-B5V6
+5V
F214
F213
2211
5230
2u2
47R
BC636
1K
3204
7205
BC847B
10u
-5V
F226
2231
7204
3205
F227
F233
2K2
F231
100u
0207
+6V
+3.3V
F245
F246
5208
3u3
3206
10K
F244
9208
Pow1
F205 F206
+5V Return
AC_CLK
+12V
+3.3V
+5V
-5V
F241
Pow1
+24V/19V
+6V
+28V
+18_23V
F230
F232
F242
A
B
TWG
0209
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CN7001
7/7
A
C
D
D
5
6
7
8
27
1
23
TS5, BCT-1510, BCT-1520,
BCT-1530
4. PCB CONNECTION DIAGRAM
4
4.1 FRONT ASSY
NOTE FOR PCB DIAGRAMS :
A
1. Part numbers in PCB diagrams match those in the schematic
diagrams.
2. A comparison between the main parts of PCB and schematic
diagrams is shown below.
Symbol In PCB
Diagrams
3. The parts mounted on this PCB include all necessary parts for
several destinations.
For further information for respective destinations, be sure to
check with the schematic diagram.
NOTES:•Parts marked by "NSP" are generally unavailable because they are not in our Master Spare Parts List.
CONTRAST OF PCB ASSEMBLIES
MarkSymbol and Description
The mark found on some component parts indicates the importance of the safety factor of the part.
•
Therefore, when replacing, be sure to use parts of identical designation.
When ordering resistors, first convert resistance values into code form as shown in the following examples.
•
Ex.1 When there are 2 effective digits (any digit apart from 0), such as 560 ohm and 47k ohm (tolerance is shown by J=5%,
and K=10%).
Idigital I-input bit 2(ADC bypass)
Idigital I-input bit 3(ADC bypass)
−digital ground 1 (core and input periphery)
Itest pin (normally connected to ground)
−digital ground 2 (core and input periphery)
Idigital I-input bit 4(ADC bypass)
Idigital I-input bit 5(ADC bypass)
Idigital I-input bit 6(ADC bypass - MSB)
Idigital Q-input bit 0(ADC bypass - LSB)
−digital supply voltage1 (core and input periphery)
Idigital Q-input bit 1(ADC bypass)
Idigital Q-input bit 2(ADC bypass)
Idigital Q-input bit 3(ADC bypass)
Idigital Q-input bit 4(ADC bypass)
−digital ground 3 (core and input periphery)
Idigital Q-input bit 5(ADC bypass)
Idigital Q-input bit 6(ADC bypass - MSB)
−digital ground 4 (output periphery)
−digital supply voltage 2 (core and input periphery)
Iset device into default mode
I/Oquasi-bidirectional I/O port (bit 3)
I/Oquasi-bidirectional I/O port (bit 2)
I/Oquasi-bidirectional I/O port (bit 1)
I/Oquasi-bidirectional I/O port (bit 0)
−digital supply voltage 3 (output periphery)
I/Oquasi-bidirectional I/O port (bit 5)
I/Oquasi-bidirectional I/O port (bit 4)
Ooutput clock for transport stream bytes
Oparallel data output (bit 0) - Serial data output
Oparallel data output (bit 1)
Oparallel data output (bit 2)
−digital ground 5 (output periphery)
Oparallel data output (bit 3)
Oparallel data output (bit 4)
Oparallel data output (bit 5)
−digital ground 6 (core and input periphery)
−digital ground 7 (core and input periphery)
Oparallel data output (bit 6)
38
Pin Function (2/3)
POR39ΟPower-on Reset
V
DDD4
40−digital supply voltage 4 (output periphery)
V
DDD5
41−digital supply voltage 5 (core and input periphery)
V
SSD8
42−digital ground 8 (core and input periphery)
V
DDD6
43−digital supply voltage 6 (core and input periphery)
V
DDD7
44−digital supply voltage 7 (output periphery)
PDO745Oparallel data output (bit 7)
n.c.46−not connected
V
SSD9
47−digital ground 9 (core and input periphery)
PDOERR48Otransport error indicator
PDOVAL49Odata valid indicator
PDOSYNC50Otransport packet synchronization signal
V
SSD10
51−digital ground 10 (output periphery)
SCL52Iserial clock of I
2
C-bus
SDA53I/Oserial data of I
2
C-bus
INT54Ointerrupt output (active LOW)
A055II
2
C hardware address
RSLOCK56OReed-Solomon lock indicator
VLOCK57OViterbi lock indicator
DLOCK58ODemodulator lock indicator
V
DDD8
59−digital supply voltage 8 (core and input periphery)
V
DDD9
60−digital supply voltage 9 (core and input periphery)
TEST61Itest pin (normally connected to ground)
TRST62IBST optional asynchronous reset (normally connected to ground)
TCK63IBST dedicated test clock (normally connected to ground)
SCLT64Οserial clock of I
2
C-bus loop-through
SDAT65I/Oserial data of I
2
C-bus loop-through
V
DDD10
66−digital supply voltage 10 (core and input periphery)
V
SSD11
67−digital ground 11 (output periphery)
V
SSD12
68−digital ground 12 (core and input periphery)
TMS69IBST input control signal (normally connected to ground)
TDO70OBST serial test data out
TDI71IBST serial test data in (normally connected to ground)
V
DDD11
72−digital supply voltage 11 (core and input periphery)
−digital supply voltage 12 (core and input periphery)
−digital supply voltage 13 (core and input periphery)
−digital ground 14 (core and input periphery)
O22 kHz / 44kHz output for dish control applications
−digital ground 15 (output periphery)
−digital ground 16 (core and input periphery)
OTuner AGC output
−not connected
−digital supply voltage 14 (output periphery)
−digital supply voltage 15 (core and input periphery)
OSigma Delta Output
Idigital I-input bit 0(ADC bypass - LSB)
Idigital I-input bit 1(ADC bypass)
Note
1. Pins I0 to I6, Q0 to Q6, SCL, SDA,
INT, SCLT, SDAT, V
and OUTSD are 5V tolerant.
AGC
2. The structure of I/O’s and the maximum output drive are specified in Section 12
40
STI5512MWD (MAIN ASSY(2/7) : IC2001)
• Programmable Transport IC
Block Diagram
•
TS5, BCT-1510, BCT-1520,
BCT-1530
Block move
DMA
Programmable
transport
interface
IEEE 1394
link layer
interface
IEEE 1284
interface
Interrupt
controller
1 OS-L ink
2 UARTs
2 I2C
3 PWM
ST20
CPU
2 Kbytes
instruction
cache
and 2 Kbytes
data cache
4 Kbyte s
SRAM
EMI
MPEG
audio and
external
decoder I/ F
MPEG
video
decoder
Diagnostic
controller
and system
services
2 SmartCard
interfaces
(ASC)
PAL/NTSC/
SECAM
encoder
Teletext
interface
41
TS5, BCT-1510, BCT-1520,
p
BCT-1530
Pin Function (1/5)
•
Signal names are prefixed by
PinNumberFunction
VDD13Power supply
GND16Ground
VClamp1-3
VDDA0-12Analog po wer supply for PAL/NTSC/SECAM encoder
VSSA0-12Analog ground for PAL/NTSC/SECAM encoder
RTCVDD1Real time clock supply
VDD_VPLL1Analog po wer supply for video PLL
VSS_VPLL1Analog ground for video PLL
1. The VClamp pins are a power supply bus used to diode clamp the voltage on 5V tolerant digital input or output pins to.
The voltage on the di gital signal pin is then clamped to within VImax (5.5V) if the applied voltage is increased above 5V.
If the devi ce is to be interfaced to 3.3V logic signals only, then the VClamp pins can be connected to the STi 5512 3.3V VDD
power supply. However if any pin is to be interfaced to a 5V logic signal, then the VClamp pins m ust be connected to the 5V
power supply (the 5V l ogic device power sup ply). Note i n thi s case t he 5V power su pply m ust b e ca pable of s inking t he c lamp
current of transient signals above 5V .
In the latter case it is important to ensure the correct power supply ramp sequence. The VClamp power supply must be applied before or at the same time as the VDD 3.3V power supply. This is to ensure that during power supply power up and
power down, VClamp > VDD + 0.5V.
1
not
if they are active low; otherwise they are active high.
outRed output
outGreen output
outBlue output
outChroma output
outComposite video output
outLuma output
inDAC current reference
inDAC current reference
inDAC volt age reference
inDAC volt age reference
CFC inputDENC color burst phase and frequency contro l.
This pin can be used in non-scart based Genlock applications.
If it is not used, this pin must
ground.
42
Table 2 Video out
ut interface pins
TS5, BCT-1510, BCT-1520,
BCT-1530
Pin Function (2/5)
•
1. The digital encoder video outputs are analogue signals and are not 5V tolerant. The same applies to the video DAC
voltage and current reference pins.
2. The YC0 pin is tri-stated during reset and then sampled at the end of the reset to determine whether the EMI pins are in
STi5510 or STi5512 mode. If the YC0 pin is sampled high (i.e at VDD) then the STi5510 mode is selected for the EMI pins
and a low v alu e selec ts STi 5512 mode. In STi5512 mode t he address
and the strobe pins are tri-stated when the EMI bus is granted to an
down
resistors shou ld be fitted to the YC0 according to the functionality
be pulled high by an internal pull-up and will default the EMI pins to
PinIn/OutFunction
SCLK/A_C_STBoutSerial clock or AC-3 data strobe
PCM_DATA/A_C_DATAoutPCM data out or AC-3 data out
PCMCLKin/outPCM clock
LRCLK/A-WORD_CLKoutLeft/right clock or AC-3 word clock
notA_C_REQ inAC-3 data request
notA_PTS_STB inAC-3 audio PTS strobe
shift for bank 3 is dependent on the boot bank width
external DMA device. Ext ernal 10KΩ pull-up or
desir ed. If t his p in is lef t
STi5510 mode.
not
connected, the pin will
pull-
Table 3 AC-3/MPEG1 audio output interface pins
PinIn/OutFunction
Interrupt0-1inInterrupt
T able 4 External interrupt pins
PinIn/OutFunction
ClockIninSystem input clock - PLL or TimesOneMode
SpeedSelect0-1inPLL speed selector
notRSTinSystem reset
CPUAnalyse / TrigIninError anal ysis / External trigger input to DCU
CPUReset inSoft reset for analyzing from OS-Link
ErrorOut / TrigOut
1. This pin is tri-stated d uring res et and t hen sa mpled at t he end of the res et to det ermine whet her the O S-Li nk is act iv e an d
to determine th e function of the shared CPUAnalyse / TrigIn and the ErrorOut / TrigOut, as described in the
ices
chapter. If the ErrorOut pin is sampled high (i.e at VDD) then the DCU signals (TrigIn and TrigOut) are selected and a
low value indicates OS-Link signals (i.e. CPUAnalyse, ErrorOut) are to be used. External 10KΩ pull-up or pull-down resis-
tors should be fitted to the ErrorOut according to the functionality desired.
1
in/out, outError indicator / Sig nal to trigger external debu g cir cui try (e.g. LSA)
T able 5 System services pins
System Serv-
43
TS5, BCT-1510, BCT-1520,
BCT-1530
Pin Function (3/5)
•
PinIn/OutFunction
MemAddr2-23 outAddress bus
MemData0-31 in/outData bus. MemData0 is the least significant bit (LSB) and MemData31 is the most
significan t bit (MSB).
MemRdnotWr outReadnotWrite strobe
MemReq inDirect memory access request
MemGrant outDirect memory access granted
MemWait inMemory cycle extender
notMemCAS0,2 outCAS strobes for SDRAM/DRAM in Banks 0 and 1
notMemCAS1 outCAS strobe for DRAM or SDRAM clock
notMemCAS3 outCAS strobe for DRAM or sub-bank chip select for bank 3
notMemRAS0 outRAS strobe for SDRAM/DRAM in Bank 0, chip select for Bank0 or
RAS strobe for lowest DRAM sub-bank in Bank0
notMemRAS1 outRAS strobe for highest DRAM sub-bank in Bank 0 or
SDRAM Chip select signal for highest sub-ba nk of Bank0
notMemRAS2 outRAS strobe for SDRAM/DRAM in bank 1, chip select f or Bank1 or
RAS strobe for lowest DRAM sub-bank in Bank1
notMemRAS3 outRAS strobe for highest DRAM sub-bank in Bank 1 or
SDRAM Chip select signal for Bank1
notMemCSROM outChip select st robe for ROM in bank3.
notSDRAMCS0outSDRAM Chip select signal for Bank0 or lowest sub-bank of Bank0
notMemOEoutOutput enable strobe - banks 0-3.
notMemBE0-3outByte enable strobes - banks 0-3.
notMemCS2outChip select strobe for me mo ry in bank 2.
BootSource0-1inBoot from ROM or from link.
ProcClockOutoutProcessor clock.
T able 6 STi5512 External memory interface pi ns
PinIn/OutFunction
AD0-12 outSDRAM address bus
DQ0-15 in/outSDRAM data bus (lower b yte)
notSDCS0 outSDRAM chip select for first SDRAM
notSDCS1/AD13 outSDRAM chip select for second SDRAM or AD13
notSDCAS outSDRAM CAS
notSDRAS outSDRAM RAS
notSDWE outSDRAM write enable
MEMCLKIN inSDRAM memory clock input
MEMCLKOUT outSDRAM memory clock out put
DQML outDQ mask enable (lower)
DQMUoutDQ mask enable (upper)
T able 7 Shared SDRAM interface pins
44
TS5, BCT-1510, BCT-1520,
BCT-1530
Pin Function (4/5)
•
PinIn/OutFunction
LPClockIn
LPClockOsc
AUX_CLK_OUToutAuxiliary clock for general use
1
1
1. The low power clock pins are not 5V tolerant.
PinI n/OutFunction
PIO0[0-7]in/outParallel input/output pin or alternative function (see
PIO1[0-7]in/outParallel input/output pin or alternative function (see )
PIO2[0-7]in/outParallel input/output pin or alternative function (see )
PIO3[0-7]in/outParallel input/output pin or alternative function (see )
PIO4[0-7]in/outParallel input/output pin or alternative function (see )
inLow power input clock
in/outLow power clock oscillator
8
T able
Low power controller and real time clock pins
IO pins
9P
Table
Table 15
Table 15
Table 15
Table 15
Table 15
)
PinIn/OutFunction
LinkIninSerial data input channel
LinkOutoutSerial data outpu t channel
Table 10 OS-Link pins
PinIn/OutFunction
TSInByteClk inLink IC byte clock
TSInByteClkValid inLi nk IC byte clock valid edge
TSInData0-7inLink IC data
TSInError inLink IC pac ket error
TSInPac ketClk inLink IC pac ket strobe
Table 11 Transport stream input pins
PinIn/OutFunction
TtxtEvennotOddinTeletext even not odd vertical sync signal
TtxtHsyncinThe HSYNC signal input when the teletext interface is operating in the inpu t mode
T able 12 Teletext interface
45
TS5, BCT-1510, BCT-1520,
BCT-1530
Pin Function (5/5)
•
The teletext clock and data inputs are shared PIO pins, as shown in Table 15 .
High speed data port pins have a dual function, and can be used either to interface to an external IEEE 1394 link layer
controller or provide an IEEE 1284 parallel port interface.
PinIn/OutFunction
1284Data0-7 / AVData0-7 in/outIEEE 1284 port data or AV data
1284notSelectI ninIEEE 1284 port control signals or A V signals
1284notInit / AVPacketTag3in
1284notFault / AVPacketTag2out
1284notAutoFd / AVPacketTag1in
1284Select / AVPacketTag0out
1284PError / A VByteClkValidout, in/out
1284Busy / A VPacketClkout, in/out
1284notAck / AVByteClkout
1284notStrobe/AVPacketErrorin
T able 13 High-speed data port pins
PinIn/OutFunction
TDIinTest data input
TDOoutTest data output
TMSinTest mode select
TCKinTest clock
notTRSTinTest logic reset
Table14TAP pins
PIO pins and alternative functions
To im prove flexibility and to allow the STi5 512 to fit into dif ferent set-top box application architectures, the input and
output signals from some of the peripherals are not directly connected to the pins of the device. Instead they are
assigned to the alternative function inputs and outputs of a PIO port bit. This scheme allows these pins to be configured
as general purpose PIO if the associated peripheral input or output is not required in that particular application.
Table 17 shows the assignmen t of the alternat ive functions to the PIO bits. Parentheses ( ) in the table indicate
suggested or possible pin usages as a PIO, not an alternative function connection.
Alternative function of PIO pins
Port
bit
PIO port 0PIO port 1PIO port 2PIO port 3PIO port 4
Analog output for the left channel. Typically 3.5V Vpp for a full-scale input signal.
AOUTR - Analog Right Cannel Output, PIN 5
Analog output for the right channel. Typically 3.5V Vpp for a full-scale input signal.
Digital Inputs
MCLK - Master Clock Input, PIN 4
The frequency must be 256x, 384x or 512x the input sample rate in Base Rate Mode (BRM)
and either 128x or 192x the input sample rate in High Rate mode (HRM).
LRCK - Left/Right Clock, PIN 3
This input determine which channel is currently being input on the Audio Serial Data Input
pin, SDATA.
SDATA - Audio Serial Data Input, PIN 1
Two's complement MSB-first serial data is input on this pin. The data is clocked into the
CS4335 via internal or external SCLK and the channel is determined by LRCK.
DEM/SCLK - De-emphasis / External serial clock input, PIN 2
A dual-purpose input used for de-emphasis filter control or external serial clock input.
52
73K324BL-IH (MAIN ASSY(6/7) : IC6005)
• Modem IC
Block Diagram
•
TXA1
18
TXA2
17
TS5, BCT-1510, BCT-1520,
BCT-1530
RXA
32
DTMF,
ANSWER,
TONE
CALLING
GUARD &
GENERATOR
FSK
MODULATOR
FILTER
EQUALIZERFILTER
QAM/
DPSK
MODULATOR
FIR
PULSE
SHAPER
2W/4W
HYBRID
ATTENUATOR
FILTER
A/D
SIGNAL
DIGITAL
FILTER
ANTI-ALIAS
PASS
BAND
FILTER
AGC
EQUALIZER
FIXED
RECEIVE
FUNCTIONS
PROCESSOR
GAIN
BOOST
DEMODULATOR
TONE
DETECTION
DI-BIT/
QUAD-BIT
ENCODER
SCRAMBLER
BUFFER
µP
BUS
8-BIT
27
DI-BIT/
INTERFACE
QUAD-BIT
DECODER
DEBUFFERDESCRAMBLER
SERIAL
INTERFACE
25
24
TXD
RXD
53
TS5, BCT-1510, BCT-1520,
BCT-1530
Pin Function (1/3)
•
POWER
NAMEPINTYPEDESCRIPTION
GND1ISystem ground
VDD16IPower supply input, 5 V ±10% (73K324BL). Bypass with 0.1
and 22 µF capacitors to GND.
VREF31OAn internally generated reference voltage. Bypass with 0.1 µF
capacitor to ground.
ISET28IChip current reference. Sets bias current for op-amps. The
chip current is set by connecting this pin to VDD through a
2 MΩ resistor. ISET should be bypassed to GND with a
0.1 µF capacitor.
PARALLEL MICROPROCESSOR CONTROL INTERFACE MODE
ALE13IADDRESS LATCH ENABLE: The falling edge of ALE latches
the address on AD0-AD2 and the chip select on &6.
AD0-AD75-12I/OADDRESS/DATA BUS: These bi-directional tri-state
multiplexed lines carry information to and from the internal
registers.
CS
CLK2OOUTPUT CLOCK: This pin is selectable under processor
INT
RD
RESET30IRESET: An active high signal on this pin will put the chip into
23ICHIP SELECT: A low on this pin during the falling edge of
ALE allows a read cycle or a write cycle to occur. AD0-AD7
will not be driven and no registers will be written if CS
(latched) is not active. The state of CS is latched on the falling
edge of ALE.
control to be either the crystal frequency (for use as a
processor clock) or 16 times the data rate for use as a baud
rate clock in DPSK modes only. The pin defaults to the cr ystal
frequency on reset.
20OINTERRUPT: This open drain output signal is used to inform
the processor that a detect flag has occurred. The processor
must then read the Detect Register to determine which detect
triggered the interrupt. INT will stay low until the processor
reads the detect register or does a full reset.
15IREAD: A low requests a read of the 73K324BL internal
registers. Data can not be output unless both RD and the
latched CS are active or low.
an inactive state. All Control Register bits (CR0, CR1, tone)
will be reset. The output of the CLK pin will be set to the
crystal frequency. An internal pull-down resistor permits
power-on-reset using a capacitor to VDD.
54
Pin Function (2/3)
PARALLEL MICROPROCESSOR INTERFACE (continued)
NAMEPINTYPEDESCRIPTION
WR
14IWRITE: A low on this informs the 73K324BL that data is
available on AD0-AD7 for writing into an internal register.
Data is latched on the rising edge of WR. No data is written
unless both WR and the latched CS are low.
SERIAL MICROPROCESSOR CONTROL INTERFACE MODE
NAMEPINTYPEDESCRIPTION
AD0-AD25-7IREGISTER ADDRESS SELECTION: These lines carry
register addresses and should be valid during any read or
write operation.
DATA (AD7)12I/OSERIAL CONTROL DATA: Data for a read/write operation is
clocked in or out on the falling edge of the EXCLK pin. The
direction of data flow is controlled by the RD pin. RD low
outputs data. RD high inputs data.
RD
15IREAD: A low on this input infor ms the 73K324BL that data or
status information is being read by the processor. The falling
edge of the RD signal will initiate a read from the addressed
register. The RD signal must continue for eight falling edges
of EXCLK in order to read all eight bits of the referenced
register. Read data is provided LSB first. Data will not be
output unless the RD signal is active.
WR
14IWRITE: A low on this input informs the 73K324BL that data
or status information has been shifted in through the DATA
pin and is available for writing to an internal register. The
normal procedure for a write is to shift in data LSB first on the
DATA pin for eight consecutive falling edges of EXCLK and
then to pulse WR low. Data is written on the rising edge of
WR.
NOTE: The serial control mode is provided by tying ALE high and CS low. In this configuration AD7 becomes
DATA and AD0, AD1 and AD2 become the register address.
•
TS5, BCT-1510, BCT-1520,
BCT-1530
55
TS5, BCT-1510, BCT-1520,
BCT-1530
Pin Function (3/3)
•
DTE USER
NAMEPINTYPEDESCRIPTION
EXCLK22IEXTERNAL CLOCK: This signal is used in synchronous
transmission when the external timing option has been
selected. In the external timing mode the rising edge of
EXCLK is used to strobe synchronous DPSK transmit data
applied to on the TXD pin. Also used for serial control
interface.
RXCLK26ORECEIVE CLOCK: The falling edge of this clock output is
coincident with the transitions in the serial received data
output. The rising edge of RXCLK can be used to latch the
valid output data. RXCLK will be valid as long as a carrier is
present.
RXD25ORECEIVED DATA OUTPUT: Serial receive data is available
on this pin. The data is always valid on the rising edge of
RXCLK when in synchronous mode. RXD will output constant
marks if no carrier is detected.
TXCLK21OTRANSMIT CLOCK: This signal is used in synchronous
transmission to latch serial input data on the TXD pin. Data
must be provided so that valid data is available on the rising
edge of the TXCLK. The transmit clock is derived from
different sources depending upon the synchronization mode
selection. In internal mode the clock is generated internally. In
external mode TXCLK is phase locked to the EXCLK pin. In
slave mode TXCLK is phase locked to the RXCLK pin.
TXCLK is always active.
TXD24ITRANSMIT DATA INPUT: Serial data for transmission is
applied on this pin. In synchronous modes, the data must be
valid on the rising edge of the TXCLK clock. In asynchronous
modes (1200/600 bps or 300/1200 baud) no clocking is
necessary. DPSK data must be 1200/600 bps +1%, -2.5% or
+2.3%, -2.5 % in extended over speed mode.
.
ANALOG INTERFACE AND OSCILLATOR
NAMEPINTYPEDESCRIPTION
RXA32IReceived modulated analog signal input from the telephone
line interface.
TXA1 / TXA 218 / 17O(differential) Transmit Analog. These pins provide the analog
output signals to be transmitted to the telephone line. The
drivers will differentially drive the impedance of the line
transformer and the line matching resistor. An external hybrid
can also be built using TXA1 as a single ended transmit
signal.
XTL1 / XTL23 / 4IThese pins are for the internal crystal oscillator requiring a
11.0592 MHz parallel mode crystal. Load capacitors should
be connected from XTL1 and XTL2 to ground. XTL2 can also
be driven from an external clock.
OH
56
27OOFF-HOOK RELAY DRIVER: This signal is an open drain
output capable of sinking 40 mA and is used for controlling a
relay. The output is the complement of the OH register bit in
the ID Register.
AMC2442ACVF(0.87) (MAIN ASSY(6/7) : IC6006)
• Modem Controller
Pinouts/Blockdiagram
•
CS0
DTR
Pinouts
CS1
CS2
CS3
RESET
TXD
RXD
RXC
TXC
CTS
6
54321
7
8
9
10
11
AMC2442ACV
12
13
14
15
16
#
17
192021222324252627
RD
WR
RTSRDDCD
CLKo
CLKi
GND
VCC1
AD0
444342
#
SPKR
AD1
#
AD2
41
RLY
AD3
39
38
37
36
35
34
33
32
31
30
29
BS
TS5, BCT-1510, BCT-1520,
BCT-1530
AD4
AD5
AD6
AD7
VCC2
ALE
HOOK
CHECK
SENCE
BLOCK DIAGRAM
DCD
CTS
RTS
DTR
RXD
TXD
2
17
4
5
13
11
UART
20
Crystal
Oscillator
Autobaud
Detection
31
19
18
33
24
36-42
Check
Sence
Hook
Shunt
Sieze
Ring Det.
In Use
RD
WR
ALE
Spkr
AD0-7
CLKiCLKo
21
Command
Interpreter
V.42
Handler
29
30
CTR-21
DAA
Drivers
Modem
AFE
Drivers
Country
Specific
Routines
AMC2442A
6
7
CS0 CS1 CS2 CS3
9
8
57
TS5, BCT-1510, BCT-1520,
BCT-1530
Pin Function
•
PIN NUMBER
Pin NameI/O TYPEDescription
DCD2OutputDTE Data Carrier Detect output signal. Indicates modem has detected carrier.
RING3InputRing detector input. This pin assumes that a half wave opto coupler is used in the
telephone line DAA circuit in the frequency detection algorithm.
RTS4InputDTE Ready To Send input signal. Used for hardware flow control.
DTR5InputDTE Data Terminal Ready input signal. Used to enable modem device
CS06IntputCountry Selection bit 0 (Internal pull up)
CS17InputCountry Selection bit 1 (Internal pull up)
CS28InputCountry Selection bit 2 (Internal pull up)
CS39InputCountry Selection bit 3 (Internal pull up)
RESET10InputReset signal to the AMC2442A Controller. Active High.
TXD11InputDTE Transmit Data Pin. All data communication from the DTE connects via this pin.
RXD13OutputDTE Receive Data Pin. All data communication to the DTE connects via this pin.
RXC14InputReceiver Clock Input from AFE. Used in PSK, QAM and synchronous data mode.
TXC15InputTransmitter Clock Input from AFE. Used in PSK, QAM and synchronous data mode.
Free16I/ODO NOT CONNECT
CTS17OutputDTE Clear To Send output signal. Used for hardware flow control.
WR18OutputWrite signal to AFE. Goes active low whenever the SMC wishes to write to the AFE
RD19OutputRead signal to AFE. Goes active low whenever the SMC wishes to read from the AFE
CLKo20OutputBuffered Clock output signal. Also used as a crystal drive signal when required.
CLKi21InputClock input signal. The SMC requires an 11.0592MHz signal on this pin.
GND22PowerController Ground connection
SPKR24OutputSpeaker Enable drive
Free25I/ODO NOT CONNECT
Free26I/ODO NOT CONNECT
RLY27OutputDAA Line Seize relay control. Used if DPCO relay is used to share the telephone with a
standard telephone instrument.
BS28OutputDAA Bell Shunt control. Used during LD dialling to provide a low impedance loop.
SENSE29InputLine-In-Use detection input.
CHECK30OutputLine-In-Use circuit drive pin.
HOOK31OutputDAA Hook switch control. Delayed from Seize to allow for a low cost opto coupler.
NC32I/ODO NOT CONNECT
LATCH33OutputALE signal to AFE. Goes active high to latch an address into the AFE
VCC235PowerAuxiliary power supply pin.
AD7->AD036->43I/OMultiplex Address / Data bus connections to AFE.
VCC144PowerMain power supply pin.
NC1I/ODO NOT CONNECT
NC12I/ODO NOT CONNECT
NC23I/ODO NOT CONNECT
NC34I/ODO NOT CONNECT
58
PE5181A (MAIN ASSY(7/7) : IC7001)
.oNMark
Active
emaNniPO/InoitcnuFniP
1
P50
LED10OLowFront LED, seg
P51
LED11OLowFront LED, seg
P52
LED12OLowFront LED, seg
P53
LED13OLowFront LED, seg
P54
LED14OLowFront LED, seg
P55
LED15OLowFront LED, seg
P56
LED16OLowFront LED, seg
P57
LED17OLowFront LED, seg
P44
LED03OLowFront LED, dig
P45
LED02OLowFront LED, dig
P46
LED01OLowFront LED, dig
P47
LED00OLowFront LED, dig
P30
IRQ_TEIDENOLowPower failure interruption (L output only at power failure)
P31
IRQ_KEYOLow
Low
Low
Any
Any
Low
Remote controller / key interruption
P35
×O
P34
×O
P36
×O
P21
×O
P20
×O
P22
×O
P24
P25
×O
P23
×O
P66
×O
P40
×O
P67
×O
P41
×O
P43
×O
P42
×O
P13
×IFor AGC Reading
P72
×O
OPower_off Mute
SDA0
I2C_SDAOI2C_SDA Output
SCL0
I2C_SCL
SUB_MUTE
P17IFor production lineTEST
LowP12IFront key inputKEY02, MENU
LowP11IFront key inputKEY01, OK
HighINTP0IRemote control inputREM
HighTI00IRemote control inputREM
LowP73OStand-by signal (H output at full power)XSTBY