Pioneer PLE42FMN2, JVC LT42DR940 Schematic

SERVICE MANUAL

8M51B CHASSIS

MUTE

FREEZE

POWER

P.P

S.M

SLEEP

ZOOM

HOME

REC CH.LIST FAV EPG

T.SHIFT

INFO

INDEX

SUBTITLE

AUDIO

MTSCC

RETURN

EXIT

VOL

SOURCE

789

Design and specifications are subject to change without prior notice.

(Only Referrence)

SIZE:A5

Description:

MODEL.

JOB NO.

Engineering Dept:

Artwork By:

Checked By:

Approved By:

SERVICE MANUAL 8M51B

Brand Name:

SKYWORTH

Date:

2012-5-23

Content--------------------------------------------------------------2

11-17

19-20

21-28

29-45

46-49

50-57

LED 8M51B

NTSC-M PAL-M PAL-N

Component

VHF LOW 2~B VHF HIGH C~W+11 VHF W+12~69

TOSHIBA CODE

55.25MHz ~ 127.25MHz

133.25MHz ~ 311.25MHz 367MHz ~ 801.25MHz

120

140

For 32” LED For 42” LED

For 47” LED

(26inches is 8 ohm)

3.3

DC Voltage, PANEL(12)

4.2 50

0.5 12000

Standard

YES

8 6

Spanish

4 2

0 40 7 0

0 40

40 85

-Y 0 5 0

30000

SYSTEM

CitAdi

Rear Terminal

AMP5707

8W + 8W

KEY PAD, IR Receiver

VGA-Audio

FLASH

DDRIII

2Gbx1+1Gbx1

IF+/-

MSD6329

Ultra high speed 32-bi RISC CPU

IF Demo. Build in

MPEG1/2/4 /H.264 Decoder

Analog

Demo

e +

LED

JPEG MP3 Decoder

PANEL

USB2

USB1

8M51B

HP AMP.

BH3544

Transformer

IP101A

R/L

HDMI1

HDMI2

USB2

IF+/-

TC90527

ISDB-T

Demodulator

Block Diagram for 8M51B series

ISDB-T

Analog IF

TUNER

Side Terminal

onent

Com

Serial TS

ompos

L/R

Audio L/R

Composite

HDMI data

Composite

HDMI4

LAN

USB1

HDMI3

IC Block Diagram

U2（3.3V/1A 3-TERMINAL POSITIVE VOL TAGEREGULATOR） LD1117-3.3 SOT-223

INPUT

Thermal

Shutdown

Ou t

OUTPUT

GND (Fixed Output)

ADJ (Adjustable Output)

U50 （1.1V/3A LOW DROPOUT LINEARAR REGULATOR）AOZ1051PI SO-8

Reference

& Bias

0.8V

UVLO

& POR

EAmp

–

5V LDO

Regulator

Softstart

5μA

Internal

PWM

–

Comp

+5V

OTP

ILimit

PWM

Control

Logic

Level

Shifter

FET

Driver

COMP

500kHz

Oscillator

ISen

VIN

–

AGND

PGND

U3 （2.5V/1A ）AS1117L-ADJ A1 SOT-223

Thermal

Shutdown

INPUT

Out

OUTPUT

GND (Fixed Output)

ADJ (Adjustable Output)

U19 （1.2V/1A）AP1122EG-13 SOT223-3L

Vin

Thermal

Shutdown

2 Vout

CURRENT

LIMIT

1.2V

GND

IC Block Diagram

U9(LCDTV CONTROLLER WITH VIDEO ECODE)MSD6329SV-Z1-SVN MSTAR

DVB Digita l T e l evision System -on -Chip

Preliminary PinDiagram /De scrip tion an d Me chan ica l D im ensions Vers ion 0.2

PIN DIAGR AM (M SD 632 9SV)

Top V iew

12345678910111213

A NC LVB0N LVB1P LVBCKN LVB3P LVA 0N LVA 1P LVACKN LVA 3P GN D G ND GN D

B USB0_DM N C N C LVB1N LVB2P LVB3N LVB4P LVA 1N LVA2P LVA3N

C USB0_DP NC NC LVB0P LVB2N LVBCKP LVB4N LVA 0P LVA2N LVACKP LVA 4P

[5 ]

RT C _X OU

GPIO _PM

D NC RTC_XIN

E HW RESET

F SDO

G SD I S C K BIN0P SPD IFO S PD IFI G PIO 198 G PIO 193 GN D GN D G PIO 195 G PIO 183 GN D GN D

H BIN0M SO G IN0 GIN 0P

J GIN 0M R IN0P R IN0M

K B IN1P B IN1M SO G IN1

L GIN 1P GIN 1M R IN1P

M R IN1M B IN2P B IN2M IRIN A V _LINK

N SO G IN2 GIN 2P GIN 2M VSY N C0 H S YN C0 SA R2

GPIO _PM

[6 ]/S C Z 1

GPIO 204 GN D GPIO197 GPIO 194 GPIO190 GPIO 202 GPIO 187 LVA4N

GPIO 203 GPIO 185 GN D GN D GPIO 199 GPIO189 GPIO 186 GPIO 188

[8 ]

SCZ0 G PIO200 G PIO192 G PIO196 GN D G N D G PIO 191 G PIO201 G PIO 184 GN D GN D

GPIO _PM

[1 0 ]

ET_TX D [1

[1 3 ]

[4 ]

ET_RX D [1]GPIO _PM

[2 ]

ET_R EF_

CLK

]

ET_M DC

ET_TX D [0]ET_TX_E

ET_M D IO

ET_RX D [0]GPIO _PM

[1 ]

GPIO _PM

[3 ]

ET_CR S_

[0 ]

GPIO _PM

[1 2 ]

DD CA _D A/ UART0_TX

DD CA _ CK/

UART0_RX

GN D GN D GN D GN D GN D GN D

A_DD R3_

A[1]

MSD6329SV

A_DD R3_

A[14]

A[12]

A[11]

A[8]

A_M C LKZ

A_DD R3_

BA[1]

A[6]

A[4]

P R IN2P R IN2M CV BS5 SA R 0 S AR1 V SY N C1 SA R 3 G N D GN D G N D GN D G N D GN D

R C V B S2 CV BS4 C V B S3 H SY N C1 N C N C PG A_ C OM BY P ASS GN D G N D GN D G N D GN D

IV E

MP LL

[6 ]

[4 ]

[5 ]

AVD D _AU

AVD D _EA

R33

GN D G N D GN D

TS1DATA

[1 ]

TS1DATA

[0 ]

TS0DATA

[7 ]

VD D C GN D GN D GN D

GN D GN D GN D

TS 1V A LID T S1 CLK G P IO 137

TS1DATA

[3 ]

TS1DATA

[2 ]

TS1DATA

[4 ]

TS1DATA

TS0VA LID TS0CLK

TS1DATA

[5 ]

[6 ]

TS0DATA

[2 ]

TS1DATA

[7 ]

PCMA D R[1

2]/CI_A[12

]

TS0DATA

[1 ]

TS0DATA

[0 ]

TS0SYNC

C25

AVD D _M

AVD D _AD

AVD D _DV

TS2VALID

HOTPLUG

T CV BS1 VCO M CVBS0 AUR0 AU L0

CVBSO UT0CVBSO UT

V AU VRM AU VAG AU L2

W AUR2 A U L3 AUR3 G N D GN D G N D N C G N D

Y AUL4 AUR4 AU L1

AA AUR1 AUO UTL1 AUOUTR1

AB AUO UT L0 AUO UTR0

EAR_O UT

AD GPIO 180 GPIO 181 GPIO 182

AE G PIO 179 IP VIFM SIFM N C N C

AF IM VIFP SIFP NC NC CEC RXCCKP RXC1N RXC2P RXD0N RXD1P RXBCKN

12345678910111213

XIN XO UT

AUVRP

EAR _O UTLDDCDD_CKDDCDB_DADD CD A_C

AVD D _RE

AVD D _DV

DDCDC_CKDDCDC_DADD CD A_DAHOTPLUGBTS0DATA

HOTPLUGCDDCDB_C

DDCDD_

RF_AGC/

F25

I_ U SB

TAGC

AVD D _AD

AVD D _DV

I_ U SB

IF_ A GC A R C0

OD33

C25

I_ U SB

AVD D _PG

A25

AVD D _AL

AVD D _MPLLAVD D _D

TS2DATA

TS2CLK TS2SYNC TS1SYNC

TS0DATA

RX CC KN RX C 0P RX C 2N RX D C KP RX D 1N RX D 2P RX B 0N

HOTPLUG

TS0DATA

[0 ]

TS0DATA

[3 ]

RX C 0N RX C1P RX D C KN RX D 0P RX D 2N RX B CKP

D o c. N o .:20120 10163

1/25/2011

2011 M Star Sem icond ucto r, Inc . A llri gh ts re s e rv e d .

MSD6329SV

20120 1 0163

DVB Digita l T e l evision System -on -Chip

Preliminary PinDiagram /De scrip tion an d Me chan ica l D im ensions Vers ion 0.2

14 15 16 1 7 18 19 20 21 22 23 24 25 2 6

GN D G N D GN D G N D GN D GN D GN D GN D GN D GN D GN D GN D G N D A

A[10]

A_DD R3_

DQL[5]

A_DD R3_

DQL[7]

A_RASZ A_CA SZ

A_M C LK

A_M CLKE

A_DD R3_

A_O DT A_W EZ

GN D G N D GN D G N D GN D GN D GN D GN D

GN D G N D

GN D G N D GN D

GN D G N D GN D G N D GN D GN D GN D GN D

GN D G N D GN D G N D GN D GN D GN D

GN D G N D GN D G N D GN D VD D C GN D GN D

GN D G N D GN D G N D GN D

VDDC VDDC

GN D G N D GN D G N D GN D VD D C A V D D _11

]

NF_AD[1]/P

CMA D R[1]/

CI_A[1]

NF_AD[4]/P

CMA D R[4]/

CI_A[4]

PCMA D R [1

4]/CI_A[14

GPIO 138

NF _ W PZ G PIO 140

PCMA D R [1

1]/CI_A[11

PCMR EG/

CI_CLK

]

RX B 1P RX AC KN RX A 0P RX A 2N

RX B 1N RX B2P RX A0N RX A1P

RX B 0P RX B 2N RX AC KP RX A 1N RX A 2P PC M W EN P C M O EN

14 15 16 1 7 18 19 20 21 22 23 24 25 2 6

A_DD R3_

DQL[1]

A_DD R3_

DQL[3]

AVD D _DDR0AVD D _DDR0AVD D _DDR0AVD D _DD

A_DD R3_

DQU[2]

A_DD R3_

DQML

A_DD R3_

BA[0]

A_DD R3_

A[3]

A_DD R3_

DQU[6]

A_DD R3_

DQU[0]

A_DD R3_

A[5]

A_DD R3_

A[7]

A_DD R3_

DQSBU

A_DD R3_

DQU[4]

A_RESET

A_DD R3_

A[9]

AVD D _DDR0AVD D _DDR1AVD D _DD

AVD D _DDR1AVD D _DD

AVD D _DD

GN D G N D GN D GN D

GN D GN D GN D

DVDD_D

NF_AD[0]/P

CMA D R[0]/

CI_A[0]

NF_AD[2]/P

CMA D R[2]/

CI_A[2]

NF_AD[7]/P

CMA D R[7]/

CI_A[7]

NF_AD[5]/P

CMA D R[5]/

CI_A[5]

NF_CEZ NF_CEZ1 GN D VD DC N C VD DP VDD P

NF_AD[3]/P

CMA D R[3]/

CI_A[3]

NF_AD[6]/P

CMA D R[6]/

CI_A[6]

GPIO 139

NF _R EZ GN D VD D C VD D C V D D C VD D C PW M2 PW M4 PW M1 AA

NF_RBZ NF_ALE GPIO 40 NC VDDC VDDC PW M3 PW M0 USB1_DP AB

PCMA D R[1 3]/CI_A[13

PCM IRQ/

CI_INT

PCM W AIT

/C I_ W A C

NF _ C LE NF _W EZ G PIO 39

]

PCM IO R/

CI_RD

PCM IO W/

CI_WR

A_DD R3_

DQSBL

A_DD R3_

DQSU

A[13]

DQU[1]

A_DD R3_

DQSL

A_DD R3_

GN D GN D

BY P ASS_

VCO RE

A[2]

A_DD R3_

DQU[7]

A_DD R3_

DQU[3]

A_DD R3_

A[0]

B_DD R3_

A[14]

B_DD R3_

A[8]

B_DD R3_

A[4]

B_DD R3_

BA[1]

B_DD R3_

A[3]

B_DD R3_

A[7]

B_DD R3_

A[9]

B_DD R3_

A[2]

B_DD R3_

BA[2]

A_DD R3_

DQMU

A_DD R3_

DQU[5]

A_DD R3_

BA[2]

B_M C LKE

B_DD R3_

A[1]

B_DD R3_

A[11]

B_DD R3_

A[6]

B_DD R3_

A[12]

B_DD R3_

A[10]

B_DD R3_

BA[0]

B_DD R3_

A[5]

B_RESET

B_DD R3_

A[13]

B_DD R3_

A[0]

A_DD R3_

DQL[0]

A_DD R3_

DQL[2]

B_DD R3_

DQL[7]

B_DD R3_

DQL[3]

B_DD R3_

DQML

B_DD R3_

DQU[0]

B_DD R3_

DQU[4]

B_DD R3_

DQSBL

B_DD R3_

DQSL

B_DD R3_

DQU[3]

B_DD R3_

DQU[5]

B_DD R3_

DQL[2]

B_DD R3_

DQL[6]

B_ODT B_RASZ GND R

B_ W EZ B_ C A SZ GND T

GN D GN D GN D GN D N C N C

GN D GN D GN D GN D

GPIO 45

PCM CEN/

CI_CS

AVD D _LP

PCMA D R [5]

/CI_A[5]

PCMA D R [0]

/CI_A[0]

GPIO 44/U

ART2_RX

GN D GN D G P IO 102

GPIO 42/U

ART1_TX

PCMA D R [2]

/CI_A[2]

PCMA D R [6]

/CI_A[6]

PCMA D R [1]

/CI_A[1]

GPIO 41/U

ART1_RX

PCMA D R [3]

/CI_A[3]

PCMA D R [4]

/CI_A[4]

CI_RST G P IO 141

I2 S _ O U T

_BCK

I2 S _ I N _ W

USB1_DM USB2_DP U SB2_DM AC

PCMA D R [8]

/CI_A[8]

PCMA D R [7]

/CI_A[7]

A_DD R3_

DQL[4]

A_DD R3_

DQL[6]

B_DD R3_

DQL[5]

B_DD R3_

DQL[1]

B_DD R3_

DQU[2]

B_DD R3_

DQU[6]

B_DD R3_

DQSBU

B_DD R3_

DQU[1]

B_DD R3_

DQU[7]

B_DD R3_

DQMU

B_DD R3_

DQL[0]

B_DD R3_

DQL[4]

I2 S _ O U T

I2 S _ I N _ SDI2 S _ I N _ B

DQSU

_WS

B_M CLKZ B

B_M CLK C

GND D

GND E

GND F

GND G

GND H

GND J

GND K

GND L

GND M

GND N

GND P

I2 S _ O U T

_SD

I2 S _ O U T

_M CK

DDCR_ CK DDCR_DA Y

PCMA D R [1 0]/CI_A[10

CI_CD

GPIO 43/UA

RT2_TX

]

GPIO 38 AD

PCMA D R [9]

/CI_A[9]

Doc.No.:

1/25/2011

2011 M Star Sem icond ucto r, Inc . A llri gh ts re s e rv e d .

MSD6329SV

20120 1 0163

DVB Digita l T e l evision System -on-Chip

Preliminary P inDiagram /De scription an d Me chan ical D im ension s Version 0.2

Pin N ame Pin Type Fun ction Pin

G PIO [40:38 ] I/O w / 5V -tolerant G eneralPurpose Input/O utput; 4m A driving strength AB 20,A C21,

AD26

G PIO _P M[ 1 3:12] I/O w / 5V -tolerant G eneralPurpose Input/O utput; 4m A driving strength J4, L7

GPIO_PM[10] I/O w/5V-tolerant G eneralPurpose Input/O utput; 4m A driving strength H 4

G PIO _PM[ 8] I/O w / 5V -tolerant G eneralPurpose Input/O utput; 4m A driving strength E3

G PIO _PM[ 6]/ SCZ1

I/O w / 5 V -t o l erant G eneralPurpose Input/O utput; 4m A driving strength /

ExternalSPI Flash C hipSelect

G PIO _P M[ 5 :0] I/O w / 5V -tolerant G eneralPurpose Input/O utput; 4m A driving strength E2,K4, M 6,L4,

L6, K7

PW M 4 O utput PulseWidth M odulation O utput; 4m A driving strength

AA25

PW M 3 O utput PulseWidth M odulation O utput; 4m A driving strength A B 24

PW M 2 O utput PulseWidth M odulation O utput; 4m A driving strength A A 2 4

PW M 1 O utput PulseWidth M odulation O utput; 4m A driving strength A A 2 6

PW M 0 O utput PulseWidth M odulation O utput; 4m A driving strength A B 25

SAR3 Analog Input SAR Low Speed AD C Input 3;

G eneralPurpose Input/O utput

SAR2 Analog Input SAR Low Speed AD C Input 2;

G eneralPurpose Input/O utput

SAR1 Analog Input SAR Low Speed AD C Input 1;

G eneralPurpose Input/O utput

SAR0 Analog Input SAR Low Speed AD C Input 0;

G eneralPurpose Input/O utput

Doc.No.:

1/25/2011

2011 M Star Sem icond ucto r, Inc . A llri gh ts re s e rv e d .

DVB Digita l T e l evision System -on-Chip

20120 1 0163

Preliminary P inDiagram /De scription an d Me chan ical D im ension s Version 0.2

DR AM Interfa ce

Pin N ame Pin Type Fun ction Pin

MSD6329SV

A_DD R3_A [1 4 :0]

O utput D RAM M em ory Address B12,D20,C12,

D 12, D 14,E19, E12,E18,D 13, D 18, E13, E 17, D21,B11,D22

A_DD R3_BA

O utput D R A M M em ory B ank A dd ress D 23, C 13, D 17

[2 :0]

A_M CLKE O utput D R A M M em ory C lock Enable C14

A_O D T I/O Reserved for future O n-D ieTermination E15

A_W EZ O utpu t W rite Enable; active low E16

A_R ASZ O utput Row Address Strobe; active low D 15

A_CASZ O utput Column Add re ss Strobe; active low D 16

A_M CLK O utput D RAM M em ory Positiv e D iffe re n t i alClock B1 4

A_M CLKZ Output DRAM M em ory Negative D ifferentialClock B13

A_DD R3_D Q MU O utput D ata M ask forLow Byte; active high B23

A_DD R3_D Q ML O utput D ata M ask forLow Byte; active high C17

A_DD R3_D Q SU I/O D ata Strobe B20

A_DD R3_D Q SL I/O Data Strobe C 21

A_DD R3_D Q SBU I/O D ata Strobe Inverse B19

A_DD R3_D Q SBL I/O D ata Strobe Inverse C 20

A_DD R3_D QU [7 :0]

I/O D RAM M em ory D ata Bus B22,B18,C23,

C19,C22,B17, B21, C18

A_DD R3_D QL [7 :0]

I/O D R A M M e m o ry D a ta B u s C 1 5 , C 2 5 , B 1 5 ,

B25, C16,C 24, B16, B24

A_R ESET Input D R A M M em ory R eset; active low D 19

B_D DR 3_A [1 4 :0]

O utput D RA M M em ory Address G 22, R2 3,K23,

H 23, L23, P22, H22,N22,J23, N23,J22,M 22, R22,G 23,T23

B_D DR 3_BA

O utput D R A M M em ory B ank A ddress T 22,K 22,M 23

[2 :0]

B_M CLKE O utput D R A M M em ory C lock Enable E23

B_O D T I/O Reserved for future O n-D ieTermination R 24

Doc.No.:

1/25/2011

2011 M Star Sem icond ucto r, Inc . A llri gh ts re s e rv e d .

DVB Digita l T e l evision System -on-Chip

20120 1 0163

Preliminary P inDiagram /De scription an d Me chan ical D im ension s Version 0.2

Pin N ame Pin Type Fun ction Pin

B_W EZ O utput W rite Enable; active low T24

B_R ASZ O utput R ow Address Strobe; active low R 25

B_CASZ O utput Column Address Strobe; active low T25

B_M CLK Output D RAM M em ory Positiv e D ifferen tialClock C26

B_ M CLK Z O utput D R A M M em ory N egative D ifferential C lock B 26

B_D D R 3_D Q MU O utput D ata M ask for Low Byte; active h igh M 25

B_DDR3_DQML Output Data Mask forLow Byte;active high F24

B_DDR3_DQSU I/O Data Strobe J25

B_DDR3_DQSL I/O Data Strobe K24

B_DDR3_DQSBU I/O Data Strobe Inverse H 25

B_DDR3_DQSBL I/O Data Strobe Inverse J24

MSD6329SV

B_D DR 3_DQU [7 :0]

I/O D R A M M em ory D ata B u s L25, G 2 5, M 24,

H 24 , L24, F25, K25, G 24

B_D DR 3_DQL [7 :0]

I/O D RA M M em ory D ata Bus D 24, P24,D 25,

P25,E24,N 24, E25,N 25

B_ RE SET In put D R A M M em ory R eset; active low P23

Ethernet RM IIInterface

Pin N ame Pin Type Fun ction Pin

ET_CR S_D V I/O w / 5V-tolerant Eth ernet M AC Ca rrier Sense/R eceive D ata Valid J7

ET_TXD [1:0] O utput w / 5V -toleran t E thernet M A C T ran sm itD ata B u s J5 ,H6

ET_TX_EN O utput w / 5V -toleran t E thernet M A C T ran sm itEnable H7

ET _R EF_C LK Input w / 5V-tolerant Ethernet M AC Synchronous C lock R eferen ce for R eceive,

Transm itand ControlInterface

ET_R XD [1:0] Input w / 5V-toleran t E th ern et M AC R eceive Da ta Bus L5, K6

ET_M D C O utput w / 5V-toleran t E thernet M A C M anagem en t Da ta Clock K5

ET_M D IO I/O w / 5V-tolerant Ethernet M AC M anagem entD ata Bus J6

Doc.No.:

1/25/2011

2011 M Star Sem icond ucto r, Inc . A llri gh ts re s e rv e d .

MSD6329SV

20120 1 0163

DVB Digita l T e l evision System -on-Chip

Preliminary P inDiagram /De scription an d Me chan ical D im ension s Version 0.2

USB Interface

Pin N ame Pin Type Fun ction Pin

USB0_DP Analog I/O U SB N on Inverting D ata Input/O utputfor Port0 C1

USB0_DM Analog I/O U SB In verting Da ta Input/O utput for Port 0 B1

USB1_DP Analog I/O U SB N on Inverting D ata Input/O utputfor Port1 AB26

USB1_DM Analog I/O U SB In verting Da ta Input/O utput for Port 1 AC 24

USB2_DP Analog I/O U SB N on Inverting D ata Input/O utputfor Port2 AC25

USB2_DM Analog I/O U SB In verting Da ta Input/O utput for Port 2 AC 26

UART Interface

Pin N ame Pin Type Fun ction Pin

GPIO44/ U ART2_RX

GPIO43/ U ART2_TX

GPIO42/ U ART1_TX

GPIO41/ U ART1_RX

D D CA _DA/ U ART0_TX

DDCA_CK/ U ART0_RX

I/O w / 5 V -t o l erant G eneralPurpose Input/O utput; 4m A driving strength /

UniversalAsynchronous R eceiver 2

I/O w / 5 V -t o l erant G eneralPurpose Input/O utput; 4m A driving strength /

UniversalAsynchronous Transm itte r 2

I/O w / 5 V -t o l erant

G eneralPurpose Input/O utput; 4m A driving strength / UniversalAsynchronous T ransm itte r 1

I/O w / 5 V -t o l erant

G eneralPurpose Input/O utput; 4m A driving strength / UniversalAsynchron ous R eceiver 1

I/O w / 5 V -t o l erant DDC D ata for A n alog port /

UniversalAsynchronous T ransm itte r 0

I/O w / 5 V -t o l eran t DDC C lock for A n alog port /

UniversalAsynchron ous R eceiver 0

AF21

AF25

AC22

AC23

VIF Interface

Pin N ame Pin Type Fun ction Pin

VIFM Analog Input N egative Video IF Input AE3

VIFP Analog Input P ositive Video IF Input AF3

RF_AGC/ TAGC

Analog O utput R F A G C /

Tun erA utom aticG ainControlO utput

AD4

PGA_CO M Analog Input V IF PG A N egative Source R7

Doc.No.:

2011 M Star Sem icond ucto r, Inc . A llri gh ts re s e rv e d .

1/25/2011

MSD6329SV

20120 1 0163

DVB Digita l T e l evision System -on-Chip

Preliminary P inDiagram /De scription an d Me chan ical D im ension s Version 0.2

Misc.Inter face

Pin N ame Pin Type Fun ction Pin

D D CA _DA/ U ART0_TX

DDCA_CK/ U ART0_RX

I/O w / 5 V -tol era nt D DC Da ta for A nalog p ort /

UniversalAsynchronous Transm itte r 0

I/O w / 5 V -tol erant DDC Clock for A n alog port /

UniversalAsynchronous Receiver 0

D D CDA _DA I/O w / 5V -tolerant H DC P SerialBus Data /DDC Data ofDVI/HDMIPortA Y6

D D CDA _CK Input w / 5V -toleran t HDC P SerialBus C lock / D D C ClockofDVI/HDMIPortA AB6

DDCDB_DA I/O w/5V-tolerant H DC P SerialBu s D ata / D D C Da ta of D VI/HD M I Port B A B5

DDCDB_CK Inputw/5V-tolerant H DC P S erialBu s C lock / D D C C lockofDVI/HDMIPortB AA5

D D CDC _DA I/O w / 5V -tolerant H DC P SerialBu s D ata / D D C Da ta of D VI/HD M I Port C Y5

D D CDC _CK Input w / 5V -toleran t HDC P SerialBus C lock / D D C ClockofDVI/HDMIPortC Y4

D D CDD _DA I/O w / 5V-tolerant H DC P SerialB us D ata / D D C Da ta o f D VI/H D M I P o rt D AC 4

D D CDD _CK Input w / 5V-tolerant H DC P S erialBus C lock / D D C C lockofDVI/HDMIPortD AB4

HOTPLUGA I/O w/5V-tolerant H ot-plug controlforDVI/HDMIPortA AE7

H O T PLU GB I/O w / 5V -tolerant H ot-plug controlfo r D VI/H D M I Po rt B Y7

HOTPLUGC I/O w/5V-tolerant H ot-plug controlforDVI/HDMIPortC AA4

HOTPLUGD I/O w/5V-tolerant H ot-plug controlforDVI/HDMIPortD AD6

D D C R _DA I/O w / 5V -toleran t D DC Da ta fo r R O M Y 26

D D C R _C K I/O w / 5V-tolerant D DC Clock for RO M Y25

XIN C rystalO scillator Inpu t CrystalO scillator Inpu t A C2

XO UT C rystalO scillator O utput C rystalO scillator O utput A C3

RTC_XOU T CrystalOscillator O u tput R TC 32KH z CrystalO utput D3

RTC_XIN CrystalOscillator Input RT C 32K H z C rystalInp ut D2

IR IN Input w / 5V-tolerant IR R eceiverInput M4

H W R ESET Schm ittTriggerInput w /

Hardware Reset;active high E1

5V-tolerant

BYP A SS For ExternalBypass Capacito r R 8

IF_AG C O utput w / 5V -tolerant IF AG C A C5

RF_AGC/ TAGC

O utput w / 5V -tolerant R F A G C /

Tun erA utom aticG ainControlO u tpu t

AD4

CEC I/O Consum er ElectronicsControl AF7

AV_LINK

BYP ASS_VCO RE

I/O

Output

AV Link

In tern al VCO R E Volta g e T e st ing Point

R21

Doc.No.:

1/25/2011

2011 M Star Sem icond ucto r, Inc . A llri gh ts re s e rv e d .

DVB Digita l T e l evision System -on-Chip

20120 1 0163

Preliminary P inDiagram /De scription an d Me chan ical D im ension s Version 0.2

Pow er Pins

Pin N ame Pin Type Fun ction Pin

AVDD _LP LL 3 .3V P ow er LPLL P ow er W 21

A V DD _D M PLL 3.3V P ow er CrystalPow er V8

A V DD _M PLL 3.3V Pow er M PLL Pow er V7

AVDD _ALIVE 3.3V Pow er Alive D om ainIO Power U8

AV DD _D VI_U SB 3.3V Pow er D VI U SB Pow er V4-V6

AV DD _EAR 33 3.3V Pow er Earphone D river Pow er U 9

A V DD _A U 33 3.3V P ow er Audio Pow er T9

AV DD _AD C25 2.5V Pow er V ideo AD C Pow er U 5, U6

AV DD _REF25 2.5V Pow er D em od AD C Pow er U 4

AV DD _M O D 33 3.3V Pow er M O D 3.3V Pow er T6

AV DD _PG A25 2.5V Pow er Dem od PG A Pow er T 7

AVDD _11 1.1V Pow er A nalog 1.1V Pow er W 20

AVDD _DD R0 1.5V Pow er D D R3 Pow er K1 6-K19,L17

MSD6329SV

AVDD _DD R1 1.5V Pow er D D R3 Pow er L18, L19,M 17,M 18,N 17

D V DD _DDR 1.1V Pow er D D R 1.1V Pow er U19,V 19

VD DP 3.3V Pow er D igitalInput/O utput Pow er Y22,Y 23

VDDC 1.1V Pow er D igitalCore Pow er T10,T 19,V14, V16,W 19,Y20,

AA20-AA23,AB22,AB23

G ND G round Ground A11-A 26,D 5,D 26, E6,E7,E26,F7,

F8, F12-F21, F26, G 8, G 9, G 12-G 2 1, G26,H8-H21,H26,J8-J21,J26,

K8-K15,K 20,K21,K26, L8-L16,L20, L21 , L26, M 8-M 16 , M 19-M 21, M 26, N 8-N 16,N 18-N 21, N 26,P8-P21,P2

R 9-R 20, R 2 6, T11-T18,T 2 0, T 21,

T26,U10,U12-U18,U20-U23,

V 9 -V 1 1 , V 2 0 -V 2 3 , W 9 - W 1 1 ,

W 13-W 18,W 22,W 23,Y19,AA 19

No Connects

Pin N ame Pin Type Fun ction Pin

NC No conn ect A2,B2,B3,C2,C3,D 1,R5,R6,T8,

U 7,U24,U 25,W 12,Y21,AB21,

A E5, AE6, AF 5, A F6

AD5 ,

Doc.No.:

1/25/2011

2011 M Star Sem icond ucto r, Inc . A llri gh ts re s e rv e d .

IC Block Diagram

U1(DUAL BTLCLASS D AUDIO AMPLIFIER) TAS5707

SDIN

MCLK

SCLK

LRCLK

SDA

SCL

Serial Audio

Port

Sample Rate

Autodetect

and PLL

Serial

Control

Terminal Control

7BQ

Microcontroller

Based System Control

mDAP

V O L U M E

DRC

Click and Pop

Control

S R C

4 Order Noise

Shaper

and

PWM

2HB´

FET Out

2HB´

FET Out

Protection

Logic

OUT_A

OUT_B

OUT_C

OUT_D

U4 ˄1.5V/5A˅AS1084R/TRͲLFADJUSTABLETOͲ252

U52 ǃU59˄5V/2A˅MP1494DJͲLFͲZTSOTͲ23Ͳ8



U18 ˄3.3V/5A˅AS1084RͲ3.3/TRͲLFTOͲ252



+ 49 hidden pages