Using PHYTEC FlashTools98 for Windows and the Raisonance
Integrated Development Environment (RIDE)
for 8051 and XA Demo Version
Note: The PHYTEC Spectrum CD includes the electronic version of
the English phyCORE-P8xC591 Hardware Manual
Hinweis: Die PHYTEC Spektrum CD beinhaltet die elektronische
Version des deutschen phyCORE-P8xC591 Hardware Manuals
Edition: July 2002
A product of a PHYTEC Technology Holding company
Page 2
phyCORE-P87C591 QuickStart Instructions
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•general information on the PHYTEC phyCORE-P87C591 Single
Board Computer (SBC)
•an overview of Raisonance’s Integrated Development
Environment (RIDE) for 51+XA, and
•instructions on how to run example programs on the
phCORE-P87C591, mounted on the PHYTEC phyCORE
Development Board LD 5V, in conjunction with RIDE for 51+XA
Please refer to the phyCORE-P8xC591 Hardware Manual for specific
information on such board-level features as jumper configuration,
memory mapping and pin layout. Selecting the links on the electronic
version of this document links to the applicable section of the
phCORE-P8xC591 Hardware Manual.
1.1 Rapid Development Kit Documentation
This “Rapid Development Kit” (RDK) includes the following
electronic documentation on the enclosed “PHYTEC Spectrum
CD-ROM”:
• the PHYTEC phyCORE-P8xC591 Hardware Manual and
phyCORE Development Board LD 5V Hardware Manual
• controller User'sManuals and Data Sheets
• this QuickStart Instruction with general “Rapid Development Kit”
description, software installation hints and three example programs
enabling quick out-of-the box start-up of the phyCORE-P87C591
in conjunction with the Raisonance Integrated Development
Environment (RIDE) for 51+XA
This QuickStart Instruction gives a general “Rapid Development Kit”
description, as well as software installation hints and three example
programs enabling quick out-of-the box start-up of the
phyCORE-P87C591 in conjunction with the Raisonance Integrated
Development Environment (RIDE) for 51+XA. It is structured as
follows:
1) The "Getting Started" section uses two example programs:
"Hello" and "Blinky" to demonstrate the download of user code
to the Flash device using PHYTEC FlashTools98 for Windows.
2) The "Getting More Involved" section provides step-by-step
instructions on how to modify both examples, create and build
new projects and generate and download output files to the
phyCORE-P87C591 using the Raisonance tool chain and
FlashTools98.
3) The "Debugging” section provides a third example
program - “Debug” - to demonstrate monitoring of the board and
simple debug functions using the Raisonance RIDE debug
environment.
In addition to dedicated data for this Rapid Development Kit, this
CD-ROM contains supplemental information on embedded
microcontroller design and development.
The phyCORE-P87C591 represents an affordable, yet highly
functional Single Board Computer (SBC) solution in subminiature
dimensions (40 x 55 mm). The standard board is populated with a
Philips P87C591 controller, featuring a 6-channel on-chip
A/D-converter with 10-bit resolution and an integrated
CAN controller.
All applicable data/address lines and applicable signals extend from
the underlying logic devices to standard-width (2.54 mm /0.10 in.) pin
headers lining the circuit board edges. This enables the
phyCORE-P87C591 to be plugged like a “big chip” into target
hardware.
The standard memory configuration of the phyCORE-P87C591
features 128 kByte external SRAM and 128 kByte external Flash for
code storage (64 kByte for FlashTools firmware and 64 kByte for
storage of user code). The Flash device allows direct on-board
programming. Three Chip Select signals are available for external
I/O connectivity.
The module communicates by means of an RS-232 transceiver and
operates within a standard industrial range of 0 to +70 degrees C. It
requires only a 250 mA power source.
PHYTEC FlashTools98 enables easy on-board download of user
programs.
The phyCORE Development Board LD 5V, in EURO-card
dimensions (160 x 100 mm), is fully equipped with all mechanical
and electrical components necessary for the speedy and secure
insertion, and subsequent programming, of PHYTEC
phyCORE series Single Board Computers with standard width
(2.54 mm/ 0.10 in.) pin header connectors. Simple jumper
configuration readies the Development Board’s connection to any
phyCORE module (standard header pins), which plug pins-down into
the contact strips mounted on the phyCORE Development
Board LD 5V.
phyCORE Development Board LD 5V Technical Highlights
• Reset signal controlled by push button or RS-232 control line
CTS0
• Boot signal controlled by push button or RS-232 control line
DSR0
• low voltage socket for supply with regulated input voltage 5 VDC
• additional supply voltage 3.3 VDC
• two DB-9 sockets (P1A, P1B) configurable as RS-232 interfaces
• two additional DB-9 plugs (P2A, P2B) configurable as
CAN interfaces, connector P2B optionally configurable as RS-485
interface
• simple jumper configuration allowing use of the
phyCORE Development Board LD 5V with various PHYTEC
phyCORE SBC’s
• one control LED D3 for quick testing of user software
• 2 x 160-pin Molex connector (X2) enabling easy connectivity to
1.5 The Raisonance Integrated Development Environment
(RIDE) for 51+XA
The Raisonance tool chain fully supports the entire Philips XA and
8051 derivative microcontroller families. It includes an ANSI-C
compiler, macroassembler, linker/locator, simulator/debugger and
ROM monitor/debugger within the RIDE development environment.
From the unique RIDE user interface projects can be developed for an
application based either on an 8051 derivative, a XA derivative, or
both. Such flexibility makes migrating from 8-bit to 16-bit
architectures easier.
The Raisonance tool chain produces OMF object files that are
supported by most in-circuit emulators. The OMF-to-HEX utility
converts a Raisonance .aof format file into an Intel hexfile that is
suitable for programming into the external Flash on the PHYTEC
phyCORE-P87C591 target board.
The Raisonance tool chain consists of the following tools; all
integrated in RIDE:
• C Compiler
• Assembler
• RTOS
• Linker/Locator
• Simulator/Debugger
• ROM Monitor
All these tools and many utility programs are available in two
versions: as Win32 DLL called internally from RIDE, and DOS-based
executables (*.exe) that can be called externally. These two versions
are strictly equivalent regarding the generated code.
The evaluation version of the RIDE development environment is
limited in manipulable code size as follows:
• 4 kByte for the 8051.
• 8 kByte for the XA.
Other than these restrictions, the evaluation tool chain functions
exactly as the full version does, enabling full evaluation of the
features and functionality of Raisonance development tools. This
demo version can be upgraded by entering a serial number.
Raisonance Integrated Development Environment (RIDE)
RIDE is a Windows-based Graphical User Interface for all
Raisonance tools. All compiler, assembler, linker/locator and
debugger options are configured with simple mouse clicks. RIDE runs
under Windows 95/98/2000 and NT.
All RIDE commands and functions are accessible via intuitive pulldown menus with prompted selections. An extensive help utility and
complete set of online manuals are included. External executables can
be run from within RIDE, including emulator software.
RC51 C Compiler
The RC51 compiler and MA51 assembler are designed specifically
for 8051 controllers.
The Raisonance RC51 compiler provides the fastest and smallest code
using industry benchmarks.
The Getting Started Guide from Raisonance provides more
information on these tools. It also includes an introduction on
RIDE includes a simulator/debugger and a ROM Monitor that
supports debugging either via software on a host-PC or in target
hardware. All the debugging functions are enabled in the demo
version with the same restrictions in manipulable code size as
follows:
What you will learn with this Getting Started example:
• installing Rapid Development Kit software
• starting PHYTEC FlashTools98 for Windows download utility
• interfacing the phyCORE-P87C591, mounted on the
phyCORE Development Board LD 5V, to a host-PC
• downloading example user code in Intel hexfile format from a
host-PC to the external Flash memory using FlashTools98
2.1 Installing Rapid Development Kit Software
• Insert the PHYTEC Spectrum CD into the CD-ROM drive of your
host-PC.
The PHYTEC Spectrum CD should automatically launch a setup
program that installs the software required for the Rapid Development
Kit as specified by the user. Otherwise the setup program start.exe
can be manually executed from the root directory of the PHYTEC
Spectrum CD.
• After accepting the Welcome window and license agreement,
select the destination location for installation of Rapid
Development Kit software and documentation.
The default destination location is C:\PHYBasic. All path and file
statements within this QuickStart Instruction are based on the
assumption that you accept the default install paths and drives. If you
decide to individually choose different paths and/or drives you must
consider this for all further file and path statements.
We recommend that you accept the default destination location.
• In the next window, select your Rapid Development Kit of choice
from the list of available products. By using the Change button,
advanced users can select in detail which options should be
installed for a specific product.
All Kit-specific content will be installed to a Kit-specific subfolder of
the Rapid Development Kit root folder that you have specified at the
beginning of the installation process.
All software and tools for this phyCORE-P87C591 RDK will be
installed to the \PHYBasic folder on your hard drive.
• In the next dialog you must choose whether to copy the selected
documentation as *.pdf files to your hard drive or to install a link
to the file on the Spectrum CD.
If you decide not to copy the documentation to your hard drive, you
will need the PHYTEC Spectrum CD-ROM each time you want to
access these documents. The installed links will refer to your
CD-ROM drive in this case.
If you decide to copy the electronic documentation to your hard drive,
the documentation for this phyCORE-P87C591 RDK will also be
installed to the kit-specific subfolder. The manuals of the
phyCORE Development Board LD 5V are copied to their own
specific subfolder (e.g.\PHYBasic\DevBLD5V) because each
Development Board is suitable for multiple SBC’s and is not
dedicated to a specific RDK.
Setup will now add program icons to the program folder, named
PHYTEC.
• Click on Finish to complete the installation of PHYTEC products.
• In the next window, choose to install the Raisonance Software
Development tool chain for 51 + XA
1
.
The applicable Raisonance tool chain must be installed to ensure
successful completion of this QuickStart Instruction. Failure to install
the proper software could lead to possible version conflicts, resulting
in functional problems.
We recommend that you install the Raisonance tool chain from the
Spectrum CD-ROM even if other versions of RIDE is already
installed on your system. These QuickStart Instructions and the demo
software included on the CD-ROM have been specifically tailored for
use with one another.
• After accepting the Welcome window and license agreement,
select the destination location for installation of the Raisonance
tool chain. The default location is C:\Ride.
1
:If installing a different software development tool chain, please refer to the applicable
The applicable Raisonance Software Development tool chain for
51+XA will be installed to your hard drive. Additional software, such
as Adobe Acrobat Reader, will also be offered for installation.
In the following windows you can decide to install FlashTools98
software and the Acrobat Reader.
The applicable FlashTools software must be installed to ensure
successful completion of this QuickStart Instruction. Failure to install
the proper software could lead to possible version conflicts, resulting
in functional problems.
This sequence of pressing and releasing the Reset (S2) and Boot (S1)
button renders the phyCORE-P87C591 into the Flash programming
mode (FPM). Use of FlashTools98 always requires the
phyCORE-P87C591 to be in FPM. See section 2.4,“DownloadingExample Code with FlashTools” for more details.
The phyCORE module should now be properly connected via the
phyCORE Development Board LD 5V to a host-PC and power
supply. After executing a Reset and rendering the board in Flash
programming mode, you are now ready to program the
phyCORE-P87C591. This phyCORE module/phyCORE Development
Board LD 5V combination is also referred to as “target hardware”.
2.3 Starting PHYTEC FlashT ools98 for Windows
FlashTools98 should have been installed during the initial setup
procedure as described in section2.1. If not, you can manually install
it using the setup.exe file located in the \Software\Flasht98\ folder of
your PHYTEC Spectrum CD.
FlashTools98 for Windows is a utility program that allows download
of user code in Intel *.hex file format from a host-PC to a PHYTEC
SBC via an RS-232 connection.
FlashTools98 consists of firmware resident in the external Flash and
corresponding software installed on the host-PC. Proper connection of
a PHYTEC SBC to a host-PC enables the software portion of
FlashTools98 to recognize and communicate to the firmware portion.
• You can start FlashTools98 by selecting it from the Programs
menu using the Window s Start button.
It is recommended that you drag the FlashTools98 icon onto the
desktop of your PC. This enables easy start of FlashTools98 by
double-clicking on the icon.
The microcontroller firmware tries to automatically adjust to the baud
rate selected within the baud rate tab. However, it may occur that the
selected baud rate can not be attained. This results in a connection
error. In this case, try other baud rates to establish a connection.
Before attempting each connection, be sure to reset the target
hardware and render it into Flash programming mode (FPM) as
described in section 2.2.
Returning to the FlashTool98 tabsheet window, you will see tabs for
the following:
Bank Utilities
2
enable erasure and status check of whole banks of
memory specified by the user:
2
:The number of banks shown on the Bank Utilities tabsheet varies depending on the size and
enable erasure and status check of individual sectors
of Flash memory specified by the user:
2.4.1 "Blinky"
The “Blinky” example downloads a program to the Flash that, when
executed, manipulates the LED D3 on the phyCORE Development
Board LD 5V that is located above the jumper field
(refer to Figure 2).
• Returning to the FlashTools98 tabsheet, choose the Bank Utilities
tab, highlight Bank #1 within the BankErase section, and click on
the Erase Bank(s) button to erase this memory bank.
• Wait until the status check in the lower left corner of the
FlashTools98 tabsheet finishes, returning the connection
properties description to the lower left corner of the window.
• Next choose the File Download tab and click on the File Open
button.
4
:The appearance of the Sector Utilities tabsheet varies depending on the size and type of the
• Click on the Download button. You can watch the status of the
download of the Blinky.hex into the external Flash memory in the
Download window.
If the selected Flash bank into which you wish to download code is
not empty (i.e. erased), a warning dialog box will appear,
indicating “Location not empty! Please erase location and try
again”. In this event, select the Bank Utilities tab from the
FlashTools98 tabsheet, highlight Bank #1 and erase the bank. Then
repeat the download procedure.
• At the end of the download, a sector-by-sector status check of the
Flash memory can be viewed in the lower left corner of the
FlashTools98 tabsheet window. Wait until the status check
finishes before returning to work with the board. Once the status
check is complete, the downloaded code can be executed.
• Returning to the Communication tab, click on the Disconnect
• Press the Reset button (S2) on the phyCORE Development
Board LD 5V to reset the target hardware and to start execution of
the downloaded software.
• Successful execution of the program will flash the LED D3 with
equal on and off durations.
2.4.2 "Hello"
The “Hello” example downloads a program to the Flash that, when
executed, performs an automatic baud rate detection and sends a
character string from the target hardware back to the host-PC. The
character string can be viewed with a terminal emulation program.
This example program provides a review of the FlashTools98
download procedure. For detailed commentary on each step,
described below in concise form, refer back tosections 2.2through 2.4.1.
• Ensure that the target hardware is properly connected to the
host-PC and a power supply.
• Reset the target hardware and force it into Flash programming
mode by simultaneously pressing the Reset (S2) and Boot (S1)
buttons on the phyCORE Development Board LD 5V and then
releasing first the Reset and, two or three seconds later, the Boot
button.
• Start FlashTools98.
• At the Communication Setup tab of the FlashTools98 tabsheet,
specify the proper serial port and transmission speed (9,600 baud)
for communication between host-PC and target hardware and click
the Connect button to establish connection to the target hardware.
• Returning to the FlashTools98 tabsheet, choose the Bank Utilities
tab, highlight Bank #1 within the BankErase section, and click on
the Erase Bank(s) button to erase this memory bank.
• Wait until the status check in the lower left corner of the
FlashTools98 tabsheet finishes, returning the connection
properties description to the lower left corner of the window.
• Next choose the File Download tab and click on the File Open
• Click on the Download button. You can watch the status of the
download of the Hello.hex into the external Flash memory in the
Download window.
If the selected Flash bank into which you wish to download code is
not empty (i.e. erased), a warning dialog box will appear,
indicating “Location not empty! Please erase location and try
again”. In this event, select the Bank Utilities tab from the
FlashTools98 tabsheet, highlight Bank #1 and erase the bank. Then
repeat the download procedure.
• At the end of the download, a sector-by-sector status check of the
Flash memory can be viewed in the lower left corner of the
FlashTools98 tabsheet window. Wait until the status check
finishes before returning to work with the board. Once the status
check is complete, the downloaded code can be executed.
• Returning to the Communication tab, click on the Disconnect
• Selecting OK advances you to the COM Direct–HyperTerminal
monitoring window. Notice the connection status report in the
lower left corner of the window.
• Resetting the phyCORE Development Board LD 5V (at S2) will
execute the Hello.hex file loaded into the Flash.
• Now push the <Space> bar on your keyboard once to start the
automatic baud rate detection on phyCORE -P87C591 module.
• Successful execution will send the character string "Hello World"
from the target hardware to the HyperTerminal window.
Pressing any other key than the <Space> bar leads to an improper
baud rate since the automatic baud rate detection is based on the
timing measurement during the transmission of a well known
character – the <Space> character. As a result you may get
incoherent characters in the HyperTerminal window.
• Click the disconnect icon in HyperTerminal toolbar and exit
HyperTerminal.
• If no output appears in the HyperTerminal window check the
power supply, the COM parameters and the RS-232 connection.
You have now successfully downloaded and executed two
pre-existing example programs in Intel *.hex file format.
• how to configure the Raisonance tools within the Integrated
Development Environment (RIDE) for 51+XA demo version
• how to modify the source code from our examples, create a new
project and build and download an output * .hex file to the target
hardware
3.1 Starting the Raisonance Tool Chain
The Raisonance Integrated Development Environment (RIDE) for
51+XA demo software should have been installed during the install
procedure, as described in section2.1.
Getting More Involved
You can also manually install the tool chain by executing install.exe
from within the \Software\Raisonance folder of your PHYTEC
Spectrum CD.
Note:
It is necessary to use the Raisonance tool chain provided on the
accompanying Spectrum CD in order to complete this QuickStart
Instructions successfully. Use of a different version could lead to
possible version conflicts, resulting in functional problems.
•Start the tool chain by selecting Ride IDE from within the
Programs|Raisonance Kit program group.
After you start RIDE, the window shown below appears. From this
window you can create projects, edit files, configure tools, compile,
assemble, link and debug.
3.2 Creating a New Project and Adding an Existing Source
File
RIDE automatically loads the most recently opened project. If you
find an existing project when starting RIDE, close it by selecting the
Project menu and Close the project.
•To create a new project file open the Project menu and choose
New within the RIDE menu bar. The window as shown below
• The source file blinky2.c is now open within the RIDE editor. If
you closed the file, double click on the reference inside the project
tree.
• Locate the following code section. Modify the section shown
below (the values shown in bold and italic font) from the original
counts to the indicated values:
while (1) /* loop forever */
{
LED = LED & 0xFE; /* output over PD port to LED D3 */
/* Bit 1 of port PD = LED D3 = off*/
for (i=0; i<
{
wait (); /* call wait function */
}
LED = LED | 0x01; /* output over PD port to LED D3 */
/* Bit 1 of port PD = LED D3 = on */
for (i=0; i<
{
wait (); /* call wait function */
}
} /* end of while(1) */
} /* EOF */
30000
40000
; i++) /* delay for 30000 counts */
; i++) /* delay for 40000 counts */
This will change the LED on/off ratio.
3.4 Saving the Modifications
•Save the modified file by choosing File|Save or by clicking the
Raisonance tools include a Make utility that controls compiling and
linking of various source files. Before using the macro preprocessor,
assembler, C compiler or linker/locator, you must configure the
corresponding options. Enter the changes as indicated below and
leave all other options set to their default values. RIDE allows you to
set various options with mouse clicks and these are all saved in your
project file.
Note:
In most cases, options can be set at the project level. However,
specific local options sometimes have to be set up differently when a
file or a group of files require special options. In this case, a popup
menu allows you to specify options at the level of the node.
Getting More Involved
To configure the Target:
• Open the Options|Target menu and select the 8xC591 as shown
You are now ready to run the compiler and linker using the Make
utility.
• Click on the ‘Make All’ Command iconfrom the RIDE
toolbar or open the Project menu and select Build All or Make All.
If the program specified (Blinky2.c) contains any errors, they will be
shown in the Message Window at the bottom of the screen.
If there are no errors, the code is compiled and linked and the
executable code is ready to be downloaded to the module. The created
hexfile will have the name of the project with .hex as the filename
extension (in this case Blinky2.hex).
Note:
A machine-readable, executable hexfile has been created. Other files
(e.g. list files *.lst and map files *.m51) are generated to help the
debugging or troubleshooting and error searching process.
• If a list of errors appears, double-click on the error to open the file
and locate the error. Use the editor to correct the error(s) in the
source code and (re-)build the project.
• Reset the target hardware and force it into Flash programming
mode by simultaneously pressing the Reset (S2) and Boot (S1)
buttons on the phyCORE Development Board LD 5V and then
releasing first the Reset and, two or three seconds later, the Boot
button.
• Start FlashTools98.
• At the Communication Setup tab of the FlashTools98 tabsheet,
specify the proper serial port and transmission speed (9,600 Baud)
for communication between host-PC and target hardware and click
the Connect button to establish connection to the target hardware.
• Returning to the FlashTools98 tabsheet, choose the Bank Utilities
tab, highlight Bank #1 within the BankErase section, and click on
the Erase Bank(s) button to erase this memory bank.
Getting More Involved
• Wait until the status check in the lower left corner of the
FlashTools98 tabsheet finishes, returning the connection
properties description to the lower left corner of the window.
• Next choose the File Download tab and click on the File Open
button.
• Browse to the correct drive and path for the phyCORE-P87C591
A return to the “Hello” program allows a review of how to modify
source code, create and build a new project, and download the
resulting output file from the host-PC to the target hardware. For
detailed commentary on each step, described below in concise form,
refer back to the “Blinky2” example starting at section 3.2.
3.8.1 Creating a New Project
•Start the Raisonance RIDE environment and close all projects that
might be open.
•Open the Project menu and create a new project called Hello2.prj
within the existing project folder
C:\PHYBasic\pC-P87C591\Demos\Raisonance\Hello2
(default location) on your hard-drive. Select the 80C51
architecture for this project.
•Add Hello2.c and Serinit.c from within the project folder to the
project Hello2.prj.
•Save the project.
At this point you have created a project called Hello2.prj consisting
of the C source files Hello2.c and Serinit.c.
• Reset the target hardware and force it into Flash programming
mode by simultaneously pressing the Reset (S2) and Boot (S1)
buttons on the phyCORE Development Board LD 5V and then
releasing first the Reset and, two or three seconds later, the Boot
button.
• Start FlashTools98.
• At the Communication Setup tab of the FlashTools98 tabsheet,
specify the proper serial port and transmission speed (9,600 baud)
for communication between host-PC and target hardware and click
the Connect button to establish connection to the target hardware.
• Returning to the FlashTools98 tabsheet, choose the Bank Utilities
tab, highlight Bank #1 within the BankErase section, and click on
the Erase Bank(s) button to erase this memory bank.
• Wait until the status check in the lower left corner of the
FlashTools98 tabsheet finishes, returning the connection
properties description to the lower left corner of the window.
• Next choose the File Download tab and click on the File Open
button.
• Browse to the correct drive and path for the phyCORE-P87C591
This Debugging section provides a basic introduction to the debug
functions included in the Raisonance RIDE tool chain. Using an
existing example, the more important features are described. For a
more detailed description of the debugging features, please refer to
the appropriate manuals provided by Raisonance.
The Raisonance RIDE integrated debugger offers two operating
modes that can be selected in the Options\Project\LX51\ROM-Monitor and Options\Debug dialog:
• The Simulator allows PC-based microcontroller simulation of
most features of the 8051 microcontroller family without actually
having target hardware. You can test and debug your embedded
application before the hardware is ready. RIDE simulates a wide
variety of peripherals, including the serial port, external I/O, and
timers.
Debugging
• The Real Mode, using either the Raisonance ROM monitor or an
In-Circuit Emulator, allows target-based debugging. When using
the ROM monitor, the debugger communicates with the target
hardware via a monitor kernel that is running on the target system.
The following examples utilize the Real Mode/ROM monitor
interface.
Note:
Use of the monitor program requires protection (reservation) of some
controller resources, such as the serial interface, the serial interrupt
and timer 1. These resources are necessary to allow communication
between the monitor program on the target hardware and the RIDE
Debugger (refer to the Raisonance manuals for further information ).
Do not use these resources when developing an application program
to be debugged using the ROM monitor interface.
Before using the ROM monitor interface, a special *.hex file (the
monitor loader firmware) must be downloaded to the target hardware.
4.1 Preparing the Target Hardware to Communicate with
ROM Monitor
• Ensure that the target hardware is properly connected to the
host-PC and a power supply.
• Reset the target hardware and force it into Flash programming
mode by simultaneously pressing the Reset (S1) and Boot (S2)
buttons on the Development Board and then releasing first the
Reset and, two or three seconds later, the Boot button.
• Start FlashTools98 for Windows.
• At the Serial Interface tab of the FlashTools98 tabsheet, specify
the proper serial port and transmission speed for communication
between host-PC and target hardware and click the Connect button
to establish connection to the target hardware.
• Returning to the FlashTools98 tabsheet, choose the Bank Utilities
tab, highlight Banks #1 and click on the Erase Bank(s) button.
• Next choose the File Download tab and click on the File Open
button.
•Download the file load51.hex from the Tools folder
C:\PHYBasic\pC-P87C591\Tools\Raisonance\Loader
(default location).
The PHYTEC Spectrum CD-ROM also contains the loadxa.hex
monitor file. This version is made for XA-compatible phyCORE
modules. Please refer to readme files within the Loader directory
for details.
• Click on the Download button and view the download procedure
in the status window.
If download is successful, the loader kernel has been programmed
into the external Flash memory. The target hardware is now prepared
to communicate with the Raisonance RIDE debugging tools installed
on the host-PC.
• Disconnect from the target hardware after the download has
finished either by clicking the Disconnect button on the
Communication Setup tabsheet or choosing the
Connect|Disconnect icon from the FlashTools98 toolbar.
• Exit FlashTools98.
4.2 Creating a Debug Project and Preparing the Debugger
4.2.1 Creating a New Project
•Start the RIDE environment and close all projects that might be
open.
•Open the Project menu and create a new project called Debug.prj
within the existing project folder
C:\PHYBasic\pC-P87C591\Demos\Raisonance\Debug
(default location) on your hard-drive. Select the 80C51
architecture for this project.
Debugging
•Add Debug.c and Serinit.c from within the project folder to the
project Debug.prj.
•Save the project.
At this point you have created a project called Debug.prj, consisting
of two C source files called Debug.c and Serinit.c.
When setting the memory configuration, the memory layout necessary
for the monitor must be taken into consideration.
The standard 8051 controller uses a Harvard memory architecture. In
this architecture, access to CODE and XDATA memory space goes to
physically different memory devices. Normally, for access to CODE
space, a non-volatile memory is utilized, i.e. ROM or Flash. For
access to XDATA space, a RAM is used. Using this memory model
with an 8051 derivative allows access to up to 64 kByte of memory
for CODE and 64 kByte for XDATA.
When debugging with the Raisonance monitor, it is important that the
user program (CODE) can be changed during runtime (e.g. to enable
setting of breakpoints). This requires the user program to be stored in
RAM and not in Flash. In order to ensure that the user program is
running in RAM, the monitor loader automatically configures a von
Neumann memory architecture in the address range 0000H-EFFFH
after reset. Here, in contrast to the Harvard architecture, access to
CODE and XDATA space is directed towards the same physical
memory device, normally RAM. With this von Neumann memory
architecture, it is now possible to change the application program
during runtime.
The following figure (see Figure 4) depicts the memory layout that is
configured by the Raisonance monitor for 64 kByte RAM.
XDATA access
Debugging
von Neumann
I/O Area (for details see Hardware Manual)
von Neumann XDATA portion of target
Monitor firmware (loader51.hex)
RAM for :
------------application CODE and XDATA
(monitor* CODE and XDATA)
(*included in application)
IO-AREA (PLD & /CS1..CS3
Read-Write (RAM)
FFFFH
FC00H
FBFFH
F000H
EFFFH
0000H
Figure 4:Memory Model for Use with the Raisonance Monitor
(64 kByte RAM)
Note:
When using the von Neumann memory architecture, ensure that the
CODE and XDATA areas within the application program do not
overlap. This is important because otherwise portions of the program
(CODE) will be overwritten by e.g. variables (XDATA), resulting in
an error when executing user code.
• Open the Options|Project\LX51 menu and choose Linker.
• Check that the Generate an Intel Hex file checkbox is disabled.
This option should be enabled by default.
Debugging
The memory ranges for off-chip CODE and off-chip XDATA
memory are configured to fit within the von Neuman memory space
as configured by the the Raisonance load51.hex monitor file (refer toFigure 4).
• In the Options|Project\LX51 menu now choose ROM-Monitor.
Activate the checkbox Use the ROM-Monitor, select the Standard
UART radio button, a Crystal Frequency of 12.000 MHz and a
Communication Baud Rate of 9600. Make sure the checkbox
Microcontroller without clock prescaler (P8xC591 like) is
enabled.
• Click on OK to save these settings.
• The linker/locator options are now suitable for the Debug project,
enabling you to build an absolute object file (*.aof).
• Click on the ‘Make All’ Command iconfrom the RIDE
toolbar or open the Project menu and select Build All or Make All.
• Click on the Real Machine button and select 80C51ROM-Monitor
as shown below:
Debugging
• Click on the Advanced Options button to specify additional
debugging options. Make sure that the 8xC591 is selected in the
microcontroller pull-down menu. Select the correct COM port and
baud rate in both the Loading Port and the Communication Port
menus as shown in the screen capture on the following page. Make
sure XEVA is selected as Loader protocol.
• The maximum code and data size that can be configured in the
memory selection section is 60 kB. This is because the monitor
loader code itself is located at address F000H. In addition, the I/O
area of the phyCORE module occupies the memory range between
FC00H and FFFFH. These memory areas can not be used by the
application code.
• Click on the OK button to exit the ROM-Monitor Options window.
If the data transfer was successful, a screen similar to the one shown
below will appear. The Project window changed to the Debugger
page. The debug toolbar is also displayed. In the lower part of the
debug screen you will see the Command and Watch window. The
Xdata window is shown in the lower right section of the screen.
Debugging
You may need to open, resize and /or move some windows to make
your screen look similar to the screen capture. You can open inactive
windows by choosing the desired window from the View pull-down
menu.
• The debugger will automatically run to the ‘main’ function and
• The Debugger toolbar gives access to the following debug
commands: Reset, Go, Stop, Step Into, Step Over, Step Out andRun to Cursor line.
• RIDE uses Step (into function calls) to single step one line at a
time. Step (into function calls) is also used to enter a function in
the same fashion. Depending on the current window
(either Disassembly or Source), the meaning of “Stepping” will be
slightly different, and automatically adapted to the context. In a
Source window, stepping will be performed at the source level
(e.g. line to line). In a Disassembly window, stepping will be
performed at the instruction level. To Step into, click on the
button, or press <F7>, or open the Debug | Step Into menu.
•Step (over function calls) means to skip over a function that you
are not interested in. To Step over, click on thebutton,
or press <F8>, or open the Debug | Step Over menu.
• To reach the cursor location, open the Debug | Run to menu.
• You can reset the application by clicking on the Reset
application button in the debug toolbar. The program will arrive
at main() when the Reset is performed from a Source window,
or at the reset vector if it is performed from the Code disassembly
window.
• The Goicon will change into a Stop icon during the
program execution.
Clicking the Go icon runs the program without active debug
functions. To stop program execution at a desired point, a
breakpoint can be placed before the Go icon is clicked.
The Stop icon interrupts and stops the running program at an
undetermined location.
•The Watch window now shows the constant "rhythm[]". The
smallsign in front of rhythm indicates that this is an array
with a group of array elements. Click thesign to expand the
view and to see all array elements of "rhythm[]".
4.6.2 Run to ...
• The Run to... command executes the program until it reaches the
code line where the cursor is currently located. Go with the cursor
to the code line led(1);.
4.8 Changing Target Settings for the "Final Version"
After successfully debugging the program, next change the target
settings in order to create an Intel hexfile. This can then be
downloaded to the Flash mem ory of the phyCORE-P87C591.
•Open the Options|Targetmenu and select the Harvard
architecture as shown below:
Debugging
• Click on OK to save this setting.
• Open the Options|Project|RC51 menu and choose Defines. Delete
the MONITOR5 1 define in the Defines input field. This will
include various printf statements in the application program that
can be viewed with a terminal emulation program. Use of the
printf statements is now possible because the serial interface is no
longer required for other communication tasks.
• Click on OK to save this setting.
• Open the Options|Project\LX51 menu and choose Linker.
• Enable the Generate an Intel Hex file checkbox.
• In the Options|Project\LX51 menu disable the checkbox ROM-
Monitor.
• The linker/locator options are now suitable for the Debug project,
enabling you to build an absolute object file (*.aof) and a hexfile.
• Click on the ‘Make All’ Commandiconfrom the RIDE
toolbar or open the Project menu and select Build All or Make All.
C:\PHYBasic\pC-P87C591\Demos\Raisonance\Debug) to the
Flash memory. For general download procedure information refer
to sections 2.2 through 2.4.
• Press the Reset button S2 on the Development Board to start the
program.
• The application is now waiting for receipt of a known character
over the serial interface. Start the HyperTerminal program and
push the <Space> bar as described in section 2.4.2. This starts the
automatic baud rate detection. Now you can watch your final
debug example execute.
This section provides advanced information for successful operation
of the phyCORE-P87C591 in conjunction with the Raisonance tools.
5.1 FlashTools98
Flash is a highly functional means of storing nonvolatile-data. One of
its advantages among many others is the possibility of on-board
programming. Programming tools for the Flash device are always
included with the phyCORE-P87C591 in the form of a
pre-programmed Flash with a resident microcontroller firmware and a
counterpart software serving as the user interface on a host-PC. Once
the firmware communicates with the PC-based software,
FlashTools98 allows the download of user code from the host-PC into
the Flash. Additionally, the re-programmable Flash device on the
phyCORE-P87C591 allows you to easily update your own code and
the target application in which the phyCORE-P87C591 has been
implemented.
Advanced User Information
Currently the phyCORE-P87C591 can be populated by two different
sized Flash devices: a 29F010 with 128 kByte or a 29F040 with
512 kByte. To support the entire memory area of these devices the
address decoder of the phyCORE-P87C591 is equipped with an
integrated banking mechanism that allows code-bank switching in
code-banks of 64 kByte each.
Please note that the FlashTools98 kernel always occupies the first
64 kByte bank (bank 0, FA[18..15] = 0000b) of the Flash memory.
This bank is pre-programmed upon delivery of the
phyCORE-P87C591. The remaining banks are available to house your
application. This makes one user application bank available if the
phyCORE-P87C591 is mounted with a 29F010 and seven user
application banks if the phyCORE-P87C591 is mounted with a
29F040 Flash memory device. Multiple user application banks can
easily be managed by using the Code Banking mechanism of the
Raisonance tool chain.
The following description is valid only for the FlashTools98 included
with the phyCORE-P87C591 and is not intended as a guideline for
using any other program.
FlashTools98 incorporates a safety mechanism that ensures that the
system bank (bank 0), in which the firmware is resident, can not be
overwritten during programming of the available user banks of the
Flash device.
Resetting the phyCORE-P87C591 also activates the system bank
(bank 0) of the Flash device, which automatically starts the
FlashTools98 firmware. Then the firmware either enters the Flash
programming mode or starts your user application.
To distinguish between download and execution modes, the firmware
latches the /BOOT signal after reset (/BOOT=0 => start Flashtools,
/BOOT=1 => start user program). This signal can be set to a low level
by pressing the Boot (S1) button located on the
phyCORE Development Board LD 5V. To enter the Flash
programming mode you must simultaneously press the Reset (S2) and
the Boot (S1) button, release the Reset (S2) button first and then, two
to three seconds later, release the Boot (S1) button.
Execution of your user application will always start in the second
64 kByte bank (bank 1, FA[18..15] = 0010b). This is to be noted
when preparing a software copy of the contents of the address
decoder’s internal write-only registers.
The extended features of the address decoder on the
phyCORE-P87C591 allows flexibility when configuring the memory
model according to your needs and addressing additional Flash banks.
Do not use Flash bank 0 in your application program in order to
preserve the FlashTools98 microcontroller firmware and the
associated Flash re-programming capability.
The Linker must combine several relocatable object modules
contained in object files and/or libraries to generate a single absolute
object.
In addition, the linker must locate several segments of code and data
to fixed address locations within the address space in regards to the
memory types of the phyCORE-P87C591. XDATA segments always
must be located to Random Access Memory (e.g. RAM), CODE
segments should be located to non-volatile memory (e.g. Flash). The
8051 family supports a Harvard memory architecture that
distinguishes between non-volatile and randomly accessible memory
and has two physically different signals for separate fetching of data
and code.
Advanced User Information
The Raisonance tool chain distinguishes the following segment ty pes:
• CODE:code
• XDATA:external data (max. 64 kByte)
• DATA:direct addressable on-chip data (max. 128 Byte)
• IDATA:indirect addressable on-chip data (max. 256 Byte)
• BIT:bit-addressable on-chip data (max. 128-bits)
The segment types DATA, IDATA and BIT always reside in the
on-chip RAM of the controller.
The segment types XDATA and CODE will usually reside in external
memory devices.
To ensure proper execution of your application, it is required that all
XDATA segments are located to the external RAM of the
phyCORE-P87C591 and that all CODE segments are located to the
external Flash memory of the phyCORE-P87C591. Exceptions may
occur if you use a 8051 derivative with on-chip portions of XDATA
(e.g. internal XRAM) or CODE (e.g. internal ROM).
Since the phyCORE-P87C591 is equipped with a software
configurable address decoder instead of simple programmable logic
device, you can configure the memory model to your needs at
runtime.
To ensure proper execution of your application, you must take the
runtime memory model into consideration when linking and locating.
This means that you must instruct the linker where to assume external
RAM for locating data segments and Flash for locating code
segments.
The standard configuration of the phyCORE-P87C591 is equipped
with 128 kByte of external RAM and 128 kByte of external Flash.
During runtime the RAM will be addressable at 0x0000 to 0xFFFF.
The user bank (bank 1, FA[18..15] = 0010b) will be addressable at
0x0000 to 0xFFFF. This default runtime memory model requires no
additional linker settings because both RAM and Flash start at
0x0000. This is also the default start address of the linkers segment
types.
Since you can not define any end address, you should always ensure
that the size of the segments fits within the available size of the
mounted memory devices. For instance all XDATA segments should
end below 0x7FFF if a 32 kByte RAM device mounted on the
phyCORE-P87C591. We recommend generation of a *.m51 map file
for your project and inspection of the memory map informa tion within
this file.
Whenever you modify the memory model (e.g. use von Neumann
rather than Harvard memory), which leads to different start addresses
of CODE or XDATA memory, you must configure this in the linker
settings.