Philips (Now NXP) 2N7002K Schematic [ru]
M3D088
1. Product profile
1.1 Description
1.2 Features
1.3 Applications
2N7002K
TrenchMOS™ logic level FET
Rev. 01 — 20 October 2003 Product data
N-channel enhancement mode field-effect transistor in a plastic package using
TrenchMOS™ technology.
■ Logic level compatible ■ Very fast switching
■ Subminiature surface mount package ■ Gate-source ESD protection diodes.
■ Relay driver ■ High speed line driver.
1.4 Quick reference data
■ VDS≤ 60 V ■ ID≤ 340 mA
■ P
≤ 0.83 W ■ R
tot
DSon
2. Pinning information
Table 1: Pinning - SOT23, simplified outline and symbol
Pin Description Simplified outline Symbol
1 gate (g)
2 source (s)
3 drain (d)
12
Top view
3
MSB003
SOT23
≤ 3.9 Ω.
d
g
03ab60
s
Philips Semiconductors
2N7002K
TrenchMOS™ logic level FET
3. Ordering information
Table 2: Ordering information
Type number Package
Name Description Version
2N7002K SOT23 Plastic surface mounted package; 3 leads. SOT23
4. Limiting values
Table 3: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
DS
V
DGR
V
GS
I
D
I
DM
P
tot
T
stg
T
j
Source-drain diode
I
S
I
SM
Electrostatic discharge voltage
V
esd
drain-source voltage (DC) 25 °C ≤ Tj≤ 150 °C - 60 V
drain-gate voltage (DC) 25 °C ≤ Tj≤ 150 °C; RGS=20kΩ -60V
gate-source voltage (DC) - ±15 V
drain current (DC) Tsp=25°C; VGS=10V;Figure 2 and 3 - 340 mA
= 100 °C; VGS=10V;Figure 2 - 215 mA
T
sp
peak drain current Tsp=25°C; pulsed; tp≤ 10 µs; Figure 3 - 680 mA
total power dissipation Tsp=25°C; Figure 1 - 0.83 W
storage temperature −65 +150 °C
junction temperature −65 +150 °C
source (diode forward) current (DC) Tsp=25°C - 340 mA
peak source (diode forward) current Tsp=25°C; pulsed; tp≤ 10 µs - 680 mA
electrostatic discharge voltage Human Body Model 1; C = 100 pF; R = 1.5 kΩ -1kV
9397 750 11703
Product data Rev. 01 — 20 October 2003 2 of 12
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Philips Semiconductors
2N7002K
TrenchMOS™ logic level FET
120
P
der
(%)
80
40
0
0 50 100 150 200
P
tot
P
der
-----------------------
P
tot 25 C°()
100%×= I
03aa17
Tsp (°C)
Fig 1. Normalized total power dissipation as a
function of solder point temperature.
1
(A)
Limit R
I
D
DSon
= VDS/ I
D
120
I
der
(%)
80
40
0
0 50 100 150 200
I
D
der
-------------------
I
D25C
()
100%×=
°
03aa25
Tsp (°C)
Fig 2. Normalized continuous drain current as a
function of solder point temperature.
03an66
tp = 10 µs
100 µs
-1
10
DC
-2
10
1 10 10
1 ms
10 ms
100 ms
VDS (V)
2
Tsp=25°C; IDM is single pulse; VGS=10V
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.
9397 750 11703
Product data Rev. 01 — 20 October 2003 3 of 12
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Philips Semiconductors
2N7002K
TrenchMOS™ logic level FET
5. Thermal characteristics
Table 4: Thermal characteristics
Symbol Parameter Conditions Min Typ Max Unit
R
th(j-sp)
R
th(j-a)
thermal resistance from junction to solder point Figure 4 - - 150 K/W
thermal resistance from junction to ambient minimum footprint;
- 350 - K/W
mounted on a printed-circuit board
5.1 Transient thermal impedance
3
10
Z
th(j-sp)
(K/W)
2
10
10
1
= 0.5
δ
0.2
0.1
0.05
0.02
single pulse
-5
10
-4
10
-3
10
-2
10
-1
10
P
t
p
T
1 10
tp (s)
Fig 4. Transient thermal impedance from junction to solder point as a function of pulse duration.
δ =
03aa39
t
p
T
t
9397 750 11703
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data Rev. 01 — 20 October 2003 4 of 12
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