Philips XA-G49 Datasheet

INTEGRATED CIRCUITS

XA-G49

XA 16-bit microcontroller family

64K FLASH/2K RAM, watchdog, 2 UARTs

Preliminary specification Supersedes data of 1999 Jun 15 IC28 Data Handbook

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2000 Apr 03

Philips Semiconductors Preliminary specification

XA 16-bit microcontroller family 64K Flash/2K RAM, watchdog, 2 UARTs

GENERAL DESCRIPTION

The XA-G49 is a member of Philips’ 80C51 XA (eXtended Architecture) family of high performance 16-bit single-chip microcontrollers.

The XA-G49 contains 64k bytes of Flash program memory, and provides three general purpose timers/counters, a watchdog timer, dual UARTs, and four general purpose I/O ports with programmable output configurations.

A default serial loader program in the Boot ROM allows In-System Programming (ISP) of the Flash memory without the need for a loader in the Flash code. User programs may erase and reprogram the Flash memory at will through the use of standard routines contained in the Boot ROM (In-Application Programming).

FEA TURES

•4.5V to 5.5V operation. For low voltage operation, consult factory.

•64K bytes of on-chip Flash program memory with In-System

Programming capability

•Five Flash blocks = two 8k byte blocks and three 16k byte blocks

•Nearly identical to XA-G3, except for double the program and

RAM memories

XA-G49

•Single supply voltage In-System Programming (ISP) of the Flash

memory (V

•Boot ROM contains low level Flash programming routines for

In-Application Programming and a default serial loader using the UART

•2048 bytes of on-chip data RAM

•Supports off-chip program and data addressing up to 1 megabyte

(20 address lines)

•Three standard counter/timers with enhanced features (same as

XA-G3 T0, T1, and T2). All timers have a toggle output capability

•Watchdog timer

•Two enhanced UARTs with independent baud rates

•Seven software interrupts

•Four 8-bit I/O ports, with 4 programmable output configurations for

each pin

•30 MHz operating frequency at 5V

•Power saving operating modes: Idle and Power-Down.

Wake-Up from power-down via an external interrupt is supported.

•44-pin PLCC and 44-pin LQFP packages

= VDD, or VPP = 12V if desired)

BLOCK DIAGRAM

64K Bytes

FLASH

2048 Bytes Static RAM

Port 0

Port 1

Port 2

Port 3

XA CPU Core

Program

Memory

Bus

Data

Bus

SFR

bus

UART 0

UART 1

Timer 0, 1

Timer 2

Watchdog

Timer

2000 Apr 03

SU01002

Philips Semiconductors Preliminary specification

XA 16-bit microcontroller family 64K Flash/2K RAM, watchdog, 2 UARTs

ORDERING INFORMATION

FLASH

PXAG49KBA

PXAG49KFA

LOGIC SYMBOL

TEMPERATURE RANGE (°C)

AND PACKAGE

0 to +70

44-pin Plastic Leaded Chip Carrier

–40 to +85

44-pin Plastic Leaded Chip Carrier

XTAL1

XTAL2

RST

EA/WAIT

PSEN

ALE

VDDV

XA-G49

FREQ.

(MHz)

30 SOT187-2

T2EX* T2* TXD1

PORT 1PORT 2

A3 A2 A1 A0/WRH

BUS

ADDRESS

DRAWING

NUMBER

ALTERNATE FUNCTIONS

* NOT AVAILABLE ON 40-PIN DIP PACKAGE

RxD0

TxD0 INT0

INT1

T1/BUSW

WRL

PORT 3

ADDRESS AND DATA BUS

PORT 0

SU00526

2000 Apr 03

Philips Semiconductors Preliminary specification

XA 16-bit microcontroller family 64K Flash/2K RAM, watchdog, 2 UARTs

PIN CONFIGURATIONS 44-Pin PLCC Package

6140

Pin Function

2 P1.0/A0/WRH 3 P1.1/A1 4 P1.2/A2 5 P1.3/A3 6 P1.4/RxD1 7 P1.5/TxD1 8 P1.6/T2

9 P1.7/T2EX 10 RST 11 P3.0/RxD0 12 NC 13 P3.1/TxD0 14 P3.2/INT0 15 P3.3/INT1 16 P3.4/T0 17 P3.5/T1/BUSW 18 P3.6/WR 19 P3.7/RD 20 XTAL2 21 XTAL1 22 V

PLCC

18 28

Pin Function

23 V 24 P2.0/A12D8 25 P2.1/A13D9 26 P2.2/A14D10 27 P2.3/A15D11 28 P2.4/A16D12 29 P2.5/A17D13 30 P2.6/A18D14 31 P2.7/A19D15 32 PSEN 33 ALE 34 NC 35 EA 36 P0.7/A11D7 37 P0.6/A10D6 38 P0.5/A9D5 39 P0.4/A8D4 40 P0.3/A7D3 41 P0.2/A6D2 42 P0.1/A5D1 43 P0.0/A4D0 44 V

/VPP/WAIT

SU01035

44-Pin LQFP Package

44 34

12 22

Pin Function

1 P1.5/TxD1 2 P1.6/T2 3 P1.7/T2EX 4 RST 5 P3.0/RxD0 6NC 7 P3.1/TxD0 8 P3.2/INT0

9 P3.3/INT1 10 P3.4/T0 11 P3.5/T1/BUSW 12 P3.6/WRL 13 P3.7/RD 14 XTAL2 15 XTAL1 16 V

17 V

18 P2.0/A12D8 19 P2.1/A13D9 20 P2.2/A14D10 21 P2.3/A15D11 22 P2.4/A16/D12

LQFP

Pin Function

23 P2.5/A17D13 24 P2.6/A18D14 25 P2.7/A19D15 26 PSEN 27 ALE 28 NC 29 EA 30 P0.7/A11D7 31 P0.6/A10D6 32 P0.5/A9D5 33 P0.4/A8D4 34 P0.3/A7D3 35 P0.2/A6D2 36 P0.1/A5D1 37 P0.0/A4D0 38 V 39 V 40 P1.0/A0/WRH 41 P1.1/A1 42 P1.2/A2 43 P1.3/A3 44 P1.4/RxD1

/VPP/WAIT

DD SS

SU01036

XA-G49

2000 Apr 03

Philips Semiconductors Preliminary specification

MNEMONIC

TYPE

NAME AND FUNCTION

XA 16-bit microcontroller family

XA-G49

64K Flash/2K RAM, watchdog, 2 UARTs

PIN DESCRIPTIONS

PIN. NO.

LCC LQFP

P0.0 – P0.7 43–36 37–30 I/O Port 0: Port 0 is an 8-bit I/O port with a user-configurable output type. Port 0 latches have 1s

P1.0 – P1.7 2–9 40–44,

P2.0 – P2.7 24–31 18–25 I/O Port 2: Port 2 is an 8-bit I/O port with a user-configurable output type. Port 2 latches have 1s

P3.0 – P3.7 11,

RST 10 4 I Reset: A low on this pin resets the microcontroller, causing I/O ports and peripherals to take on

ALE 33 27 I/O Address Latch Enable: A high output on the ALE pin signals external circuitry to latch the address

1, 22 16 I Ground: 0V reference.

23, 44 17 I Power Supply: This is the power supply voltage for normal, idle, and power down operation.

written to them and are configured in the quasi-bidirectional mode during reset. The operation of port 0 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to the section on I/O port configuration and the DC Electrical Characteristics for details.

When the external program/data bus is used, Port 0 becomes the multiplexed low data/instruction byte and address lines 4 through 11.

1–3

2 40 O A0/WRH: Address bit 0 of the external address bus when the external data bus is

3 41 O A1: Address bit 1 of the external address bus. 4 42 O A2: Address bit 2 of the external address bus.

5 43 O A3: Address bit 3 of the external address bus. 6 44 I RxD1 (P1.4): Receiver input for serial port 1. 7 1 O TxD1 (P1.5): Transmitter output for serial port 1.

8 2 I/O T2 (P1.6): Timer/counter 2 external count input/clockout. 9 3 I T2EX (P1.7): Timer/counter 2 reload/capture/direction control

13–195,7–13

11 5 I RxD0 (P3.0): Receiver input for serial port 0. 13 7 O TxD0 (P3.1): Transmitter output for serial port 0. 14 8 I INT0 (P3.2): External interrupt 0 input. 15 9 I INT1 (P3.3): External interrupt 1 input. 16 10 I/O T0 (P3.4): Timer 0 external input, or timer 0 overflow output.

17 11 I/O T1/BUSW (P3.5): Timer 1 external input, or timer 1 overflow output. The value on this pin is

18 12 O WRL (P3.6): External data memory low byte write strobe. 19 13 O RD (P3.7): External data memory read strobe.

I/O Port 1: Port 1 is an 8-bit I/O port with a user-configurable output type. Port 1 latches have 1s

written to them and are configured in the quasi-bidirectional mode during reset. The operation of port 1 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to the section on I/O port configuration and the DC Electrical Characteristics for details.

Port 1 also provides special functions as described below.

configured for an 8 bit width. When the external data bus is configured for a 16 bit width, this pin becomes the high byte write strobe.

written to them and are configured in the quasi-bidirectional mode during reset. The operation of port 2 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to the section on I/O port configuration and the DC Electrical Characteristics for details.

When the external program/data bus is used in 16-bit mode, Port 2 becomes the multiplexed high data/instruction byte and address lines 12 through 19. When the external program/data bus is used in 8-bit mode, the number of address lines that appear on port 2 is user programmable.

I/O Port 3: Port 3 is an 8-bit I/O port with a user configurable output type. Port 3 latches have 1s

written to them and are configured in the quasi-bidirectional mode during reset. the operation of port 3 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to the section on I/O port configuration and the DC Electrical Characteristics for details.

Port 3 also provides various special functions as described below.

latched as the external reset input is released and defines the default external data bus width (BUSW). 0 = 8-bit bus and 1 = 16-bit bus.

their default states, and the processor to begin execution at the address contained in the reset vector. Refer to the section on Reset for details.

portion of the multiplexed address/data bus. A pulse on ALE occurs only when it is needed in order to process a bus cycle.

2000 Apr 03

Philips Semiconductors Preliminary specification

SFR

NAME

DESCRIPTION

SFR

XA 16-bit microcontroller family

XA-G49

64K Flash/2K RAM, watchdog, 2 UARTs

MNEMONIC NAME AND FUNCTIONTYPE

PSEN 32 26 O Program Store Enable: The read strobe for external program memory. When the microcontroller

EA/WAIT/

XTAL1 21 15 I Crystal 1: Input to the inverting amplifier used in the oscillator circuit and input to the internal clock

XTAL2 20 14 O Crystal 2: Output from the oscillator amplifier.

SPECIAL FUNCTION REGISTERS

PIN. NO.

LQFPLCC

accesses external program memory, PSEN is only active when external code accesses are performed.

35 29 I External Access/Wait/Programming Supply Voltage: The EA input determines whether the

internal program memory of the microcontroller is used for code execution. The value on the EA pin is latched as the external reset input is released and applies during later execution. When latched as a 0, external program memory is used exclusively, when latched as a 1, internal program memory will be used up to its limit, and external program memory used above that point. After reset is released, this pin takes on the function of bus Wait input. If Wait is asserted high during any external bus access, that cycle will be extended until Wait is released. During EPROM programming, this pin is also the programming supply voltage input.

generator circuits.

BIT FUNCTIONS AND ADDRESSES

ADDRESS

MSB LSB

is driven low in order to enable memory devices. PSEN

RESET VALUE

AUXR Auxiliary function register 44C BCR Bus configuration register 46A — — — WAITD BUSD BC2 BC1 BC0 Note 1 BTRH Bus timing register high byte 469 DW1 DW0 DWA1 DWA0 DR1 DR0 DRA1 DRA0 FF BTRL Bus timing register low byte 468 WM1 WM0 ALEW — CR1 CR0 CRA1 CRA0 EF

CS Code segment 443 00 DS Data segment 441 00 ES Extra segment 442 00

IEH* Interrupt enable high byte 427 — — — — ETI1 ERI1 ETI0 ERI0 00

IEL* Interrupt enable low byte 426 EA — — ET2 ET1 EX1 ET0 EX0 00

IPA0 Interrupt priority 0 4A0 — PT0 — PX0 00 IPA1 Interrupt priority 1 4A1 — PT1 — PX1 00 IPA2 Interrupt priority 2 4A2 — — — PT2 00 IPA4 Interrupt priority 4 4A4 — PTI0 — PRI0 00 IPA5 Interrupt priority 5 4A5 — PTI1 — PRI1 00

P0* Port 0 430 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 FF

P1* Port 1 431 T2EX T2 TxD1 RxD1 A3 A2 A1 WRH FF

P2* Port 2 432 P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 FF

P3* Port 3 433 RD WR T1 T0 INT1 INT0 TxD0 RxD0 FF

ENBOOT FMIDLE PWR_VLD

33F 33E 33D 33C 33B 33A 339 338

337 336 335 334 333 332 331 330

387 386 385 384 383 382 381 380

38F 38E 38D 38C 38B 38A 389 388

397 396 395 394 393 392 391 390

39F 39E 39D 39C 39B 39A 399 398

— — — — —

2000 Apr 03

Philips Semiconductors Preliminary specification

XA 16-bit microcontroller family

XA-G49

64K Flash/2K RAM, watchdog, 2 UARTs

SFR

NAME

P0CFGA Port 0 configuration A 470 Note 5 P1CFGA Port 1 configuration A 471 Note 5 P2CFGA Port 2 configuration A 472 Note 5 P3CFGA Port 3 configuration A 473 Note 5 P0CFGB Port 0 configuration B 4F0 Note 5 P1CFGB Port 1 configuration B 4F1 Note 5 P2CFGB Port 2 configuration B 4F2 Note 5 P3CFGB Port 3 configuration B 4F3 Note 5

PCON* Power control register 404 — — — — — — PD IDL 00

PSWH* Program status word

PSWL* Program status word (low byte) 400 C AC — — — V N Z Note 2

PSW51* 80C51 compatible PSW 402 C AC F0 RS1 RS0 V F1 P Note 3

DESCRIPTION

(high byte)

SFR

ADDRESS

227 226 225 224 223 222 221 220

20F 20E 20D 20C 20B 20A 209 208

401 SM TM RS1 RS0 IM3 IM2 IM1 IM0 Note 2

207 206 205 204 203 202 201 200

217 216 215 214 213 212 211 210

BIT FUNCTIONS AND ADDRESSES

RESET

RESET VALUE

VALUE

LSBMSB

RTH0 T imer 0 extended reload,

high byte

RTH1 T imer 1 extended reload,

high byte

RTL0 Timer 0 extended reload,

low byte

RTL1 Timer 1 extended reload,

low byte

S0CON* Serial port 0 control register 420 SM0_0 SM1_0 SM2_0 REN_0 TB8_0 RB8_0 TI_0 RI_0 00

S0STAT* Serial port 0 extended status 421 — — — — FE0 BR0 OE0 S0BUF Serial port 0 buffer register 460 x

S0ADDR Serial port 0 address register 461 00 S0ADEN Serial port 0 address enable

S1CON* Serial port 1 control register 424 SM0_1 SM1_1 SM2_1 REN_1 TB8_1 RB8_1 TI_1 RI_1 00

S1STAT* Serial port 1 extended status 425 — — — — FE1 BR1 OE1 S1BUF Serial port 1 buffer register 464 x

S1ADDR Serial port 1 address register 465 00 S1ADEN Serial port 1 address enable

455 00

457 00

454 00

456 00

307 306 305 304 303 302 301 300

30F 30E 30D 30C 30B 30A 309 308

STINT0

462 00

327 326 325 324 323 322 321 320

32F 32E 32D 32C 32B 32A 329 328

STINT1

466 00

SCR System configuration register 440 — — — — PT1 PT0 CM PZ 00

21F 21E 21D 21C 21B 21A 219 218 SSEL* Segment selection register 403 SWE Software Interrupt Enable 47A — SWE7 SWE6 SWE5 SWE4 SWE3 SWE2 SWE1 00

2000 Apr 03

ESWEN

R6SEG R5SEG R4SEG R3SEG R2SEG R1SEG R0SEG

Philips Semiconductors Preliminary specification

XA 16-bit microcontroller family

XA-G49

64K Flash/2K RAM, watchdog, 2 UARTs

SFR

NAME

SWR* Software Interrupt Request 42A — SWR7 SWR6 SWR5 SWR4 SWR3 SWR2 SWR1 00

T2CON* Timer 2 control register 418 TF2 EXF2 RCLK0 TCLK0

T2MOD* Timer 2 mode control 419 — — RCLK1 TCLK1 — — T2OE DCEN 00 TH2 Timer 2 high byte 459 00

TL2 Timer 2 low byte 458 00 T2CAPH Timer 2 capture register,

T2CAPL Timer 2 capture register,

TCON* Timer 0 and 1 control register 410 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00 TH0 Timer 0 high byte 451 00

TH1 Timer 1 high byte 453 00 TL0 Timer 0 low byte 450 00 TL1 Timer 1 low byte 452 00

TMOD Timer 0 and 1 mode control 45C GATE C/T M1 M0 GATE C/T M1 M0 00

TSTAT* Timer 0 and 1 extended status 411 — — — — — T1OE — T0OE 00

WDCON*

WDL Watchdog timer reload 45F 00

WFEED1 WFEED2

NOTES:

* SFRs are bit addressable.

1. At reset, the BCR register is loaded with the binary value 0000 0a11, where “a” is the value on the BUSW pin. This defaults the address bus size to 20 bits since the XA-G49 has only 20 address lines.

2. SFR is loaded from the reset vector.

3. All bits except F1, F0, and P are loaded from the reset vector. Those bits are all 0.

4. Unimplemented bits in SFRs are X (unknown) at all times. Ones should not be written to these bits since they may be used for other purposes in future XA derivatives. The reset value shown for these bits is 0.

5. Port configurations default to quasi-bidirectional when the XA begins execution from internal code memory after reset, based on the condition found on the EA pin. Thus all PnCFGA registers will contain FF and PnCFGB registers will contain 00. When the XA begins execution using external code memory, the default configuration for pins that are associated with the external bus will be push-pull. The PnCFGA and PnCFGB register contents will reflect this difference.

6. The WDCON reset value is E6 for a W atchdog reset, E4 for all other reset causes.

7. The XA-G49 implements an 8-bit SFR bus, as stated in Chapter 8 of the to write 16 bits to an SFR will actually write only the lower 8 bits. Sixteen bit SFR reads will return undefined data in the upper byte.

8. The AUXR reset value is typically 00h. If the Boot Loader is activated at reset because the Flash status byte is non-zero or because the Boot Vector has been forced (by PSEN

generator is running and ready, otherwise it will be a 0.

DESCRIPTION

high byte

low byte

Watchdog control register 41F PRE2 PRE1 PRE0 — —

Watchdog feed 1 45D x Watchdog feed 2 45E x

= 0, ALE = 1, EA = 1 at reset), the AUXR reset value will be 1x00 0000b. Bit 6 will be a 1 if the on-chip

SFR

ADDRESS

357 356 355 354 353 352 351 350

2C7 2C6 2C5 2C4 2C3 2C2 2C1 2C0

2CF 2CE 2CD 2CC 2CB 2CA 2C9 2C8

45B 00

45A 00

287 286 285 284 283 282 281 280

28F 28E 28D 28C 28B 28A 289 288

2FF 2FE 2FD 2FC 2FB 2FA 2F9 2F8

BIT FUNCTIONS AND ADDRESSES

XA User Guide

EXEN2

. All SFR accesses must be 8-bit operations. Attempts

TR2 C/T2

WDRUN WDTOF

CP/RL2

RESET

RESET VALUE

VALUE

LSBMSB

—

Note 6

2000 Apr 03

Philips Semiconductors Preliminary specification

XA 16-bit microcontroller family 64K Flash/2K RAM, watchdog, 2 UARTs

FFFFFh

UP TO 1M BYTES

TOTAL CODE

MEMORY

10000h

FFFFh

0000h

64k BYTES

ON-CHIP

CODE MEMORY

Note: The Boot ROM replaces the top 2k bytes of Flash memory when it is enabled via the xxx bit in xxx.

Figure 1. XA-G49 Program Memory Map

2k BYTE BOOT ROM

XA-G49

FFFFh F800h

SU01194

2k BYTES

ON-CHIP DATA

MEMORY

(RAM)

Data Segment 0

DATA MEMORY

(INDIRECTLY ADDRESSED,

OFF-CHIP)

DATA MEMORY

(INDIRECTLY ADDRESSED,

ON CHIP)

DATA MEMORY

(DIRECTLY AND INDIRECTLY

ADDRESSABLE, ON CHIP)

BIT-ADDRESSABLE

DATA AREA

DATA MEMORY

(DIRECTLY AND INDIRECTLY

ADDRESSABLE, ON CHIP)

FFFFFh

0800h 07FFh

0400H 03FFh

0040h 003Fh

0020h 001Fh

0000h

DIRECTLY ADDRESSED DATA

(1k PER SEGMENT)

FFFFFh

0400H 03FFh

0040h

003Fh

0020h

001Fh

0000h

Other Data Segments

DATA MEMORY

(INDIRECTLY ADDRESSED,

OFF-CHIP)

DATA MEMORY

(DIRECTLY AND INDIRECTLY

ADDRESSABLE, OFF-CHIP)

BIT-ADDRESSABLE

DATA AREA

DATA MEMORY

(DIRECTLY AND INDIRECTLY

ADDRESSABLE, OFF-CHIP)

2000 Apr 03

SU01195

Figure 2. XA-G49 Data Memory Map

Philips Semiconductors Preliminary specification

XA 16-bit microcontroller family 64K Flash/2K RAM, watchdog, 2 UARTs

FLASH EPROM MEMORY

GENERAL DESCRIPTION

The XA-G49 Flash memory augments EPROM functionality with in-circuit electrical erasure and programming. The Flash can be read and written as bytes. The Chip Erase operation will erase the entire program memory. The Block Erase function can erase any single Flash block. In-circuit programming and standard parallel programming are both available. On-chip erase and write timing generation contribute to a user friendly programming interface.

The XA-G49 Flash reliably stores memory contents even after 10,000 erase and program cycles. The cell is designed to optimize the erase and programming mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling. For In-System Programming, the XA-G49 can use a single +5 V power supply. Faster In-System Programming may be obtained, if required, through the use of a +12 V V Parallel programming (using separate programming hardware) uses a +12 V V

supply

FEATURES

•Flash EPROM internal program memory with Single Voltage

Programming and Block Erase capability.

•Internal 2k byte fixed boot ROM, containing low-level

programming routines and a default loader. The Boot ROM can be turned off to provide access to the full 64k byte Flash memory.

•Boot vector allows user provided Flash loader code to reside

anywhere in the Flash memory space. This configuration provides flexibility to the user.

•Default loader in Boot ROM allows programming via the serial port

without the need for a user provided loader.

•Up to 1 Mbyte external program memory if the internal program

memory is disabled (EA

•Programming and erase voltage: V

power supply), or 12V ±5% for In System Programming. Using 12V V

for ISP may improve programming and erase time.

= 0).

= VDD (single 5V ±5% chip

•Read/Programming/Erase:

– Byte-wise read (60 ns access time at 4.5 V). – Byte Programming (40 ms). – Typical erase times:

Block Erase (8k bytes or 16k bytes) in t.b.d. seconds. Full Erase (64k bytes) in t.b.d. seconds.

•In-circuit programming via user selected method, typically RS232

or parallel I/O port interface.

•Programmable security for the code in the Flash

•1,000 minimum erase/program cycles each byte over operating

temperature range

•10 year minimum data retention.

supply.

XA-G49

CAPABILITIES OF THE PHILIPS 89C51 FLASH-BASED MICROCONTROLLERS

Flash organization

The XA-G49 contains 64k bytes of Flash program memory. This memory is organized as 5 separate blocks. The first two blocks are 8k bytes in size, filling the program memory space from address 0 through 3FFF hex. The final three blocks are 16k bytes in size and occupy addresses from 4000 through FFFF hex.

Figure 3 depicts the Flash memory configuration.

Flash Programming and Erasure

The XA-G49 Flash microcontroller supports a number of programming possibilities for the on-chip Flash memory. The Flash memory may be programmed in a parallel fashion on standard programming equipment in a manner similar to an EPROM microcontroller. The XA-G49 microcontroller is able to program its own Flash memory while the application code is running. Also, a default loader built into a Boot ROM allows programming blank devices serially through the UART.

Using any of these types of programming, any of the individual blocks may be erased separately, or the entire chip may be erased. Programming of the Flash memory is accomplished one byte at a time.

Boot ROM

When the microcontroller programs its own Flash memory, all of the low level details are handled by code that is permanently contained in a 2k byte “Boot ROM” that is separate from the Flash memory. A user program simply calls the entry point with the appropriate parameters to accomplish the desired operation. Boot ROM operations include things like: erase block, program byte, verify byte, program security lock bit, etc. The Boot ROM overlays the program memory space at the top of the address space from F800 to FFFF hex, when it is enabled by setting the ENBOOT bit at AUXR1.7.. The Boot ROM may be turned off so that the upper 2k bytes of Flash program memory are accessible for execution.

ENBOOT and PWR_VLD

Setting the ENBOOT bit in the AUXR register enables the Boot ROM and activates the on-chip V V

rather than 12V externally. The PWR_VLD flag indicates that

is available for programming and erase operations. This flag

should be checked prior to calling the Boot ROM for programming and erase services. When ENBOOT is set, it typically takes 5 microseconds for the internal programming voltage to be ready.

The ENBOOT bit will automatically be set if the status byte is non-zero during reset, or when PSEN high at the falling edge of reset. Otherwise, ENBOOT will be cleared during reset.

When programming functions are not needed, ENBOOT may be cleared. This enables access to the 2k bytes of Flash code memory that is overlaid by the Boot ROM, allowing a full 64k bytes of Flash code memory.

generator if VPP is connected to

is low, ALE is high, and EA is

2000 Apr 03

Philips Semiconductors Preliminary specification

XA 16-bit microcontroller family 64K Flash/2K RAM, watchdog, 2 UARTs

FFFF

BLOCK 4

16k BYTES

C000

BLOCK 3

16k BYTES

PROGRAM

ADDRESS

8000

BLOCK 2

16k BYTES

4000

BLOCK 1

2000

0000

8k BYTES

BLOCK 0 8k BYTES

Figure 3. Flash Memory Configuration

BOOT ROM

SU01034

XA-G49

FFFF F800

FMIDLE

The FMIDLE bit in the AUXR register allows saving additional power by turning off the Flash memory when the CPU is in the Idle mode. This must be done just prior to initiating the Idle mode, as shown below.

OR AUXR,#$40 ; Set Flash memory

to idle mode. OR PCON,#$01 ; Turn on Idle mode. . . ; Execution resumes

here when Idle

mode terminates.

When the Flash memory is put into the Idle mode by setting FMIDLE, restarting the CPU upon exiting Idle mode takes slightly longer, about 3 microseconds. However, the standby current consumed by the Flash memory is reduced from about 8mA to about 1mA.

Default Loader

A default loader that accepts programming commands in a predetermined format is contained permanently in the Boot ROM. A factory fresh device will enter this loader automatically if it is powered up without first being programmed by the user. Loader commands include functions such as erase block; program Flash memory; read Flash memory; and blank check.

Boot Vector

The XA-G49 contains two special FLASH registers: the BOOT VECTOR and the STATUS BYTE.

The “Boot Vector” allows forcing the execution of a user supplied Flash loader upon reset, under two specific sets of conditions. At the falling edge of reset, the XA-G49 examines the contents of the Status Byte. If the Status Byte is set to zero, power-up execution starts at location 0000H, which is the normal start address of the user’s application code.

When the Status Byte is set to a value other than zero, the Boot Vector is used as the reset vector (4 bytes), including the Boot Program Counter (BPC) and the Boot PSW (BPSW). The factory default settings are 8000h for the BPSW and F800h for the BPC, which corresponds to the address F900h for the factory masked-ROM ISP boot loader. The Status Byte is automatically set to a non-zero value when a programming error occurs. A custom boot loader can be written with the Boot Vector set to the custom boot loader.

NOTE: When erasing the Status Byte or Boot Vector, these bytes are erased at the same time. It is necessary to reprogram the Boot Vector after erasing and updating the Status Byte.

Hardware Activation of the Boot Vector

Program execution at the Boot Vector may also be forced from outside of the microcontroller by setting the correct state on a few pins. While Reset is asserted, the PSEN ALE pin allowed to float high (need not be pulled up externally), and

pin driven to a logic high (or up to VPP). Then reset may be

the EA released. This is the same effect as having a non-zero status byte. This allows building an application that will normally execute the end user’s code but can be manually forced into ISP operation. The Boot ROM is enabled when use of the Boot Vector is forced as described above, so the branch may go to the default loader. Conversely, user code in the top 2k bytes of the Flash memory may not be executed when the Boot Vector is used.

If the factory default setting for the BPC (F800h) is changed, it will no longer point to the ISP masked-ROM boot loader code. If this happens, the only possible way to change the contents of the Boot Vector is through the parallel programming method, provided that the end user application does not contain a customized loader that provides for erasing and reprogramming of the Boot Vector and Status Byte.

After programming the FLASH, the status byte should be erased to zero in order to allow execution of the user’s application code beginning at address 0000H.

pin must be pulled low, the

2000 Apr 03

Philips Semiconductors Preliminary specification

XA 16-bit microcontroller family 64K Flash/2K RAM, watchdog, 2 UARTs

RST

XTAL2

XTAL1

Figure 4. In-System Programming with a Minimum of Pins

In-System Programming (ISP)

In-System Programming (ISP) is performed without removing the microcontroller from the system. The In-System Programming (ISP) facility consists of a series of internal hardware resources coupled with internal firmware to facilitate remote programming of the XA-G49 through the serial port. This firmware is provided by Philips and embedded within each XA-G49 device.

The Philips In-System Programming (ISP) facility has made in-circuit programming in an embedded application possible with a minimum of additional expense in components and circuit board area.

The ISP function uses five pins: TxD, RxD, V Figure 4). Only a small connector needs to be available to interface your application to an external circuit in order to use this feature. The V

supply should be adequately decoupled and VPP not

allowed to exceed datasheet limits.

Table 1. ISP typical programming currents

@ 25°C, 22 MHz, 5 V

5.0 V 5.0 V 60 µA 25 mA

ISP increases IDD by less than 1mA.

ISP software is available on the Philips web site

1. With your browser, open this page:

www.semiconductors.com

2. Enter winzip.zip into the Search box at the top of the Philips web page.

3. Click on Microcontrollers Software support.

4. Download disk1.zip and disk2.zip.

5. Create a directory on your hard drive named WINISP.

6. Unzip the two disk files into this new directory WINISP.

Using In-System Programming (ISP)

When ISP mode is entered, the default loader first disables the watchdog timer to prevent a watchdog reset from occurring during programming.

The ISP feature allows for a wide range of baud rates to be used in the application, independent of the oscillator frequency. It is also

TxD RxD

, VDD, and VPP (see

XA-G49

VDD SUPPLY OR +12V ±5%

5V ±5% TxD RxD V

TRANSCEIVER

MC145406, MAX232,

OR EQUIVALENT

adaptable to a wide range of oscillator frequencies. This is accomplished by measuring the bit-time of a single bit in a received character. This information is then used to program the baud rate in terms of timer counts based on the oscillator frequency. The ISP feature requires that an initial character (a lowercase f) be sent to the XA-G49 to establish the baud rate. The ISP firmware provides auto-echo of received characters.

Once baud rate initialization has been performed, the ISP firmware will only accept specific Intel Hex-type records. Intel Hex records consist of ASCII characters used to represent hexadecimal values and are summarized below:

:NNAAAARRDD..DDCC<crlf>

In the Intel Hex record, the “NN” represents the number of data bytes in the record. The XA-G49 will accept up to 16 (10H) data bytes. The “AAAA” string represents the address of the first byte in the record. If there are zero bytes in the record, this field is often set to 0000. The “RR” string indicates the record type. A record type of “00” is a data record. A record type of “01” indicates the end-of-file mark. In this application, additional record types will be added to indicate either commands or data for the ISP facility. The maximum number of data bytes in a record is limited to 16 (decimal). ISP commands are summarized in Table 2.

As a record is received by the XA-G49, the information in the record is stored internally and a checksum calculation is performed. The operation indicated by the record type is not performed until the entire record has been received. Should an error occur in the checksum, the XA-G49 will send an “X” out the serial port indicating a checksum error. If the checksum calculation is found to match the checksum in the record, then the command will be executed. In most cases, successful reception of the record will be indicated by transmitting a “.” character out the serial port (displaying the contents of the internal program memory is an exception).

In the case of a Data Record (record type 00), an additional check is made. A “.” character will NOT be sent unless the record checksum matched the calculated checksum and all of the bytes in the record were successfully programmed. For a data record, an “X” indicates that the checksum failed to match, and an “R” character indicates that one of the bytes did not properly program.

The ISP facility was designed so that specific crystal frequencies were not required in order to generate baud rates or time the programming pulses.

FOR USE WITH WINISP

RS-232

FEMALE

DB-9

SU01072

2 3

2000 Apr 03

Philips Semiconductors Preliminary specification

XA 16-bit microcontroller family 64K Flash/2K RAM, watchdog, 2 UARTs

User Supplied Loader

A user program can simply decide at any time, for any reason, to begin Flash programming operations. All it has to do in advance is to instruct external circuitry to apply +5V or +12V to the V make certain that the Boot ROM is enabled. User code may contain a loader designed to replace the application code contained in the Flash memory by loading new code through any communication medium available in the application. This is completely flexible and defined by the designer of the system. It could be done serially using RS-232, serially using some other method, or even parallel over a user defined I/O port. The user has the freedom to choose a method that does not interfere with the application circuit. As an added feature, the application program may also use the Flash memory as a long term data storage, saving configuration information, sensor readings, or any other desired data.

The actual loader code would typically be programmed by the user into the microcontroller in a parallel fashion or via the default loader during their manufacturing process. The entire initial Flash contents may be programmed at that time, or the rest of the application may be programmed into the Flash memory at a later time, possibly using the loader code to do the programming.

pin, and

XA-G49

This application controlled programming capability allows for the possibility of changing the application code in the field. If the application circuit is embedded in a PC, or has a way to establish a telephone data link to a user’s or manufacturer’s computer, new code could be downloaded from diskette or a manufacturer’s support system. There is even the possibility of conducting very specialized remote testing of a failing circuit board by the manufacturer by remotely programming a series of detailed test programs into the application board and checking the results.

Any user supplied loader should take the watchdog timer into account. Typically, the watchdog timer would be disabled upon entry to the loader if it might be running, in order to prevent a watchdog reset from occurring during programming.

XA Programming Specifications on Philips web site

Programming specifications for the XA family can be located on the Philips Semiconductors web site at:

www.semiconductors.com/mcu/

Click on Support and Training, then Programming Specifications.

2000 Apr 03

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