Philips UDA1384 User Guide

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UDA1384

Multichannel audio coder-decoder

Rev. 02 — 17 January 2005 Product data sheet

1. General description

The UDA1384 is a single-chip consisting of 4 plus 1 Analog-to-Digital Converters (ADC) and 6 Digital-to-Analog Converters (DAC) with signal processing features employing bitstream conversion techniques. The multichannel conﬁguration makes the device eminently suitable for use in digital audio equipment which incorporates surround feature.

The UDA1384 supports conventional 2 channels per line data transfer conformable to the I2S-bus format with word lengths of up to 24 bits, the MSB-justiﬁed format with word lengths of up to 24 bits and the LSB-justiﬁed format with word lengths of 16 bits, 20 bits and 24 bits, as well as 4 channels to 6 channels per line transfer mode. The device also supports a combination of the MSB-justiﬁed output format and the LSB-justiﬁed input format. The UDA1384 has special sound processing features in the Direct Stream Digital (DSD) playback mode, de-emphasis, volume and mute which can be controlled via the L3-bus or I2C-bus interface.

2. Features

2.1 General

■ 2.7 V to 3.6 V power supply

■ 5 V tolerant digital inputs

■ 24-bit data path

■ Selectable control: via L3-bus or I2C-bus microcontroller interface

■ Supports sample frequency ranges for:

◆ Audio ADC: fs = 16 kHz to 100 kHz

◆ Voice ADC: fs = 7 kHz to 50 kHz

◆ Audio DAC: fs = 16 kHz to 200 kHz

■ Separate power control for ADC and DAC

■ ADC plus integrated high-pass ﬁlter to cancel DC offset

■ Integrated digital ﬁlter plus DAC

■ Slave mode only applications

■ Easy application

Philips Semiconductors

2.2 Multiple format data interface

■ Audio interface supports standard I2S-bus, MSB-justiﬁed, LSB-justiﬁed and two

multichannel formats

■ Voice interface supports I2S-bus and mono channel formats

2.3 Digital sound processing

■ Control via L3-bus or I2C-bus:

◆ Channel independent digital logarithmic volume

◆ Digital de-emphasis for fs = 32 kHz, 44.1 kHz, 48 kHz or 96 kHz

◆ Soft or quick mute

◆ Output signal polarity control

2.4 Advanced audio conﬁguration

■ Inputs:

◆ 4 single-ended audio inputs (2 × stereo) with programmable gain ampliﬁers

◆ 1 single-ended voice input

■ Outputs:

◆ 6 differential audio outputs (3 × stereo)

■ DSD mode to support stereo DSD playback

■ High linearity, wide dynamic range and low distortion

■ DAC digital ﬁlter with selectable sharp or soft roll-off

UDA1384

Multichannel audio coder-decoder

3. Applications

■ Excellently suitable for multichannel home audio-video application

4. Quick reference data

Table 1: Quick reference data

= V

DDD

(pins V

Symbol Parameter Conditions Min Typ Max Unit

Supplies

V I

DDA(AD)

DDA(DA)

DDD

DDA(AD)

); unless otherwise speciﬁed.

DDA(AD)

DDA(DA)

DDD

= V

ADC analog supply voltage

DAC analog supply voltage

digital supply voltage 2.7 3.3 3.6 V ADC analog supply

current DAC analog supply

current digital supply current f

DDA(DA)

= 3.3 V; T

= 25°C; RL = 22 kΩ; all voltages referenced to ground

amb

2.7 3.3 3.6 V

= 48 kHz - 30 - mA

ADC

= 48 kHz - 20 - mA

DAC

ADC=fDAC

= 48 kHz

VOICE

= 48 kHz;

-31-mA

Product data sheet Rev. 02 — 17 January 2005 2 of 55

Philips Semiconductors

UDA1384

Multichannel audio coder-decoder

Table 1: Quick reference data

DDD

(pins V

= V

DDA(AD)

DDA(DA)

); unless otherwise speciﬁed.

…continued

= 3.3 V; T

= 25°C; RL = 22 kΩ; all voltages referenced to ground

amb

Symbol Parameter Conditions Min Typ Max Unit

DDD(pd)

digital supply current in Power-down mode

audio and voice ADCs power-down

-18-mA

DAC power-down - 14 - mA

amb

ambient temperature −20 - +85 °C

Audio analog-to-digital converter

digital output level at 0 dB setting;

[1] [2]

−2.5 −1.2 −0.7 dB

900 mV input

(THD+N)/S total harmonic

distortion-plus-noise to signal ratio

at −1 dBFS - −88 −82 dB at −60 dBFS;

- −37 −30 dB

A-weighted

S/N signal-to-noise ratio code = 0; A-weighted 89 98 - dB

channel separation - 100 - dB

Digital-to-analog converter

Differential mode

o(rms)

output voltage (RMS value)

(THD+N)/S total harmonic

distortion-plus-noise to signal ratio

at 0 dBFS digital

1.9 2.0 2.1 V

input at 0 dBFS - −98 −89 dB at −60 dBFS;

- −50 −45 dB

A-weighted

S/N signal-to-noise ratio code = 0; A-weighted 100 110 - dB

channel separation - 114 - dB

Single-ended mode

o(rms)

output voltage

(RMS value) (THD+N)/S total harmonic

distortion-plus-noise

to signal ratio

at 0 dBFS digital

- 1.0 - V

input at 0 dBFS - −88 - dB at −60 dBFS;

- −45 - dB

A-weighted

S/N signal-to-noise ratio code = 0; A-weighted - 105 - dB

channel separation - 110 - dB

[1] The input voltage can be up to 2 V (RMS) when the current through the ADC input pin is limited to

approximately 1 mA by using a series resistor.

[2] The input voltage to the ADC scales proportionally with the power supply voltage.

5. Ordering information

Table 2: Ordering information

Type number Package

Name Description Version

UDA1384H QFP44 plastic quad ﬂat package; 44 leads (lead length

1.3 mm); body 10 × 10 × 1.75 mm

Product data sheet Rev. 02 — 17 January 2005 3 of 55

SOT307-2

Philips Semiconductors

6. Block diagram

UDA1384

Multichannel audio coder-decoder

VINL1

VINL2

VVOICE

DATAV

BCKV

WSV

MCCLK

MCMODE

MCDATA

I2C_L3

16 17

21 20 22 30

PGA ADC 1L

PGA

LNA

ADC 2L

ADC

DECIMATION

FILTER

HP FILTER

I2S-BUS

INTERFACE 3

PLL

L3-BUS OR

I2C-BUS

CONTROL

INTERFACE

UDA1384

DDA(AD)

DC-CANCELLATION FILTER

VOLUME, MUTE, DE-EMPHASIS

INTERPOLATION FILTER

SSA(AD)

DECIMATION FILTER

I2S-BUS

INTERFACE 1

I2S-BUS

INTERFACE 2

NOISE SHAPER

ADCP

ADC 1R

ADC 2R

ADCN

TEST

CLOCK

PLL

PGA

ref

VINR1

VINR2

TEST

SYSCLK

DATAAD1

DATAAD2

BCKAD

WSAD

WSDA

BCKDA

DATADA1

DATADA2

DATADA3

DDD

SSD

VOUT1N VOUT1P

VOUT3N VOUT3P

VOUT5N VOUT5P

32 31

36 35

42 41

−

DAC 1

−

DAC 3

−

DAC 5

37 40

DDA(DA)

SSA(DA)

DAC 2

DAC 4

DAC 6

34 33

39 38

44 43

VOUT2N VOUT2P

VOUT4N VOUT4P

VOUT6N VOUT6P

− +

mce639

Fig 1. Block diagram

Product data sheet Rev. 02 — 17 January 2005 4 of 55

Philips Semiconductors

7. Pinning information

7.1 Pinning

UDA1384

Multichannel audio coder-decoder

SSA(DA)

4443424140393837363534

ref

VINL1 VOUT1N

SSA(AD)

DDA(AD)

VVOICE BCKDA

3 4

VINR1 I2C_L3

5 6

VINL2 V

ADCN

VINR2 DATADA2

ADCP

10 11

TEST WSDA

1213141516171819202122

DATAAD2 VOUT6N

BCKAD VOUT5N

DATAAD1 VOUT6P

UDA1384H

WSAD VOUT5P

DATAV V

WSV VOUT4P

BCKV VOUT4N

DDA(DA)

SYSCLK V

MCCLK VOUT3P

MCMODE VOUT3N

33 32 31 30 29 28 27 26 25 24 23

001aac311

MCDATA VOUT2N

Fig 2. Pin conﬁguration

7.2 Pin description

Table 3: Pin description

Symbol Pin Type Description

ref

VINL1 2 AIO ADC 1 input left V

SSA(AD)

VINR1 4 AIO ADC 1 input right V

DDA(AD)

VINL2 6 AIO ADC 2 input left V

ADCN

VINR2 8 AIO ADC 2 input right V

ADCP

VVOICE 10 AIO voice ADC input TEST 11 DID test input; must be connected to digital ground (V

DATAAD2 12 DO ADC 2 data output DATAAD1 13 DO ADC 1 data output BCKAD 14 DIS ADC bit clock input WSAD 15 DI ADC word select input

1 AIO ADC reference voltage

3 AGND ADC analog ground

5 AS ADC analog supply voltage

7 AIO ADC reference voltage N

9 AIO ADC reference voltage P

application

VOUT2P

VOUT1P

DDD SSD

DATADA3

DATADA1

SSD

) in

Product data sheet Rev. 02 — 17 January 2005 5 of 55

Philips Semiconductors

UDA1384

Multichannel audio coder-decoder

Table 3: Pin description

…continued

Symbol Pin Type Description

DATAV 16 DO voice data output BCKV 17 DIS voice bit clock input WSV 18 DIO voice word select input or output SYSCLK 19 DIS system clock input: 256f

, 384fs, 512fs or 768f

MCMODE 20 DI L3-bus L3MODE input or I2C-bus DAC mute control input

MCCLK 21 DIS L3-bus L3CLOCK input or I MCDATA 22 IIC L3-bus L3DATA input and output or I

C-bus SCL input

C-bus SDA input and

output WSDA 23 DI DAC word select input BCKDA 24 DIS DAC bit clock input DATADA1 25 DI DAC channel 1 and channel 2 data input DATADA2 26 DI DAC channel 3 and channel 4 data input DATADA3 27 DI DAC channel 5 and channel 6 data input V

SSD

DDD

I2C_L3 30 DI selection input for L3-bus or I

28 DGND digital ground 29 DS digital supply voltage

C-bus control VOUT1P 31 AIO DAC 1 positive output VOUT1N 32 AIO DAC 1 negative output VOUT2P 33 AIO DAC 2 positive output VOUT2N 34 AIO DAC 2 negative output VOUT3P 35 AIO DAC 3 positive output VOUT3N 36 AIO DAC 3 negative output V

DDA(DA)

37 AS DAC analog supply voltage VOUT4P 38 AIO DAC 4 positive output VOUT4N 39 AIO DAC 4 negative output V

SSA(DA)

40 AGND DAC analog ground VOUT5P 41 AIO DAC 5 positive output VOUT5N 42 AIO DAC 5 negative output VOUT6P 43 AIO DAC 6 positive output VOUT6N 44 AIO DAC 6 negative output

[1] See Table 4.

Table 4: Pin types

Type Description

AGND analog ground AIO analog input and output AS analog supply DGND digital ground DI digital input DID digital input with internal pull-down resistor DIO digital input and output

Product data sheet Rev. 02 — 17 January 2005 6 of 55

Philips Semiconductors

UDA1384

Multichannel audio coder-decoder

Table 4: Pin types

Type Description

DIS digital Schmitt-triggered input DO digital output DS digital supply IIC input and open-drain output for I

8. Functional description

8.1 System clock

The UDA1384 operates in slave mode only; this means that in all applications the system must provide either the system clock (the bit clock for the voice ADC) or the word clock.

The audio ADC part, the voice ADC part and the DAC part can operate at different sampling frequencies (DAC-WS and ADC-WS modes) as well as a common frequency (SYSCLK, WSDA and DSD modes).

The voice ADC part supports a sampling frequency up to 50 kHz and the audio ADC supports a sampling frequency up to 100 kHz. The DAC sampling frequency range is extended up to 200 kHz with the range above 100 kHz being supported through 192 kHz sampling mode, which halves the oversampling ratio of SYSCLK and internal clocks.

…continued

C-bus

The mode of operation of the audio and voice channels can be set via the L3-bus or I2C-bus microcontroller interface and are summarized in Table 5 and Table 6.

When applied, the system clock must be locked in frequency to the corresponding digital interface clocks.

The voice ADC part can either receive or generate the WSV signal as shown in Table 6.

Table 5: Audio ADC and DAC operating clock mode

Mode Audio ADC Audio DAC

Clock Frequency Clock Frequency

SYSCLK SYSCLK 256f

DAC-WS SYSCLK 256f ADC-WS WSAD 1f

WSDA WSDA 1f DSD SYSCLK 44.1 kHz × 512 SYSCLK 44.1 kHz × 512

Table 6: Voice ADC operating clock mode

Mode Voice ADC

Bit clock frequency (BCKV) Word select (WSV)

WSV-in input: 32f WSV-out input: 32f

Product data sheet Rev. 02 — 17 January 2005 7 of 55

, 384fs, 512fs or 768fsSYSCLK 256fs, 384fs, 512fs or 768f

SYSCLK 128fs, 192fs, 256fs or 384fs;

192 kHz sampling mode

, 384fs, 512fs or 768fsWSDA 1f

, 64fs, 128fs or 256f

SYSCLK 256fs, 384fs, 512fs or 768f SYSCLK 128fs, 192fs, 256fs or 384fs;

WSDA 1f

s s

192 kHz sampling mode

input output

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8.2 Audio analog-to-digital converter (audio ADC)

The audio analog-to-digital front-end of the UDA1384 consists of 4-channel single-ended ADCs with programmable gain stage (from 0 dB to 24 dB with 3 dB steps), controlled via the microcontroller interface.Using the PGA feature,it is possible to accept an input signal of 900 mV (RMS) or 1.8 V (RMS) if an external resistor of 10 kΩ is used in series. The schematic of audio ADC front-end is shown in Figure 3.

Fig 3. Schematic of audio ADC front-end

input signal

2 V (RMS)

10 kΩ

VINL, VINR

Multichannel audio coder-decoder

10 kΩ (0 dB setting)

10 kΩ

ref

DDA

mgu582

= 3.3 V

UDA1384

ADC

8.3 Voice Analog-to-Digital Converter (voice ADC)

The voice analog-to-digital front-end of the UDA1384 consists of a single-channel single-ended ADC with a ﬁxed gain (26 dB) Low Noise Ampliﬁer (LNA). Together with the digital variable gain ampliﬁcation stage, the voice ADC provides optimal processing and reproduction of the microphone signal. The supported sampling frequency range is from 7 kHz to 50 kHz. Power-down of the LNA and the ADC can be controlled separately.

8.4 Decimation ﬁlter of audio ADC

The decimation from 64fs is performed in two stages. The ﬁrst stage realizes characteristics with a decimation factor of 8. The second stage consists of three half-band

ﬁlters, each decimating by a factor of 2. The ﬁlter characteristics are shown in Table 7.

Table 7: Decimation ﬁlter characteristics (audio ADC)

Item Condition Value (dB)

Pass-band ripple 0f

to 0.45f

Pass-band droop 0.45f Stop band > 0.55f Dynamic range 0f

to 0.45f

±0.01

−0.2

−70

> 135

8.5 Decimation ﬁlter of voice ADC

xsin



----------



The voice ADC decimation ﬁlter is realized with the combination of a Finite Impulse Response (FIR) ﬁlter and Inﬁnite Impulse Response (IIR) ﬁlter forshorter group delay. The ﬁlter characteristics are shown in Table 8. During the power-on sequence, the output of the ADC is hard muted for a certain period. This hard-mute time can be chosen between 1024 samples and 2048 samples.

Product data sheet Rev. 02 — 17 January 2005 8 of 55

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Table 8: Decimation ﬁlter characteristics (voice ADC)

Item Condition Value (dB)

Pass-band ripple 0f Pass-band droop 0.45f Stop band > 0.55f Dynamic range 0f

8.6 Interpolation ﬁlter of DAC

The digital interpolation ﬁlter interpolates from 1fsto 128fs (or to 64fs in the 192 kHz sampling mode) by cascading FIR ﬁlters, and has two sets of ﬁlter coefﬁcients for sharp and slow roll-off as given in Table 9 and Table 10.

Table 9: Interpolation ﬁlter characteristics (sharp roll-off)

Item Condition Value (dB)

Pass-band ripple 0f Stop band > 0.55f Dynamic range 0f

to 0.45f

UDA1384

Multichannel audio coder-decoder

±0.05

−0.2

−65

> 110

±0.002

−75

> 135

Table 10: Interpolation ﬁlter characteristics (slow roll-off)

Item Condition Value (dB)

Pass-band ripple 0f

to 0.22f

Pass-band droop 0.45f Stop band > 0.78f Dynamic range 0f

to 0.22f

±0.002

−3.1

−94

> 135

8.7 Noise shaper of DAC

The 3rd-order noise shaper operates at either 128fs or 64fs (in the 192 kHz sampling mode), and converts the 24-bit input signal into a 5-bit signal stream. The noise shaper shifts in-band quantization noise to frequencies well above the audio band. This noise shaping technique enables high signal-to-noise ratios to be achieved.

8.8 Digital mixer

The UDA1384 has 6 digital mixers inside the interpolator (see Figure 4). The ADC signals can be mixed with the I2S-bus input signals. The mixing of the ADC signals can be selected by the bits MIX[1:0].

Product data sheet Rev. 02 — 17 January 2005 9 of 55

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]

MIX[1:0

from ADC

ch1 ch2

ch3 ch4

from I

S-bus

mixer input

MIXER

VOLUME

VOLUMEDE-EMPHASIS MUTE

MIXER

MUTE

UDA1384

Multichannel audio coder-decoder

INTERPOLATION

FILTER

DAC1

DATADA1

DATADA2

DATADA3

]

DIS[1:0

]

ICS[1:0

Fig 4. Block diagram of DAC mixer

8.9 Audio digital-to-analog converters

The audio digital-to-analog front-end of the UDA1384 consists of 6-channel differential SDACs: an SDAC is a multi-bit DAC based upon switched resistors. To minimize data dependent modulation effects, a Dynamic Element Matching (DEM) algorithm scrambler circuit and DC current compensation circuit are implemented with the SDAC.

same as above

DAC2

DAC3

DAC4

DAC5

DAC6

mgw786

8.10 Power-on reset

The UDA1384 has an internal power-on reset circuit which initializes the device (see

Figure 5). All the digital sound processing features and the system controlling features are

set to their default values in the L3-bus and the I2C-bus modes. The reset time (see Figure 6) is determined by an external capacitor which is connected

between pin V When V

DDA(AD)

During the reset time, the system clock should be running.

Product data sheet Rev. 02 — 17 January 2005 10 of 55

and ground. The reset time should be at least 250 µs for V

ref

is switched off, the device will be reset again for V

< 0.75 V.

ref

< 1.25 V.

ref

Philips Semiconductors

UDA1384

Multichannel audio coder-decoder

3.3

DDD

(V)

DDA(AD)

C1 > 10 µF

9 kΩ

ref

9 kΩ

RESET

CIRCUIT

mgu585

DDA(AD)

(V)

3.3

ref

(V)

1.65

1.25

0.75

>250 µs

Fig 5. Power-on reset circuit Fig 6. Power-on reset timing

8.11 Audio digital interface

The following audio formats can be selected via the microcontroller interface:

• I

S-bus format with data word length of up to 24 bits

• MSB-justiﬁed format with data word length of up to 24 bits

• LSB-justiﬁed format with data word length of 16 bits, 20 bits or 24 bits

• Multichannel formats with data word length of 20 bits or 24 bits. The used data lines

are DATAAD1 and DATADA1 and the sampling frequency must be below 50 kHz

rst

mgu586

The formats are illustrated in Figure 7 and Figure 8.

Product data sheet Rev. 02 — 17 January 2005 11 of 55

Philips Semiconductors

B15 LSB

UDA1384

Multichannel audio coder-decoder

mgt020

B19 LSB

B23 LSB

RIGHT

> = 8

21> = 812 3

MSB MSBB2

S-BUS FORMAT

RIGHT

LEFT

1518 1720 19 2 1

MSB B2 B3 B4 B5 B6

LSB

B19

LSB-JUSTIFIED FORMAT 20 BITS

1518 1720 19 2 1

MSB B2 B3 B4 B5 B6

15 2 1

MSB B2

RIGHT

LSB

B15

LSB-JUSTIFIED FORMAT 16 BITS

321321

> = 8 > = 8

MSB-JUSTIFIED FORMAT

LEFT

15 2 1

MSB

RIGHT

LEFT

1518 1720 1922 212324 21

B5 B6 B7 B8 B9 B10

B3 B4

MSB

LSB

B23

LSB-JUSTIFIED FORMAT 24 BITS

1518 1720 1922 212324 2 1

B5 B6 B7 B8 B9 B10

B3 B4

BCK

MSB

DATA

LEFT

MSB B2

MSB B2 MSBLSB LSB MSB B2B2

BCK

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx

xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

DATA

BCK

DATA

BCK

DATA

BCK

DATA

Fig 7. Formats of input and output data (single-channel)

Product data sheet Rev. 02 — 17 January 2005 12 of 55

Philips Semiconductors

LSB

CH6

UDA1384

Multichannel audio coder-decoder

mgu588

LSB

CH6

4241 61

MSBLSB

CH4

MSBLSBMSB

CH2

212221

MULTICHANNEL FORMAT 20 BITS

LSB

CH5

4241 61

MSBLSB

5049 73

MSBLSB

CH4

MSBLSBMSB

CH2

(1)

212625

LSB

MULTICHANNEL FORMAT 24 BITS

CH5

5049 73

MSBLSB

73 97

CH4

5049 74

MSBLSBMSB

CH2

(2)

12625

LSB

MULTICHANNEL FORMAT 24 BITS

CH5

MSBLSB

73 97

CH3

MSBLSBMSB

CH1

212221

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx

xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

BCK

DATA

MSBLSBMSB

CH1

212625

BCK

DATA

5049 74

MSBLSBMSB

CH1

12625

BCK

DATA

(1) Format 1.

(2) Format 2.

Fig 8. Formats of input and output data (multichannel)

Product data sheet Rev. 02 — 17 January 2005 13 of 55

Philips Semiconductors

8.12 Voice digital interface

The following voice formats can be selected via the microcontroller interface:

• I

S-bus format with data word length of up to 20 bits. The left and the right channels

contain the same data.

• Mono channel format with data word length of up to 20 bits.

The formats are illustrated in Figure 9.

UDA1384

Multichannel audio coder-decoder

BCK

DATA

BCK

DATA

MSB B2

LEFT

Fig 9. Voice digital interface formats

8.13 DSD mode

The UDA1384 can receive 2.8224 MHz DSD signals and generate 88.2 kHz multibit PCM signals as well as analog signal outputs. The conﬁguration of the UDA1384 in the DSD mode is shown in Figure 10.

21≥ 812 3

MSB MSBB2

S-BUS FORMAT

MONO CHANNEL FORMAT

RIGHT

≥ 8

21≥ 8123

MSB B2

mgu587

OUT1N

OUT1P

OUT2N

OUT2P

mgu584

left channel

right channel

analog output

2.8224 MHz DSD

left

channel

right

channel

5.6448 MHz

88.2 kHz

DATADA2

DATADA3

BCKAD WSAD

DECIMATION

FILTER

I2S-BUS

INTERFACE 1

DATADA1DATAAD1 BCKDA SYSCLK

88.2 kHz

PCM data

S-bus

(left and right)

DAC

INTERPOLATION

NOISE SHAPING

DAC

I2S-BUS

INTERFACE 2

WSDA

88.2 kHz 22.5792 MHz

5.6448 MHz

− +

Fig 10. DSD mode

Product data sheet Rev. 02 — 17 January 2005 14 of 55

Philips Semiconductors

8.14 Microcontroller interface mode

The microcontroller interface mode can be selected as shown in Table 11:

• L3-bus mode when pin I2C_L3 = LOW

• I

C-bus mode when pin I2C_L3 = HIGH

Table 11: Pin function in the L3-bus or I2C-bus mode

Pin Level on pin I2C_L3

MCCLK L3CLOCK SCL MCDATA L3DATA SDA MCMODE L3MODE QMUTE

Table 12: QMUTE

Signal QMUTE Function

LOW no muting HIGH muting

UDA1384

Multichannel audio coder-decoder

LOW HIGH L3-bus mode signal I2C-bus mode signal

All the features are accessible with the I2C-bus interface protocol as with the L3-bus interface protocol.

The detailed description of the device operation in the L3-bus mode and I2C-bus mode is given in Section 9 and Section 10, respectively.

9. L3-bus interface

9.1 General

The UDA1384 has an L3-bus microcontroller interface and all the digital sound processing features and various system settings can be controlled by a microcontroller.

The exchange of data and control information between the microcontroller and the UDA1384 is LSB ﬁrst and is accomplished through a serial hardware L3-bus interface comprising the following pins:

• MCCLK: clock line with signal L3CLOCK

• MCDATA: data line with signal L3DATA

• MCMODE: mode line with signal L3MODE

The L3-bus format has two modes of operation:

• Address mode

• Data transfer mode

The address mode is used to select a device for a subsequent data transfer. The address mode is characterized by signal L3MODE = LOW and a burst of 8 pulses for signal L3CLOCK, accompanied by 8 bits (see Figure 11).

Product data sheet Rev. 02 — 17 January 2005 15 of 55

Philips Semiconductors

The data transfer mode is characterized by signal L3MODE = HIGH and is used to transfer one or more bytes representing a register address, instruction or data.

Basically, two types of data transfers can be deﬁned:

• Write action: data transfer to the device

• Read action: data transfer from the device.

9.2 Device addressing

The device address consists of one byte with:

• Data Operating Mode (DOM) bits 0 and 1 representing the type of data transfer (see

Table 13)

• Address bits 2 to 7 representing a 6-bit device address. The address of the UDA1384

is 01 0100 (bits 2 to 7).

Table 13: Selection of data transfer

DOM Transfer

UDA1384

Multichannel audio coder-decoder

Bit 1 Bit 0

0 0 not used 0 1 not used 1 0 write data or prepare read 1 1 read data

9.3 Register addressing

After sending the device address (including DOM bits), indicating whether the information is to be read or written, one data byte is sent using bit 0 to indicate whether the information will be read or written and bits 1 to 7 for the destination register address.

Basically, there are 3 methods for register addressing:

1. Addressing for write data: bit 0 is logic 0 indicating a write action to the destination register, followed by bits 1 to 7 indicating the register address (see Figure 11).

2. Addressing for prepare read: bit is logic 1, indicating that data will be read from the register (see Figure 12).

3. Addressing for data read action. Here, the device returns a register address prior to sending data from that register. When bit 0 is logic 0, the register address is valid; when bit 0 is logic 1, the register address is invalid (see Figure 12).

Product data sheet Rev. 02 — 17 January 2005 16 of 55

Philips Semiconductors

UDA1384

Multichannel audio coder-decoder

mbl565

mbl567

data byte 1 data byte 2

L3CLOCK

data byte 1 data byte 2

device address

L3MODE

write

10 0

DOM bits

L3DATA

requesting

0/1

valid/invalid

read

prepare read sent by the device

device address

111 0

DOM bits

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xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x

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Fig 11. Data write mode

L3CLOCK

L3MODE

L3DATA

Fig 12. Data read mode

Product data sheet Rev. 02 — 17 January 2005 17 of 55

Philips Semiconductors

9.4 Data write mode

The data write mode is explained in the signal diagram of Figure 11. For writing data to a device, 4 bytes must be sent (see Table 14):

1. Byte 1 starting with ‘01’ for signalling the write action to the device, followed by the device address ‘01 0100’

2. Byte2 starting with a ‘0’ for signalling the write action, followed by 7 bits indicating the destination address in binary format with bit A6 being the MSB and bit A0 being the LSB

3. Byte 3 with bit D15 being the MSB

4. Byte 4 with bit D0 being the LSB

It should be noted that each time a new destination register address needs to be written, the device address must be sent again.

Table 14: L3-bus write data

Byte L3-bus

1 address device

2 data

3 data

4 data

mode

transfer

UDA1384

Multichannel audio coder-decoder

Action First in time Latest in time

Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7

01010100

address register

address data

byte 1 data

byte 2

0 A6A5A4A3A2A1A0

D15 D14 D13 D12 D11 D10 D9 D8

D7 D6 D5 D4 D3 D2 D1 D0

9.5 Data read mode

To read data from the device, a prepare read must ﬁrst be done and then data read. The data read mode is explained in the signal diagram of Figure 12.

For reading data from a device, the following 6 bytes are involved (see Table 15):

1. Byte 1 with the device address, including ‘01’ for signalling the write action to the device.

2. Byte 2 is sent with the register address from which data needs to be read. This byte starts with a ‘1’, which indicates that there will be a read action from the register, followed by 7 bits for the destination address in binary format, with bit A6 being the MSB and bit A0 being the LSB.

3. Byte 3 with the device address, including ‘11’ is sent to the device. The ‘11’ indicates that the device must write data to the microcontroller.

4. Byte 4 sent by the device to the bus, with the (requested) register address and a ﬂag bit indicating whether the requested register was valid (bit is logic 0) or invalid (bit is logic 1).

5. Byte 5 sent by the device to the bus, with the data information in binary format, with bit D15 being the MSB.

6. Byte 6 sent by the device to the bus, with the data information in binary format, with bit D0 being the LSB.

Product data sheet Rev. 02 — 17 January 2005 18 of 55

Philips Semiconductors

Table 15: L3-bus read data

Byte L3-bus

1 address device

2 data

3 address device

4 data

5 data

6 data

10. I2C-bus interface

mode

transfer

UDA1384

Multichannel audio coder-decoder

Action First in time Latest in time

Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7

01010100

address register

address

address register

address data

byte 1 data

byte 2

1 A6A5A4A3A2A1A0

11010100

0 or 1A6A5A4A3A2A1A0

D15 D14 D13 D12 D11 D10 D9 D8

D7 D6 D5 D4 D3 D2 D1 D0

10.1 General

The UDA1384 has an I2C-bus microcontroller interface. All the features are accessible with the I2C-bus interface protocol. In the I2C-bus mode, the DAC mute function is accessible via pin MCMODE with signal QMUTE.

The exchange of data and control information between the microcontroller and the UDA1384 is accomplished through a serial hardware interface comprising the following pins as shown in Table 11:

• MCCLK: clock line with signal SCL

• MCDATA: data line with signal SDA

10.2 Characteristics of the I2C-bus

The bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to the supply voltage VDD via a pull-up resistor when connected to the output stages of a microcontroller. For a 400 kHz IC, the recommendation for this type of bus from Philips Semiconductors must be followed (e.g. up to loads of 200 pF on the bus a pull-up resistor can be used, between 200 pF and 400 pF a current source or switched resistor must be used). Data transfer can only be initiated when the bus is not busy.

10.3 Bit transfer

One data bit is transferred during each clock pulse (see Figure 13). The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals. The maximum clock frequency is 400 kHz.

To be able to run on this high frequency, all the inputs and outputs connected to this bus must be designed for this high-speed I2C-bus according to the Philips speciﬁcation.

Product data sheet Rev. 02 — 17 January 2005 19 of 55

Philips Semiconductors

UDA1384

Multichannel audio coder-decoder

SDA

SCL

Fig 13. Bit transfer on the I2C-bus

10.4 Byte transfer

Each byte (8 bits) is transferred with the MSB ﬁrst (see Table 16).

Table 16: Byte transfer

Bit number

MSB LSB

76543210

10.5 Data transfer

A device generating a message is a transmitter; a device receiving a message is the receiver. The device that controls the message is the master and the devices which are controlled by the master are the slaves.

10.6 Start and stop conditions

Both data and clock line will remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH, is deﬁned as a start condition (S); see

Figure 14. A LOW-to-HIGH transition of the data line while the clock is HIGH is deﬁned as

a stop condition (P).

data line

stable;

data valid

change

of data

allowed

mbc621

SDA

SCL

START condition

STOP condition

SDA

SCL

mbc622

Fig 14. START and STOP conditions on the I2C-bus

10.7 Acknowledgment

The number of data bits transferred between the start and stop conditions from the transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit (see Figure 15). At the acknowledge bit the data line is released by the master and the master generates an extra acknowledge related clock pulse.

Product data sheet Rev. 02 — 17 January 2005 20 of 55

Philips Semiconductors

A slave receiver which is addressed, must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter.

The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Set-up and hold times must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a stop condition.

data output

by transmitter

data output

by receiver

UDA1384

Multichannel audio coder-decoder

not acknowledge

acknowledge

SCL from

master

Fig 15. Acknowledge on the I2C-bus

10.8 Device address

Before any data is transmitted on the I2C-bus, the device which should respond is addressed ﬁrst. The addressing is always done with byte 1 transmitted after the start procedure. The UDA1384 acts as a slave receiver or a slave transmitter.

Therefore, the clock signal SCL is only an input signal. The data signal SDA is a bidirectional line. The UDA1384 device address is shown in Table 17.

Table 17: I2C-bus device address of UDA1384

Device address R/W

A6 A5 A4 A3 A2 A1 A0

00110000/1

10.9 Register address

The register addresses in the I2C-bus mode are the same as in the L3-bus mode. The register addresses are deﬁned in Section 11.

START

condition

9821

clock pulse for

acknowledgement

mbc602

10.10 Write and read data

The I2C-bus conﬁgurations for a write and read cycle are shown in Table 18 and Table 19, respectively.

Product data sheet Rev. 02 — 17 January 2005 21 of 55

Philips Semiconductors

The write cycle is used to write groups of two bytes to the internal registers for the settings. It is also possible to read the registers for the device status information.

10.11 Write cycle

The I2C-bus conﬁguration for a write cycle is shown in Table 18. The write cycle is used to write the data to the internal registers. The device and register addresses are one byte each, the setting data is always a pair of two bytes.

The format of the write cycle is as follows:

1. The microcontroller starts with a start condition (S).

2. The ﬁrst byte (8 bits) contains the device address ‘0011 000’ and a logic 0 (write) for the R/W bit.

3. This is followed by an acknowledge (A) from the UDA1384.

4. After this the microcontroller writes the 8-bit register address (ADDR) where the writing of the register content of the UDA1384 must start.

5. The UDA1384 acknowledges this register address (A).

6. The microcontroller sends 2 bytes data with the Most Signiﬁcant (MS) byte ﬁrst and then the Least Signiﬁcant (LS) byte. After each byte an acknowledge is followed from the UDA1384.

7. If repeated groups of 2 bytes data are transmitted, then the register address is auto incremented. After each byte an acknowledge is followed from the UDA1384.

8. Finally, the UDA1384 frees the I2C-bus and the microcontroller can generate a stop condition (P).

UDA1384

Multichannel audio coder-decoder

Table 18: Master transmitter writes to UDA1384 registers in the I2C-bus mode

Device address

S 0011 000 0 A ADDR A MS1 A LS1 A MS2 A LS2 A MSn A LSn A P

A = acknowledge from UDA1384

[1] Auto increment of register address.

10.12 Read cycle

The read cycle is used to read the data values from the internal registers. The I2C-bus conﬁguration for a read cycle is shown in Table 19.

The format of the read cycle is as follows:

1. The microcontroller starts with a start condition (S).

2. The ﬁrst byte (8 bits) contains the device address ‘0011 000’ and a logic 0 (write) for the R/W bit.

3. This is followed by an acknowledge (A) from the UDA1384.

4. After this the microcontroller writes the 8-bit register address (ADDR) where the reading of the register content of the UDA1384 must start.

5. The UDA1384 acknowledges this register address.

6. Then the microcontroller generates a repeated start (Sr).

R/W Register

address

Data 1 Data 2

[1]

Data n

[1]

Product data sheet Rev. 02 — 17 January 2005 22 of 55

Philips Semiconductors

UDA1384

Multichannel audio coder-decoder

7. Thenthe microcontroller generates the device address ‘0011 000’ again, but this time followed by a logic 1 (read) of the R/W bit. An acknowledge is followed from the UDA1384.

8. The UDA1384 sends 2 bytes data with the Most Signiﬁcant (MS) byte ﬁrst and then the Least Signiﬁcant (LS) byte. After each byte an acknowledge is followed from the microcontroller (master).

9. If repeated groups of 2 bytes are transmitted, then the register address is auto incremented. After each byte an acknowledge is followed from the microcontroller.

10.The microcontroller stops this cycle by generating a Negative Acknowledge (NA).

11.Finally, the UDA1384 frees the I2C-bus and the microcontroller can generate a stop condition (P).

Table 19: Master transmitter reads from the UDA1384 registers in the I2C-bus mode

Device address

S 0011 000 0 A ADDR A Sr 0011 000 1 A MS1 A LS1 A MS2 A LS2 A MSn A LSn NA P

A = acknowledge from UDA1384 A = acknowledge from master

R/W Register

address

Device address

R/W Data 1 Data 2

[1]

Data n

[1]

[1] Auto increment of register address.

11. Register mapping

In this chapter the register addressing and mapping of the microcontroller interface of the UDA1384 is given.

In Table 20 an overview of the register mapping is given. In Table 21 the actual register mapping is given and the register deﬁnitions are explained

in Section 11.3 to Section 11.14.

11.1 Address mapping

Table 20: Overview of register mapping

Address Function

System settings

00h system 01h audio ADC and DAC subsystem 02h voice ADC system

Status (read out registers)

0Fh status outputs

Interpolator settings

10h DAC channel and feature selection 11h DAC feature control 12h DAC channel1 13h DAC channel2 14h DAC channel3 15h DAC channel4

Product data sheet Rev. 02 — 17 January 2005 23 of 55

Philips Semiconductors

UDA1384

Multichannel audio coder-decoder

Table 20: Overview of register mapping

Address Function

16h DAC channel5 17h DAC channel6 18h DAC mixing channel1 19h DAC mixing channel2 1Ah DAC mixing channel3 1Bh DAC mixing channel4 1Ch DAC mixing channel 5 1Dh DAC mixing channel 6

ADC input ampliﬁer gain settings

20h audio ADC input ampliﬁer gain 21h voice ADC input ampliﬁer gain

Supplemental settings

30h supplemental settings 1 31h supplemental settings 2

…continued

Product data sheet Rev. 02 — 17 January 2005 24 of 55

Philips Semiconductors

UDA1384

Multichannel audio coder-decoder

[1]

VFS1 VFS0 VCE VAP DSD SC1 SC0 OP1 OP0 FS1 FS0 ACE ADP DCE DAP

[2]

- 001000000011010

DC PAB PAA MTB MTA AIF2 AIF1 AIF0 DAG FIL DVD DIS1 DIS0 DIF2 DIF1 DIF0

1 000000000000000

0 000000001101000

MIX1 MIX0 MC5 MC4 MC3 MC2 MC1 MC0 SEL1 SEL0 CS5 CS4 CS3 CS2 CS1 CS0

0 000000000000000

ICS1 ICS0 ---PDMTQMVC7VC6VC5VC4VC3VC2VC1VC0

0 000000000000000

11.2 Register mapping

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xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

subsystem

System settings

Add Function D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Table 21: UDA1384 register mapping

Product data sheet Rev. 02 — 17 January 2005 25 of 55

00h system RST

01h audio ADCandDAC

02h voice ADC system - -------BCK1 BCK0 WSM VH1 VH0 PVA MTV VIF

Status (read out only)

0Fh status outputs - ---------VSAS1AS0DS2DS1DS0

feature selection

Interpolator settings

10h DAC channel and

11h DAC feature control ICS1 ICS0 DE2 DE1 DE0 PD MT QM VC7 VC6 VC5 VC4 VC3 VC2 VC1 VC0

12h DAC channel 1 ICS1 ICS0 DE2 DE1 DE0 PD MT QM VC7 VC6 VC5 VC4 VC3 VC2 VC1 VC0

13h DAC channel 2 - - DE2 DE1 DE0 PD MT QM VC7 VC6 VC5 VC4 VC3 VC2 VC1 VC0

14h DAC channel 3 ICS1 ICS0 DE2 DE1 DE0 PD MT QM VC7 VC6 VC5 VC4 VC3 VC2 VC1 VC0

15h DAC channel 4 - - DE2 DE1 DE0 PD MT QM VC7 VC6 VC5 VC4 VC3 VC2 VC1 VC0

16h DAC channel 5 ICS1 ICS0 DE2 DE1 DE0 PD MT QM VC7 VC6 VC5 VC4 VC3 VC2 VC1 VC0

17h DAC channel 6 - - DE2 DE1 DE0 PD MT QM VC7 VC6 VC5 VC4 VC3 VC2 VC1 VC0

channel 1

18h DAC mixing

Philips Semiconductors

UDA1384

Multichannel audio coder-decoder

…continued

[1]

- ----PDMTQMVC7VC6VC5VC4VC3VC2VC1VC0

0 000000000000000

ICS1 ICS0 ---PDMTQMVC7VC6VC5VC4VC3VC2VC1VC0

0 000000000000000

- ----PDMTQMVC7VC6VC5VC4VC3VC2VC1VC0

0 000000000000000

ICS1 ICS0 ---PDMTQMVC7VC6VC5VC4VC3VC2VC1VC0

0 000000000000000

- ----PDMTQMVC7VC6VC5VC4VC3VC2VC1VC0

0 000000000000000

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xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x

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xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

channel 2

19h DAC mixing

Add Function D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Table 21: UDA1384 register mapping

Product data sheet Rev. 02 — 17 January 2005 26 of 55

channel 3

1Ah DAC mixing

channel 4

1Bh DAC mixing

channel 5

1Ch DAC mixing

channel 6

1Dh DAC mixing

- ---IB3IB2IB1IB0----IA3IA2IA1IA0

0 000000000000000

- ----------IV4IV3IV2IV1IV0

- -------00000000

- -------PDT-------

0 000000000000000

- --------DITH2 DITH1 DITH0 - - VMTP PDLNA

input ampliﬁer gain

ADC input ampliﬁer gain settings

20h ADC 1 and ADC 2

ampliﬁer gain

21h voice ADC input

settings 1

Supplemental settings

30h supplemental

settings 2

31h supplemental

0 000000000000000

mute control bits MTA, MTB, MTV, MT and QM are set to logic 1. All other registers have non ﬁxed values.

return valid data.

[1] When writing new settings via the L3-bus interface, the default values should always be set to warrant correct operation. Read access to the DAC features register 11h will not

[2] When bit RST is set to logic 1, the default values are set to all the registers as shown in Table 21. When start-up, all the registers in 00h are initialized as the default valuesandthe

Philips Semiconductors

11.3 System settings

Table 22: System register (address 00h) bit allocation

Bit 15 14 13 12 11 10 9 8 Symbol RST VFS1 VFS0 VCE VAP DSD SC1 SC0 Reset -0010000 Access read and write Bit 7 6 5 4 3 2 1 0 Symbol OP1 OP0 FS1 FS0 ACE ADP DCE DAP Reset 00011010 Access read and write

Table 23: Description of system register bits

Bit Symbol Description

15 RST Reset. Bit RST initializes the L3-bus registers with the default settings.

14 to 13 VFS[1:0] Voice ADC sampling frequency. A 2-bit value to select the voice ADC

12 VCE Voice ADC clock enable.

11 VAP Voice ADC power control. Bit VAP is to reduce the power consumption of

10 DSD DSD mode selection. Bit DSD selects the DSD mode.

9 to 8 SC[1:0] System clock frequency. A 2-bit value to select the used external clock

7 to 6 OP[1:0] Operating mode selection. A 2-bit value to select the operation mode of

5 to 4 FS[1:0] Sampling frequency. A 2-bit value to select the sampling frequency of the

3ACEADC clock enable. Bit ACE enables the audio ADC clock

2 ADP ADC power control. Bit ADP is to reduce the power consumption of the

Multichannel audio coder-decoder

1 = Reset to default settings 0 = No reset

sampling frequency. Default 00. See

1 = clock enabled (default) 0 = clock disabled

the voice ADC.

1 = state is power-on 0 = state is power-off (default)

1 = DSD mode 0 = normal mode (default)

frequency. 128f bit DVD = 1. Default 00. See

the audio ADC and DAC. Default 00. See

audio ADC and DAC in the WSmode. Default 01. See

1 = clock enabled (default) 0 = clock disabled

audio ADC.

1 = state is power-on 0 = state is power-off (default)

system clock for the DAC can be used by setting

Table 25.

Table 24.

Table 26.

UDA1384

Table 27.

Product data sheet Rev. 02 — 17 January 2005 27 of 55

Philips Semiconductors

UDA1384

Multichannel audio coder-decoder

Table 23: Description of system register bits

…continued

Bit Symbol Description

1 DCE DAC clock enable. Bit DCE enables the DAC clock.

1 = clock enabled (default) 0 = clock disabled

0DAPDAC power control. Bit DAP is to reduce the power consumption of the

DAC.

1 = state is power-on 0 = state is power-off (default)

Table 24: Voice ADC sampling frequency bits

VFS1 VFS0 Function

0 0 6.25 kHz to 12.5 kHz (default) 0 1 12.5 kHz to 25 kHz 1 0 25 kHz to 50 kHz 1 1 reserved

Table 25: System clock frequency bits

SC1 SC0 ADC DAC Remark

Bit DVD = 0 Bit DVD = 1

0 0 256f 0 1 384f 1 0 512f 1 1 768f

s s s s

256f 384f 512f 768f

s s s s

128f 192f 256f 384f

s s s s

default

Table 26: Operating mode bits

OP1 OP0 ADC mode DAC mode Remark

0 0 SYSCLK (256f

0 1 SYSCLK (256f 1 0 WSAD (1f

1 1 WSDA (1f

) SYSCLK (128fs, 256fs, 384fs,

) WSDA (1fs)

, 384fs, 512fs or 768fs) SYSCLK (128fs, 256fs, 384fs,

, 384fs, 512fs or 768fs) WSDA (1fs)

512f

or 768fs)

default

Table 27: Audio ADC and DAC sampling frequency bits

FS1 FS0 Function

0 0 12.5 kHz to 25 kHz 0 1 25 kHz to 50 kHz (default) 1 0 50 kHz to 100 kHz 1 1 100 kHz to 200 kHz

Product data sheet Rev. 02 — 17 January 2005 28 of 55

Philips Semiconductors

UDA1384

Multichannel audio coder-decoder

11.4 Audio ADC and DAC subsystem settings

Table 28: Audio ADC and DAC subsystem register (address 01h) bit allocation

Bit 15 14 13 12 11 10 9 8 Symbol DC PAB PAA MTB MTA AIF2 AIF1 AIF0 Reset 10000000 Access read and write Bit 7 6 5 4 3 2 1 0 Symbol DAG FIL DVD DIS1 DIS0 DIF2 DIF1 DIF0 Reset 00000000 Access read and write

Table 29: Description of the audio ADC and DAC subsystem register bit

Bit Symbol Description

15 DC ADC DC-ﬁlter. Bit DC enables the digital DC-ﬁlter of the ADC.

1 = DC-ﬁltering is active (default) 0 = no DC-ﬁltering

14 PAB Polarity ADC 2 control. Bit PAB controls the ADC 2 polarity.

1 = polarity is inverted 0 = polarity is not-inverted (default)

13 PAA Polarity ADC 1 control. Bit PAA controls the ADC 1 polarity.

1 = polarity is inverted 0 = polarity is not-inverted (default)

12 MTB Mute ADC 2. Bit MTB enables the digital mute of ADC 2.

1 = ADC 2 is soft muted 0 = ADC 2 is not muted (default)

11 MTA Mute ADC 1. Bit MTA enables the digital mute of ADC 1.

1 = ADC 1 is soft muted 0 = ADC 1 is not muted (default)

10 to 8 AIF[2:0] ADC output data interface format. A 3-bit value to select the used data

format to the I

7DAGDAC gain switch. Bit DAG selects the DAC gain.

1=gain=6dB 0 = gain = 0 dB (default)

6 FIL Filter selection. Bit FIL selects the interpolation ﬁlter characteristics.

1 = slow roll-off 0 = sharp roll-off (default)

5DVD192 kHz sampling mode selection. Bit DVDselects the oversampling rate

of the noise shaper.

1 = 64f 0 = 128f

4 to 3 DIS[1:0] Data interface selection. A 2-bit value to select the data interface

connection. Default 00. See

2 to 0 DIF[2:0] DAC input data interface format. A 3-bit value to select the used data

format to the I

Product data sheet Rev. 02 — 17 January 2005 29 of 55

S-bus ADC output interface. Default 000. See Table 30.

rate; used for 192 kHz and 176.4 kHz sampling frequencies

rate (default)

Table 31.

S-bus DAC input interface. Default000. See Table 30.

Philips Semiconductors

Table 30: Data interface format bits

AIF2 AIF1 AIF0 Function DIF2 DIF1 DIF0

000I 0 0 1 LSB-justiﬁed format, 16 bits 0 1 0 LSB-justiﬁed format, 20 bits 0 1 1 LSB-justiﬁed format, 24 bits 1 0 0 MSB-justiﬁed format 1 0 1 multichannel format, 20 bits 1 1 0 multichannel format, 24 bits (format 1) 1 1 1 multichannel format, 24 bits (format 2)

Table 31: Data interface selection bits

DIS1 DIS0 Input to DAC

0 0 DATADA1 to DAC channel 1 and 2, DATADA2 to DAC channel 3

0 1 DATADA1 to DAC channels 1 to 6 1 0 DATADA2 to DAC channels 1 to 6 1 1 DATADA3 to DAC channels 1 to 6

UDA1384

Multichannel audio coder-decoder

S-bus format (default)

and 4, and DATADA3 to DAC channel 5 and 6 (default)

11.5 Voice ADC system settings

Table 32: Voice ADC system register (address 02h) bit allocation

Bit 15 14 13 12 11 10 9 8 Symbol -------Reset -------Access read and write Bit 7 6 5 4 3 2 1 0 Symbol BCK1 BCK0 WSM VH1 VH0 PVA MTV VIF Reset 01101000 Access read and write

Table 33: Description of the voice ADC system register bits

Bit Symbol Description

15 to 8 - default 0000 0000 7 to 6 BCK[1:0] BCK frequency of voice ADC. A 2-bit value to select the BCK

frequency of the voice ADC in the WSV-out mode. Default 01.

Table 34.

See

5 WSM WSV mode selection. Bit WSM selects the WSV mode of the voice

ADC

1 = WSV-in mode (default) 0 = WSV-out mode

4 to 3 VH[1:0] Voice ADC high-pass ﬁlter setting. A 2-bit value to enable the

high-pass ﬁlter of the voice ADC. Default 01. See

Table 35.

Product data sheet Rev. 02 — 17 January 2005 30 of 55

Philips Semiconductors

UDA1384

Multichannel audio coder-decoder

Table 33: Description of the voice ADC system register bits

…continued

Bit Symbol Description

2PVA Polarity voice ADC control. Bit PVA controls the voice ADC polarity.

1 = polarity is inverted 0 = polarity is not-inverted (default)

1 MTV Mute voice ADC. Bit MTV enables the digital mute of the voice ADC.

1 = ADC 1 is soft muted 0 = ADC 1 is not muted (default)

0 VIF Voice ADC interface format. Bit VIF selects the data interface format

of the voice ADC.

1 = mono-channel format

S-bus format (default)

0=I

Table 34: BCK frequency of voice ADC bits

BCK1 BCK0 Function

0 0 32f

0 1 64fs (default) 1 0 128f 1 1 256f

s s

Table 35: Voice ADC high-pass ﬁlter setting bits

VH1 VH0 Function

0 0 high-pass ﬁlter off 01f 10f 11f

= 0.00008fs (default)

= 0.0125f

= 0.025f

Product data sheet Rev. 02 — 17 January 2005 31 of 55

Philips Semiconductors

11.6 Status output register

Table 36: Status output register (address 0Fh) bit allocation

Bit 15 14 13 12 11 10 9 8 Symbol -------Reset -------Access read only Bit 7 6 5 4 3 2 1 0 Symbol - - VS AS1 AS0 DS2 DS1 DS0 Reset -------Access read only

Table 37: Description of status output register bits

Bit Symbol Description

15 to 6 - not used 5VSVoice ADC status. Bit VS indicates the hard mute status of the voice ADC.

4 AS1 ADC 2 status. Bit AS1 indicates the hard mute status of ADC 2.

3 AS0 ADC 1 status. Bit AS0 indicates the hard mute status of ADC 1.

2 DS2 DAC channel 5 and 6 status. Bit DS2 indicates the hard mute status of DAC

1 DS1 DAC channel 3 and 4 status. Bit DS1 indicates the hard mute status of DAC

0 DS0 DAC channel 1 and 2 status. Bit DS0 indicates the hard mute status of DAC

UDA1384

Multichannel audio coder-decoder

1 = power-down is ready and the clock may be disabled 0 = power-down is not ready and the clock should not be disabled

channel 5 and 6.

1 = power-down is ready and the clock may be disabled 0 = power-down is not ready and the clock should not be disabled

channel 3 and 4.

1 = power-down is ready and the clock may be disabled 0 = power-down is not ready and the clock should not be disabled

channel 1 and 2.

1 = power-down is ready and the clock may be disabled 0 = power-down is not ready and the clock should not be disabled

Product data sheet Rev. 02 — 17 January 2005 32 of 55

Philips Semiconductors

11.7 DAC channel selection

Table 38: DAC channel select register (address 10h) bit allocation

Bit 15 14 13 12 11 10 9 8 Symbol MIX1 MIX0 MC5 MC4 MC3 MC2 MC1 MC0 Reset 00000000 Access read and write Bit 7 6 5 4 3 2 1 0 Symbol SEL1 SEL0 CS5 CS4 CS3 CS2 CS1 CS0 Reset 00000000 Access read and write

Table 39: Description of DAC channel select register bits

Bit Symbol Description

15 to 14 MIX[1:0] DAC mixer setting. A 2-bit value to enable the DAC mixer. Default 00.

13 to 8 MC[5:0] DAC mixing channel selection. A group of 6 enable bits to make DAC

7 and 6 SEL[1:0] Feature selection. A 2-bit value to select the features to be set through

5 to 0 CS[5:0] DAC channel selection. A group of 6 enable bits to make DAC channel

UDA1384

Multichannel audio coder-decoder

Table 40.

See

mixing channels ready for receiving feature settings through register address 11h. Only selected registers accept new settings. Default 00 0000 (no channel ready). See

register address 11h. When the feature settings are written, only selected feature settings are changed and non selected features are kept unchanged. Default 00. See

ready for receiving feature settings through register address 11h. Default 00 0000 (no channel ready). See

Table 41.

Table 42.

Table 41.

Table 40: DAC mixer setting bits

MIX1 MIX0 Function

0 0 no mixing (default) 0 1 no mixing 1 0 mixing ADC 1 1 1 mixing ADC 2

Table 41: DAC channel and mixing channel selection bits

MC5 MC4 MC3 MC2 MC1 MC0 Function

CS5 CS4 CS3 CS2 CS1 CS0

000000no channel ready (default) 000001channel 1 selected

::::::

001010channel 2 and channel 4 selected

::::::

111111all channels selected

Product data sheet Rev. 02 — 17 January 2005 33 of 55

Philips Semiconductors

Table 42: Feature selection bits

SEL1 SEL0 Function

0 0 all features (default) 0 1 volume 1 0 mute and quick mute 1 1 de-emphasis, polarity and input channel selection

11.8 DAC features settings

Table 43: DAC features register (address 11h) bit allocation

Bit 15 14 13 12 11 10 9 8 Symbol ICS1 ICS0 DE2 DE1 DE0 PD MT QM Reset 00000000 Access read and write Bit 7 6 5 4 3 2 1 0 Symbol VC7 VC6 VC5 VC4 VC3 VC2 VC1 VC0 Reset 00000000 Access read and write

UDA1384

Multichannel audio coder-decoder

Table 44: Description of DAC features register bits

Bit Symbol Description

15 to 14 ICS[1:0] Inputchannelselection.A2-bitvaluetoselectthe input channels. As

the controlled channels are paired off, this 2-bit value must be written to each odd channel register. Default 00. See

13 to 11 DE[2:0] De-emphasis setting. A 3-bit value to enable the digital de-emphasis

ﬁlter. Default 000. See

10 PD Polarity DAC control. Bit PD controls the DAC polarity.

1 = polarity is inverted 0 = polarity is not-inverted (default)

9MT Muting. Bit MT enables the digital mute. All the DAC outputs are

muted at start-up. It is necessary to explicitly switch off for the audio output by means of bit MT.

1 = muting (start-up) 0 = no muting (default)

8QM Quick mute. Bit QM sets the quick mute mode.

1 = quick mute mode 0 = soft mute mode (default)

7 to 0 VC[7:0] Interpolator volume control. An 8-bit value to program the volume

attenuation of each channel. The range is from 0 dB to −53 dB in steps of 0.25 dB, from −53 dB to −80 dB in steps of 3 dB and −∞ dB. Default 0000 0000. See

Table 46.

Table 47.

Table 45.

Product data sheet Rev. 02 — 17 January 2005 34 of 55

Philips Semiconductors

Table 45: Input channel selection bits

ICS1 ICS0 Input to DAC output

0 0 left channel input data to odd channel output; right channel input

0 1 left channel input data to odd and even channel outputs 1 0 right channel input data to odd and even channel outputs 1 1 left channel input data to even channel output; right channel input

Table 46: De-emphasis bits

DE2 DE1 DE0 Function

0 0 0 no de-emphasis (default) 0 0 1 de-emphasis of 32 kHz 0 1 0 de-emphasis of 44.1 kHz 0 1 1 de-emphasis of 48 kHz 1 0 0 de-emphasis of 96 kHz 1 0 1 not used 1 1 0 not used 1 1 1 not used

UDA1384

Multichannel audio coder-decoder

data to even channel output

data to odd channel output

Table 47: Interpolator volume control bits

VC7 VC6 VC5 VC4 VC3 VC2 VC1 VC0 Volume (dB)

000000000 (default) 00000001−0.25 00000010−0.50 00000011−0.75 00000100−1.00 00000101−1.25

:::::::::

11010100−53 11011000−56 11011100−59 11100000−62 11100100−65 11101000−68 11101100−71 11110000−74 11110100−77 11111000−80 11111100−∞

:::::::::

11111111−∞

Product data sheet Rev. 02 — 17 January 2005 35 of 55

Philips Semiconductors

11.9 DAC channel 1 to channel 6 settings

All the DAC features which are written in register 11h are copied into the odd channel registers.

Table 48: DAC channel 1, 3 and 5 registers (address 12h, 14h and 16h) bit allocation

Bit 15 14 13 12 11 10 9 8 Symbol ICS1 ICS0 DE2 DE1 DE0 PD MT QM Reset 00000000 Access read and write Bit 7 6 5 4 3 2 1 0 Symbol VC7 VC6 VC5 VC4 VC3 VC2 VC1 VC0 Reset 00000000 Access read and write

All the DAC features which are written in register 11h are copied into the even channel registers, except the bits ICS[1:0].

Table 49: DAC channel 2, 4 and 6 registers (address 13h, 15h and 17h) bit allocation

Bit 15 14 13 12 11 10 9 8 Symbol - - DE2 DE1 DE0 PD MT QM Reset 00000000 Access read and write Bit 7 6 5 4 3 2 1 0 Symbol VC7 VC6 VC5 VC4 VC3 VC2 VC1 VC0 Reset 00000000 Access read and write

UDA1384

Multichannel audio coder-decoder

11.10 DAC mixing channel settings

All the DAC features which are written in register 11h are copied into the odd mixing channel registers, except the bits DE[2:0].

Table 50: DAC mixing channel 1, 3 and 5 registers (address 18h, 1Ah and 1Ch) bit

allocation

Bit 15 14 13 12 11 10 9 8 Symbol ICS1 ICS0 - - - PD MT QM Reset 00000000 Access read and write Bit 7 6 5 4 3 2 1 0 Symbol VC7 VC6 VC5 VC4 VC3 VC2 VC1 VC0 Reset 00000000 Access read and write

Product data sheet Rev. 02 — 17 January 2005 36 of 55

Philips Semiconductors

All the DAC features which are written in register 11h are copied into the even channel registers, except the bits ICS[1:0] and DE[2:0].

Table 51: DAC mixing channel 2, 4 and 6 registers (address 19h, 1Bh and 1Dh) bit

Bit 15 14 13 12 11 10 9 8 Symbol -----PDMTQM Reset 00000000 Access read and write Bit 7 6 5 4 3 2 1 0 Symbol VC7 VC6 VC5 VC4 VC3 VC2 VC1 VC0 Reset 00000000 Access read and write

11.11 Audio ADC 1 and ADC 2 input ampliﬁer gain settings

Table 52: Audio ADC input ampliﬁer gain register (address 20h) bit allocation

Bit 15 14 13 12 11 10 9 8 Symbol ----IB3IB2IB1IB0 Reset 00000000 Access read and write Bit 7 6 5 4 3 2 1 0 Symbol ----IA3IA2IA1IA0 Reset 00000000 Access read and write

UDA1384

Multichannel audio coder-decoder

allocation

Table 53: Description of audio ADC input ampliﬁer gain register bits

Bit Symbol Description

15 to 12 - default 0000 11 to 8 IB[3:0] Audio ADC 2 input ampliﬁer gain. A 4-bit value to program the input

ampliﬁer gain in steps of 3 dB (9 settings). Default 0000. See 7 to 4 - default 0000 3 to 0 IA[3:0] Audio ADC 1 input ampliﬁer gain. A 4-bit value to program the input

ampliﬁer gain in steps of 3 dB (9 settings). Default 0000. See

Table 54: Audio ADC input ampliﬁer gain bits

IA3 IA2 IA1 IA0 Gain (dB) IB3 IB2 IB1 IB0

00000 (default) 0001+3 0010+6 0011+9 0100+12 0101+15

Product data sheet Rev. 02 — 17 January 2005 37 of 55

Table 54.

Philips Semiconductors

UDA1384

Multichannel audio coder-decoder

Table 54: Audio ADC input ampliﬁer gain bits

IA3 IA2 IA1 IA0 Gain (dB) IB3 IB2 IB1 IB0

0110+18 0111+21 1000+24

11.12 Voice ADC gain settings

Table 55: Voice ADC input ampliﬁer gain register (address 21h) bit allocation

Bit 15 14 13 12 11 10 9 8 Symbol -------Reset -------Access read and write Bit 7 6 5 4 3 2 1 0 Symbol - - - IV4 IV3 IV2 IV1 IV0 Reset 00000000 Access read and write

Table 56: Description of voice ADC input ampliﬁer gain register bits

Bit Symbol Description

15 to 8 - not used 7 to 5 - default 000 4 to 0 IV[4:0] Voice ADC input ampliﬁer gain. A 5-bit value to program the voice

ampliﬁer gain in steps of 1.5 dB (21 settings). Default 0 0000.

See

…continued

Table 57.

Table 57: Voice ADC input ampliﬁer gain bits

IV4 IV3 IV2 IV1 IV0 Gain (dB)

000000 (default) 00001+1.5 00010+3 00011+4.5 00100+6 00101+7.5

:::::: 10011+28.5 10100+30

:::::not used 11111not used

Product data sheet Rev. 02 — 17 January 2005 38 of 55

Philips Semiconductors

11.13 Supplemental settings 1

Table 58: Supplemental settings 1 register (address 30h) bit allocation

Bit 15 14 13 12 11 10 9 8 Symbol -------Reset 00000000 Access read and write Bit 7 6 5 4 3 2 1 0 Symbol PDT------- Reset 00000000 Access read and write

Table 59: Description of supplemental settings 1 register bits

Bit Symbol Description

15 to 8 - default 0000 0000 7 PDT Power down time. Bit PDT selects the time of the SDAC power-down

6 to 0 - default 000 0000

sequence.

1 = 1024/f 0 = 512/f

seconds

seconds (default)

UDA1384

Multichannel audio coder-decoder

11.14 Supplemental settings 2

Table 60: Supplemental settings 2 register (address 31h) bit allocation

Bit 15 14 13 12 11 10 9 8 Symbol -------Reset 00000000 Access read and write Bit 7 6 5 4 3 2 1 0 Symbol - DITH2 DITH1 DITH0 - - VMTP PDLNA Reset 00000000 Access read and write

Table 61: Description of supplemental settings 2 register bits

Bit Symbol Description

15 to 7 - default 0000 0000 0 6 to 4 DITH[2:0] DAC dither control. A 3-bit value to control the dithering of the SDAC.

Default 000. See 3 to 2 - default 00 1 VMTP Voice mute period control. Bit VMPT selects the voice ADC mute

period at power-up.

1 = mute for 1024 samples (1024/f 0 = mute for 2048 samples (2048/f

Table 62.

)

; default)

Product data sheet Rev. 02 — 17 January 2005 39 of 55

Philips Semiconductors

UDA1384

Multichannel audio coder-decoder

Table 61: Description of supplemental settings 2 register bits

Bit Symbol Description 0 PDLNA Power-down voice LNA. Bit PDLNA is to power-down the voice ADC

Table 62: DAC dither control bits

DITH2 DITH1 DITH0 Function

12. Limiting values

…continued

LNA. It should be noted that disabling the LNA requires a recovery

time deﬁned by the external RC circuit.

1 = power-down 0 = power-on (default)

0 0 0 DC dither (mid level); default 0 0 1 reserved 0 1 0 reserved 0 1 1 reserved 1 0 0 DC dither (low level) 1 0 1 DC plus AC dither (low level) 1 1 0 DC dither (high level) 1 1 1 DC plus AC dither (high level)

Table 63: Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

xtal(max)

supply voltage maximum crystal

temperature T T V

stg amb

esd

storage temperature −65 +125 °C

ambient temperature −20 +85 °C

electrostatic discharge

voltage

[1] All supply connections must be made to the same power supply. [2] ESD behavior is tested in accordance with JEDEC II standard:

a) Human Body Model (HBM); equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series

resistor.

b) Machine Model (MM); equivalent to discharging a 200 pF capacitor through a 0.75 µH series inductor.

13. Thermal characteristics

Table 64: Thermal characteristics

Symbol Parameter Conditions Typ Unit

th(j-a)

thermal resistance from junction

to ambient

[1]

- 4.0 V

- 150 °C

HBM MM

[2]

−2000 +2000 V

[2]

−200 +200 V

in free air 85 K/W

Product data sheet Rev. 02 — 17 January 2005 40 of 55

Philips Semiconductors

UDA1384

Multichannel audio coder-decoder

14. Static characteristics

Table 65: Characteristics

DDD=VDDA(AD)=VDDA(DA)

speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Supplies

DDA(AD)

ADC analog supply voltage

DDA(DA)

DAC analog supply voltage

DDD

DDA(AD)

digital supply voltage ADC analog supply

current

DDA(DA)

DAC analog supply current

DDD

DDD(pd)

digital supply current f

digital supply current in Power down-mode

Digital input pins (5 V tolerant TTL compatible)

HIGH-level input voltage

LOW-level input voltage

 input leakage current - - 1 µA

I

input capacitance - - 10 pF

Digital output pins

HIGH-level output voltage

LOW-level output voltage

Analog-to-digital converter

ref

ADCP

reference voltage on pin V

ref

positive reference voltage of ADC

ADCN

negative reference voltage of ADC

i(ADC)

output resistance on pin V

ref

input resistance of audio ADC

= 3.3 V; T

=25°C; RL=22kΩ; all voltages referenced to ground (pins VSS); unless otherwise

amb

[1]

2.7 3.3 3.6 V

[1]

2.7 3.3 3.6 V

[1]

2.7 3.3 3.6 V

= 48 kHz - 30 - mA

ADC

= 96 kHz - 31 - mA

ADC

= 48 kHz - 20 - mA

DAC

= 96 kHz - 32 - mA

DAC

= f

DAC

= 48 kHz

= f

DAC

= 48 kHz

= 48 kHz;

= 96 kHz;

ADC

VOICE

ADC

VOICE

audio and voice ADCs

-31-mA

-55-mA

-18-mA

power-down DAC power-down - 14 - mA

2.0 - - V

- - 0.8 V

IOH = −2 mA 0.85V

DDD

--V

IOL = 2 mA - - 0.4 V

with respect to V

SSA(AD)

0.45V

DDA(AD)

-V

0.5V

DDA(AD)

0.55V

DDA(AD)

-V

0.0 0.0 0.0 V

-5-kΩ

-10-kΩ

Product data sheet Rev. 02 — 17 January 2005 41 of 55

Philips Semiconductors

UDA1384

Multichannel audio coder-decoder

Table 65: Characteristics

DDD=VDDA(AD)=VDDA(DA)

…continued

= 3.3 V; T

=25°C; RL=22kΩ; all voltages referenced to ground (pins VSS); unless otherwise

amb

speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

i(VADC)

input resistance of

-5-kΩ

voice ADC

Digital-to-analog converter

[1] All supply connections must be made to the same power supply unit.

load resistance 4 - - kΩ output resistance - 1 - kΩ

15. Dynamic characteristics

Table 66: Characteristics

= V

DDD

referenced to ground (pins V

Symbol Parameter Conditions Min Typ Max Unit

Audio analog-to-digital converter

∆V

DDA(AD)

= V

= 3.3 V; fi = 1 kHz; T

DDA(DA)

); unless otherwise speciﬁed.

= 25°C; RL = 22 kΩ; sampling frequency fs = 48 kHz; all voltages

amb

digital output level at 0 dB setting; 900 mV input

at 3 dB setting; 637 mV input at 6 dB setting; 451 mV input at 9 dB setting; 319 mV input at 12 dB setting; 226 mV input at 15 dB setting; 160 mV input at 18 dB setting; 113 mV input at 21 dB setting; 80 mV input at 24 dB setting; 57 mV input

input voltage unbalance between channels

[1] [2]

−2.5 −1.2 −0.7 dB

[2]

- −1.2 - dB

[2]

- −1.2 - dB

[2]

- −1.2 - dB

[2]

- −1.2 - dB

[2]

- −1.2 - dB

[2]

- −1.2 - dB

[2]

- −1.2 - dB

[2]

- −1.2 - dB

- 0.1 - dB

Product data sheet Rev. 02 — 17 January 2005 42 of 55

Philips Semiconductors

UDA1384

Multichannel audio coder-decoder

Table 66: Characteristics

DDD

= V

DDA(AD)

= V

DDA(DA)

referenced to ground (pins V

…continued

= 3.3 V; fi = 1 kHz; T

); unless otherwise speciﬁed.

amb

= 25°C; RL = 22 kΩ; sampling frequency fs = 48 kHz; all voltages

Symbol Parameter Conditions Min Typ Max Unit

(THD + N)/S total harmonic

distortion-plus-noise to signal ratio

normal mode; at −1 dBFS

at 0 dB setting - −88 −82 dB at 3 dB setting - −88 - dB at 6 dB setting - −88 - dB at 9 dB setting - −88 - dB at 12 dB setting - −88 - dB at 15 dB setting - −87 - dB at 18 dB setting - −85 - dB at 21 dB setting - −83 - dB at 24 dB setting - −82 - dB

normal mode; at −60 dBFS; A-weighted

at 0 dB setting - −37 −30 dB at 3 dB setting - −37 - dB at 6 dB setting - −37 - dB at 9 dB setting - −37 - dB at 12 dB setting - −37 - dB at 15 dB setting - −37 - dB at 18 dB setting - −35 - dB at 21 dB setting - −32 - dB at 24 dB setting - −30 - dB

S/N signal-to-noise ratio code = 0; A-weighted 89 98 - dB

channel separation - 100 - dB

Voice analog-to-digital converter

i(rms)

input voltage (RMS value) at 0 dBFS digital output; 2.2 kΩ

- 50.0 - mV

source impedance

(THD + N)/S total harmonic

distortion-plus-noise to signal ratio

at −1 dBFS - −78 - dB at −20 dBFS - −65 - dB at −40 dBFS; A-weighted - −47 - dB

S/N signal-to-noise ratio code = 0; A-weighted - 87 - dB

Digital-to-analog converter

Differential mode

V ∆V

o(rms)

output voltage (RMS value) at 0 dBFS digital input 1.9 2.0 2.1 V output voltage unbalance between

- < 0.1 - dB

channels

(THD + N)/S total harmonic

distortion-plus-noise to signal ratio

at 0 dBFS - −98 −93 dB at −20 dBFS - −90 - dB at −60 dBFS; A-weighted - −50 −45 dB

S/N signal-to-noise ratio code = 0; A-weighted 100 110 - dB

channel separation - 114 - dB

Product data sheet Rev. 02 — 17 January 2005 43 of 55

Philips Semiconductors

UDA1384

Multichannel audio coder-decoder

Table 66: Characteristics

DDD

= V

DDA(AD)

= V

DDA(DA)

referenced to ground (pins V

…continued

= 3.3 V; fi = 1 kHz; T

); unless otherwise speciﬁed.

amb

= 25°C; RL = 22 kΩ; sampling frequency fs = 48 kHz; all voltages

Symbol Parameter Conditions Min Typ Max Unit

Single-ended mode

V ∆V

o(rms)

output voltage (RMS value) at 0 dBFS digital input - 1.0 - V output voltage unbalance between

- < 0.1 - dB

channels

(THD + N)/S total harmonic

distortion-plus-noise to signal ratio

at 0 dBFS - −88 - dB at −20 dBFS - −85 - dB at −60 dBFS; A-weighted - −45 - dB

S/N signal-to-noise ratio code = 0; A-weighted - 105 - dB

[1] The input voltage can be up to 2 V (RMS) when the current through the ADC input pin is limited to approximately 1 mA by using a series

resistor.

[2] The input voltage to the ADC scales proportionally with the power supply voltage.

channel separation - 110 - dB

15.1 Timing

Table 67: Timing

= V

DDD

= 48 kHz; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

System clock (see

sys

CWL

CWH

S-bus interface

Serial data of audio ADC and DAC (see

BCK

cy(BCK)

BCKH

BCKL

su(WS)

h(WS)

su(DATAI)

h(DATAI)

h(DATAO)

DDA(AD)

= V

= 2.7 V to 3.6 V; T

DDA(AD)

=−20°C to +85°C; typical timing speciﬁed at sampling frequency

amb

Figure 16)

system clock cycle time f

system clock LOW time f

system clock HIGH time f

= 256f f f f

sys sys sys sys sys sys sys sys

= 384f

= 512f

= 768f

< 19.2 MHz 0.3T

≥ 19.2 MHz 0.4T

< 19.2 MHz 0.3T

≥ 19.2 MHz 0.4T

[1]

35 81 780 ns

[1]

23 54 520 ns

[1]

17 41 390 ns

[1]

17 27 260 ns

sys sys sys sys

- 0.7T

- 0.6T

- 0.7T

- 0.6T

Figure 17)

audio bit clock frequency

[2]

- - 12.8 MHz BCK cycle time - - 78 ns bit clock HIGH time 30 - - ns bit clock LOW time 30 - - ns rise time - - 20 ns fall time - - 20 ns word select set-up time 10 - - ns word select hold time 10 - - ns data input set-up time 10 - - ns data input hold time 10 - - ns data output hold time 0 - - ns

sys sys sys sys

ns ns ns ns

Product data sheet Rev. 02 — 17 January 2005 44 of 55

Philips Semiconductors

UDA1384

Multichannel audio coder-decoder

Table 67: Timing

= V

DDD

DDA(AD)

= 48 kHz; unless otherwise speciﬁed.

…continued

= V

DDA(AD)

= 2.7 V to 3.6 V; T

=−20°C to +85°C; typical timing speciﬁed at sampling frequency

amb

Symbol Parameter Conditions Min Typ Max Unit

d(DATAO-BCK)

d(DATAO-WS)

data output to bit clock delay - - 30 ns data output to word select

- - 30 ns delay

Serial data of voice ADC

BCKV

cy(BCKV)

BCKVH

BCKVL

su(WSV)

h(WSV)

h(DATAV)

d(DATAV-BCKV)

d(DATAV-WSV)

voice bit clock frequency BCKV cycle time - - 156 ns bit clock HIGH time 50 - - ns bit clock LOW time 50 - - ns rise time - - 20 ns fall time - - 20 ns word select set-up time 10 - - ns word select hold time 10 - - ns data output hold time 0 - - ns data output to bit clock delay - - 30 ns data output to word select

[2]

- - 6.4 MHz

- - 30 ns delay

d(WSV-BCKV)

L3-bus interface (see

word select to bit clock delay WSV-out mode −30 - +30 ns

Figure 18 and Figure 19)

L3CLOCK timing

cy(CLK)L3

CLK(L3)H

CLK(L3)L

L3CLOCK frequency - - 2000 kHz L3CLOCK cycle time 500 - - ns L3CLOCK HIGH time 250 - - ns L3CLOCK LOW time 250 - - ns

L3MODE timing

su(L3)A

L3MODE set-up time in

190 - - ns

address mode

h(L3)A

L3MODE hold time in

190 - - ns

address mode

su(L3)D

L3MODE set-up time in data

190 - - ns

transfer mode

h(L3)D

L3MODE hold time in data

190 - - ns

transfer mode

stp(L3)

L3MODE stop time in data

190 - - ns

transfer mode

L3DATA timing

su(L3)DA

L3DATA set-up time in data

190 - - ns

transfer and address mode

h(L3)DA

L3DATA hold time in data

30--ns

transfer and address mode

d(L3)R

L3DATA delay time for read

0 - 50 ns

data

Product data sheet Rev. 02 — 17 January 2005 45 of 55

Philips Semiconductors

UDA1384

Multichannel audio coder-decoder

Table 67: Timing

= V

DDD

DDA(AD)

= 48 kHz; unless otherwise speciﬁed.

…continued

= V

DDA(AD)

= 2.7 V to 3.6 V; T

=−20°C to +85°C; typical timing speciﬁed at sampling frequency

amb

Symbol Parameter Conditions Min Typ Max Unit

dis(L3)R

L3DATA disable time for read

0 - 50 ns

data

C-bus interface timing (see Figure 20)

SCL timing

SCL

LOW

HIGH

SCL clock frequency 0 - 400 kHz SCL LOW time 1.3 - - µs SCL HIGH time 0.6 - - µs rise time SDA and SCL fall time SDA and SCL

[3]

20 + 0.1Cb- 300 ns

[3]

20 + 0.1Cb- 300 ns

SDA timing

BUF

bus free time between STOP

1.3 - - µs

and START condition

SU;STA

HD;STA

SU;DAT

HD;DAT

SU;STO

set-up time repeated START 0.6 - - µs hold time START condition 0.6 - - µs data set-up time 100 - - ns data hold time 0 - - µs set-up time STOP condition 0.6 - - µs pulse width of spikes capacitive load for each bus

[4]

0 - 50 ns

- - 400 pF

line

[1] The system clock should not exceed 58 MHz in any mode. [2] The bit clock frequency should not exceed 256 times the corresponding sampling frequency. [3] Cb is the total capacitance for each bus line. [4] To be suppressed by the input ﬁlter.

CWH

CWL

sys

Fig 16. System clock timing

mgr984

Product data sheet Rev. 02 — 17 January 2005 46 of 55

Philips Semiconductors

BCKH

BCK

DATAO

DATAI

cy(BCK)

UDA1384

Multichannel audio coder-decoder

h(DATAO)

su(DATAI)

d(DATAO-BCK)

h(DATAI)

mgs756

BCKL

h(WS)

d(DATAO-WS)

su(WS)

Fig 17. I2S-bus serial interface timing

L3MODE

h(L3)A

L3CLOCK

L3DATA

Fig 18. L3-bus address mode timing

BIT 0

su(L3)A

su(L3)DA

CLK(L3)L

CLK(L3)H

h(L3)DA

su(L3)A

cy(CLK)(L3)

BIT 7

h(L3)A

mgl723

Product data sheet Rev. 02 — 17 January 2005 47 of 55

Philips Semiconductors

UDA1384

Multichannel audio coder-decoder

stp(L3)

L3MODE

L3CLOCK

L3DATA

write

L3DATA

read

su(L3)D

en(L3)R

su(L3)DA

BIT 0

CLK(L3)H

h(L3)DA

h(L3)R

CLK(L3)L

Fig 19. L3-bus data transfer (write and read) mode timing

SDA

cy(CLK)L3

su(L3)R

BIT 7

dis(L3)R

h(L3)D

mgu015

LOW

HD;STA

SCL

Fig 20. I2C-bus timing

16. Test information

16.1 Quality information

The

General Quality Speciﬁcation for Integrated Circuits, SNW-FQ-611

HD;DAT

SU;DAT

HIGH

SU;STA

HD;STA

SU;STO

BUF

msc610

is applicable.

Product data sheet Rev. 02 — 17 January 2005 48 of 55

Philips Semiconductors

17. Package outline

UDA1384

Multichannel audio coder-decoder

QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm

33 23

pin 1 index

w M

SOT307-2

(A )

detail X

w M

DIMENSIONS (mm are the original dimensions)

OUTLINE

VERSION

SOT307-2

max.

2.1

0.25

0.05

1.85

1.65

UNIT A1A2A3bpcE

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0.4

0.2

0.25

0.14

0.25

IEC JEDEC JEITA

0 2.5 5 mm

(1)

(1) (1)(1)

10.1

9.9

REFERENCES

v M

scale

eHELL

12.9

0.8 1.3

12.3

0.95

0.55

0.15 0.10.15

EUROPEAN

PROJECTION

1.2

0.8

Zywv θ

1.2

0.8

ISSUE DATE

97-08-01 03-02-25

Fig 21. Package outline SOT307-2 (QFP44)

Product data sheet Rev. 02 — 17 January 2005 49 of 55

Philips Semiconductors

18. Handling information

Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be completely safe, it is desirable to take normal precautions appropriate to handling integrated circuits.

19. Soldering

19.1 Introduction to soldering surface mount packages

This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our (document order number 9398 652 90011).

There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for ﬁne pitch SMDs. In these situations reﬂow soldering is recommended.

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Data Handbook IC26; Integrated Circuit Packages

19.2 Reﬂow soldering

Reﬂow soldering requires solder paste (a suspension of ﬁne solder particles, ﬂux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing.

Several methods exist for reﬂowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 seconds and 200 seconds depending on heating method.

Typical reﬂow peak temperatures range from 215 °Cto270°C depending on solder paste material. The top-surface temperature of the packages should preferably be kept:

• below 225 °C (SnPb process) or below 245 °C (Pb-free process)

– for all BGA, HTSSON..T and SSOP..T packages – for packages with a thickness ≥ 2.5 mm – for packages with a thickness < 2.5 mm and a volume ≥ 350 mm3 so called

thick/large packages.

• below 240 °C (SnPb process) or below 260 °C (Pb-free process) for packages with a

thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages.

Moisture sensitivity precautions, as indicated on packing, must be respected at all times.

19.3 Wave soldering

Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems.

To overcome these problems the double-wave soldering method was speciﬁcally developed.

If wave soldering is used the following conditions must be observed for optimal results:

Product data sheet Rev. 02 — 17 January 2005 50 of 55

Philips Semiconductors

• Use a double-wave soldering method comprising a turbulent wave with high upward

pressure followed by a smooth laminar wave.

• For packages with leads on two sides and a pitch (e):

– larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be

– smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the

The footprint must incorporate solder thieves at the downstream end.

• For packages with leads on four sides, the footprint must be placed at a 45° angle to

the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners.

During placement and before soldering, the package must be ﬁxed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured.

Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 °C or 265 °C, depending on solder material applied, SnPb or Pb-free respectively.

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parallel to the transport direction of the printed-circuit board;

transport direction of the printed-circuit board.

A mildly-activated ﬂux will eliminate the need for removal of corrosive residues in most applications.

19.4 Manual soldering

Fix the component by ﬁrst soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the ﬂat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C.

When using a dedicated tool, all other leads can be soldered in one operation within 2 seconds to 5 seconds between 270 °C and 320 °C.

19.5 Package related soldering information

Table 68: Suitability of surface mount IC packages for wave and reﬂow soldering methods

Package

BGA, HTSSON..T SSOP..T

DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, SMS

PLCC LQFP, QFP, TQFP not recommended SSOP, TSSOP, VSO, VSSOP not recommended CWQCCN..L

[1]

[3]

, TFBGA, VFBGA, XSON

[5]

, SO, SOJ suitable suitable

, LBGA, LFBGA, SQFP,

[8]

, PMFP

[9]

, WQCCN..L

[8]

Soldering method Wave Reﬂow

not suitable suitable

not suitable

not suitable not suitable

[2]

[4]

[5] [6] [7]

suitable

suitable suitable

[1] For more detailed information on the BGA packages refer to the

order a copy from your Philips Semiconductors sales ofﬁce.

Product data sheet Rev. 02 — 17 January 2005 51 of 55

(LF)BGA Application Note

(AN01026);

Philips Semiconductors

[2] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the

maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the

Packages; Section: Packing Methods

[3] These transparent plastic packages are extremely sensitive to reﬂow soldering conditions and must on no

account be processed through more than one soldering cycle or subjected to infrared reﬂow soldering with peak temperature exceeding 217 °C ± 10 °C measured in the atmosphere of the reﬂow oven. The package body peak temperature must be kept as low as possible.

[4] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the

solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface.

[5] If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave

direction. The package footprint must incorporate solder thieves downstream and at the side corners.

[6] Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is

deﬁnitely not suitable for packages with a pitch (e) equal to or smaller than 0.65mm.

[7] Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger

than 0.65 mm; it is deﬁnitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

[8] Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered

pre-mounted on ﬂex foil. However, the image sensor package can be mounted by the client on a ﬂex foil by using a hot bar soldering process. The appropriate soldering proﬁle can be provided on request.

[9] Hot bar soldering or manual soldering is suitable for PMFP packages.

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Data Handbook IC26; Integrated Circuit

Product data sheet Rev. 02 — 17 January 2005 52 of 55

Philips Semiconductors

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UDA1384

20. Revision history

Table 69: Revision history

Document ID Release date Data sheet status Change notice Doc. number Supersedes

UDA1384_2 20050117 Product data sheet - 9397 750 14366 UDA1384_1 Modiﬁcations:

UDA1384_1 20031009 Preliminary speciﬁcation - 9397 750 12043 -

• The format of this data sheet has been redesigned to comply with the new presentation and

information standard of Philips Semiconductors

• Section 4 “Quick reference data”: Added values for I

• Section 14 “Static characteristics”: Added values for I

DDD(pd)

• Section 15 “Dynamic characteristics”: Removed PSRR speciﬁcation and (THD+N)/S at

−20 dBFS, added (THD+N)/S for DAC differential mode

Product data sheet Rev. 02 — 17 January 2005 53 of 55

Philips Semiconductors

21. Data sheet status

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Level Data sheet status

I Objective data Development This data sheet contains data from the objective speciﬁcation for product development. Philips

II Preliminary data Qualiﬁcation This data sheet containsdata from the preliminaryspeciﬁcation. Supplementary data will bepublished

III Product data Production This data sheet contains data from the product speciﬁcation. Philips Semiconductors reserves the

[1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at

URL http://www.semiconductors.philips.com.

[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

[1]

Product status

22. Deﬁnitions

Short-form speciﬁcation — The data in a short-form speciﬁcation is

extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook.

Limiting values deﬁnition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the speciﬁcation is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warrantythat such applications will be suitable for the speciﬁed use without further testing or modiﬁcation.

[2] [3]

Deﬁnition

Semiconductors reserves the right to change the speciﬁcation in any manner without notice.

at a laterdate. Philips Semiconductors reserves the right tochange the speciﬁcation without notice,in order to improve the design and supply the best possible product.

right to make changesat any time in order to improvethe design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notiﬁcation (CPCN).

23. Disclaimers

Life support — These products are not designed for use in life support

appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notiﬁcation (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, andmakes norepresentations or warrantiesthat these productsare free frompatent, copyright, or maskwork right infringement, unlessotherwise speciﬁed.

24. Contact information

For additional information, please visit: http://www.semiconductors.philips.com For sales ofﬁce addresses, send an email to: sales.addresses@www.semiconductors.philips.com

Product data sheet Rev. 02 — 17 January 2005 54 of 55

Philips Semiconductors

25. Contents

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1 General description . . . . . . . . . . . . . . . . . . . . . . 1

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2.2 Multiple format data interface . . . . . . . . . . . . . . 2

2.3 Digital sound processing. . . . . . . . . . . . . . . . . . 2

2.4 Advanced audio conﬁguration . . . . . . . . . . . . . 2

3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

4 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2

5 Ordering information. . . . . . . . . . . . . . . . . . . . . 3

6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4

7 Pinning information. . . . . . . . . . . . . . . . . . . . . . 5

7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

8 Functional description . . . . . . . . . . . . . . . . . . . 7

8.1 System clock. . . . . . . . . . . . . . . . . . . . . . . . . . . 7

8.2 Audio analog-to-digital converter (audio ADC). 8

8.3 Voice Analog-to-Digital Converter (voice ADC) 8

8.4 Decimation ﬁlter of audio ADC . . . . . . . . . . . . . 8

8.5 Decimation ﬁlter of voice ADC . . . . . . . . . . . . . 8

8.6 Interpolation ﬁlter of DAC . . . . . . . . . . . . . . . . . 9

8.7 Noise shaper of DAC . . . . . . . . . . . . . . . . . . . . 9

8.8 Digital mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

8.9 Audio digital-to-analog converters . . . . . . . . . 10

8.10 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 10

8.11 Audio digital interface . . . . . . . . . . . . . . . . . . . 11

8.12 Voice digital interface . . . . . . . . . . . . . . . . . . . 14

8.13 DSD mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

8.14 Microcontroller interface mode . . . . . . . . . . . . 15

9 L3-bus interface . . . . . . . . . . . . . . . . . . . . . . . . 15

9.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

9.2 Device addressing . . . . . . . . . . . . . . . . . . . . . 16

9.3 Register addressing . . . . . . . . . . . . . . . . . . . . 16

9.4 Data write mode . . . . . . . . . . . . . . . . . . . . . . . 18

9.5 Data read mode . . . . . . . . . . . . . . . . . . . . . . . 18

10 I

C-bus interface . . . . . . . . . . . . . . . . . . . . . . . 19

10.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

10.2 Characteristics of the I

C-bus. . . . . . . . . . . . . 19

10.3 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

10.4 Byte transfer . . . . . . . . . . . . . . . . . . . . . . . . . . 20

10.5 Data transfer. . . . . . . . . . . . . . . . . . . . . . . . . . 20

10.6 Start and stop conditions . . . . . . . . . . . . . . . . 20

10.7 Acknowledgment . . . . . . . . . . . . . . . . . . . . . . 20

10.8 Device address. . . . . . . . . . . . . . . . . . . . . . . . 21

10.9 Register address. . . . . . . . . . . . . . . . . . . . . . . 21

10.10 Write and read data . . . . . . . . . . . . . . . . . . . . 21

10.11 Write cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

10.12 Read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

11 Register mapping . . . . . . . . . . . . . . . . . . . . . . 23

11.1 Address mapping . . . . . . . . . . . . . . . . . . . . . . 23

11.2 Register mapping. . . . . . . . . . . . . . . . . . . . . . 25

11.3 System settings . . . . . . . . . . . . . . . . . . . . . . . 27

11.4 Audio ADC and DAC subsystem settings. . . . 29

11.5 Voice ADC system settings . . . . . . . . . . . . . . 30

11.6 Status output register. . . . . . . . . . . . . . . . . . . 32

11.7 DAC channel selection. . . . . . . . . . . . . . . . . . 33

11.8 DAC features settings. . . . . . . . . . . . . . . . . . . 34

11.9 DAC channel 1 to channel 6 settings . . . . . . . 36

11.10 DAC mixing channel settings. . . . . . . . . . . . . 36

11.11 Audio ADC 1 and ADC 2 input ampliﬁer gain

settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

11.12 Voice ADC gain settings. . . . . . . . . . . . . . . . . 38

11.13 Supplemental settings 1. . . . . . . . . . . . . . . . . 39

11.14 Supplemental settings 2. . . . . . . . . . . . . . . . . 39

12 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 40

13 Thermal characteristics . . . . . . . . . . . . . . . . . 40

14 Static characteristics . . . . . . . . . . . . . . . . . . . 41

15 Dynamic characteristics. . . . . . . . . . . . . . . . . 42

15.1 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

16 Test information. . . . . . . . . . . . . . . . . . . . . . . . 48

16.1 Quality information . . . . . . . . . . . . . . . . . . . . . 48

17 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 49

18 Handling information . . . . . . . . . . . . . . . . . . . 50

19 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

19.1 Introduction to soldering surface mount packages 50

19.2 Reﬂow soldering. . . . . . . . . . . . . . . . . . . . . . . 50

19.3 Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 50

19.4 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 51

19.5 Package related soldering information. . . . . . 51

20 Revision history . . . . . . . . . . . . . . . . . . . . . . . 53

21 Data sheet status. . . . . . . . . . . . . . . . . . . . . . . 54

22 Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

23 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

24 Licenses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

25 Contact information . . . . . . . . . . . . . . . . . . . . 54

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form partof any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.

Published in The Netherlands

Date of release: 17 January 2005

Document number: 9397 750 14366

Philips UDA1384 User Guide

Specifications and Main Features

Frequently Asked Questions

User Manual