Philips UDA1384 User Guide

UDA1384

UDA1384

Multichannel audio coder-decoder

Rev. 02 — 17 January 2005	Product data sheet

1. General description

The UDA1384 is a single-chip consisting of 4 plus 1 Analog-to-Digital Converters (ADC) and 6 Digital-to-Analog Converters (DAC) with signal processing features employing bitstream conversion techniques. The multichannel configuration makes the device eminently suitable for use in digital audio equipment which incorporates surround feature.

The UDA1384 supports conventional 2 channels per line data transfer conformable to the I2S-bus format with word lengths of up to 24 bits, the MSB-justified format with word lengths of up to 24 bits and the LSB-justified format with word lengths of 16 bits, 20 bits and 24 bits, as well as 4 channels to 6 channels per line transfer mode. The device also supports a combination of the MSB-justified output format and the LSB-justified input format. The UDA1384 has special sound processing features in the Direct Stream Digital (DSD) playback mode, de-emphasis, volume and mute which can be controlled via the L3-bus or I2C-bus interface.

2.Features

2.1General

■2.7 V to 3.6 V power supply

■5 V tolerant digital inputs

■24-bit data path

■Selectable control: via L3-bus or I2C-bus microcontroller interface

■Supports sample frequency ranges for:

Audio ADC: fs = 16 kHz to 100 kHz

Voice ADC: fs = 7 kHz to 50 kHz

Audio DAC: fs = 16 kHz to 200 kHz

■Separate power control for ADC and DAC

■ADC plus integrated high-pass filter to cancel DC offset

■Integrated digital filter plus DAC

■Slave mode only applications

■Easy application

Philips Semiconductors			UDA1384
			Multichannel audio coder-decoder

2.2Multiple format data interface

■Audio interface supports standard I2S-bus, MSB-justified, LSB-justified and two multichannel formats

■Voice interface supports I2S-bus and mono channel formats

2.3Digital sound processing

■Control via L3-bus or I2C-bus:

Channel independent digital logarithmic volume

Digital de-emphasis for fs = 32 kHz, 44.1 kHz, 48 kHz or 96 kHz

Soft or quick mute

Output signal polarity control

2.4Advanced audio configuration

■Inputs:

4 single-ended audio inputs (2 × stereo) with programmable gain amplifiers

1 single-ended voice input

■Outputs:

6 differential audio outputs (3 × stereo)

■DSD mode to support stereo DSD playback

■High linearity, wide dynamic range and low distortion

■DAC digital filter with selectable sharp or soft roll-off

3.Applications

■Excellently suitable for multichannel home audio-video application

4.Quick reference data

Table 1: Quick reference data

VDDD = VDDA(AD) = VDDA(DA) = 3.3 V; Tamb = 25 °C; RL = 22 kΩ; all voltages referenced to ground (pins VSS); unless otherwise specified.

	Symbol	Parameter	Conditions	Min	Typ	Max	Unit
	Supplies
	VDDA(AD)	ADC analog supply		2.7	3.3	3.6	V
		voltage
	VDDA(DA)	DAC analog supply		2.7	3.3	3.6	V
		voltage
	VDDD	digital supply voltage		2.7	3.3	3.6	V
	IDDA(AD)	ADC analog supply	fADC = 48 kHz	-	30	-	mA
		current
	IDDA(DA)	DAC analog supply	fDAC = 48 kHz	-	20	-	mA
		current
	IDDD	digital supply current	fADC = fDAC = 48 kHz;	-	31	-	mA
			fVOICE = 48 kHz
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Product data sheet

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			Multichannel audio coder-decoder

Table 1: Quick reference data …continued

VDDD = VDDA(AD) = VDDA(DA) = 3.3 V; Tamb = 25 °C; RL = 22 kΩ; all voltages referenced to ground (pins VSS); unless otherwise specified.

Symbol	Parameter	Conditions				Min	Typ	Max	Unit
IDDD(pd)	digital supply current	audio and voice	-				18	-	mA
	in Power-down mode	ADCs power-down
		DAC power-down	-				14	-	mA
Tamb	ambient temperature					−20	-	+85	°C
Audio analog-to-digital converter
D0	digital output level	at 0 dB setting;	[1]		[2]	−2.5	−1.2	−0.7	dB
		900 mV input
(THD+N)/S	total harmonic	at −1 dBFS	-				−88	−82	dB
	distortion-plus-noise
		at −60 dBFS;	-				−37	−30	dB
	to signal ratio
		A-weighted
S/N	signal-to-noise ratio	code = 0; A-weighted	89				98	-	dB
αcs	channel separation		-				100	-	dB
Digital-to-analog converter
Differential mode
Vo(rms)	output voltage	at 0 dBFS digital	1.9				2.0	2.1	V
	(RMS value)	input
(THD+N)/S	total harmonic	at 0 dBFS	-				−98	−89	dB
	distortion-plus-noise
		at −60 dBFS;	-				−50	−45	dB
	to signal ratio
		A-weighted
S/N	signal-to-noise ratio	code = 0; A-weighted	100				110	-	dB
αcs	channel separation		-				114	-	dB
Single-ended mode
Vo(rms)	output voltage	at 0 dBFS digital	-				1.0	-	V
	(RMS value)	input
(THD+N)/S	total harmonic	at 0 dBFS	-				−88	-	dB
	distortion-plus-noise
		at −60 dBFS;	-				−45	-	dB
	to signal ratio
		A-weighted
S/N	signal-to-noise ratio	code = 0; A-weighted	-				105	-	dB
αcs	channel separation		-				110	-	dB

[1]The input voltage can be up to 2 V (RMS) when the current through the ADC input pin is limited to approximately 1 mA by using a series resistor.

[2]The input voltage to the ADC scales proportionally with the power supply voltage.

5.Ordering information

Table 2: Ordering information

Type number	Package
	Name	Description	Version
UDA1384H	QFP44	plastic quad flat package; 44 leads (lead length	SOT307-2
		1.3 mm); body 10 × 10 × 1.75 mm

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Product data sheet

Rev. 02 — 17 January 2005

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			Multichannel audio coder-decoder

6. Block diagram

				VDDA(AD)		VSSA(AD)	VADCP	VADCN		Vref
					5	3	9		7	1
VINL1	2	PGA	ADC 1L				ADC 1R		PGA	4	VINR1
VINL2	6	PGA	ADC 2L				ADC 2R		PGA	8	VINR2
VVOICE	10	LNA
					DECIMATION FILTER				TEST	11	TEST
			ADC
		DECIMATION			DC-CANCELLATION FILTER			CLOCK		19	SYSCLK
		FILTER
		HP FILTER								13	DATAAD1
						I2S-BUS				12
											DATAAD2
						INTERFACE 1				14
DATAV	16										BCKAD
										15
	17	I2S-BUS									WSAD
BCKV
	18	INTERFACE 3
WSV
									PLL
			PLL							23	WSDA
										24
											BCKDA
	21					I2S-BUS				25
MCCLK											DATADA1
						INTERFACE 2				26
	20	L3-BUS OR									DATADA2
										27
MCMODE	22	I2C-BUS									DATADA3
		CONTROL
MCDATA
	30	INTERFACE
				VOLUME, MUTE, DE-EMPHASIS
I2C_L3
					INTERPOLATION FILTER					29	VDDD
		UDA1384								28	VSSD
					NOISE SHAPER
VOUT1N	32		−						−	34	VOUT2N
				DAC 1			DAC 2
VOUT1P	31		+						+	33	VOUT2P
VOUT3N	36		−						−	39	VOUT4N
				DAC 3			DAC 4
VOUT3P	35		+						+	38	VOUT4P
VOUT5N	42		−						−	44	VOUT6N
				DAC 5			DAC 6
VOUT5P	41		+						+	43	VOUT6P
			37			40
			VDDA(DA)		VSSA(DA)					mce639

Fig 1. Block diagram

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Rev. 02 — 17 January 2005

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			Multichannel audio coder-decoder

7.Pinning information

7.1Pinning

			VOUT6N		VOUT6P		VOUT5N		VOUT5P		SSA(DA)		VOUT4N		VOUT4P		DDA(DA)		VOUT3N		VOUT3P		VOUT2N
											V						V
			44		43		42		41		40		39		38		37		36		35		34
Vref	1																								33	VOUT2P
VINL1	2																								32	VOUT1N
VSSA(AD)	3																								31	VOUT1P
VINR1	4																								30	I2C_L3
VDDA(AD)	5																								29	VDDD
										UDA1384H
VINL2	6																								28	VSSD
VADCN	7																								27	DATADA3
VINR2	8																								26	DATADA2
VADCP	9																								25	DATADA1
VVOICE	10																								24	BCKDA
TEST	11																								23	WSDA

12		13		14		15		16		17		18		19		20		21		22
DATAAD2		DATAAD1		BCKAD		WSAD		DATAV		BCKV		WSV		SYSCLK		MCMODE		MCCLK		MCDATA

001aac311

Fig 2. Pin configuration

7.2 Pin description

	Table 3:	Pin description
	Symbol	Pin	Type	Description
	Vref	1	AIO	ADC reference voltage
	VINL1	2	AIO	ADC 1 input left
	VSSA(AD)	3	AGND	ADC analog ground
	VINR1	4	AIO	ADC 1 input right
	VDDA(AD)	5	AS	ADC analog supply voltage
	VINL2	6	AIO	ADC 2 input left
	VADCN	7	AIO	ADC reference voltage N
	VINR2	8	AIO	ADC 2 input right
	VADCP	9	AIO	ADC reference voltage P
	VVOICE	10	AIO	voice ADC input
	TEST	11	DID	test input; must be connected to digital ground (VSSD) in
				application
	DATAAD2	12	DO	ADC 2 data output
	DATAAD1	13	DO	ADC 1 data output
	BCKAD	14	DIS	ADC bit clock input
	WSAD	15	DI	ADC word select input
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Philips Semiconductors						UDA1384
						Multichannel audio coder-decoder
			Table 3:	Pin description …continued
			Symbol	Pin	Type	Description
			DATAV	16	DO	voice data output
			BCKV	17	DIS	voice bit clock input
			WSV	18	DIO	voice word select input or output
			SYSCLK	19	DIS	system clock input: 256fs, 384fs, 512fs or 768fs
			MCMODE	20	DI	L3-bus L3MODE input or I2C-bus DAC mute control input
			MCCLK	21	DIS	L3-bus L3CLOCK input or I2C-bus SCL input
			MCDATA	22	IIC	L3-bus L3DATA input and output or I2C-bus SDA input and
						output
			WSDA	23	DI	DAC word select input
			BCKDA	24	DIS	DAC bit clock input
			DATADA1	25	DI	DAC channel 1 and channel 2 data input
			DATADA2	26	DI	DAC channel 3 and channel 4 data input
			DATADA3	27	DI	DAC channel 5 and channel 6 data input
			VSSD	28	DGND	digital ground
			VDDD	29	DS	digital supply voltage
			I2C_L3	30	DI	selection input for L3-bus or I2C-bus control
			VOUT1P	31	AIO	DAC 1 positive output
			VOUT1N	32	AIO	DAC 1 negative output
			VOUT2P	33	AIO	DAC 2 positive output
			VOUT2N	34	AIO	DAC 2 negative output
			VOUT3P	35	AIO	DAC 3 positive output
			VOUT3N	36	AIO	DAC 3 negative output
			VDDA(DA)	37	AS	DAC analog supply voltage
			VOUT4P	38	AIO	DAC 4 positive output
			VOUT4N	39	AIO	DAC 4 negative output
			VSSA(DA)	40	AGND	DAC analog ground
			VOUT5P	41	AIO	DAC 5 positive output
			VOUT5N	42	AIO	DAC 5 negative output
			VOUT6P	43	AIO	DAC 6 positive output
			VOUT6N	44	AIO	DAC 6 negative output

[1]See Table 4.

	Table 4:	Pin types
	Type	Description
	AGND	analog ground
	AIO	analog input and output
	AS	analog supply
	DGND	digital ground
	DI	digital input
	DID	digital input with internal pull-down resistor
	DIO	digital input and output
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Product data sheet

Rev. 02 — 17 January 2005

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Philips Semiconductors				UDA1384
				Multichannel audio coder-decoder
			Table 4:	Pin types …continued
			Type	Description
			DIS	digital Schmitt-triggered input
			DO	digital output
			DS	digital supply
			IIC	input and open-drain output for I2C-bus

8.Functional description

8.1System clock

The UDA1384 operates in slave mode only; this means that in all applications the system must provide either the system clock (the bit clock for the voice ADC) or the word clock.

The audio ADC part, the voice ADC part and the DAC part can operate at different sampling frequencies (DAC-WS and ADC-WS modes) as well as a common frequency (SYSCLK, WSDA and DSD modes).

The voice ADC part supports a sampling frequency up to 50 kHz and the audio ADC supports a sampling frequency up to 100 kHz. The DAC sampling frequency range is extended up to 200 kHz with the range above 100 kHz being supported through 192 kHz sampling mode, which halves the oversampling ratio of SYSCLK and internal clocks.

The mode of operation of the audio and voice channels can be set via the L3-bus or

I2C-bus microcontroller interface and are summarized in Table 5 and Table 6.

When applied, the system clock must be locked in frequency to the corresponding digital interface clocks.

The voice ADC part can either receive or generate the WSV signal as shown in Table 6.

Table 5:	Audio ADC and DAC operating clock mode
Mode	Audio ADC		Audio DAC
	Clock	Frequency	Clock	Frequency
SYSCLK	SYSCLK	256fs, 384fs, 512fs or 768fs	SYSCLK	256fs, 384fs, 512fs or 768fs
			SYSCLK	128fs, 192fs, 256fs or 384fs;
				192 kHz sampling mode
DAC-WS	SYSCLK	256fs, 384fs, 512fs or 768fs	WSDA	1fs
ADC-WS	WSAD	1fs	SYSCLK	256fs, 384fs, 512fs or 768fs
			SYSCLK	128fs, 192fs, 256fs or 384fs;
				192 kHz sampling mode
WSDA	WSDA	1fs	WSDA	1fs
DSD	SYSCLK	44.1 kHz × 512	SYSCLK	44.1 kHz × 512

	Table 6:	Voice ADC operating clock mode
	Mode		Voice ADC
			Bit clock frequency (BCKV)		Word select (WSV)
	WSV-in		input: 32fs, 64fs, 128fs or 256fs		input
	WSV-out		input: 32fs, 64fs, 128fs or 256fs		output
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Product data sheet

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Philips Semiconductors			UDA1384
			Multichannel audio coder-decoder

8.2 Audio analog-to-digital converter (audio ADC)

The audio analog-to-digital front-end of the UDA1384 consists of 4-channel single-ended ADCs with programmable gain stage (from 0 dB to 24 dB with 3 dB steps), controlled via the microcontroller interface. Using the PGA feature, it is possible to accept an input signal of 900 mV (RMS) or 1.8 V (RMS) if an external resistor of 10 kW is used in series. The schematic of audio ADC front-end is shown in Figure 3.

10 kΩ (0 dB setting)

10 kΩ

VINL,

10 kΩ

input signal

VINR

2 V (RMS)

ADC

VDDA = 3.3 V

Vref

mgu582

Fig 3. Schematic of audio ADC front-end

8.3 Voice Analog-to-Digital Converter (voice ADC)

The voice analog-to-digital front-end of the UDA1384 consists of a single-channel single-ended ADC with a fixed gain (26 dB) Low Noise Amplifier (LNA). Together with the digital variable gain amplification stage, the voice ADC provides optimal processing and reproduction of the microphone signal. The supported sampling frequency range is from 7 kHz to 50 kHz. Power-down of the LNA and the ADC can be controlled separately.

8.4 Decimation filter of audio ADC

æ sin xö 4

The decimation from 64fs is performed in two stages. The first stage realizes è----------ø x

characteristics with a decimation factor of 8. The second stage consists of three half-band filters, each decimating by a factor of 2. The filter characteristics are shown in Table 7.

Table 7: Decimation filter characteristics (audio ADC)

Item	Condition	Value (dB)
Pass-band ripple	0fs to 0.45fs	±0.01
Pass-band droop	0.45fs	−0.2
Stop band	> 0.55fs	−70
Dynamic range	0fs to 0.45fs	> 135

8.5 Decimation filter of voice ADC

The voice ADC decimation filter is realized with the combination of a Finite Impulse Response (FIR) filter and Infinite Impulse Response (IIR) filter for shorter group delay. The filter characteristics are shown in Table 8. During the power-on sequence, the output of the ADC is hard muted for a certain period. This hard-mute time can be chosen between 1024 samples and 2048 samples.

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			Multichannel audio coder-decoder

Table 8: Decimation filter characteristics (voice ADC)

Item	Condition	Value (dB)
Pass-band ripple	0fs to 0.45fs	±0.05
Pass-band droop	0.45fs	−0.2
Stop band	> 0.55fs	−65
Dynamic range	0fs to 0.45fs	> 110

8.6 Interpolation filter of DAC

The digital interpolation filter interpolates from 1fs to 128fs (or to 64fs in the 192 kHz sampling mode) by cascading FIR filters, and has two sets of filter coefficients for sharp and slow roll-off as given in Table 9 and Table 10.

Table 9: Interpolation filter characteristics (sharp roll-off)

Item	Condition	Value (dB)
Pass-band ripple	0fs to 0.45fs	±0.002
Stop band	> 0.55fs	−75
Dynamic range	0fs to 0.45fs	> 135
Table 10: Interpolation filter characteristics (slow roll-off)
Item	Condition	Value (dB)
Pass-band ripple	0fs to 0.22fs	±0.002
Pass-band droop	0.45fs	−3.1
Stop band	> 0.78fs	−94
Dynamic range	0fs to 0.22fs	> 135

8.7 Noise shaper of DAC

The 3rd-order noise shaper operates at either 128fs or 64fs (in the 192 kHz sampling mode), and converts the 24-bit input signal into a 5-bit signal stream. The noise shaper shifts in-band quantization noise to frequencies well above the audio band. This noise shaping technique enables high signal-to-noise ratios to be achieved.

8.8 Digital mixer

The UDA1384 has 6 digital mixers inside the interpolator (see Figure 4). The ADC signals can be mixed with the I2S-bus input signals. The mixing of the ADC signals can be selected by the bits MIX[1:0].

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			Multichannel audio coder-decoder

MIX[1:0]
from ADC
ch1	mixer input	MIXER	MIXER
ch2
		VOLUME	MUTE
ch3
ch4
	DE-EMPHASIS	VOLUME	MUTE	+	INTERPOLATION	DAC1
					FILTER
from I2S-bus				1fs
DATADA1
			same as above			DAC2
			same as above			DAC3
DATADA2
			same as above			DAC4
DATADA3			same as above			DAC5
			same as above			DAC6
DIS[1:0]					mgw786
ICS[1:0]
Fig 4. Block diagram of DAC mixer

8.9 Audio digital-to-analog converters

The audio digital-to-analog front-end of the UDA1384 consists of 6-channel differential SDACs: an SDAC is a multi-bit DAC based upon switched resistors. To minimize data dependent modulation effects, a Dynamic Element Matching (DEM) algorithm scrambler circuit and DC current compensation circuit are implemented with the SDAC.

8.10 Power-on reset

The UDA1384 has an internal power-on reset circuit which initializes the device (see Figure 5). All the digital sound processing features and the system controlling features are set to their default values in the L3-bus and the I2C-bus modes.

The reset time (see Figure 6) is determined by an external capacitor which is connected

between pin Vref and ground. The reset time should be at least 250 μs for Vref < 1.25 V. When VDDA(AD) is switched off, the device will be reset again for Vref < 0.75 V.

During the reset time, the system clock should be running.

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			Multichannel audio coder-decoder

	3.3
	VDDD
	(V)
	0
	t
VDDA(AD)	3.3

9 kΩ

VDDA(AD)

		(V)
Vref		RESET
		CIRCUIT
C1 >	9 kΩ
10 μF		0
			t
		mgu585
		Vref
		(V)
		1.65
		1.25
		0.75
		0	t
		trst
		>250 μs	mgu586

Fig 5. Power-on reset circuit

Fig 6. Power-on reset timing

8.11 Audio digital interface

The following audio formats can be selected via the microcontroller interface:

•I2S-bus format with data word length of up to 24 bits

•MSB-justified format with data word length of up to 24 bits

•LSB-justified format with data word length of 16 bits, 20 bits or 24 bits

•Multichannel formats with data word length of 20 bits or 24 bits. The used data lines are DATAAD1 and DATADA1 and the sampling frequency must be below 50 kHz

The formats are illustrated in Figure 7 and Figure 8.

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WS		LEFT						RIGHT
1	2	3	> = 8	1	2		3			> = 8
BCK
DATA	MSB	B2			MSB	B2				MSB
			I2S-BUS FORMAT
WS		LEFT						RIGHT
1	2	3		> = 8		1	2	3		> = 8
BCK
DATA MSB	B2			LSB	MSB		B2			LSB MSB B2
			MSB-JUSTIFIED FORMAT
WS			LEFT
							16	15	2	1
BCK
DATA							MSB	B2	B15	LSB
									LSB-JUSTIFIED FORMAT 16 BITS
WS			LEFT
			20	19	18	17	16	15	2	1
BCK
DATA			MSB B2 B3			B4	B5	B6	B19	LSB
									LSB-JUSTIFIED FORMAT 20 BITS

RIGHT

16

15

2

1

MSB B2 B15 LSB

RIGHT
20	19	18	17	16	15	2	1
MSB	B2	B3	B4	B5	B6	B19	LSB

WS					LEFT												RIGHT
	24	23	22	21	20	19	18	17	16	15	2	1	24	23	22	21	20	19	18	17	16	15	2	1
BCK
DATA	MSB	B2	B3	B4	B5	B6	B7	B8	B9	B10	B23	LSB	MSB	B2	B3	B4	B5	B6	B7	B8	B9	B10	B23	LSB
											LSB-JUSTIFIED FORMAT 24 BITS													mgt020

Fig 7. Formats of input and output data (single-channel)

Semiconductors Philips

decoder-coder audio Multichannel

UDA1384

sheet data Product

2005 January 17 — 02 .Rev

55 of 13

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WS
1	2		21	22		41	42			61	1	2		21	22		41	42			61
BCK
DATA	MSB		LSB MSB			LSB	MSB			LSB		MSB		LSB MSB			LSB	MSB			LSB
	CH1				CH3				CH5				CH2		CH4					CH6
										MULTICHANNEL FORMAT 20 BITS
WS
1	2		25	26			49		50	73	1	2		25	26			49		50	73
BCK
DATA	MSB		LSB	MSB			LSB	MSB		LSB		MSB		LSB	MSB			LSB	MSB		LSB
	CH1				CH3					CH5			CH2			CH4					CH6
										MULTICHANNEL FORMAT 24 BITS (1)
WS
1	25	26		49	50			73	74	97	1		25	26	49	50			73	74	97
BCK
DATA		MSB		LSB MSB			LSB MSB			LSB				MSB	LSB MSB			LSB MSB			LSB
			CH1			CH3				CH5				CH2			CH4				CH6
										MULTICHANNEL FORMAT 24 BITS (2)											mgu588

(1)Format 1.

(2)Format 2.

Fig 8. Formats of input and output data (multichannel)

Semiconductors Philips

decoder-coder audio Multichannel

UDA1384

Philips Semiconductors			UDA1384
			Multichannel audio coder-decoder

8.12 Voice digital interface

The following voice formats can be selected via the microcontroller interface:

•I2S-bus format with data word length of up to 20 bits. The left and the right channels contain the same data.

•Mono channel format with data word length of up to 20 bits.

The formats are illustrated in Figure 9.

WS			LEFT				RIGHT
1	2	3		³ 8	1	2	3	³ 8
BCK
DATA	MSB	B2				MSB	B2	MSB
				I2S-BUS FORMAT
WS
	1	2	3			³ 8	1	2
BCK
DATA	MSB	B2					MSB	B2
				MONO CHANNEL FORMAT				mgu587
Fig 9. Voice digital interface formats

8.13 DSD mode

The UDA1384 can receive 2.8224 MHz DSD signals and generate 88.2 kHz multibit PCM signals as well as analog signal outputs. The configuration of the UDA1384 in the DSD mode is shown in Figure 10.

left	DATADA2					-	VOUT1N	left
					DAC		VOUT1P
channel						+		channel
2.8224 MHz		DECIMATION		INTERPOLATION				analog
DSD	DATADA3	FILTER		NOISE SHAPING		-	VOUT2N	output
right					DAC		VOUT2P	right
channel						+		channel
5.6448 MHz	BCKAD	I2S-BUS		I2S-BUS
	WSAD
88.2 kHz		INTERFACE 1		INTERFACE 2
							mgu584
		DATAAD1	DATADA1	WSDA	BCKDA	SYSCLK

	88.2 kHz	88.2 kHz	22.5792 MHz
	PCM data
		5.6448 MHz
	I2S-bus
	(left and right)
	Fig 10. DSD mode
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Product data sheet

Rev. 02 — 17 January 2005

14 of 55

Philips Semiconductors			UDA1384
			Multichannel audio coder-decoder

8.14 Microcontroller interface mode

The microcontroller interface mode can be selected as shown in Table 11:

•L3-bus mode when pin I2C_L3 = LOW

•I2C-bus mode when pin I2C_L3 = HIGH

Table 11: Pin function in the L3-bus or I2C-bus mode

Pin	Level on pin I2C_L3
	LOW	HIGH
	L3-bus mode signal	I2C-bus mode signal
MCCLK	L3CLOCK	SCL
MCDATA	L3DATA	SDA
MCMODE	L3MODE	QMUTE

Table 12: QMUTE

Signal QMUTE	Function
LOW	no muting
HIGH	muting

All the features are accessible with the I2C-bus interface protocol as with the L3-bus interface protocol.

The detailed description of the device operation in the L3-bus mode and I2C-bus mode is given in Section 9 and Section 10, respectively.

9.L3-bus interface

9.1General

The UDA1384 has an L3-bus microcontroller interface and all the digital sound processing features and various system settings can be controlled by a microcontroller.

The exchange of data and control information between the microcontroller and the UDA1384 is LSB first and is accomplished through a serial hardware L3-bus interface comprising the following pins:

•MCCLK: clock line with signal L3CLOCK

•MCDATA: data line with signal L3DATA

•MCMODE: mode line with signal L3MODE

The L3-bus format has two modes of operation:

•Address mode

•Data transfer mode

The address mode is used to select a device for a subsequent data transfer. The address mode is characterized by signal L3MODE = LOW and a burst of 8 pulses for signal L3CLOCK, accompanied by 8 bits (see Figure 11).

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Product data sheet

Rev. 02 — 17 January 2005

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Philips Semiconductors			UDA1384
			Multichannel audio coder-decoder

The data transfer mode is characterized by signal L3MODE = HIGH and is used to transfer one or more bytes representing a register address, instruction or data.

Basically, two types of data transfers can be defined:

•Write action: data transfer to the device

•Read action: data transfer from the device.

9.2Device addressing

The device address consists of one byte with:

•Data Operating Mode (DOM) bits 0 and 1 representing the type of data transfer (see Table 13)

•Address bits 2 to 7 representing a 6-bit device address. The address of the UDA1384 is 01 0100 (bits 2 to 7).

Table 13: Selection of data transfer

DOM		Transfer
Bit 1	Bit 0
0	0	not used
0	1	not used
1	0	write data or prepare read
1	1	read data

9.3 Register addressing

After sending the device address (including DOM bits), indicating whether the information is to be read or written, one data byte is sent using bit 0 to indicate whether the information will be read or written and bits 1 to 7 for the destination register address.

Basically, there are 3 methods for register addressing:

1.Addressing for write data: bit 0 is logic 0 indicating a write action to the destination register, followed by bits 1 to 7 indicating the register address (see Figure 11).

2.Addressing for prepare read: bit is logic 1, indicating that data will be read from the register (see Figure 12).

3.Addressing for data read action. Here, the device returns a register address prior to sending data from that register. When bit 0 is logic 0, the register address is valid; when bit 0 is logic 1, the register address is invalid (see Figure 12).

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© Koninklijke Philips Electronics N.V. 2005. All rights reserved.

Product data sheet

Rev. 02 — 17 January 2005

16 of 55

Philips Semiconductors

UDA1384

mbl567

data byte 2

data byte 1

register address

0

write

device address

1	bits
0	DOM

L3CLOCK

L3MODE

L3DATA

9397 750 14366

Multichannel audio coder-decoder

data byte 2 mbl565

			data byte 1		by the device
					sent
		requesting address register address	0/1	valid/invalid
		device
			1
			1
		register address
		address	1	read	prepare read
		device		DOM bits
mode			0 1		mode
Data write	L3CLOCK	L3MODE	L3DATA		Data read
Fig 11.					Fig 12.

© Koninklijke Philips Electronics N.V. 2005. All rights reserved.

Product data sheet

Rev. 02 — 17 January 2005

17 of 55