Philips UDA1384 User Guide

查询UDA1384供应商

UDA1384

Multichannel audio coder-decoder

Rev. 02 — 17 January 2005 Product data sheet

1. General description

The UDA1384 is a single-chip consisting of 4 plus 1 Analog-to-Digital Converters (ADC) and 6 Digital-to-Analog Converters (DAC) with signal processing features employing bitstream conversion techniques. The multichannel conﬁguration makes the device eminently suitable for use in digital audio equipment which incorporates surround feature.

The UDA1384 supports conventional 2 channels per line data transfer conformable to the I2S-bus format with word lengths of up to 24 bits, the MSB-justiﬁed format with word lengths of up to 24 bits and the LSB-justiﬁed format with word lengths of 16 bits, 20 bits and 24 bits, as well as 4 channels to 6 channels per line transfer mode. The device also supports a combination of the MSB-justiﬁed output format and the LSB-justiﬁed input format. The UDA1384 has special sound processing features in the Direct Stream Digital (DSD) playback mode, de-emphasis, volume and mute which can be controlled via the L3-bus or I2C-bus interface.

2. Features

2.1 General

■ 2.7 V to 3.6 V power supply

■ 5 V tolerant digital inputs

■ 24-bit data path

■ Selectable control: via L3-bus or I2C-bus microcontroller interface

■ Supports sample frequency ranges for:

◆ Audio ADC: fs = 16 kHz to 100 kHz

◆ Voice ADC: fs = 7 kHz to 50 kHz

◆ Audio DAC: fs = 16 kHz to 200 kHz

■ Separate power control for ADC and DAC

■ ADC plus integrated high-pass ﬁlter to cancel DC offset

■ Integrated digital ﬁlter plus DAC

■ Slave mode only applications

■ Easy application

Philips Semiconductors

2.2 Multiple format data interface

■ Audio interface supports standard I2S-bus, MSB-justiﬁed, LSB-justiﬁed and two

multichannel formats

■ Voice interface supports I2S-bus and mono channel formats

2.3 Digital sound processing

■ Control via L3-bus or I2C-bus:

◆ Channel independent digital logarithmic volume

◆ Digital de-emphasis for fs = 32 kHz, 44.1 kHz, 48 kHz or 96 kHz

◆ Soft or quick mute

◆ Output signal polarity control

2.4 Advanced audio conﬁguration

■ Inputs:

◆ 4 single-ended audio inputs (2 × stereo) with programmable gain ampliﬁers

◆ 1 single-ended voice input

■ Outputs:

◆ 6 differential audio outputs (3 × stereo)

■ DSD mode to support stereo DSD playback

■ High linearity, wide dynamic range and low distortion

■ DAC digital ﬁlter with selectable sharp or soft roll-off

UDA1384

Multichannel audio coder-decoder

3. Applications

■ Excellently suitable for multichannel home audio-video application

4. Quick reference data

Table 1: Quick reference data

= V

DDD

(pins V

Symbol Parameter Conditions Min Typ Max Unit

Supplies

V I

DDA(AD)

DDA(DA)

DDD

DDA(AD)

); unless otherwise speciﬁed.

DDA(AD)

DDA(DA)

DDD

= V

ADC analog supply voltage

DAC analog supply voltage

digital supply voltage 2.7 3.3 3.6 V ADC analog supply

current DAC analog supply

current digital supply current f

DDA(DA)

= 3.3 V; T

= 25°C; RL = 22 kΩ; all voltages referenced to ground

amb

2.7 3.3 3.6 V

= 48 kHz - 30 - mA

ADC

= 48 kHz - 20 - mA

DAC

ADC=fDAC

= 48 kHz

VOICE

= 48 kHz;

-31-mA

Product data sheet Rev. 02 — 17 January 2005 2 of 55

Philips Semiconductors

UDA1384

Multichannel audio coder-decoder

Table 1: Quick reference data

DDD

(pins V

= V

DDA(AD)

DDA(DA)

); unless otherwise speciﬁed.

…continued

= 3.3 V; T

= 25°C; RL = 22 kΩ; all voltages referenced to ground

amb

Symbol Parameter Conditions Min Typ Max Unit

DDD(pd)

digital supply current in Power-down mode

audio and voice ADCs power-down

-18-mA

DAC power-down - 14 - mA

amb

ambient temperature −20 - +85 °C

Audio analog-to-digital converter

digital output level at 0 dB setting;

[1] [2]

−2.5 −1.2 −0.7 dB

900 mV input

(THD+N)/S total harmonic

distortion-plus-noise to signal ratio

at −1 dBFS - −88 −82 dB at −60 dBFS;

- −37 −30 dB

A-weighted

S/N signal-to-noise ratio code = 0; A-weighted 89 98 - dB

channel separation - 100 - dB

Digital-to-analog converter

Differential mode

o(rms)

output voltage (RMS value)

(THD+N)/S total harmonic

distortion-plus-noise to signal ratio

at 0 dBFS digital

1.9 2.0 2.1 V

input at 0 dBFS - −98 −89 dB at −60 dBFS;

- −50 −45 dB

A-weighted

S/N signal-to-noise ratio code = 0; A-weighted 100 110 - dB

channel separation - 114 - dB

Single-ended mode

o(rms)

output voltage

(RMS value) (THD+N)/S total harmonic

distortion-plus-noise

to signal ratio

at 0 dBFS digital

- 1.0 - V

input at 0 dBFS - −88 - dB at −60 dBFS;

- −45 - dB

A-weighted

S/N signal-to-noise ratio code = 0; A-weighted - 105 - dB

channel separation - 110 - dB

[1] The input voltage can be up to 2 V (RMS) when the current through the ADC input pin is limited to

approximately 1 mA by using a series resistor.

[2] The input voltage to the ADC scales proportionally with the power supply voltage.

5. Ordering information

Table 2: Ordering information

Type number Package

Name Description Version

UDA1384H QFP44 plastic quad ﬂat package; 44 leads (lead length

1.3 mm); body 10 × 10 × 1.75 mm

Product data sheet Rev. 02 — 17 January 2005 3 of 55

SOT307-2

Philips Semiconductors

6. Block diagram

UDA1384

Multichannel audio coder-decoder

VINL1

VINL2

VVOICE

DATAV

BCKV

WSV

MCCLK

MCMODE

MCDATA

I2C_L3

16 17

21 20 22 30

PGA ADC 1L

PGA

LNA

ADC 2L

ADC

DECIMATION

FILTER

HP FILTER

I2S-BUS

INTERFACE 3

PLL

L3-BUS OR

I2C-BUS

CONTROL

INTERFACE

UDA1384

DDA(AD)

DC-CANCELLATION FILTER

VOLUME, MUTE, DE-EMPHASIS

INTERPOLATION FILTER

SSA(AD)

DECIMATION FILTER

I2S-BUS

INTERFACE 1

I2S-BUS

INTERFACE 2

NOISE SHAPER

ADCP

ADC 1R

ADC 2R

ADCN

TEST

CLOCK

PLL

PGA

ref

VINR1

VINR2

TEST

SYSCLK

DATAAD1

DATAAD2

BCKAD

WSAD

WSDA

BCKDA

DATADA1

DATADA2

DATADA3

DDD

SSD

VOUT1N VOUT1P

VOUT3N VOUT3P

VOUT5N VOUT5P

32 31

36 35

42 41

−

DAC 1

−

DAC 3

−

DAC 5

37 40

DDA(DA)

SSA(DA)

DAC 2

DAC 4

DAC 6

34 33

39 38

44 43

VOUT2N VOUT2P

VOUT4N VOUT4P

VOUT6N VOUT6P

− +

mce639

Fig 1. Block diagram

Product data sheet Rev. 02 — 17 January 2005 4 of 55

Philips Semiconductors

7. Pinning information

7.1 Pinning

UDA1384

Multichannel audio coder-decoder

SSA(DA)

4443424140393837363534

ref

VINL1 VOUT1N

SSA(AD)

DDA(AD)

VVOICE BCKDA

3 4

VINR1 I2C_L3

5 6

VINL2 V

ADCN

VINR2 DATADA2

ADCP

10 11

TEST WSDA

1213141516171819202122

DATAAD2 VOUT6N

BCKAD VOUT5N

DATAAD1 VOUT6P

UDA1384H

WSAD VOUT5P

DATAV V

WSV VOUT4P

BCKV VOUT4N

DDA(DA)

SYSCLK V

MCCLK VOUT3P

MCMODE VOUT3N

33 32 31 30 29 28 27 26 25 24 23

001aac311

MCDATA VOUT2N

Fig 2. Pin conﬁguration

7.2 Pin description

Table 3: Pin description

Symbol Pin Type Description

ref

VINL1 2 AIO ADC 1 input left V

SSA(AD)

VINR1 4 AIO ADC 1 input right V

DDA(AD)

VINL2 6 AIO ADC 2 input left V

ADCN

VINR2 8 AIO ADC 2 input right V

ADCP

VVOICE 10 AIO voice ADC input TEST 11 DID test input; must be connected to digital ground (V

DATAAD2 12 DO ADC 2 data output DATAAD1 13 DO ADC 1 data output BCKAD 14 DIS ADC bit clock input WSAD 15 DI ADC word select input

1 AIO ADC reference voltage

3 AGND ADC analog ground

5 AS ADC analog supply voltage

7 AIO ADC reference voltage N

9 AIO ADC reference voltage P

application

VOUT2P

VOUT1P

DDD SSD

DATADA3

DATADA1

SSD

) in

Product data sheet Rev. 02 — 17 January 2005 5 of 55

Philips Semiconductors

UDA1384

Multichannel audio coder-decoder

Table 3: Pin description

…continued

Symbol Pin Type Description

DATAV 16 DO voice data output BCKV 17 DIS voice bit clock input WSV 18 DIO voice word select input or output SYSCLK 19 DIS system clock input: 256f

, 384fs, 512fs or 768f

MCMODE 20 DI L3-bus L3MODE input or I2C-bus DAC mute control input

MCCLK 21 DIS L3-bus L3CLOCK input or I MCDATA 22 IIC L3-bus L3DATA input and output or I

C-bus SCL input

C-bus SDA input and

output WSDA 23 DI DAC word select input BCKDA 24 DIS DAC bit clock input DATADA1 25 DI DAC channel 1 and channel 2 data input DATADA2 26 DI DAC channel 3 and channel 4 data input DATADA3 27 DI DAC channel 5 and channel 6 data input V

SSD

DDD

I2C_L3 30 DI selection input for L3-bus or I

28 DGND digital ground 29 DS digital supply voltage

C-bus control VOUT1P 31 AIO DAC 1 positive output VOUT1N 32 AIO DAC 1 negative output VOUT2P 33 AIO DAC 2 positive output VOUT2N 34 AIO DAC 2 negative output VOUT3P 35 AIO DAC 3 positive output VOUT3N 36 AIO DAC 3 negative output V

DDA(DA)

37 AS DAC analog supply voltage VOUT4P 38 AIO DAC 4 positive output VOUT4N 39 AIO DAC 4 negative output V

SSA(DA)

40 AGND DAC analog ground VOUT5P 41 AIO DAC 5 positive output VOUT5N 42 AIO DAC 5 negative output VOUT6P 43 AIO DAC 6 positive output VOUT6N 44 AIO DAC 6 negative output

[1] See Table 4.

Table 4: Pin types

Type Description

AGND analog ground AIO analog input and output AS analog supply DGND digital ground DI digital input DID digital input with internal pull-down resistor DIO digital input and output

Product data sheet Rev. 02 — 17 January 2005 6 of 55

Philips Semiconductors

UDA1384

Multichannel audio coder-decoder

Table 4: Pin types

Type Description

DIS digital Schmitt-triggered input DO digital output DS digital supply IIC input and open-drain output for I

8. Functional description

8.1 System clock

The UDA1384 operates in slave mode only; this means that in all applications the system must provide either the system clock (the bit clock for the voice ADC) or the word clock.

The audio ADC part, the voice ADC part and the DAC part can operate at different sampling frequencies (DAC-WS and ADC-WS modes) as well as a common frequency (SYSCLK, WSDA and DSD modes).

The voice ADC part supports a sampling frequency up to 50 kHz and the audio ADC supports a sampling frequency up to 100 kHz. The DAC sampling frequency range is extended up to 200 kHz with the range above 100 kHz being supported through 192 kHz sampling mode, which halves the oversampling ratio of SYSCLK and internal clocks.

…continued

C-bus

The mode of operation of the audio and voice channels can be set via the L3-bus or I2C-bus microcontroller interface and are summarized in Table 5 and Table 6.

When applied, the system clock must be locked in frequency to the corresponding digital interface clocks.

The voice ADC part can either receive or generate the WSV signal as shown in Table 6.

Table 5: Audio ADC and DAC operating clock mode

Mode Audio ADC Audio DAC

Clock Frequency Clock Frequency

SYSCLK SYSCLK 256f

DAC-WS SYSCLK 256f ADC-WS WSAD 1f

WSDA WSDA 1f DSD SYSCLK 44.1 kHz × 512 SYSCLK 44.1 kHz × 512

Table 6: Voice ADC operating clock mode

Mode Voice ADC

Bit clock frequency (BCKV) Word select (WSV)

WSV-in input: 32f WSV-out input: 32f

Product data sheet Rev. 02 — 17 January 2005 7 of 55

, 384fs, 512fs or 768fsSYSCLK 256fs, 384fs, 512fs or 768f

SYSCLK 128fs, 192fs, 256fs or 384fs;

192 kHz sampling mode

, 384fs, 512fs or 768fsWSDA 1f

, 64fs, 128fs or 256f

SYSCLK 256fs, 384fs, 512fs or 768f SYSCLK 128fs, 192fs, 256fs or 384fs;

WSDA 1f

s s

192 kHz sampling mode

input output

Philips Semiconductors

8.2 Audio analog-to-digital converter (audio ADC)

The audio analog-to-digital front-end of the UDA1384 consists of 4-channel single-ended ADCs with programmable gain stage (from 0 dB to 24 dB with 3 dB steps), controlled via the microcontroller interface.Using the PGA feature,it is possible to accept an input signal of 900 mV (RMS) or 1.8 V (RMS) if an external resistor of 10 kΩ is used in series. The schematic of audio ADC front-end is shown in Figure 3.

Fig 3. Schematic of audio ADC front-end

input signal

2 V (RMS)

10 kΩ

VINL, VINR

Multichannel audio coder-decoder

10 kΩ (0 dB setting)

10 kΩ

ref

DDA

mgu582

= 3.3 V

UDA1384

ADC

8.3 Voice Analog-to-Digital Converter (voice ADC)

The voice analog-to-digital front-end of the UDA1384 consists of a single-channel single-ended ADC with a ﬁxed gain (26 dB) Low Noise Ampliﬁer (LNA). Together with the digital variable gain ampliﬁcation stage, the voice ADC provides optimal processing and reproduction of the microphone signal. The supported sampling frequency range is from 7 kHz to 50 kHz. Power-down of the LNA and the ADC can be controlled separately.

8.4 Decimation ﬁlter of audio ADC

The decimation from 64fs is performed in two stages. The ﬁrst stage realizes characteristics with a decimation factor of 8. The second stage consists of three half-band

ﬁlters, each decimating by a factor of 2. The ﬁlter characteristics are shown in Table 7.

Table 7: Decimation ﬁlter characteristics (audio ADC)

Item Condition Value (dB)

Pass-band ripple 0f

to 0.45f

Pass-band droop 0.45f Stop band > 0.55f Dynamic range 0f

to 0.45f

±0.01

−0.2

−70

> 135

8.5 Decimation ﬁlter of voice ADC

xsin



----------



The voice ADC decimation ﬁlter is realized with the combination of a Finite Impulse Response (FIR) ﬁlter and Inﬁnite Impulse Response (IIR) ﬁlter forshorter group delay. The ﬁlter characteristics are shown in Table 8. During the power-on sequence, the output of the ADC is hard muted for a certain period. This hard-mute time can be chosen between 1024 samples and 2048 samples.

Product data sheet Rev. 02 — 17 January 2005 8 of 55

Philips Semiconductors

Table 8: Decimation ﬁlter characteristics (voice ADC)

Item Condition Value (dB)

Pass-band ripple 0f Pass-band droop 0.45f Stop band > 0.55f Dynamic range 0f

8.6 Interpolation ﬁlter of DAC

The digital interpolation ﬁlter interpolates from 1fsto 128fs (or to 64fs in the 192 kHz sampling mode) by cascading FIR ﬁlters, and has two sets of ﬁlter coefﬁcients for sharp and slow roll-off as given in Table 9 and Table 10.

Table 9: Interpolation ﬁlter characteristics (sharp roll-off)

Item Condition Value (dB)

Pass-band ripple 0f Stop band > 0.55f Dynamic range 0f

to 0.45f

UDA1384

Multichannel audio coder-decoder

±0.05

−0.2

−65

> 110

±0.002

−75

> 135

Table 10: Interpolation ﬁlter characteristics (slow roll-off)

Item Condition Value (dB)

Pass-band ripple 0f

to 0.22f

Pass-band droop 0.45f Stop band > 0.78f Dynamic range 0f

to 0.22f

±0.002

−3.1

−94

> 135

8.7 Noise shaper of DAC

The 3rd-order noise shaper operates at either 128fs or 64fs (in the 192 kHz sampling mode), and converts the 24-bit input signal into a 5-bit signal stream. The noise shaper shifts in-band quantization noise to frequencies well above the audio band. This noise shaping technique enables high signal-to-noise ratios to be achieved.

8.8 Digital mixer

The UDA1384 has 6 digital mixers inside the interpolator (see Figure 4). The ADC signals can be mixed with the I2S-bus input signals. The mixing of the ADC signals can be selected by the bits MIX[1:0].

Product data sheet Rev. 02 — 17 January 2005 9 of 55

Philips Semiconductors

]

MIX[1:0

from ADC

ch1 ch2

ch3 ch4

from I

S-bus

mixer input

MIXER

VOLUME

VOLUMEDE-EMPHASIS MUTE

MIXER

MUTE

UDA1384

Multichannel audio coder-decoder

INTERPOLATION

FILTER

DAC1

DATADA1

DATADA2

DATADA3

]

DIS[1:0

]

ICS[1:0

Fig 4. Block diagram of DAC mixer

8.9 Audio digital-to-analog converters

The audio digital-to-analog front-end of the UDA1384 consists of 6-channel differential SDACs: an SDAC is a multi-bit DAC based upon switched resistors. To minimize data dependent modulation effects, a Dynamic Element Matching (DEM) algorithm scrambler circuit and DC current compensation circuit are implemented with the SDAC.

same as above

DAC2

DAC3

DAC4

DAC5

DAC6

mgw786

8.10 Power-on reset

The UDA1384 has an internal power-on reset circuit which initializes the device (see

Figure 5). All the digital sound processing features and the system controlling features are

set to their default values in the L3-bus and the I2C-bus modes. The reset time (see Figure 6) is determined by an external capacitor which is connected

between pin V When V

DDA(AD)

During the reset time, the system clock should be running.

Product data sheet Rev. 02 — 17 January 2005 10 of 55

and ground. The reset time should be at least 250 µs for V

ref

is switched off, the device will be reset again for V

< 0.75 V.

ref

< 1.25 V.

ref

Philips Semiconductors

UDA1384

Multichannel audio coder-decoder

3.3

DDD

(V)

DDA(AD)

C1 > 10 µF

9 kΩ

ref

9 kΩ

RESET

CIRCUIT

mgu585

DDA(AD)

(V)

3.3

ref

(V)

1.65

1.25

0.75

>250 µs

Fig 5. Power-on reset circuit Fig 6. Power-on reset timing

8.11 Audio digital interface

The following audio formats can be selected via the microcontroller interface:

• I

S-bus format with data word length of up to 24 bits

• MSB-justiﬁed format with data word length of up to 24 bits

• LSB-justiﬁed format with data word length of 16 bits, 20 bits or 24 bits

• Multichannel formats with data word length of 20 bits or 24 bits. The used data lines

are DATAAD1 and DATADA1 and the sampling frequency must be below 50 kHz

rst

mgu586

The formats are illustrated in Figure 7 and Figure 8.

Product data sheet Rev. 02 — 17 January 2005 11 of 55

Philips Semiconductors

B15 LSB

UDA1384

Multichannel audio coder-decoder

mgt020

B19 LSB

B23 LSB

RIGHT

> = 8

21> = 812 3

MSB MSBB2

S-BUS FORMAT

RIGHT

LEFT

1518 1720 19 2 1

MSB B2 B3 B4 B5 B6

LSB

B19

LSB-JUSTIFIED FORMAT 20 BITS

1518 1720 19 2 1

MSB B2 B3 B4 B5 B6

15 2 1

MSB B2

RIGHT

LSB

B15

LSB-JUSTIFIED FORMAT 16 BITS

321321

> = 8 > = 8

MSB-JUSTIFIED FORMAT

LEFT

15 2 1

MSB

RIGHT

LEFT

1518 1720 1922 212324 21

B5 B6 B7 B8 B9 B10

B3 B4

MSB

LSB

B23

LSB-JUSTIFIED FORMAT 24 BITS

1518 1720 1922 212324 2 1

B5 B6 B7 B8 B9 B10

B3 B4

BCK

MSB

DATA

LEFT

MSB B2

MSB B2 MSBLSB LSB MSB B2B2

BCK

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx

xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

DATA

BCK

DATA

BCK

DATA

BCK

DATA

Fig 7. Formats of input and output data (single-channel)

Product data sheet Rev. 02 — 17 January 2005 12 of 55

Philips Semiconductors

LSB

CH6

UDA1384

Multichannel audio coder-decoder

mgu588

LSB

CH6

4241 61

MSBLSB

CH4

MSBLSBMSB

CH2

212221

MULTICHANNEL FORMAT 20 BITS

LSB

CH5

4241 61

MSBLSB

5049 73

MSBLSB

CH4

MSBLSBMSB

CH2

(1)

212625

LSB

MULTICHANNEL FORMAT 24 BITS

CH5

5049 73

MSBLSB

73 97

CH4

5049 74

MSBLSBMSB

CH2

(2)

12625

LSB

MULTICHANNEL FORMAT 24 BITS

CH5

MSBLSB

73 97

CH3

MSBLSBMSB

CH1

212221

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx

xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

BCK

DATA

MSBLSBMSB

CH1

212625

BCK

DATA

5049 74

MSBLSBMSB

CH1

12625

BCK

DATA

(1) Format 1.

(2) Format 2.

Fig 8. Formats of input and output data (multichannel)

Product data sheet Rev. 02 — 17 January 2005 13 of 55

Philips Semiconductors

8.12 Voice digital interface

The following voice formats can be selected via the microcontroller interface:

• I

S-bus format with data word length of up to 20 bits. The left and the right channels

contain the same data.

• Mono channel format with data word length of up to 20 bits.

The formats are illustrated in Figure 9.

UDA1384

Multichannel audio coder-decoder

BCK

DATA

BCK

DATA

MSB B2

LEFT

Fig 9. Voice digital interface formats

8.13 DSD mode

The UDA1384 can receive 2.8224 MHz DSD signals and generate 88.2 kHz multibit PCM signals as well as analog signal outputs. The conﬁguration of the UDA1384 in the DSD mode is shown in Figure 10.

21≥ 812 3

MSB MSBB2

S-BUS FORMAT

MONO CHANNEL FORMAT

RIGHT

≥ 8

21≥ 8123

MSB B2

mgu587

OUT1N

OUT1P

OUT2N

OUT2P

mgu584

left channel

right channel

analog output

2.8224 MHz DSD

left

channel

right

channel

5.6448 MHz

88.2 kHz

DATADA2

DATADA3

BCKAD WSAD

DECIMATION

FILTER

I2S-BUS

INTERFACE 1

DATADA1DATAAD1 BCKDA SYSCLK

88.2 kHz

PCM data

S-bus

(left and right)

DAC

INTERPOLATION

NOISE SHAPING

DAC

I2S-BUS

INTERFACE 2

WSDA

88.2 kHz 22.5792 MHz

5.6448 MHz

− +

Fig 10. DSD mode

Product data sheet Rev. 02 — 17 January 2005 14 of 55

Philips Semiconductors

8.14 Microcontroller interface mode

The microcontroller interface mode can be selected as shown in Table 11:

• L3-bus mode when pin I2C_L3 = LOW

• I

C-bus mode when pin I2C_L3 = HIGH

Table 11: Pin function in the L3-bus or I2C-bus mode

Pin Level on pin I2C_L3

MCCLK L3CLOCK SCL MCDATA L3DATA SDA MCMODE L3MODE QMUTE

Table 12: QMUTE

Signal QMUTE Function

LOW no muting HIGH muting

UDA1384

Multichannel audio coder-decoder

LOW HIGH L3-bus mode signal I2C-bus mode signal

All the features are accessible with the I2C-bus interface protocol as with the L3-bus interface protocol.

The detailed description of the device operation in the L3-bus mode and I2C-bus mode is given in Section 9 and Section 10, respectively.

9. L3-bus interface

9.1 General

The UDA1384 has an L3-bus microcontroller interface and all the digital sound processing features and various system settings can be controlled by a microcontroller.

The exchange of data and control information between the microcontroller and the UDA1384 is LSB ﬁrst and is accomplished through a serial hardware L3-bus interface comprising the following pins:

• MCCLK: clock line with signal L3CLOCK

• MCDATA: data line with signal L3DATA

• MCMODE: mode line with signal L3MODE

The L3-bus format has two modes of operation:

• Address mode

• Data transfer mode

The address mode is used to select a device for a subsequent data transfer. The address mode is characterized by signal L3MODE = LOW and a burst of 8 pulses for signal L3CLOCK, accompanied by 8 bits (see Figure 11).

Product data sheet Rev. 02 — 17 January 2005 15 of 55

Philips Semiconductors

The data transfer mode is characterized by signal L3MODE = HIGH and is used to transfer one or more bytes representing a register address, instruction or data.

Basically, two types of data transfers can be deﬁned:

• Write action: data transfer to the device

• Read action: data transfer from the device.

9.2 Device addressing

The device address consists of one byte with:

• Data Operating Mode (DOM) bits 0 and 1 representing the type of data transfer (see

Table 13)

• Address bits 2 to 7 representing a 6-bit device address. The address of the UDA1384

is 01 0100 (bits 2 to 7).

Table 13: Selection of data transfer

DOM Transfer

UDA1384

Multichannel audio coder-decoder

Bit 1 Bit 0

0 0 not used 0 1 not used 1 0 write data or prepare read 1 1 read data

9.3 Register addressing

After sending the device address (including DOM bits), indicating whether the information is to be read or written, one data byte is sent using bit 0 to indicate whether the information will be read or written and bits 1 to 7 for the destination register address.

Basically, there are 3 methods for register addressing:

1. Addressing for write data: bit 0 is logic 0 indicating a write action to the destination register, followed by bits 1 to 7 indicating the register address (see Figure 11).

2. Addressing for prepare read: bit is logic 1, indicating that data will be read from the register (see Figure 12).

3. Addressing for data read action. Here, the device returns a register address prior to sending data from that register. When bit 0 is logic 0, the register address is valid; when bit 0 is logic 1, the register address is invalid (see Figure 12).

Product data sheet Rev. 02 — 17 January 2005 16 of 55

Philips Semiconductors

UDA1384

Multichannel audio coder-decoder

mbl565

mbl567

data byte 1 data byte 2

L3CLOCK

data byte 1 data byte 2

device address

L3MODE

write

10 0

DOM bits

L3DATA

requesting

0/1

valid/invalid

read

prepare read sent by the device

device address

111 0

DOM bits

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx

xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

Fig 11. Data write mode

L3CLOCK

L3MODE

L3DATA

Fig 12. Data read mode

Product data sheet Rev. 02 — 17 January 2005 17 of 55

+ 38 hidden pages