Philips TZA3034U, TZA3034T Datasheet

INTEGRATED CIRCUITS

DATA SH EET

TZA3034T; TZA3034U

SDH/SONET STM1/OC3 postamplifiers

Objective speciﬁcation File under Integrated Circuits, IC19

1998 Jul 07

Philips Semiconductors Objective speciﬁcation

SDH/SONET STM1/OC3 postampliﬁers TZA3034T; TZA3034U

FEATURES

• Pin compatible with the NE/SA5224 and NE/SA5225 but with extended power supply range and less external component count

• Wideband operation from 1.0 kHz to 150 MHz typical

APPLICATIONS

• Digital fibre optic receiver in short, medium and long haul optical telecommunications transmission systems or in high speed data networks

• Wideband RF gain block.

• Applicable in 155 Mbits/s SDH/SONET receivers

• Single supply voltage from 3.0 to 5.5 V

• PECL (Positive Emitter Coupled Logic) compatible data

outputs

• Programmable input signal level-detection which can be adjusted using a single external resistor

• On-chip DC offset compensation without external capacitor

• Fully differential for excellent PSRR.

GENERAL DESCRIPTION

The TZA3034 is a high gain limiting amplifier that is designed to process signals from fibre optic preamplifiers like the TZA3033. It is pin compatible with the NE/SA5224 and NE/SA5225 but with extended power supply range, and needs less external components. Capable of operating at 155 Mbits/s, the chip has input signal level detection with a user-programmable threshold. The data and level-detection status outputs are differential outputs for optimum noise margin and ease of use.

ORDERING INFORMATION

TYPE

NUMBER

NAME DESCRIPTION VERSION

PACKAGE

TZA3034T SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 TZA3034U naked die die in wafﬂe pack carriers; die dimensions 1.58 × 1.58 mm −

BLOCK DIAGRAM

ref

TEST

2 (2, 10, 15, 21, 26)

4 (7) 5 (8)

16 (30)

15 (29)

AGND V

A1 A2 A3

1 kΩ

(3, 4, 6, 9) 3

BAND GAP

REFERENCE

(1, 14) 1

SUB

DC-OFFSET

COMPENSATION

RECTIFIER

CCA

handbook, full pagewidth

DIN

DINQ

RSET

The numbers in brackets refer to the pad numbers of the naked die version.

Fig.1 Block diagram.

(11, 12) 6

25 kΩ

(19, 20, 22, 25)11(27, 28)

(13) 7

DGND V

TZA3034

CCD

(24) 13 (23) 12

(16) 8

(18) 10

(17) 9

DOUT DOUTQ

JAM

ST STQ

MGR281

1998 Jul 07 2

Philips Semiconductors Objective speciﬁcation

SDH/SONET STM1/OC3 postampliﬁers TZA3034T; TZA3034U

PINNING

SYMBOL PIN TYPE DESCRIPTION

SUB 1 substrate substrate pin; must be at the same potential as AGND (pin 3) TEST 2 test pin for test purpose only; to be left open in the application AGND 3 ground analog ground; must be at the same potential as DGND (pin 11) DIN 4 analog input differential input; DC bias level is set internally at approximately 2.55 V;

complimentary to DINQ (pin 5)

DINQ 5 analog input differential input; DC bias level is set internally at approximately 2.55 V;

complimentary to DIN (pin 4)

CCA

CF 7 analog input ﬁlter capacitor for input signal level detector; capacitor should be connected

JAM 8 PECL input PECL-compatible input; controls the output buffers DOUT and DOUTQ

STQ 9 PECL output PECL-compatible status output of the input signal level detector; when the input

ST 10 PECL output PECL-compatible status output of the input signal level detector; when the input

DGND 11 ground digital ground; must be at the same potential as AGND (pin 3) DOUTQ 12 PECL output PECL-compatible differential output; when JAM is HIGH, this pin will be forced

DOUT 13 PECL output PECL-compatible differential output; when JAM is HIGH, this pin will be forced

CCD

ref

RSET 16 analog input input signal level detector programming; nominal DC voltage is V

6 supply analog supply voltage; must be at the same potential as V

between this pin and V

CCA

(pin 6)

CCD

(pin 14)

(pins 13 and 12). When a LOW signal is applied, the outputs will follow the input signal3 When a HIGH signal is applied, the DOUT and DOUTQ pins will latch into LOW and HIGH states, respectively. When left unconnected, this pin is actively pulled LOW (JAM OFF).

signal is below the user-programmed threshold level, this output is HIGH; complimentary to ST (pin 10)

signal is below the user-programmed threshold level, this output is LOW; complimentary to STQ (pin 9)

into a HIGH condition; complimentary to DOUT (pin 13)

into a LOW condition; complimentary to DOUTQ (pin 12)

14 supply digital supply voltage; must be at the same potential as V

CCA

(pin 6)

15 analog output band gap reference voltage; typical value is 1.2 V; internal series resistor of 1 kΩ

− 1.5 V;

CCA

threshold level is set by connecting an external resistor between RSET and V

CCA

or by forcing a current into RSET; default value for this resistor is 180 kΩ which corresponds with approximately 4 mV (p-p) differential input signal

1998 Jul 07 3

Philips Semiconductors Objective speciﬁcation

SDH/SONET STM1/OC3 postampliﬁers TZA3034T; TZA3034U

PAD CONFIGURATION Pad centre locations

handbook, halfpage

SUB

TEST

2 3

AGND

DIN

DINQ

CCA

JAM

TZA3034T

5 6 7 8

MGR282

Fig.2 Pin configuration.

16 15 14 13 12 11 10

RSET V

ref

CCD

DOUT DOUTQ DGND ST STQ

COORDINATES

(1)

SYMBOL PAD

SUB 1 −235.7 +647.8 TEST 2 −392.8 +647.8 AGND 3 −532.8 +647.8 AGND 4 −647.8 +507.1 n.c. 5 −647.8 +350.0 AGND 6 −647.8 +210.0 DIN 7 −647.8 +70.0 DINQ 8 −647.8 −70.0 AGND 9 −647.8 −210.0 TEST 10 −647.8 −350.0 V V

CCA CCA

11 −647.8 −507.1

12 −532.8 −647.8 CF 13 −392.8 −647.8 SUB 14 −235.7 −647.8 TEST 15 −78.6 −647.8 JAM 16 +61.4 −647.8 STQ 17 +218.5 −647.8 ST 18 +375.6 −647.8 DGND 19 +532.7 −647.8 DGND 20 +647.8 −507.1 TEST 21 +647.8 −350.0 DGND 22 +647.8 −210.0 DOUTQ 23 +647.8 −70.0 DOUT 24 647.8 70.0 DGND 25 647.8 210.0 TEST 26 647.8 350.0 V V V

CCD CCD ref

27 647.8 507.1

28 532.7 647.8

29 392.7 647.8 RSET 30 235.6 647.8 n.c. 31 78.5 647.8 n.c. 32 −78.6 +647.8

1998 Jul 07 4

Note

1. Coordinates represent the position of the centre of the pad, in µm, with respect to the centre of the die.

Philips Semiconductors Objective speciﬁcation

SDH/SONET STM1/OC3 postampliﬁers TZA3034T; TZA3034U

Bonding pad locations

handbook, full pagewidth

(1) Typical value. Pad size: 90 ×90 µm.

1.58 mm

AGND 4

n.c.

AGND

DIN

(1)

DINQ

AGND 9

TEST 10

CCA

AGND2TEST1SUB32n.c.31n.c.30RSET29V

5 6 7 8

TZA3034U

CCA

13CF14

SUB

TEST

1.58 mm

JAM

(1)

STQ

ref

18ST19

DGND

CCD

26 25 24 23 22

MGR283

CCD

TEST DGND DOUT DOUTQ DGND TEST21

DGND

Fig.3 Bonding pad locations: TZA3034U.

FUNCTIONAL DESCRIPTION

The TZA3034 accepts up to 155 Mbits/s SD/SONET data streams, with amplitudes from 2 mV (p-p) up to 1 V (p-p) single-ended. The input signal will be amplified and limited to differential PECL output levels (see Fig.1).

The input buffer A1 presents an impedance of approximately 4.5 kΩ to the data stream on the inputs DIN and DINQ. The input can be used both single-ended and differential, but differential operation is preferred for better performance.

Because of the high gain of the postamplifier, a very small offset voltage would shift the decision level in such a way that the input sensitivity decreases drastically. Therefore a DC offset compensation circuit is implemented in the TZA3034, which keeps the input of buffer A3 at its toggle point in the absence of any input signal.

An input signal level detection is implemented to check if the input signal is above the user-programmed level.

The outcome of this test is available at the PECL outputs ST and STQ. This flag can also be used to prevent the PECL outputs DOUT and DOUTQ from reacting to noise in the absence of a valid input signal, by connecting the output STQ to the input JAM. This insures that data will only be transmitted when the input signal-to-noise ratio is sufficient for low bit error rate system operation.

PECL logic

The logic level symbol definitions for PECL are shown in Fig.4.

Input biasing

The input pins DIN and DINQ are DC biased at approximately 2.55 V by an internal reference generator (see Fig.5). The TZA3034 can be DC coupled, but AC coupling is preferred. In case of DC coupling, the driving source must operate within the allowable input signal range (2.0 V to V

+ 0.5 V). Also a DC offset voltage of

CCA

1998 Jul 07 5

Philips Semiconductors Objective speciﬁcation

SDH/SONET STM1/OC3 postampliﬁers TZA3034T; TZA3034U

more than a few millivolt should be avoided, since the internal DC offset compensation circuit has a limited correction range.

If AC coupling is used to remove any DC compatibility requirement, the coupling capacitors must be large enough to pass the lowest input frequency of interest. For example, 1 nF coupling capacitors react with the internal 4.5 kΩ input bias resistors to yield a lower −3dB frequency of 35 kHz. This then sets a limit on the maximum number of consecutive pulses that can be sensed accurately at the system data rate. Capacitor tolerance and resistor variation must be included for an accurate calculation.

DC-offset compensation

A control loop connected between the inputs of buffer A3 and amplifier A1 (see Fig.1) will keep the input of buffer A3 at its toggle point in the absence of any input signal. Because of the active offset compensation which is integrated in the TZA3034, no external capacitor is required. The loop time constant determines the lower cut-off frequency of the amplifier chain, which is set at approximately 850 Hz.

Input signal level-detection

The TZA3034 allows for user-programmable input signal level-detection and can automatically disable the switching of the PECL outputs if the input signal is below a set threshold. This prevents the outputs from reacting to noise in the absence of a valid input signal, and insures that data will only be transmitted when the signal-to-noise ratio of the input signal is sufficient for low bit-error-rate system operation. Complementary PECL flags (ST and STQ) indicate whether the input signal is above or below the programmed threshold level.

The input signal is amplified and rectified before being compared to a programmable threshold reference. A filter is included to prevent noise spikes from triggering the level-detector. This filter has a nominal 1 µs time constant and additional filtering can be achieved by using an external capacitor between pin CF and V

(the internal

CCA

driving impedance nominally is 25 kΩ). The resultant signal is then compared to a threshold current through pin RSET (see Fig.6). This current can be set by connecting an external resistor R pin RSET and V

, or by forcing a current into pin RSET.

CCA

DETECT

between

The relationship between the threshold current and the detected input voltage is approximately:

RSET

0.002 V

–()A[]×=

DINVDINQ

(1)I

Since the voltage on pin RSET is held constant at 1.5 V below V

RSET

, the current flowing into this pin will be:

CCA

1.5

----------------------- R

DETECT

A[]=

(2)

Combining these two formulas results in a general formula to calculate R

for a given input signal

DETECT

level-detection:

DETECT

----------------------------------------- V

In this formula, V

750

–()

DINVDINQ

and V

DIN

Ω[]=

are in V (p-p).

DINQ

(3)

Example: Detection should occur if the differential voltage of the input signals drops below 4 mV (p-p). In this case, a reference current of 0.002 × 0.004 = 8 µA should flow into pin RSET. This can be set using a current source or simply by connecting a resistor of the appropriate value. The resistor must be connected between V

CCA

and

pin RSET. In this example the resistor would be:

DETECT

750

---------------- -

0.004

187.5 kΩ==

The hysteresis is fixed internally at 3 dB electrical. In the example of above, a differential level below 4 mV (p-p) of the input signal will drive pin ST to LOW, and an input signal level above 5.7 mV (p-p) will drive pin ST to HIGH.

Since a JAM function is provided which forces the data outputs to a predetermined state (DOUT = LOW and DOUTQ = HIGH), the pins STQ and JAM can be connected to automatically disable the signal transmission when the chip senses that the input signal is below the programmed threshold.

Response time of the input signal level-detection circuit is determined by the time constant of the input capacitors, together with the filter time constant (1 µs internal plus the additional capacitor at pin CF).

PECL output circuits

The output circuit of ST and STQ is given in Fig.7. The output circuit of DOUT and DOUTQ is given in Fig.8. Some PECL termination schemes are given in Fig.9.

1998 Jul 07 6

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