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TZA3023

SDH/SONET STM4/OC12
transimpedance amplifier

Product specification
Supersedes data of 1997 Oct 17
File under Integrated Circuits, IC19

2000 Mar 29

Philips Semiconductors Product specification

SDH/SONET STM4/OC12

TZA3023

transimpedance amplifier

FEATURES

• Wide dynamic input range from 1 µA to 1.5 mA

• Low equivalent input noise of 3.5 pA/√Hz (typical)

• Differential transimpedance of 21 kΩ

• Wide bandwidth from DC to 600 MHz

• Differential outputs

• On-chip Automatic Gain Control (AGC)

• No external components required

• Single supply voltage from 3.0 to 5.5 V

• Bias voltage for PIN diode

• Pin compatible with SA5223.

ORDERING INFORMATION

TYPE

NUMBER

NAME DESCRIPTION VERSION

TZA3023T SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1
TZA3023U − bare die in waffle pack carriers; die dimensions 1.030 × 1.300 mm −

APPLICATIONS

• Digital fibre optic receiver in short, medium and long
haul optical telecommunications transmission systems
or in high-speed data networks

• Wideband RF gain block.

DESCRIPTION

TheTZA3023isalow-noisetransimpedanceamplifierwith
AGC designed to be used in STM4/OC12 fibre optic links.
It amplifies the current generated by a photo detector
(PIN diode or avalanche photodiode) and converts it to a
differential output voltage.

PACKAGE

BLOCK DIAGRAM

handbook, full pagewidth

DREF

The numbers in brackets refer to the pad numbers of the bare die version.
(1) AGC analog I/O is only available on the TZA3023U (pad 13).

V

CC

8 (11, 12)

2

kΩ

1 (1)

3 (4)IPhoto

2, 4, 5 (2, 3, 5, 6, 7, 8)

GND

GAIN

CONTROL

TZA3023

(1)

AGC

(13)

peak detector

A1

low noise

amplifier single-ended to

differential converter

BIASING

7 (10) OUTQ

6 (9) OUT

MGK918

Fig.1 Block diagram.

2000 Mar 29 2

Philips Semiconductors Product specification

SDH/SONET STM4/OC12

TZA3023

transimpedance amplifier

PINNING

SYMBOL

PIN

TZA3023T

DREF 1 1 analog output bias voltage for PIN diode; cathode should be connected to

GND 2 2, 3 ground ground
IPhoto 3 4 analog input current input; anode of PIN diode should be connected to this

GND 4 5, 6 ground ground
GND 5 7, 8 ground ground
OUT 6 9 output data output; pin OUT goes HIGH when current flows into

OUTQ 7 10 output data output; compliment of pin OUT
V

CC

8 11, 12 supply supply voltage

AGC − 13 input/output AGC analog I/O

PAD

TZA3023U

TYPE DESCRIPTION

this pin

pin; DC bias level of 800 mV, one diode voltage aboveground

pin IPhoto

handbook, halfpage

DREF

1
2

TZA3023T

3

IPhoto

4

GND

MGK917

Fig.2 Pin configuration.

V

8

CC

OUTQGND

7

OUT

6

GND

5

2000 Mar 29 3

Philips Semiconductors Product specification

SDH/SONET STM4/OC12
transimpedance amplifier

FUNCTIONAL DESCRIPTION

The TZA3023 is a transimpedance amplifier intended for
use in fibre optic links for signal recovery in STM4/OC12
applications. It amplifies the current generated by a photo
detector (PIN diode or avalanche photodiode) and
transforms it into a differential output voltage. The most
important characteristics of theTZA3023 are highreceiver
sensitivity and wide dynamic range.

Highreceiver sensitivity is achieved by minimizing noisein
the transimpedance amplifier. The signal current
generated by a PIN diode can vary between
1 µA to 1.5 mA (p-p). An AGC loop is implemented to
make it possible to handle such a wide dynamic range.
TheAGCloop increases the dynamic rangeofthe receiver
by reducing the feedback resistance of the preamplifier.

handbook, full pagewidth

V

CC

600 Ω 600 Ω

TZA3023

The AGC loop hold capacitor is integrated on-chip, so an
external capacitor is not needed for AGC. The AGC
voltage can be monitored at pad 13 on the bare die
(TZA3023U).Pad 13isnotbondedin the packaged device
(TZA3023T). This pad can be left unconnected during
normal operation. It can also be used to force an external
AGC voltage. If pad 13 is connected to GND, the internal
AGC loop is disabled and the receiver gain is at a
maximum. The maximum input current is then
approximately 50 µA.

A differential amplifier converts the single-ended output of
the preamplifier to a differential output voltage (see Fig.3).

handbook, full pagewidth

V

O(max)

V

V

V

O(min)

OQH

V

OH

OQL

V

OL

2 mA

4.5 mA

Fig.3 Data output buffer.

CML/PECL OUTPUT

V

OO

30 Ω
30 Ω

4.5 mA

MGK922

V

CC

V

o (p-p)

MGK885

V

OUTQ

V

OUT

Fig.4 Logic level symbol definitions for data outputs OUT and OUTQ.

2000 Mar 29 4

Philips Semiconductors Product specification

SDH/SONET STM4/OC12
transimpedance amplifier

PIN diode bias voltage DREF

The transimpedance amplifier together with the PIN diode
determines the performance of an optical receiver for a
large extent. Especially how the PIN diode is connected to
the input and the layout around the input pin influence the
key parameters like sensitivity, bandwidth and the Power
Supply Rejection Ratio (PSRR) of a transimpedance
amplifier. The total capacitance at the input pin is critical to
obtain the highest sensitivity. It should be kept to a
minimum by reducing the capacitor of the PIN diode and
the parasitics around the input pin. The PIN diode should
be placed very close to the IC to reduce the parasitics.
Because the capacitance ofthe PIN diode dependson the
reverse voltage across it, the reverse voltage should be
chosen as high as possible.

The PIN diode can be connected to the input in two ways
as shown in Figs 5 and 6. In Fig.5 the PIN diode is
connectedbetweenDREFandIPhoto.Pin DREFprovides
an easy bias voltage for the PIN diode. The voltage at
DREF is derived from VCC by a low-pass filter. The
low-passfilterconsistingof the internal resistor R1, C1 and
the external capacitor C2 rejects the supply voltage noise.
The external capacitor C2 should be equal or larger then
1 nF for a high PSRR.

TZA3023

The reverse voltage across the PIN diode is 4.2 V
(5 − 0.8 V) for 5 V supply or 2.5 V (3.3 − 0.8 V) for 3.3 V
supply.

The DC voltage at DREFdecreases with increasingsignal
levels. Consequently the reverse voltage across the
PIN diode will also decrease with increasing signal levels.
This can be explained with an example. When the
PIN diode delivers a peak-to-peak current of 1 mA, the
average DC current will be 0.5 mA. This DC current is
delivered by VCC through the internal resistor R1 of 2 kΩ
which will cause a voltage drop of 1 V across the resistor
and the reverse voltage across the PIN diode will be
reduced by 1 V.

It is preferable to connect the cathode of the PIN diode to
a higher voltage then VCC when such a voltage source is
available on the board. In this case pin DREF can be left
unconnected.Whenanegativesupplyvoltageisavailable,
the configuration in Fig.6 can be used. It should be noted
that in this case the direction of the signal current is
reversed compared to Fig.5. Proper filtering of the bias
voltage for the PIN diode is essential to achieve the
highest sensitivity level.

V

CC

8

R1

2 kΩ

4

C1

10 pF

7

TZA3023

MCD900

C2

1 nF

I

DREF

i

IPhoto

Fig.5 ThePIN diodeconnected between the input

and pin DREF.

2000 Mar 29 5

V

CC

8

R1

DREF

IPhoto

I

i

negative supply voltage

2 kΩ

4

C1

10 pF

7

TZA3023

MCD901

Fig.6 ThePIN diodeconnected between the input

and a negative supply voltage.

Philips Semiconductors Product specification

SDH/SONET STM4/OC12
transimpedance amplifier

AGC

TZA3023 transimpedance amplifier can handle input
currents from 0.5 µA to 1.5 mA. This means a dynamic
range of 72 dB. At low input currents, the transimpedance
must be high to get enough output voltage, and the noise
should be low enough to guaranty minimum bit error rate.
At high input currents however, the transimpedance
should be low to avoid pulse width distortion. This means
that the gain of the amplifier has to vary depending on the
input signal level to handle such a wide dynamic range.
This is achieved in the TZA3023 by implementing an
Automatic Gain Control (AGC) loop.

TheAGCloop consists of a peak detector, aholdcapacitor
and a gain control circuit. The peak amplitude of the signal
isdetected by the peakdetectorand it is storedonthe hold
capacitor.Thevoltage over the hold capacitor iscompared
to a threshold level. The threshold level is set to
10 µA (p-p) input current. AGC becomes active only for
input signals larger than the threshold level.

TZA3023

It is disabled for smaller signals. The transimpedance is
then at its maximum value (21 kΩ differential).

When the AGC is active, the feedback resistor of the
transimpedance amplifier is reduced to keep the output
voltage constant. The transimpedance is regulated from
21 kΩ at low currents (I < 10 µA) to 800 Ω at high currents
(I < 500 µA). Above 500 µA the transimpedance is at its
minimum and can not be reduced further but the front-end
remains linear until input currents of 1.5 mA.

The upper part of Fig.7 shows the output voltages of the
TZA3023 (OUT and OUTQ) as a function of the DC input
current. In the lower part, the difference of both voltages is
shown. It can be seen from the figure that the output
changes linearly up to 10 µA input current where AGC
becomes active. From this point on, AGC tries to keep the
differential output voltage constant around 200 mV for
medium range input currents (input currents <200 µA).
The AGC can not regulate any more above 600 µA input
current, and the output voltage rises again with the input
current.

1.8

handbook, full pagewidth

V

o

(V)

1.6

1.4

1.2

1

600

V

o(dif)

(mV)

400

200

0

110

V

o(dif)=VOUT

(1) VCC=3V.
(2) VCC= 3.3 V.
(3) VCC=5V.

− V

OUTQ

MCD914

V

OUT

VCC = 3 V

V

OUTQ

(1)

(2)
(3)

10

.

2

3

10

Ii (µA)

4

10

Fig.7 AGC characteristics.

2000 Mar 29 6

Philips Semiconductors Product specification

SDH/SONET STM4/OC12

TZA3023

transimpedance amplifier

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134).

SYMBOL PARAMETER MIN. MAX. UNIT

V

CC

V

n

I

n

P

tot

T

stg

T

j

T

amb

supply voltage −0.5 +6 V
DC voltage

pin 3/pad 4: IPhoto −0.5 +1 V
pins 6 and 7/pads 9 and 10: OUT and OUTQ −0.5 V
pad 13: AGC (TZA3023U only) −0.5 V
pin 1/pad 1: DREF −0.5 V

+ 0.5 V

CC

+ 0.5 V

CC

+ 0.5 V

CC

DC current

pin 3/pad 4: IPhoto −1 +2.5 mA
pins 6 and 7/pads 9 and 10: OUT and OUTQ −15 +15 mA
pad 13: AGC (TZA3023U only) −0.2 +0.2 mA

pin 1/pad 1: DREF −2.5 +2.5 mA
total power dissipation − 300 mW
storage temperature −65 +150 °C
junction temperature − 125 °C
ambient temperature −40 +85 °C

HANDLING

Precautions should be taken to avoid damage through electrostatic discharge. This is particularly important during
assembly and handling of the bare die. Additional safety can be obtained by bonding the VCC and GND pads first, the
remaining pads may then be bonded to their external connections in any order.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER VALUE UNIT

R

th(j-a)

thermal resistance from junction to ambient 160 K/W

2000 Mar 29 7

Philips Semiconductors Product specification

SDH/SONET STM4/OC12

TZA3023

transimpedance amplifier

CHARACTERISTICS

Typical values at T
temperature range and supply range; all voltages are measured with respect to ground; unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V
I

P

T
T
R

CC

CC

tot

j
amb
tr

supply voltage 3 5 5.5 V
supply current VCC= 5 V; ACcoupled;

total power dissipation VCC=5V − 140 248 mW

junction temperature −40 − +125 °C
ambient temperature −40 +25 +85 °C
differential small-signal

transresistance of the
receiver

f

−3dB(h)

high frequency −3 dB point VCC=5V; Ci= 0.7 pF 450 580 750 MHz

PSRR power supply rejection ratio measured differentially;

Bias voltage: pin DREF

R

DREF

resistance between
pins DREF and V

Input: pin IPhoto

V

bias(IPhoto)

input bias voltage on
pin IPhoto

I

i(IPhoto)(p-p)

input current on pin IPhoto
(peak-to-peak value)

R

i

I

n(tot)

small-signal input resistance fi= 1 MHz; input current

total integrated RMS noise
current over bandwidth
(referenced to input)

=25°C and VCC= 5 V; minimum and maximum values are valid over the entire ambient

amb

23 28 45 mA

=50Ω

R

L

V

= 3.3V; ACcoupled;

CC

20 28 42 mA

RL=50Ω

V

= 3.3 V − 95 152 mW

CC

VCC= 5 V; ACcoupled;

17.5 21 25 kΩ

RL=50Ω
V

= 3.3 V; AC coupled;

CC

16 19.5 25 kΩ

RL=50Ω

V

= 3.3 V; Ci= 0.7 pF 440 520 600 MHz

CC

note 1

f = 100 kHz to 10 MHz − 12µA/V
f = 10 to 100 MHz − 25µA/V
f = 100 MHz to 1 GHz − 5 100 µA/V

DC tested 1680 2000 2320 Ω

CC

720 800 970 mV

VCC= 5 V; note 2 −1500 +4 +1500 µA
V

= 3.3 V; note 2 −1000 +4 +1000 µA

CC

− 95 −Ω

<2 µA (p-p)
note 3

∆f = 311 MHz − 55 − nA
∆f = 450 MHz − 80 − nA
∆f = 622 MHz − 120 − nA

2000 Mar 29 8