Philips TMS320C6713 User Manual
Application Report
SPRA921 - June 2003
TMS320C6713 Digital Signal Processor Optimized for High
Performance Multichannel Audio Systems
Roshan Gummattira, Philip Baltz,
Nat Seshan
ABSTRACT
The TMS320C6713’s high performance CPU and rich peripheral set are tailored for
multichannel audio applications such as broadcast and recording mixing, home and large
venue audio decoders, and multi-zone audio distribution. The TMS320C6713 device is
based on the high-performance advanced VelociTI very-long-instruction-word (VLIW)
architecture developed by T exas Instruments (TI). The VelociTI architecture provides ample
performance to decode a variety of existing digital audio formats and the flexibility to add
future formats.
This paper will describe the following parts of the TMS32C6713 processor and their impact
on high performance multichannel audio systems:
• The external peripheral architecture
• The C67x CPU architectural features and performance
• The real-time two-level cache architecture
• The multichannel audio serial ports (McASPs)
DSP Applications
Contents
1 Introduction 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 System I/O 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 C67x CPU and Instruction Set 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 Functional Units 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Fixed and Floating Point Instruction Set 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 Load/Store Architecture 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4 Benchmark Performance 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Two-Level Cache 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Cache Overview 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Cache Hides Off-Chip Latency 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 Unified L2 for Program and Data 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4 Real Time Features 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.1 Interrupt Handling 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.2 Real Time I/O 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5 Cache Summary 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks are the property of their respective owners.
1
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4 McASP 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 McASP Overview 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2 TDM Synchronous Transfer Mode 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3 DIT Transfer Mode 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4 McASP clock generators 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5 McASP Error Handling and Management 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6 McASP Summary 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 Conclusion 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6 References 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Figures
Figure 1 Digital Surround Receiver Block Diagram 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 2 Generalized High Performance Multichannel Audio System 4. . . . . . . . . . . . . . . . . . . . . . . .
Figure 3 TMS3206713 CPU and Peripheral Connectivity. 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Tables
Table 1 C6713 Benchmark Performance 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1 Introduction
High performance, multichannel audio applications are evolving at a rapid rate. In the consumer
space, many standards have been defined. For example:
• Theater and home theater surround standards including: Dolby Pro Logic (II), Dolby Digital
(EX), DTS(-ES), Sony Dynamic Digital Sound (SDDS).
• Digital audio formats for portable and/or higher density (greater compression) playback:
MPEG 2 Layer 3 (MP3), AAC, MPEG 4, Microsoft Windows Media, Meridian Lossless
Packing(MLP) (DVD-Audio), Rich Music Format (RMF).
In addition to consumer standards, many companies are developing their own high performance
multichannel audio applications. Digital technology is being applied to large venues such as
stadiums, auditoriums, and movie theaters to tune the listening experience to the room
acoustics. Audio broadcast, production, and recording equipment implement effects generation
as well as multichannel audio mixing, equalization, enhancement, and music.
1.1 System I/O
Figure 1 shows a block diagram of a digital surround receiver. Figure 2 generalizes that to many
high performance multichannel audio systems. The TMS320C6713’s peripheral set enables
ease of connection to the major elements of these systems. The peripheral set includes:
• Two McASPs that provide simple cost effective, connectivity to multiple serial digital audio
streams
• Two Inter-IC (I2C) buses for connection to serial ROMs or to control other system interface
devices like user I/O
• A dedicated general-purpose input/output (GPIO) module to provide direct control lines to
system components, eliminating much of the glue logic in many designs
2 TMS320C6713 Digital Signal Processor Optimized for High Performance Multichannel Audio Systems
SPRA921
• Glueless external memory interface (EMIF) capable of interfacing to SDRAM for bulk
external storage of additional code or delay buffers. The EMIF also supports synchronous
burst SRAM (SBSRAM), asynchronous memories, and peripherals with parallel interfaces.
• A host-port interface (HPI) for direct connection to a host processor
Figure 3 shows additional peripherals and the internal connection of the device. This includes:
• A highly efficient 16-channel enhanced direct memory access (EDMA) controller connects
the peripherals to the internal and external memory. This controller can interleave transfers
from different sources/destinations on a cycle-by-cycle basis, avoiding dead time of most
DMAs when a higher priority transfer interrupts a lower priority one.
• Highly configurable PLL and clocking control logic to enable a variety of ratios of system and
CPU clocks
• 256K bytes of internal memory to provide a large internal program and data store
• Two multichannel buffered serial ports (McBSPs) provide general connection to multiple
serial standards including SPI
• Two general-purpose timers to count system events or generate clock outputs
Optical
digital
Coaxial
digital
Optical
digital
receiver
in
in
S/P DIF
receiver
RAM/ROM
L
Record out
R
Multichannel
analog
Stereo
analog
Multichannel
TMS320C6713
in
Multichannel
L
R
L
R
L
R
in
L
R
L
R
Tuner
Multiplexer
A to D
conversion
User displays
and controls
System
controller
IR receiver
D to A
conversion
Amp
Amp
Amp
Amp
Amp
Multichannel
analog
out
Speaker
level
out
Subwoofer
out
Figure 1. Digital Surround Receiver Block Diagram
TMS320C6713 Digital Signal Processor Optimized for High Performance Multichannel Audio Systems
3
SPRA921
SDRAM
Directly
connected to
other system
components
GPIO
McASP
port 0
McASP
port 1
Serially
controlled
interface
devices
Multiple serial
input streams
(A/D converters,
DIR/SPDIF
receivers)
EMIF
McASP
port 0
McASP
port 1
HPI IIC IIC
Host
processor
TMS320C6713
digital
signal
processor
ROM
Figure 2. Generalized High Performance Multichannel Audio System
32
EMIF
McASP1
McASP0
McBSP1
McBSP0
Pin multiplexing
Timer 1
I2C1
I2C0
L2Cache/
memory
4 banks
64K
bytes
total
(up to
4–way)
Enhanced
DMA
controller
(16
channel)
L2
memory
192K
bytes
C6713 digital signal processor
L1P cache
direct mapped
4K bytes total
C67x CPU
L1D cache 2–way
set associative
4K bytes
Multiple serial
output streams
(D/A converters,
DIT/SPDIF line
converters)
Timer 0
Clock generator
32
GRO
HPI
oscillator and PLL
x4 through x25
multiplier
/1 through /32
dividers
Power–
down
logic
Figure 3. TMS3206713 CPU and Peripheral Connectivity.
4 TMS320C6713 Digital Signal Processor Optimized for High Performance Multichannel Audio Systems
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