Philips TEA5880TS User Manual

TEA5880TS

Integrated FM stereo radio IC for host processor tuning in handheld applications

Rev. 02 — 26 April 2004 Preliminary data sheet

1. General description

The TEA5880TS stereo FM radio IC dramatically reduces the printed-circuit board area (only 100 mm2) needed to integrate FM radio functionality into portable devices. This makes it invaluable for any application where space is at a premium.

Relying on a system host processor for radio tuning, the TEA5880TS is ideally suited for powerful devices such as PDAs, notebooks, portable CD and MP3 players.

2. Features

■ No alignments necessary

■ Complete adjustment-free stereo decoder; no external crystal required

■ Fully integrated MPX VCO circuit

■ Fully integrated low IF selectivity and demodulation

■ The full integration level means no or few external components required

■ No external FM discriminator needed due to full integration

■ Built-in adjacent channel interference total reduction (no 114 kHz, no 190 kHz)

■ The leveloftheincomingsignalatwhichtheradiomust lock is software programmable

■ Due to new tuning concept, the tuning is independent of the channel spacing

■ Very high sensitivity due to integrated low noise RF input ampliﬁer

■ RF Automatic Gain Control (AGC) circuit

■ Standby mode for power-down, no power switch circuitry required

■ 2.7 V minimum supply voltage

■ MPX output for RDS

■ 3-wire bus

■ In combination withthe host, fast, low power operation of preset mode, manual search,

automatic search and automatic store are possible

■ Host can be in Sleep mode after tuning; a minute retuning is recommended to

compensate for temperature and voltage ﬂuctuations

■ Covers all Japanese, European and US bands.

Philips Semiconductors

TEA5880TS

Integrated FM stereo radio IC for host processor tuning

3. Quick reference data

Table 1: Quick reference data

= V

CCA

Symbol Parameter Conditions Min Typ Max Unit

V V I

CCA

CCD

LED

FM(ant)

FM overall system parameters

SUP IP3

IP3

IR image rejection f V

V (S+N)/N maximum signal plus

CCA CCD

amb

i(RF)

out

−300

+300

−200

+200

AUDL AUDR

CCD

analog supply voltage 2.7 3.0 5.0 V digital supply voltage 2.7 3.0 5.0 V analog supply current operating - 17 22 mA

standby - 1 100 µA

digital supply current operating - 250 500 mA

standby - 1 100 µA optional stereo LED - 1 2 mA FM input frequency 76 - 108 MHz ambient temperature V

RF sensitivity input voltage

CCA CCA

= V = V

CC(VCO) CC(VCO)

= V = V

= 3 V −10 - +75 °C

CCD

= 5 V −40 - +85 °C

CCD

fRF = 76 MHz to 108 MHz; ∆f = 22.5 kHz;

= 1 kHz; (S+N)/N = 26 dB;

mod

-13µV

de-emphasis = 75 us;

= 300 Hz to 15 kHz; left = right

pilot suppression ∆f

pilot

in-band 3rd order

= 6.75 kHz; ∆f = 68.5 kHz 40 dB

pilot

-95-dBµV intercept point at LNA input

out-band 3rd order

-95-dBµV intercept point at LNA input

LOW side 300 kHz

∆f = −300 kHz; fRF= 76 MHz to 108 MHz - 40 - dB

selectivity HIGH side 300 kHz

∆f = 300 kHz; fRF = 76 MHz to 108 MHz - 50 - dB

selectivity LOW side 200 kHz

∆f = −200 kHz; fRF = 76 MHz to 108 MHz - 30 - dB

selectivity HIGH side 200 kHz

∆f = 200 kHz; fRF = 76 MHz to 108 MHz - 40 - dB

selectivity

= 76 MHz to 108 MHz - 26 - dB

;

left and right audio output voltage

noise-to-noise ratio

stereo channel separation

VRF = 1 mV; left = right; ∆f = 22.5 kHz; f

= 1 kHz

mod

= 1 mV; left = right; ∆f = 22.5 kHz;

= 1 kHz de-emphasis = 75 µs;

mod

= 300 Hz to 15 kHz

VRF = 1 mV; right = 1 and left = 0 or right = 0 and left = 1; f ∆f

= 6.75 kHz; ∆f

pilot

∆f

= 0 or ∆f

right

= 68.5 kHz and ∆f

right

= 1 kHz;

mod

= 68.5 kHz and

left

- 100 - mV

48 56 - dB

15 25 - dB

= 0

Preliminary data sheet Rev. 02 — 26 April 2004 2 of 27

Philips Semiconductors

TEA5880TS

Integrated FM stereo radio IC for host processor tuning

Table 1: Quick reference data

= V

CCA

Symbol Parameter Conditions Min Typ Max Unit

THD total harmonic distortion VRF = 1 mV; left = right; ∆f = 75 kHz;

DEEM

CCD

integrated de-emphasis - 50/75 - µs

…continued

= 1 kHz; BAF = 300 Hz to 15 kHz

mod

= 1 mV; left = right; ∆f = 22.5 kHz;

= 1 kHz; BAF = 300 Hz to 15 kHz

mod

- 0.7 1.5 %

- 0.2 0.7 %

4. Ordering information

Table 2: Ordering information

Type number Package

Name Description Version

TEA5880TS SSOP24 plastic shrink small outline package; 24 leads; body width 5.3 mm SOT340-1

Preliminary data sheet Rev. 02 — 26 April 2004 3 of 27

Preliminary data sheet Rev. 02 — 26 April 2004 4 of 27

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MICROCONTROLLER

LR1 V

CC1VCC1

LL1

reserved

2117 18 19 20

R/W CLOCK 68 7

DATA

5. Block diagram

Philips Semiconductors

RFIN

RFGND

QUADRATURE

OSCILLATOR

QUADRATURE

STABILISATOR

MIXER

SELECTIVITY DEMODULATOR

TUNING

SYSTEM

CCA

POWER SWITCH

CCD

DIGITAL

INTERFACE

STEREO

DECODER

DE-EMPHASIS

50/75 µs

TEA5880TS

4 3, 13, 24

GND LED n.c.

12 14, 15, 16, 22, 23

LEVEL VOLTAGE

GENERATOR

DE-EMPHASIS

15 kHz

MIXER

001aaa665

AUDL

AUDR

MPX

Fig 1. Block diagram.

Depending on the antenna design the ﬁlter components at pins 1 and 2 may not be necessary.The only two remaining coils connected to pin 17 to 20 can be replaced by printed-circuit board traces that will ﬁt underneath the TEA5880TS resulting in a design without any external components; see Section 14 for details on the printed-circuit board coils.

Integrated FM stereo radio IC for host processor tuning

TEA5880TS

Preliminary data sheet Rev. 02 — 26 April 2004 5 of 27

MICROCONTROLLER

LR1 V

CC1VCC1

LL1

reserved

2117 18 19 20

R/W CLOCK 68 7

DATA

Philips Semiconductors

QUADRATURE

OSCILLATOR

RFIN

RFGND

QUADRATURE

MIXER

STABILISATOR

SELECTIVITY DEMODULATOR

Fig 2. Block diagram (no external components).

TUNING

SYSTEM

CCA

POWER SWITCH

CCD

DIGITAL

INTERFACE

STEREO

DECODER

DE-EMPHASIS

50/75 µs

TEA5880TS

4 3, 13, 24

GND LED n.c.

12 14, 15, 16, 22, 23

LEVEL VOLTAGE

GENERATOR

DE-EMPHASIS

15 kHz

MIXER

001aaa666

AUDL

AUDR

MPX

Integrated FM stereo radio IC for host processor tuning

TEA5880TS

Philips Semiconductors

6. Pinning information

6.1 Pin description

Table 3: Pin description

Symbol Pin Description

RFIN 1 RF input RFGND 2 RF ground GND 3 ground V

CCD

CCA

R/W 6 digital read/write command input DATA 7 bidirectional digital data line CLOCK 8 digital data clock line input MPX 9 FM MPX signal output AUDL 10 audio left channel output AUDR 11 audio right channel output LED 12 stereo LED output GND 13 ground n.c. 14 not connected n.c. 15 not connected n.c. 16 not connected LR1 17 coil right V

CC1

LL1 20 coil left reserved 21 reserved for testing use n.c. 22 not connected n.c. 23 not connected GND 24 ground

TEA5880TS

Integrated FM stereo radio IC for host processor tuning

4 digital supply voltage 5 analog supply voltage

18 internal analog voltage 19 internal analog voltage

Preliminary data sheet Rev. 02 — 26 April 2004 6 of 27

Philips Semiconductors

TEA5880TS

Integrated FM stereo radio IC for host processor tuning

Fig 3. Pin conﬁguration.

7. Functional description

7.1 FM quadrature mixer

The FM quadrature mixer converts FM RF (76 MHz to 108 MHz) to an IF of 110 kHz. The FM quadrature mixer provides inherent image rejection.

RFIN GND

RFGND n.c.

CLOCK LR1

GND n.c.

CCD

CCA

R/W V

6 7 8

9 10 11 12

TEA5880TS

001aaa667

DATA V

MPX n.c.

AUDL n.c.

AUDR n.c.

LED GND

24 23 22 21 20 19 18 17 16 15 14 13

reserved LL1

CC1 CC1

7.2 Quadrature oscillator

The internally tuned LC VCO provides the Local Oscillator (LO) signal for the FM quadrature mixer. The VCO frequency range is 150 MHz to 217 MHz.

7.3 Selectivity

Fully integrated I and Q channel IF ﬁlter.

7.4 Demodulator

The FM quadrature demodulator is an integrated PLL demodulator.

7.5 Level voltage generator and analog-to-digital converter

The level voltage is analog-to-digital converted with 3 bits and output via the data line.

7.6 IF counter

The IF counter outputs a 16-bit count result via the data line.

7.7 Mute

The digital interface controls the audio mute and output level.

Preliminary data sheet Rev. 02 — 26 April 2004 7 of 27

Philips Semiconductors

7.8 Stereo decoder

The PLL stereo decoder is adjustment free. The stereo decoder can be switched to mono via the digital interface.

8. Digital interface (3-wire bus)

The TEA5880TS has a 3-wire bus with read/write, clock and data line. The register set of the TEA5880TS can be accessed via the digital interface. The pins given in Table 4 are deﬁned for the digital interface of the TEA5880TS.

Table 4: Digital interface pins

Pin number Name Type Description Remark

Pin 6

Pin 8 CLOCK input clock rising edge Pin 7 DATA input/output bidirectional data

R/W input LOW is read from TEA5880TS;

TEA5880TS

Integrated FM stereo radio IC for host processor tuning

HIGH is write to TEA5880TS

DATA

R/W

enable

counter 1

R/W

OUTPUT SOURCE

SELECTOR

CLOCK

15 BITS SIPO (SERIAL IN PARALLEL OUT)

4 bits data

ADDRESS

DECODER

COUNTER 1 (16 bits)

16 bits data 16 bits data

16 BITS PISO (PARALLEL IN SERIAL OUT)

CLOCK R/W

stereo LED stereo clock IF OSC FM OSC

REST OF THE

REGISTERS

STATUS REGISTER

R/W

11 bits data

CONTROL

control bits

1-bit data

001aaa668

Fig 4. Digital interface block diagram.

Preliminary data sheet Rev. 02 — 26 April 2004 8 of 27

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8.1 Register description

Table 5: TEA5880TS registers description

Address Register name Access Operation Data width Clocks

0000b VADC write only VADC register 11 bits 15 0001b CTRL_C write only control register C 11 bits 15 0010b CTRL_A write only control register A 11 bits 15 0011b OSC_STEREO write only oscillator stereo

0100b CTRL_B write only control register B 11 bits 15 0101b CAP_FM write only capacitor bank FM 11 bits 15 0110b OSC_IF write only oscillator IF 11 bits 15 0111b OSC_FM write only oscillator FM 11 bits 15

- STATUS read only status register 16 bits 15

- COUNTER read only counter register 16 bits 15

Table 6: VADC - (address 0h) bit description

Bit Symbol Description

14 to 11 - address bits 10 to 6 VADC2[4:0] controls the width ﬁlter 5 - not applicable; should be written to logic 0 4 to 0 VADC1[4:0] controls the center ﬁlter

TEA5880TS

Integrated FM stereo radio IC for host processor tuning

11 bits 15

decoder clock

Table 7: CTRL_C - (address 1h) bit description

Bit Symbol Description

14 to 11 - address bits 10 and 9 - reserved for production test; should be written to logic 0 8 - reserved for swapping counters1 and 2; should be written to logic 0 7 to 4 - not applicable; should be written to logic 0 3 to 1 - reserved for time delay selection (counter 2); application should keep

bits 3 to 1 at logic 0; see

0 - reserved for enable counter 2; should be written to logic 0

[1] The application should write logic 0 to this register at start-up to ensure that the device functions correctly.

Table 8: Time delay selection

Value Decimal Stop value

000b 0 count 2 001b 1 count 8 010b 2 count 32 011b 3 count 128 100b 4 count 512 101b 5 count 2048 110b 6 count 8192 111b 7 count 32768

[1]

Table 8

Preliminary data sheet Rev. 02 — 26 April 2004 9 of 27

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