Philips TEA5767HN, X7, X5 DATA SHEET

INTEGRATED CIRCUITS

DATA SHEET

TEA5767HN

Low-power FM stereo radio for handheld applications

Preliminary specification			2002 Mar 12

Philips Semiconductors	Preliminary specification
Low-power FM stereo radio for handheld applications	TEA5767HN

FEATURES

∙High sensitivity due to integrated low-noise RF input amplifier

∙FM mixer for conversion of the US/Europe (87.5 to 108 MHz) and Japanese FM band (76 to 91MHz) to IF

∙Preset tuning to receive Japanese TV audio up to 108 MHz

∙RF Automatic Gain Control (AGC) circuit

∙LC tuner oscillator operating with low cost fixed chip inductors

∙FM IF selectivity completely done internal

∙No external discriminator needed due to fully integrated FM demodulator

∙Crystal reference frequency oscillator; the oscillator operates with a 32.768 kHz clock crystal or with a

13 MHz crystal and with an externally applied 6.5 MHz reference frequency

∙PLL synthesizer tuning system

∙7-bit IF counter output via bus

∙4-bit level information output via bus

∙Soft mute

∙Signal dependent mono/stereo blend [Stereo Noise Cancelling (SNC)]

ORDERING INFORMATION

∙Signal dependent High Cut Control (HCC)

∙Soft mute, SNC and HCC can be switched off via bus

∙Adjustment-free stereo decoder

∙I2C-bus and 3-wire bus, selectable via pin BUSMODE

∙Autonomous search tuning function

∙Standby mode

∙Two software programmable ports

∙Bus enable line to switch bus input and output lines into 3-state mode

∙Automotive temperature range (at VCCA, VCC(VCO) and VCCD = 5 V).

GENERAL DESCRIPTION

The TEA5767HN is a single-chip electronically tuned FM stereo radio for low-voltage application with fully integrated IF selectivity and demodulation. The radio is completely adjustment-free and does only require a minimum of small and low cost external components. The radio can tune the European, US and Japan FM bands.

TYPE		PACKAGE
NUMBER	NAME	DESCRIPTION	VERSION
TEA5767HN	HVQFN40	plastic, heatsink very thin quad flat package; no leads; 40 terminals;	SOT618-1
		body 6 × 6 × 0.85 mm

2002 Mar 12

2

Philips Semiconductors			Preliminary specification
Low-power FM stereo radio for handheld applications				TEA5767HN
QUICK REFERENCE DATA
VCCA = VCC(VCO) = VCCD.
SYMBOL	PARAMETER	CONDITIONS	MIN.		TYP.	MAX.	UNIT
VCCA	analog supply voltage		2.5		3.0	5.0	V
VCC(VCO)	voltage controlled oscillator		2.5		3.0	5.0	V
	supply voltage
VCCD	digital supply voltage		2.5		3.0	5.0	V
ICCA	analog supply current	operational; VCCA = 3 V	6.0		8.4	10.5	mA
		standby mode; VCCA = 3 V	−		3	6	μA
ICC(VCO)	voltage controlled oscillator	operational; VVCOTANK1 = VVCOTANK2 = 3 V	560		750	940	μA
	supply current	standby mode; VVCOTANK1 = VVCOTANK2 = 3 V	−		1	2	μA
ICCD	digital supply current	operational; VCCD = 3 V	2.1		3.0	3.9	mA
		standby mode; VCCD = 3 V
		bus enable line HIGH	30		56	80	μA
		bus enable line LOW	11		19	26	μA
fFM(ant)	FM input frequency		76		−	108	MHz
Tamb	ambient temperature	VCCA = VCC(VCO) = VCCD = 2.5 V	−10		−	+75	°C
		VCCA = VCC(VCO) = VCCD = 5 V	−40		−	+85	°C
FM overall system parameters; see Fig.7
VRF	RF sensitivity input voltage	fRF = 76 to 108 MHz; f = 22.5 kHz;	−		2	3.5	μV
		fmod = 1 kHz; (S+N)/N = 26 dB;
		de-emphasis = 75 μs; L = R;
		BAF = 300 Hz to 15 kHz
S−200	LOW side 200 kHz selectivity	f = −200 kHz; fRF = 76 to 108 MHz; note 1	32		36	−	dB
S+200	HIGH side 200 kHz	f = +200 kHz; fRF = 76 to 108 MHz; note 1	39		43	−	dB
	selectivity
VAFL; VAFR	left and right audio frequency	VRF = 1 mV; L = R; f = 22.5 kHz;	60		75	90	mV
	output voltage	fmod = 1 kHz; de-emphasis = 75 μs
(S+N)/N	maximum signal plus	VRF = 1 mV; L = R; f = 22.5 kHz;	54		60	−	dB
	noise-to-noise ratio	fmod = 1 kHz; de-emphasis = 75 μs;
		BAF = 300 Hz to 15 kHz
αcs(stereo)	stereo channel separation	VRF = 1 mV; R = L = 0 or R = 0 and L = 1	24		30	−	dB
		including 9% pilot; f = 75 kHz; fmod = 1 kHz;
		data byte 3: bit 3 = 0; data byte 4: bit 1 = 1
THD	total harmonic distortion	VRF = 1 mV; L = R; f = 75 kHz; fmod = 1 kHz;	−		0.4	1	%
		de-emphasis = 75 μs
Note

1. LOW side and HIGH side selectivity can be switched by changing the mixer from HIGH side to LOW side LO injection.

2002 Mar 12

3

n.c

MPXO

VAFR

n.c

F

DIAGRAMBLOCK

47 nF

47 nF

47

33

VAFL

nF

nF

33 nF

n.c.

31

30

29

28

27

26

25

24

23

22

21

32

R1

33

GAIN

POWER

20

n.c.

STABILISATOR

SUPPLY

4.7 Ω

22 μF

34

12Mar2002

FMpowerLow-

SemiconductorsPhilips

DEMODULATOR

VCCA

22 nF

RESONANCE

SOFT

stereo

LIMITER

AMPLIFIER

MUTE

SDS

FM antenna

LEVEL

IF COUNTER

radio

I/Q-MIXER

ADC

: 2

1st FM

1 nF

100 pF

N1

IF CENTRE

19

Iref

MPX

FREQUENCY

for

27 pF

35

DECODER

ADJUST

18

22 nF

36

L1

47 pF

37

AGC

TEA5767HN

33 kΩ

22 n

handheld

17

Ccomp(1)

38

CRYSTAL

(1)

OSCILLATOR

16

32.768 kHz

4

4.7 nF

Cpull

or

15

10 kΩ

13 MHz

programmable divider output

SOFTWARE

39

applications

TUNING SYSTEM

reference frequency divider output

MUX

PROGRAMMABLE

14

VCCA

PORT

10 kΩ

pilot

I2C-BUS

mono

13

BUSENABLE

40

VCO

12

n.c.

BUSMODE

3-WIRE BUS

11

WRITE/READ

1

2

3

4

5

6

7

8

9

10

n.c.

39 nF

10 nF

10

VCCD

CLOCK

n.c.

kΩ

12 Ω

DATA

D1

D2

22 nF

specification Preliminary

100

L3

L2

TEA5767HN

kΩ

47 Ω

22 nF

VCC(VCO)

(1) Ccomp and Cpull data depends on crystal specification.

Fig.1

Block diagram.

Philips Semiconductors						Preliminary specification
Low-power FM stereo radio for handheld applications							TEA5767HN
Table 1 Component list for Figs 1 and 7
COMPONENT			PARAMETER	VALUE	TOLERANCE	TYPE		MANUFACTURER
R1	resistor with low temperature coefficient			18 kΩ	±1%	RC12G		Philips
D1 and D2	varicap for VCO tuning			−	−	BB202		Philips
L1	RF band filter coil			120 nH	±2%	Qmin = 40
L2 and L3	VCO coil			33 nH	±2%	Qmin = 40
XTAL13	13 MHz crystal			−	−	NX4025GA
Cpull	pulling capacitor for NX4025GA			10 pF	−
XTAL32.768	32.768 kHz crystal			−	−
PINNING
SYMBOL		PIN		DESCRIPTION
n.c.		1	not connected
CPOUT		2	charge pump output of synthesizer PLL
VCOTANK1		3	voltage controlled oscillator tuned circuit output 1
VCOTANK2		4	voltage controlled oscillator tuned circuit output 2
VCC(VCO)		5	voltage controlled oscillator supply voltage
DGND		6	digital ground
VCCD		7	digital supply voltage
DATA		8	bus data line input/output
CLOCK		9	bus-clock line input
n.c.		10	not connected
WRITE/READ		11	write/read control input for the 3-wire bus
BUSMODE		12	bus mode select input
BUSENABLE		13	bus enable input
SWPORT1		14	software programmable port 1
SWPORT2		15	software programmable port 2
XTAL1		16	crystal oscillator input 1
XTAL2		17	crystal oscillator input 2
PHASEFIL		18	phase detector loop filter
PILFIL		19	pilot detector low-pass filter
n.c.		20	not connected
n.c.		21	not connected
VAFL		22	left audio frequency output voltage
VAFR		23	right audio frequency output voltage
TMUTE		24	time constant for soft mute
MPXO		25	FM demodulator MPX signal output
Vref		26	reference voltage
TIFC		27	time constant for IF centre adjust
LIMDEC1		28	decoupling IF limiter 1
LIMDEC2		29	decoupling IF limiter 2

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Philips Semiconductors				Preliminary specification
Low-power FM stereo radio for handheld applications				TEA5767HN
SYMBOL		PIN	DESCRIPTION
n.c.		30	not connected
n.c.		31	not connected
Igain		32	gain control current for IF filter
AGND		33	analog ground
VCCA		34	analog supply voltage
RFI1		35	RF input 1
RFGND		36	RF ground
RFI2		37	RF input 2
TAGC		38	time constant RF AGC
LOOPSW		39	switch output of synthesizer PLL loop filter
n.c.		40	not connected

WRITE/READ	BUSMODE	BUSENABLE	SWPORT1	SWPORT2	XTAL1	XTAL2	PHASEFIL	PILFIL	n.c.
11	12	13	14	15	16	17	18	19	20

n.c. 10

CLOCK 9

DATA 8

VCCD 7

DGND 6

TEA5767HN

VCC(VCO) 5

VCOTANK2 4

VCOTANK1 3

CPOUT 2

n.c. 1

40	39	38	37	36	35	34	33	32	31
n.c.	LOOPSW	TAGC	RFI2	RFGND	RFI1	CCA	AGND	gain	n.c.
						V		I

21n.c.

22VAFL

23VAFR

24TMUTE

25MPXO

26Vref

27TIFC

28LIMDEC1

29LIMDEC2

30n.c.

MXXxxx

Fig.2 Pin configuration (bottom view).

2002 Mar 12

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Philips Semiconductors	Preliminary specification
Low-power FM stereo radio for handheld applications	TEA5767HN

FUNCTIONAL DESCRIPTION

Low-noise RF amplifier

The LNA input impedance together with the LC RF input circuit defines an FM band filter. The gain of the LNA is controlled by the RF AGC circuit.

FM mixer

FM quadrature mixer converts FM RF (76 to 108 MHz) to an IF of 225 kHz.

VCO

The varactor tuned LC VCO provides the Local Oscillator (LO) signal for the FM quadrature mixer. The VCO frequency range is 150 to 217 MHz.

Crystal oscillator

The crystal oscillator can operate with a 32.768 kHz clock crystal or a 13 MHz crystal. The temperature drift of standard 32.768 kHz clock crystals limits the operational temperature range from −10 to +60 °C.

Via pin XTAL2 the PLL synthesizer can be clocked externally with a 32.768 kHz, a 6.5 MHz or a 13 MHz signal.

The crystal oscillator generates the reference frequency for

∙The reference frequency divider for synthesizer PLL

∙The timing for the IF counter

∙The free-running frequency adjust of the stereo decoder VCO

∙The centre frequency adjust of the IF filters.

PLL tuning system

The PLL synthesizer tuning system is suitable to operate with a 32.768 kHz or a 13 MHz reference frequency generated by the crystal oscillator or fed into the IC. The synthesizer can also be clocked via pin XTAL2 with

6.5 MHz. The PLL tuning system can perform an autonomous search tuning function.

RF AGC

The RF AGC prevents overloading and limits the amount of intermodulation products created by strong adjacent channels.

IF filter

Fully integrated IF filter.

FM demodulator

The FM quadrature demodulator has an integrated resonator to perform the phase shift of the IF signal.

Level voltage generator and analog-to-digital converter

The level voltage is analog-to-digital converted with 4 bits and output via the bus.

IF counter

The IF counter outputs a 7-bit count result via the bus.

Soft mute

The low-pass filtered level voltage drives the soft mute attenuator at low RF input levels. The soft mute function can also be switched off via bus.

MPX decoder

The PLL stereo decoder is adjustment-free. The stereo decoder can be switched to mono via bus.

Signal dependent mono/stereo blend

With decreasing RF input level the MPX decoder blends from stereo to mono to limit the output noise. The continuous mono-to-stereo blend can also be programmed by bus to an RF level depending switched mono-to-stereo transition. Stereo Noise Cancelling (SNC) can be switched off via bus.

Signal dependent AF response

With decreasing RF input level the audio bandwidth is reduced. The function can also be switched off via bus.

Software programmable ports

Two software programmable ports (open-collector) can be addressed via bus.

With write data byte 4 bit 0 the port 1 (pin SWPORT1) function can be changed (see Table 14). Pin SWPORT1 is then output for the ready flag of read byte 1.

I2C-bus and 3-wire bus

The 3-wire bus operates with a maximum clock frequency of 1 MHz.

The I2C-bus operates with a maximum clock frequency of 400 kHz.

2002 Mar 12

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Philips Semiconductors	Preliminary specification
Low-power FM stereo radio for handheld applications	TEA5767HN

With BUSMODE pin LOW the I2C-bus mode is selected, with BUSMODE pin HIGH the 3-wire bus mode is selected.

I2C-BUS, 3-WIRE BUS AND BUS CONTROLLED FUNCTIONS

I2C-bus specification

Information about the I2C-bus can be found in the brochure

“The I2C-bus and how to use it” (order number 9398 393 40011).

The standard I2C-bus specification is expanded by the following definitions.

IC address C0: 1100000.

Structure of the I2C-bus logic: slave transceiver.

Subaddresses are not used.

The maximum LOW-level input and the minimum HIGH-level input are specified to 0.2VCCD respectively 0.45VCCD.

The pin BUSMODE must be connected to ground to operate the IC with the I2C-bus.

Hint: The bus operates at a maximum clock frequency of 400 kHz. It is not allowed to connect the IC to a bus operating at a higher clock rate.

DATA TRANSFER FOR THE TEA5767HN

Data sequence: address, byte 1, byte 2, byte 3, byte 4, and byte 5. The data transfer has to be in this order. The LSB = 0 of the address indicates a WRITE operation to the TEA5767HN.

I2C-bus protocol

Bit 7 of each byte is considered the MSB and has to be transferred as the first bit of the byte.

The data becomes valid bitwise at the appropriate falling edge of the clock. A STOP condition after any byte can shorten transmission times.

When writing to the transceiver by using the STOP condition before completion of the whole transfer:

∙The remaining bytes will contain the old information

∙If the transfer of a byte is not completed, the new bits will be used, but a new tuning cycle will not be started.

With the standby bit the IC can be switched in a low current standby mode. The bus is then still active. The standby current can be reduced by deactivation of the bus interface (pin BUSENABLE LOW). Is the bus interface deactivated (pin BUSENABLE LOW) without programmed standby mode, the IC keeps its normal operation, but is isolated from the bus lines.

The software programmable output (SWPORT1) can be programmed to operate as tuning indicator output. As long as the IC has not completed a tuning action, the SWPORT1 pin is LOW. The pin becomes HIGH, when a preset or search tuning was completed or when a band limit was reached.

With the MSB in byte 5 set to logic 1 the reference frequency divider of the synthesizer PLL is changed. The tuning system can then be clocked via pin XTAL2 with 6.5 MHz.

POWER-ON RESET

The mute is set, all other bits are set to LOW. To initialize the IC all bytes have to be transferred.

Table 2	Write mode
S(1)		address (write)	A(2)	data byte(s)	A(2)	P(3)
Table 3	Read mode
S(1)		address (read)	A(2)		data byte 1

Notes to Tables 2 and 3

1.S = START condition.

2.A = acknowledge.

3.P = STOP condition.

2002 Mar 12

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Philips Semiconductors						Preliminary specification
Low-power FM stereo radio for handheld applications							TEA5767HN
Table 4 IC address byte
			IC ADDRESS					MODE
1	1	0	0	0	0	0				(1)
								R/W

Note

1.Read or write mode:

a)0 = write operation to TEA5767HN

b)1 = read operation from TEA5767HN.

3-wire bus specification

3-wire bus with write/read, clock and data line.

The bus operates at a maximum clock frequency of 1 MHz.

Hint: With the standby bit the IC can be switched in a low current standby mode. The bus is then still active. The standby current can be reduced by deactivation of the bus interface (pin BUSENABLE LOW). Is the bus interface deactivated (pin BUSENABLE LOW) without programmed standby mode, the IC keeps its normal operation, but is isolated from the clock and data line.

DATA TRANSFER FOR THE TEA5767HN

Data sequence: byte 1, byte 2, byte 3, byte 4, and byte 5. The data transfer has to be in this order.

A positive edge at pin WRITE/READ enables the data transfer into the IC. Data have to be stable at the positive edge of the clock. Data may change while clock is LOW and is written with the positive edge of the clock into the IC. Data transfer can be stopped after the transmission of a new tuning information with the first two bytes or after each following byte.

A negative edge at pin WRITE/READ enables the data transfer out of the IC. The WRITE/READ pin changes while the clock is LOW. With the negative edge of

pin WRITE/READ the MSB of the first byte occurs at pin DATA. The bits are shifted with the negative clock

edge to pin DATA and can be read with the positive edge.

To do two consecutive read or write actions,

pin WRITE/READ has to be toggled for at least one clock period. Was a search tuning request sent, the IC autonomously starts searching the FM band. Search direction and search stop level can be chosen. Was a station with a field-strength equal to or higher than this stop level found, the tuning system stops and the ready flag bit is set to HIGH. Was during search a band limit reached, the tuning system stops at the band limit and the band limit flag bit is set to HIGH. Also the ready flag is set to HIGH in this case.

The software programmable output (SWPORT1) can be programmed to operate as a tuning indicator output. As long as the IC has not completed a tuning action

pin SWPORT1 is LOW. The pin becomes HIGH, when a preset or search tuning was completed or when a band limit was reached. With the MSB in byte 5 set to logic 1 the reference frequency divider of the synthesizer PLL is changed. The tuning system can then be clocked via

pin XTAL2 with 6.5 MHz.

POWER-ON RESET

The mute is set, all other bits are random. To initialize the IC all bytes have to be transferred.

2002 Mar 12

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Philips Semiconductors	Preliminary specification
Low-power FM stereo radio for handheld applications	TEA5767HN

Writing data

tW(write)

WRITE/READ

50%

	tsu(clk)
CLOCK	50%	50%	th(write)
		tsu(write)
DATA		50%	valid
			data

Fig.3 3-wire bus write data.

Table 5

Write mode

DATA BYTE 1

DATA BYTE 2

DATA BYTE 3

DATA BYTE 4

DATA BYTE 5

Table 6 Format of 1st data byte

BIT 7 (MSB)

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0 (LSB)

MUTE

SM

PLL13

PLL12

PLL11

PLL10

PLL9

PLL8

Table 7

Description of 1st data byte bits

BIT

SYMBOL

DESCRIPTION

7

MUTE

If MUTE = 1, then L and R audio muted. If MUTE = 0, then audio not muted.

6

SM

Search Mode. If SM = 1, then search mode. If SM = 0, then no search mode.

5 to 0

PLL[13:8]

Setting of synthesizer programmable counter for search or preset.

Table 8

Format of 2nd data byte

BIT 7 (MSB)

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0 (LSB)

PLL7

PLL6

PLL5

PLL4

PLL3

PLL2

PLL1

PLL0

Table 9

Description of 2nd data byte bits

BIT

SYMBOL

DESCRIPTION

7 to 0

PLL[7:0]

Setting of synthesizer programmable counter for search or preset.

Table 10 Format of 3rd data byte

BIT 7 (MSB)

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0 (LSB)

SUD

SSL1

SSL0

HLSI

MS

ML

MR

SWP1

2002 Mar 12

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Philips Semiconductors							Preliminary specification
Low-power FM stereo radio for handheld applications							TEA5767HN
Table 11 Description of 3rd data byte bits
BIT	SYMBOL				DESCRIPTION
7	SUD	Search up/down. If SUD = 1, then search up. If SUD = 0, then search down.
6 and 5	SSL[1:0]	Search Stop Level. See Table 12.
4	HLSI	HIGH/LOW Side Injection. If HLSI = 1, then HIGH side LO injection. If HLSI = 0, then
		LOW side LO injection.
3	MS	Mono/Stereo. If MS = 1, then forced mono. If MS = 0, then stereo ON.
2	ML	Mute Left. If ML = 1, then left audio channel muted and forced mono. If ML = 0, then not
		muted.
1	MR	Mute Right. If MR = 1, then right audio channel muted and forced mono. If MR = 0, then
		not muted.
0	SWP1	Software programmable port 1. If SWP1 = 1, then port 1 is HIGH. If SWP1 = 0, then
		port 1 is LOW.
Table 12 Search stop level setting
SSL1	SSL0				SEARCH STOP LEVEL
0	0	not allowed in search mode
0	1	low; level ADC output = 5
1	0	mid; level ADC output = 7
1	1	high; level ADC output = 10
Table 13 Format of 4th data byte
BIT 7 (MSB)	BIT 6	BIT 5		BIT 4	BIT 3	BIT 2	BIT 1	BIT 0 (LSB)
SWP2	STBY	BL		XTAL	SMUTE	HCC	SNC	SI
Table 14 Description of 4th data byte bits
BIT	SYMBOL				DESCRIPTION
7	SWP2	Software programmable port 2. If SWP2 = 1, then port 2 is HIGH. If SWP2 = 0, then
		port 2 is LOW.
6	STBY	Standby. If STBY = 1, then standby. If STBY = 0, then no standby.
5	BL	Band Limits. If BL = 1, then Japan FM band. If BL = 0, then US/Europe FM band.
4	XTAL	If XTAL = 1, then fxtal = 32.768 kHz. If XTAL = 0, then fxtal = 13 MHz.
3	SMUTE	Soft Mute. If SMUTE = 1, then soft mute is ON. If SMUTE = 0, then soft mute is OFF.
2	HCC	High Cut Control. If HCC = 1, then high cut control is ON. If HCC = 0, then high cut
		control is OFF.
1	SNC	Stereo noise cancelling. If SNC = 1, then stereo noise cancelling is ON. If SNC = 0,
		then stereo noise cancelling is OFF.
0	SI	Search indicator. If SI = 1, then pin SWPORT1 is output for the ‘ready flag’. If SI = 0,
		then pin SWPORT1 is software programmable port 1.
Table 15 Format of 5th data byte
BIT 7 (MSB)	BIT 6	BIT 5		BIT 4	BIT 3	BIT 2	BIT 1	BIT 0 (LSB)
PLLREF	DTC	−		−	−	−	−	−

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