Philips TDA9964 User Manual
1. Description
2. Features
TDA9964
12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD
cameras
Rev. 03 — 16 January 2001 Objective specification
The TDA9964 is a 12-bit analog-to-digital interface for CCD cameras. The device
includes a correlated double sampling circuit, PGA, clamp loops and a low-power
12-bit ADC together with its reference voltage regulator.
The PGA gain and the ADC input clamp level are controlled via the serial interface.
An additional DAC is provided for additional system controls; its output voltage range
is 1.0 V p-p, which is available at pin OFDOUT.
c
c
3. Applications
■ Correlated Double Sampling (CDS), Programmable Gain Amplifier (PGA), 12-bit
Analog-to-Digital Converter (ADC) and reference regulator included
■ Fully programmable via a 3-wire serial interface
■ Sampling frequency up to 30 MHz
■ PGA gain range of 24 dB (in steps of 0.1 dB)
■ Low power consumption of only 175 mW at 2.7 V
■ Power consumption in standby mode of 4.5 mW (typ.)
■ 3.0 V operation and 2.5 to 3.6 V operation for the digital outputs
■ All digital inputs accept 5 V signals
■ Active control pulses polarity selectable via serial interface
■ 8-bit DAC included for analog settings
■ TTL compatible inputs, CMOS compatible outputs.
■ Low-power, low-voltage CCD camera systems.
Philips Semiconductors
TDA9964
12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras
4. Quick reference data
Table 1: Quick reference data
Symbol Parameter Conditions Min Typ Max Unit
V
CCA
V
CCD
V
CCO
I
CCA
I
CCD
I
CCO
ADC
res
V
i(CDS)(p-p)
f
pix(max)
f
pix(min)
DR
PGA
N
tot(rms)
E
in(rms)
P
tot
analog supply voltage 2.7 3.0 3.6 V
digital supply voltage 2.7 3.0 3.6 V
digital outputs supply voltage 2.5 2.7 3.6 V
analog supply current all clamps active − 60 − mA
digital supply current − 3 − mA
digital outputs supply current f
= 30 MHz; CL= 10 pF; input ramp
pix
− 1 − mA
response time is 800 µs
ADC resolution − 12 − bits
maximum CDS input voltage
(peak-to-peak value)
VCC= 2.85 V 650 −−mV
≥ 3.0 V 800 −−mV
V
CC
maximum pixel frequency 30 −−MHz
minimum pixel frequency tbf −−MHz
PGA dynamic range − 24 − dB
total noise from CDS input to
PGA gain = 0 dB; see Figure 8 − 1.5 − LSB
ADC output
equivalent input noise (RMS
gain=24dB − 70 −µV
value)
total power consumption V
CCA=VCCD=VCCO
V
CCA=VCCD=VCCO
=3V − 195 − mW
= 2.7 V − 175 − mW
5. Ordering information
Table 2: Ordering information
Type number Package
Name Description Version
TDA9964HL LQFP48 plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm SOT313-2
9397 750 07918
Objective specification Rev. 03 — 16 January 2001 2 of 23
© Philips Electronics N.V. 2001. All rights reserved.
9397 750 07918
Objective specification Rev. 03 — 16 January 2001 3 of 23
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6. Block diagram
Philips Semiconductors
CLK
43
DATA
FLIPFLOP
20
BLK
BLANKING
42
STDBY
SHD
AGND4
V
CCA1
1
46
SHIFT
V
ref
13
AGND5
SHP
45
CDS CLOCK GENERATOR
CPCDS1
CPCDS2
V
CCA2
AGND2
V
CCA3
AGND3
OFDOUT
© Philips Electronics N.V. 2001. All rights reserved.
8
9
7
3
CORRELATED
4
IN
14
5
11
DOUBLE
SAMPLING
OFD DAC
12 6
TEST
CLAMP
AGND1
2
CLAMP
V
CCA4
41
AGND6
40
PGA
8-BIT
REGISTER
8-BIT
REGISTER
CLPDM
CLPOB
44
15
OPGA OPGAC
48
TDA9964
16
BLACK
LEVEL
SHIFT
SEN
19
7-BIT
REGISTER
SERIAL
INTERFACE
18
SCLK
SDATA
12-bit ADC
17
VSYNC
47
REGULATOR
OE
39
OUTPUT
BUFFER
22
21
37
38
36
35
34
33
32
31
30
29
28
27
26
25
24
23
10
FCE515
DGND1
V
CCD1
OGND2
V
CCO2
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
OGND1
V
CCO1
DCLPC
12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras
Fig 1. Block diagram.
TDA9964
Philips Semiconductors
7. Pinning information
7.1 Pinning
TDA9964
12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras
Fig 2. Pin configuration.
V
CCA1
AGND1
AGND2
AGND3
AGND4
V
CCA2
CPCDS1
CPCDS2
DCLPC
OFDOUT
TEST
CLPDM
48
1
2
3
4
IN
5
6
7
8
9
10
11
12
13
AGND5
SHD
CLK
474645
141516
CCA3
OPGA
V
SHP
CLPOB
44
TDA9964HL
17
SDATA
OPGAC
BLK
43
181920
SCLK
STDBY
42
SEN
VSYNC
CCA4
V
414039
V
CCO2
AGND6
V
OE
38
21
22
23
CCD1VCCO1
DGND1
OGND2
37
24
OGND1
36
35
34
33
32
31
30
29
28
27
26
25
FCE516
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
7.2 Pin description
Table 3: Pin description
Symbol Pin Description
V
CCA1
AGND1 2 analog ground 1
AGND2 3 analog ground 2
IN 4 input signal from CCD
AGND3 5 analog ground 3
AGND4 6 analog ground 4
V
CCA2
CPCDS1 8 clamp storage capacitor pin 1
CPCDS2 9 clamp storage capacitor pin 2
DCLPC 10 regulator decoupling pin
OFDOUT 11 analog output of the additional 8-bit control DAC
TEST 12 test mode input pin (should be connected to AGND5)
AGND5 13 analog ground 5
V
CCA3
9397 750 07918
Objective specification Rev. 03 — 16 January 2001 4 of 23
1 analog supply voltage 1
7 analog supply voltage 2
14 analog supply 3
© Philips Electronics N.V. 2001. All rights reserved.
Philips Semiconductors
TDA9964
12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras
Table 3: Pin description
…continued
Symbol Pin Description
OPGA 15 PGA output (test pin)
OPGAC 16 PGA complementary output (test pin)
SDATA 17 serial data input for serial interface control
SCLK 18 serial clock input for serial interface
SEN 19 strobe pin for serial interface
VSYNC 20 vertical sync pulse input
V
CCD1
21 digital supply voltage 1
DGND1 22 digital ground 1
V
CCO1
23 output supply voltage 1
OGND1 24 digital output ground 1
D0 25 ADC digital output 0 (LSB)
D1 26 ADC digital output 1
D2 27 ADC digital output 2
D3 28 ADC digital output 3
D4 29 ADC digital output 4
D5 30 ADC digital output 5
D6 31 ADC digital output 6
D7 32 ADC digital output 7
D8 33 ADC digital output 8
D9 34 ADC digital output 9
D10 35 ADC digital output 10
D11 36 ADC digital output 11 (MSB)
OGND2 37 output digital ground 2
V
CCO2
38 output supply voltage 2
OE 39 output enable control input (LOW: outputs active; HIGH:
outputs are high impedance)
AGND6 40 analog ground 6
V
CCA4
41 analog supply voltage 4
STDBY 42 standby mode control input (LOW: TDA9964 active; HIGH:
TDA9964 standby)
BLK 43 blanking control input
CLPOB 44 clamp pulse input at optical black
SHP 45 preset sample-and-hold pulse input
SHD 46 data sample-and-hold pulse input
CLK 47 data clock input
CLPDM 48 clamp pulse input at dummy pixel
9397 750 07918
Objective specification Rev. 03 — 16 January 2001 5 of 23
© Philips Electronics N.V. 2001. All rights reserved.
Philips Semiconductors
TDA9964
12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras
8. Limiting values
Table 4: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
V
V
∆V
V
I
o
T
T
T
CCA
CCD
CCO
CC
i
stg
amb
j
analog supply voltage
digital supply voltage
digital outputs supply voltage
supply voltage difference:
between V
between V
between V
CCA
CCA
CCD
and V
and V
and V
CCD
CCO
CCO
input voltage referenced to AGND −0.3 +7.0 V
data output current −±10 mA
storage temperature −55 +150 °C
ambient temperature −20 +75 °C
junction temperature − 150 °C
[1]
−0.3 +7.0 V
[1]
−0.3 +7.0 V
[1]
−0.3 +7.0 V
−0.5 +0.5 V
−0.5 +1.2 V
−0.5 +1.2 V
[1] The supply voltages V
∆VCC remains as indicated.
CCA
, V
CCD
and V
may have any value between −0.3 and +7.0 V provided that the supply voltage difference
CCO
9. Thermal characteristics
Table 5: Thermal characteristics
Symbol Parameter Conditions Value Unit
R
th(j-a)
thermal resistance from junction to ambient in free air 76 K/W
10. Characteristics
Table 6: Characteristics
V
CCA=VCCD
Symbol Parameter Conditions Min Typ Max Unit
Supplies
V
CCA
V
CCD
V
CCO
I
CCA
I
CCD
I
CCO
= 3.0 V; V
CCO
= 2.7 V; f
= 30 MHz; T
pix
=25°C; unless otherwise specified.
amb
analog supply voltage 2.7 3.0 3.6 V
digital supply voltage 2.7 3.0 3.6 V
digital outputs supply voltage 2.5 2.7 3.6 V
analog supply current all clamps active − 60 − mA
digital supply current − 3 − mA
digital outputs supply current CL= 10 pF on all data
− 1 − mA
outputs; input ramp
response time is 800 µs
9397 750 07918
Objective specification Rev. 03 — 16 January 2001 6 of 23
© Philips Electronics N.V. 2001. All rights reserved.
Philips Semiconductors
TDA9964
12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras
Table 6: Characteristics
V
CCA=VCCD
= 3.0 V; V
…continued
= 2.7 V; f
CCO
= 30 MHz; T
pix
=25°C; unless otherwise specified.
amb
Symbol Parameter Conditions Min Typ Max Unit
Digital inputs
Pins: SHP, SHD and CLK (referenced to DGND)
V
IL
V
IH
I
i
Z
i
C
i
Pins: CLPDM, CLPOB, SEN, SCLK, SDATA, STBY,
V
IL
V
IH
I
i
LOW-level input voltage 0 − 0.6 V
HIGH-level input voltage 2.2 − 5.5 V
input current 0 ≤ Vi≤ 5.5 V −3 − +3 µA
input impedance f
input capacitance f
= 30 MHz − 50 − kΩ
CLK
= 30 MHz −− 2pF
CLK
OE, BLK, VSYNC
LOW-level input voltage 0 − 0.6 V
HIGH-level input voltage 2.2 − 5.5 V
input current 0 ≤ Vi≤ 5.5 V −2 − +2 µA
Clamps
Global characteristics of the clamp loops
t
W(clamp)
clamp active pulse width in
number of pixels
PGA code = 255 for
maximum 4 LSB error
12 −−pixels
Input clamp (driven by CLPDM)
g
m(CDS)
CDS input clamp
− 20 − mS
transconductance
Correlated Double Sampling (CDS)
V
i(CDS)(p-p)
V
reset(max)
maximum peak-to-peak CDS
input amplitude (video signal)
maximum CDS input reset
VCC= 2.85 V 650 −−mV
≥ 3.0 V 800 −−mV
V
CC
500 −−mV
pulse amplitude
I
i(IN)
C
i
t
CDS(min)
input current into pin IN at floating gate level tbf − tbf µA
input capacitance − 2 − pF
CDS control pulsesminimum
active time
V
i(CDS)(p-p)
= 800 mV
black to white transition in
8 −−ns
1 pixel with 98.5%
recovery
V
i
t
h(IN;SHP)
CDS input hold time (pin IN)
see Figure 3 and 4 4 −−ns
compared to control pulse
SHP
t
h(IN;SHD)
CDS input hold time (pin IN)
see Figure 3 and 4 4 −−ns
compared to control pulse
SHD
Amplifier
DR
∆G
PGA
PGA
PGA dynamic range − 24 − dB
PGA gain step 0.08 0.10 0.12 dB
Analog-to-Digital Converter (ADC)
DNL differential non linearity f
= 30 MHz; ramp input −±0.5 ±0.9 LSB
pix
Total chain characteristics (CDS + PGA + ADC)
f
pix(max)
maximum pixel frequency 30 −−MHz
9397 750 07918
Objective specification Rev. 03 — 16 January 2001 7 of 23
© Philips Electronics N.V. 2001. All rights reserved.
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