Philips TDA9802T, TDA9802 Datasheet

INTEGRATED CIRCUITS

DATA SHEET

TDA9802

Multistandard VIF-PLL demodulator and FM-PLL detector

Preliminary specification			November 1992
File under Integrated Circuits, IC02

Philips Semiconductors	Preliminary specification

Multistandard VIF-PLL demodulator

TDA9802

and FM-PLL detector

FEATURES

∙Suitable for negative and positive vision modulation

∙Gain controlled 3-stage IF amplifier; suitable for VIF frequencies up to 60 MHz

∙True synchronous demodulation with active carrier regeneration (ultra-linear demodulation, good intermodulation figures, reduced harmonics and excellent pulse response)

∙Peak sync AGC for negative modulation, e.g. B/G standard

∙Peak white AGC for positive modulation, e.g. L standard

∙Video amplifier to match sound trap and sound filter

QUICK REFERENCE DATA

∙AGC output voltage for tuner; adjustable take-over point (TOP)

∙AFC detector without extra reference circuit

∙Alignment-free FM-PLL detector with high linearity

∙Stabilizer circuit for ripple rejection and to achieve constant output signals

∙5 to 8 V positive supply voltage range, low power consumption (300 mW at +5 V supply voltage)

GENERAL DESCRIPTION

The TDA9802 is a monolithic integrated circuit for vision and sound IF signal processing in multistandard TV and VTR sets.

SYMBOL	PARAMETER	MIN.	TYP.	MAX.	UNIT
VP	positive supply voltage (pin 20)	4.5	5	8.8	V
IP	supply current	51	60	69	mA
Vi IF	vision IF input signal sensitivity (RMS value, pins 1 and 2)	−	50	90	μV
	maximum vision IF input signal (RMS value, pins 1 and 2)	70	150	−	mV
Gv	IF gain control range	64	70	73	dB
Vo CVBS	CVBS output signal on pin 7 (peak-to-peak value)	1.7	2.0	2.3	V
B	−3 dB video bandwidth on pin 7	6	8	−	MHz
S/N (W)	signal-to-noise ratio weighted; for video	56	59	−	dB
α1.1	intermodulation attenuation	56	62	−	dB
α3.3		56	62	−	dB
αH	suppression of harmonics in video signal	35	40	−	dB
Vo AF	maximum AF output signal for THD < 1.5% (RMS value,	0.8	−	−	V
	pin 9)
Tamb	operating ambient temperature range	0	−	+70	°C

ORDERING INFORMATION

EXTENDED			PACKAGE
TYPE NUMBER	PINS	PIN POSITION	MATERIAL	CODE
TDA9802	20	DIL	plastic	SOT146(1)
TDA9802T	20	mini-pack	plastic	SOT163A(2)

Note

1.SOT146-1; 1996 November 19.

2.SOT163-1; 1996 November 19.

November 1992

2

Philips Semiconductors	Preliminary specification

Multistandard VIF-PLL demodulator and

TDA9802

FM-PLL detector

Fig.1 Block diagram.

November 1992

3

Philips Semiconductors	Preliminary specification

Multistandard VIF-PLL demodulator and

TDA9802

FM-PLL detector

PINNING
SYMBOL	PIN	DESCRIPTION
Vi IF	1	vision IF differential input signal
	2
TADJ	3	tuner AGC take-over adjust (TOP)
φADJ	4	phase detector adjust
CBL	5	black level capacitor, mute switch input
TPLL	6	PLL time constant of phase detector
Vo CVBS	7	CVBS (positive) output signal
STD	8	standard switch (negative = HIGH,
		positive = LOW)
Vo AF	9	audio frequency output signal
CAF	10	decoupling capacitor of audio frequency amplifier
Vi IC	11	sound intercarrier input signal
TAGC	12	tuner AGC output
Vo VID	13	video and sound intercarrier output signal
Vi VID	14	video input signal to buffer amplifier
AFC	15	automatic frequency control output
VCO1	16	VCO reference circuit for 2 fPC
VCO2	17
GND	18	ground (0 V)
CAGC	19	AGC capacitor		Fig.2 Pin configuration.
VP	20	positive supply voltage

November 1992

4

Philips Semiconductors	Preliminary specification

Multistandard VIF-PLL demodulator and

TDA9802

FM-PLL detector

FUNCTIONAL DESCRIPTION

Vision IF input

The vision IF amplifier consists of three AC-coupled differential amplifier stages; each stage comprises a controlled feedback network by means of emitter degeneration.

IF and tuner AGC

The automatic control voltage to maintain the video output signal at a constant level is generated according to the transmission standard. For negative modulation the peak-sync level is detected, for positive modulation the peak white level is detected. The AGC detector charges and discharges the capacitor on pin 19 to set the IF gain and the tuner gain. The standard is switched by the voltage on pin 8. To reduce the response time for positive modulation (which needs a very long time constant) a black level detector (CBL) increases the AGC capacitor discharge current for low-level video signals.

The AGC capacitor voltage is transferred to an internal IF control signal, and is fed to the tuner AGC to generate the tuner AGC output current on pin 12 (open-collector output). The tuner AGC voltage take over point is adjusted on pin 3. This allows the tuner and the IF SAW filter to be matched to achieve the optimum IF input level.

Frequency detector, phase detector and video demodulator

The IF amplifier output signal is fed to a frequency detector and to a phase detector. The frequency detector is operational before lock-in. A DC current is generated which is proportional to the frequency difference between the input frequency and the VCO frequency. After lock-in, the frequency detector and the phase detector generate a DC current proportional to the phase difference between VCO and input signals. The control signal for the VCO is provided by the phase detector. The video demodulator is a linear multiplier, designed for low distortion and wide bandwidth. The vision IF input signal is multiplied by the in-phase component of the VCO output. The demodulated output signal is fed via an integrated low-pass filter

(fg = 12 MHz) to the video amplifier for suppression of the carrier harmonics. The polarity of the video signal is switched in the demodulator stage according to the TV standard.

VCO and travelling wave divider

The VCO operates with a symmetrically-connected reference LC-circuit, operating at double vision carrier frequency. Frequency control is performed by an internal varicap diode. The voltage to set the VCO frequency to the actual frequency of double vision carrier frequency, is also amplified and converted for the AFC output current.

The VCO signal is divided-by-two in a travelling wave divider, which generates two differential output signals with 90 degree phase difference independent of frequency.

Video amplifier, buffer and noise clipping

The video amplifier is a wide bandwidth operational amplifier with internal feedback. Dependent on transmission standard, a level shifter provides the same sync level for positive as for negative modulation. A nominal positive modulated video signal of 1 V (p-p) is present on the composite video output (pin 13).

The input impedance of the 7 dB wideband buffer amplifier (with internal feedback) is suitable for ceramic sound trap filters.

The CVBS output (pin 7) provides a positive video signal of 2 V (p-p). Noise clipping is provided internally.

Sound demodulation

The FM sound intercarrier signal is fed to pin 11 and through a limiter amplifier before it is demodulated. This achieves high sensitivity and high AM suppression. The limiter amplifier consists of seven internal AC-coupled stages, minimizing the DC offset.

The FM-PLL demodulator consists of an RC-oscillator, loop filter and phase detector. The oscillator frequency is locked on the FM intercarrier signal from the limiter amplifier.

As a result of this locking, the RC-oscillator is frequency-modulated. The modulating signal voltage (AF signal) is used to control the oscillator frequency. By this, the FM-PLL operates as an FM demodulator.

The audio frequency amplifier with internal feedback is designed for high gain and high common mode rejection. The low-level AF signal output from the FM-PLL demodulator is amplified and buffered in a low-ohmic audio signal output stage (pin 9). An external decoupling capacitor on pin 10 removes the DC voltage from the audio amplifier input.

November 1992

5

Philips Semiconductors	Preliminary specification

Multistandard VIF-PLL demodulator and

TDA9802

FM-PLL detector

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC134)

SYMBOL	PARAMETER	MIN.	MAX.	UNIT
VP	supply voltage (pin 20) for a maximum chip temperature (note 1)
	SOT146 at + 120 °C	0	8.8	V
	SO163A at + 100 °C	0	5.5	V
VI	voltage on pins 1, 2, 7, 8, 11, 13, 14, 15 and 19	0	VP	V
ts max	short-circuit time	−	10	s
V12	tuner AGC output voltage	−	13.2	V
Tstg	storage temperature range	−25	+150	°C
VESD	electrostatic handling for all pins (note 2)	−	±300	V

Notes to the Limiting Values

1.Supply current IP = 69 mA at Tamb = +70 °C.

2.Equivalent to discharging a 200 pF capacitor through a 0 Ω series resistor (negative and positive voltage).

THERMAL RESISTANCE

SYMBOL	PARAMETER	THERMAL RESISTANCE
Rth j-a	from junction to ambient in free air
	SOT146	73 K/W
	SOT163A	85 K/W

November 1992

6

Philips Semiconductors	Preliminary specification

Multistandard VIF-PLL demodulator and

TDA9802

FM-PLL detector

CHARACTERISTICS

VP = 5 V; Tamb = +25 °C; fPC = 38.9 MHz; fSC = 33.4 MHz with VPC/VSC = 13 dB (B/G); ViIF = 10 mV RMS value (sync level at B/G; peak-white level at L); video modulation DSB; residual carrier: B/G = 10%, L = 3%; video signal in accordance with CCIR line 17; measurements taken in Fig.3 unless otherwise specified

SYMBOL	PARAMETER	CONDITIONS	MIN.	TYP.	MAX.	UNIT
VP	supply voltage range (pin 20)	see note 1	4.5	5	8.8	V
IP	supply current		51	60	69	mA
Standard switch input (pin 8)
VIH	input voltage for negative modulation	see note 2	1.5	−	VP	V
VIL	input voltage for positive modulation		0	−	0.8	V
IIL	LOW level input current	V8 = 0 V	−	−300	−360	μA
Vision IF input (pins 1 and 2)		B/G standard
Vi	input signal sensitivity (RMS value)	−1 dB video at output	−	50	90	μV
	maximum input signal (RMS value)	+1 dB video at output	70	150	−	mV
Vi	IF amplitude difference between picture and	within AGC range	−	0.7	1	dB
	sound carrier
GIF	IF gain control range	see Fig.4	64	70	73	dB
B	−3 dB IF bandwidth	upper cut-off frequency	70	100	−	MHz
Ri	input resistance		1.7	2.2	2.7	kΩ
Ci	input capacitance		1.2	1.7	2.5	pF
V1, 2	DC input voltage		3.0	3.4	3.8	V
True synchronous video demodulator		see note 3
fVCO	maximum oscillator frequency for carrier	f = 2fPC	125	130	−	MHz
	regeneration
fVCO	oscillator drift (free running) as a function of	see note 4;	−	−	±1300	10−6
	temperature	T = 0 to+70 °C
Vo ref	oscillator swing at pins 16 and 17		tbn	120	tbn	mV
	(RMS value)
fPC	vision carrier capture range (negative)		1.5	2	−	MHz
	vision carrier capture range (positive)		1.5	2	−	MHz
tacqu	acquisition time	see note 5; BL = 60 kHz	−	−	30	ms
Vi IF	IF input signal sensitivity (RMS value, pins 1
	and 2)
	for PLL still locked	see note 6;	−	70	100	μV
		maximum IF gain
	for C/N = 10 dB	see note 7	−	100	140	μV
Iloop	FPLL loop offset current at pin 6	see note 8	−	−	±4.5	μA

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