Philips TDA9725-V2 Datasheet

DATA SH EET

Product specification
Supersedes data of 1995 Dec 06
File under Integrated Circuits, IC02

1996 Oct 14

INTEGRATED CIRCUITS

TDA9725

Y/C automatic adjustment
processor (VHS standard)

1996 Oct 14 2

Philips Semiconductors Product specification

Y/C automatic adjustment processor
(VHS standard)

TDA9725

FEATURES

• Automatic adjustment by control loops

• Integrated filters

• Simple SVHS playback

• Colour sequence correction for long-play still mode

• Automatic gain control for FM.

GENERAL DESCRIPTION

The TDA9725 is an integrated circuit for chrominance and
luminance processing (record and playback) in VHS tape
recorders for PAL, SECAM/ME and NTSC systems
(4.43 MHz playback only) with internal filter and without
adjustments.

QUICK REFERENCE DATA

ORDERING INFORMATION

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

CC

supply voltage 4.5 5.0 5.5 V

I

CC

supply current VCC= 5 V; playback 140 170 200 mA

V

i(p-p)

video input voltage; CVBS signal
(peak-to-peak value)

0.6 1.0 2.0 V

V

oREC(p-p)

video output record voltage
(peak-to-peak value)

video/sync = 7/3 2.03 2.14 2.25 V

V

oPB(p-p)

video output playback voltage
(peak-to-peak value)

video/sync = 7/3;
nominal FM signal

2.03 2.14 2.25 V

V

iFM(p-p)

FM input voltage (peak-to-peak value) FM AGC active 63 200 632 mV

V

oFM(p-p)

FM output voltage (peak-to-peak value) RL=1kΩ 0.7 0.9 1.1 V

V

CFT(p-p)

chrominance input voltage (+FM) from tape
(peak-to-peak value)

11 110 310 mV

V

CTT(p-p)

chrominance output voltage to tape
(peak-to-peak value)

467 660 932 mV

T

stg

storage temperature −25 − +150 °C

T

amb

operating ambient temperature −20 − +70 °C

TYPE

NUMBER

PACKAGE

NAME DESCRIPTION VERSION

TDA9725 SDIP52 plastic shrink dual in-line package; 52 leads (600 mil) SOT247-1

1996 Oct 14 3

Philips Semiconductors Product specification

Y/C automatic adjustment processor
(VHS standard)

TDA9725

BLOCK DIAGRAM

Fig.1 Block diagram (continued in Fig.2).

(1) Low leakage current.
All capacitors for loop filter ±10%; all other capacitors+10%/−50%; all resistors ±5%; all inductors ±10%; unless otherwise specified.

handbook, full pagewidth

1HDL

CCD

CLAMP

1

CLAMP

2

CCD
AGC

SYNC

SEPARATOR

HSS

AGC

DETECTOR

CLPA

AGC

LPF

SCL

NLDE

CLPB

W/DC

NLE
DTE

CLAMP

3

YLPF

NOISE

CLIP

Y/C

MIXER

CHARACTER

INSERT

2.5 dB

YNR

PROCESSOR

NOISE

CANCELLER

1

DEVIATION

CONTROL

FM DEMODULATOR

SUBLPF

DOUBLE
LIMITER

FM

AGC

DROP-OUT
DETECTOR

ENVELOPE
DETECTOR

f

0

PROCESSOR

DEVIATION/PLAYBACK

DETECTOR

YNR

MIXER



10 
µF

1.3
kΩ

47
nF

1 µF

VTC

VFC

LPNC

C

CCD

C

SS

C

AGC

V

CC(Y)

GND(Y)

50 kΩ

22 nF

YNR

SYNC

CVBSI

CVBSO

CHI

22
µH

10
µF

0.1
µF

0.33
µF

0.01
µF

4.7 µF 4.7 µF

A

50
kΩ

50 kΩ

1 kΩ

REC

PB

DOP

PICTURE

EDIT

EDIT

EDIT

25 kΩ

50 kΩ

to pin 6

SQPB

GATE

DOP

REC

PB

ME

SQPB

MODULATOR

to BPF 4.43

52 51 50 49 48 47 46 45 44 43 42 41 40

REC

PB

PB

REC

REC

PB

PB

PB

pin 14

HIGH

1.5 kΩ1.5 kΩ

1 kΩ

470 Ω

270 Ω

680 pF

5%

peaking

0.1
µF

0.1 µF

4.7 
µF

22
nF

V

CC(FM)

C

F0E

CDEV

C

CLP3

C

FMA

FMO

PTR

FMI

1 nF

5%

NFB

PCTL

TP2

SQPB

to CLP3

(1)

12 34 5 6 7 8 9 10 11 12 13 14

1.6 V

MDEBMDECMEO

TDA9725

MGB694

1996 Oct 14 4

Philips Semiconductors Product specification

Y/C automatic adjustment processor
(VHS standard)

TDA9725

handbook, full pagewidth

COMB

DRIVER

BURST
DOWN

BURST UP

BPF

4.43

CK/FPC

DETECTOR

FREQUENCY

DETECTOR

DIVIDER

SUBMIXER

LPF

PHI/PB

VXO

RECORD

AFC

LPF
630

BPF

630

15
µH

0.1
µF

10 nF

COMB

-15 dB

LPF

f

H/2

C

*

BALANCED

MIXER

ACC

TIMER

MUTE

MUTE

: 40

4 PHI : 4SLD

VCO

VXO

X2

3rd

LOCK

ACC

DETECTOR

f

H/2

f

sc

f

sc

2 f

sc

from

4 PHI

HSS

PBCI

PBCO

AGCKP1

CFI CDO

TP1

1.3
kΩ

CF892

270 Ω

50 kΩ

8.0
kΩ

50 kΩ

22 kΩ

120

kΩ

680

Ω

4.7 kΩ

4

2

3

SNP

BMI ACCO

10 nF

GND(C)

V

CC(C)

V

CC(C)

V

CC(C)

CFT

CTT

f

H/2

39 38 37 36 35 34 33 32 31 30 29 28 27

CK
H BLANK

SEC

PB

REC

CK

PB

PB

CK

PB/SP

NAP

REC

REC

RECPB/LP

from pin 43

REC

REC

REC
PB

SEC
MUTE

PB

FPC

to BM

ELS

CK

0.1
µF

0.1 µF
(1)

1 µF

(1)

6.8
µH

(1)

1 µF

FCO

BGP ROT

LFVXO LFVCO

XTALI XTALO

TEW 8H

470

pF

47

nF

33
pF

4.43619
MHz

15 16 17 18 19 20 21 22 23 24 25 26

TDA9725

10 nF

MGB695

A

Fig.2 Block diagram (continued from Fig.1).

(1) Low leakage current.

1996 Oct 14 5

Philips Semiconductors Product specification

Y/C automatic adjustment processor
(VHS standard)

TDA9725

Table 1 Explanation of symbols in Figs 1 and 2

PINNING

SYMBOL DESCRIPTION

AGCKP1 mode with shortened key pulse for AGC
BGP burst gate pulse
DOP dropout pulse
f

H

line frequency

f

sc

subcarrier frequency (4.433619 MHz)
HDL CCD charged coupled device with 1H delay
NLDE non-linear de-emphasis
NLEDTE non-linear emphasis/detail enhancer
ROT rotary pulse
VXO voltage controlled XTAL oscillator
YNR vertical noise reduction
YLPF luminance low-pass filter

SYMBOL PIN DESCRIPTION

PCTL 1 picture control/edit switch input
CDEV 2 deviation/playback AGC detector input
TP2 3 test pin 2/correlation detector output
NFB

4

negative feedback input of main
emphasis

MEO

5

main emphasis output/white
clip/modulator input/SQPB selector

C

CLP3

6 capacitor for clamp 3

C

F0E

7

storage capacitor for f0 processor

(record)/envelope detector (playback)
MDEC 8 main de-emphasis output
MDEB 9 main de-emphasis and peaking output
V

CC(FM)

10 FM supply voltage
FMO 11 FM output
PTR 12 switch (PB/TRICK/REC)
FMI 13 playback FM input
C

FMA

14 storage capacitor for FM AGC
ELS

15

PAL: switch (LP C*/LP/SP); NTSC:

switch (EP/LP/SP)
CK 16 colour killer terminal
FCO 17 frequency correction output
BGP 18 burst gate pulse output

Note

1. It is recommended that this pin should be connected to
ground.

ROT 19 rotary pulse input
LFVXO 20 loop filter VXO
LFVCO 21 loop filter VCO
n.c. 22 not connected; note 1
f

sc

23 fsc output
XTALI 24 VXO input from crystal
XTALO 25 VXO output to crystal
2f

sc

26 2fsc output
f

H/2

27 f

H/2

output
CTT 28 chrominance output to tape
V

CC(C)

29 chrominance supply voltage
CFT 30 playback chrominance input from tape
GND(C) 31 chrominance ground
ACCO 32 automatic chrominance control output
BMI 33 balanced mixer input
SNP 34 switch (SECAM/NTSC/PAL)
CDO 35 comb driver output
CFI 36 chrominance input from comb filter
TP1 37 test pin 1; note 1
PBCO 38 playback chrominance output
PBCI 39 playback chrominance input
V

CC(Y)

40 luminance supply voltage
CVBSO 41 CVBS output
CHI 42 character insertion input (artificial

sync/black/white/through)
CVBSI 43 CVBS input
C

AGC

44 AGC detector capacitor
SYNC 45 sync separator push-pull output
C

SS

46 sync separator detector capacitor
YNR 47 YNR switch
VFC 48 video input from 1HDL CCD
VTC 49 video output to 1HDL CCD
C

CCD

50 storage capacitor for CCD AGC level
GND(Y) 51 luminance ground
LPNC 52 low-pass filter noise canceller

SYMBOL PIN DESCRIPTION

1996 Oct 14 6

Philips Semiconductors Product specification

Y/C automatic adjustment processor
(VHS standard)

TDA9725

Fig.3 Pin configuration.

handbook, halfpage

TDA9725

MGB693

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19

20
21
22
23
24
25
26

52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27

PCTL

CDEV

TP2

NFB

MEO

C

CLP3
C

F0E

MDEC
MDEB

V

CC(FM)

FMO

PTR

FMI

C

FMA

ELS

CK
FCO
BGP
ROT

LFVXO

LFVCO

n.c.

f

sc

XTALI

XTALO

2f

sc

LPNC
GND(Y)
C

CCD

VTC
VFC
YNR
C

SS

SYNC
C

AGC

CVBSI
CHI
CVBSO
V

CC(Y)

PBCI
PBCO
TP1
CFI
CDO
SNP
BMI
ACCO
GND(C)
CFT
V

CC(C)

CTT
f

H/2

1996 Oct 14 7

Philips Semiconductors Product specification

Y/C automatic adjustment processor
(VHS standard)

TDA9725

FUNCTIONAL DESCRIPTION
Record (REC)/electric to electric (EE) mode

L

UMINANCE

From input pin 43 the CVBS signal is fed via the automatic
gain control (AGC) and subclamp (SCL) to the output
pin 41. Instead of the controlled and clamped CVBS signal
it is also possible to switch (dependent on the level at
pin 42) white, black or sync-level to this pin. To eliminate
chrominance parts the CVBS signal is fed to the luminance
low-pass filter (YLPF) and to the sync separator stage.
The sync signal is available at pin 45. The signal is also fed
via vertical emphasis non-linear emphasis (NLE),
deviation control stage, main emphasis and white-dark clip
to the FM modulator. The FM signal is available at pin 11.

C

HROMINANCE

The chrominance signal is selected out of CVBS (from
pin 43) in BPF 4.43 MHz (band-pass filter) and controlled
in automatic chrominance control (ACC).
The chrominance signal is mixed with 5.06 MHz to
627 kHz and via LPF 627 kHz to the output pin 30.

Playback (PB)/video to video (VV) mode

LUMINANCE
The FM signal is fed via FM AGC and double limiter to the

controlled FM demodulator. After demodulation and
filtering in sub low-pass filter (SUBLPF) main
de-emphasis, YLPF and non-linear de-emphasis the
signal is fed to the vertical noise reduction (YNR) and in
parallel to the sync separator. The chrominance signal is
added in the Y/C mixer. The complete CVBS signal is
available at pin 41.

C

HROMINANCE

The 627 kHz chrominance signal coming from tape via
BPF 627 kHz and field ACC to the balanced mixer. Mixed
with 5.06 MHz the 4.43 MHz chrominance signal is fed via
comb driver stage to the external comb filter (pin 35) and
via internal conjugated complex (C*) stage and internal AC
coupling to the luminance part.

Record and playback

In both modes record (REC) and playback (PB) the

5.06 MHz mixer frequency is produced by the 20.24 MHz
voltage controlled oscillator (VCO) and a divide-by-four.

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

Note

1. Charge device model class B: discharging a 200 pF capacitor via a 0 Ω series resistor.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

CC

supply voltage 0 − 6.0 V

V

I

input voltage at pin 22 0 − 1.6 V

V

n

input voltage on all other pins 0 − V

CC

V

I

I

input current at pin 22 −−10 mA

P

tot

total power dissipation −−1250 mW

T

stg

storage temperature −25 − +150 °C

T

amb

operating ambient temperature −20 − +70 °C

V

es

electrostatic handling for all pins note 1 −300 − +300 V

SYMBOL PARAMETER VALUE UNIT

R

th j-a

thermal resistance from junction to ambient in free air 43 K/W

1996 Oct 14 8

Philips Semiconductors Product specification

Y/C automatic adjustment processor
(VHS standard)

TDA9725

CHARACTERISTICS

VCC=5V; T

amb

= +25 °C and typical application (see Figs 1 and 2), unless otherwise specified.
Luminance part: All amplitudes are VBS peak-to-peak values, unless otherwise specified.
Chrominance part: All amplitudes for P AL and NTSC are red values with 75% saturation and chrominance-to-burst ratio
of 2.2 : 1, unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V

CC

supply voltage 4.5 5.0 5.5 V

I

PB

current consumption
(I10+I29+I40)

playback mode 140 170 200 mA

I

REC

current consumption
(I10+I29+I40)

record mode 125 155 185 mA

FM SUPPLY (PIN 10)
I

PB

DC playback current − 22 − mA

I

REC

DC record current − 12 − mA
CHROMINANCE SUPPLY (PIN 29)
I

CC(C)

DC supply current playback mode − 85 − mA

record mode − 85 − mA

L

UMINANCE SUPPLY (PIN 40)

I

PB

DC playback current − 63 − mA
I

REC

DC record current − 57 − mA

Picture control/edit switch input (pin 1)

V

1

DC input voltage pin open-circuit − 1.6 − V

sharp picture 0 − 1.6 V
soft picture 1.6 − 3.2 V
edit mode 4.1 − 5.0 V

Deviation/playback AGC detector input (pin 2)

V

2

detection voltage 1.8 2.5 3.2 V

Test pin 2/correlation detector output (pin 3)

V

OH

HIGH level output voltage correlation of Y signal;

pin 37 LOW; RL≥ 10 kΩ

1.5 2.1 3.0 V

V

OL

LOW level output voltage non-correlation of Y signal − 0.1 0.5 V

1996 Oct 14 9

Philips Semiconductors Product specification

Y/C automatic adjustment processor
(VHS standard)

TDA9725

Negative feedback input of main emphasis (pin 4; open-base) and main emphasis
output/white-clip/modulator/SQPB selector (pin 5)

F

EEDBACK LOOP CLOSED (PIN 4 CONNECTED TO PIN 5; MAIN EMPHASIS OFF)

V

SY

DC voltage level sync tip − 1.9 − V
V

oREC(p-p)

record output voltage level;

standard output level

(peak-to-peak value)

video/sync = 7/3;
∆VCC= ±0.25 V;
T

amb

= −10 to +70 °C

450 500 550 mV

t

FRAMEDET

time for correcting carrier

interleave relationship to

half picture

HIGH during half picture 1; note 1 −−200 ms

NON-LINEAR EMPHASIS/DETAIL ENHANCER; notes 2 and 3
RD1 response D1 −20 dB; f

i

= 500 kHz; SP; NORM 1.7 2.7 3.7 dB

RD2 response D2 −20 dB; f

i

= 2 MHz; SP; NORM 6.0 7.5 9.0 dB

RS1 response S1 −20 dB; f

i

= 500 kHz; SP; EDIT 1.0 1.7 2.4 dB

RS1 response S2 −20 dB; f

i

= 2 MHz; SP; EDIT 4.5 5.5 6.5 dB

RL1 response L1 −20 dB; f

i

= 500 kHz; LP 3.1 4.4 5.7 dB

RL2 response L2 −20 dB; f

i

= 2 MHz; LP 7.0 9.0 11 dB

RL3 response L3 0 dB; f

i

= 2 MHz; LP 1.6 2.3 3.0 dB
VERTICAL EMPHASIS
PL1 peak level 1 −30 dB recursive; note 4 3.5 4.3 5.3 dB

PL2 peak level 2 −20 dB recursive; note 4 3.5 4.0 4.5 dB
PL3 peak level 3 0 dB recursive 0 0.4 1.0 dB

F

EEDBACK LOOP NORMAL APPLICATION

DCL dark-clip level 50 60 70 %
WCL white-clip level 180 187 194 %
V

5

SQPB input voltage playback mode 4.0 −−V

Record storage capacitor for f

0

processor and playback storage capacitor for envelope detector (pin 7)

V

I

DC voltage record mode − 1.2 − V

V

NOR

DC voltage of normal mode playback mode;

V

i

= 350 mV (p-p); pin 14 HIGH

2.3 3.3 4.0 V

V

OFF

DC voltage of dropout
correction (DOC) off mode

playback mode 0 − 1.3 V

V

NS

DC voltage at no input
signal

playback mode 1.1 1.6 2.1 V

G

Eon

envelope detector
switch-on level
(dropout active)

playback mode;
0dB=Vi= 350 mV (p-p);
fi= 3.8 MHz; pin 14 HIGH

−13 −10 −7dB

t

env

envelope detector operating
time

Ci= 0.1 µF 380 500 620 µs

SYMBOL PARAMETER CONDITIONS MIN. TYP . MAX. UNIT

1996 Oct 14 10

Philips Semiconductors Product specification

Y/C automatic adjustment processor
(VHS standard)

TDA9725

Main de-emphasis output (pin 8; open collector)

V

8

DC output voltage fi= 3.8 MHz at VHS 2.9 3.4 3.9 V

V

VID(p-p)

video output voltage level
(peak-to-peak value)

f

DEV

= 1 MHz 230 300 370 mV

Φ

DEM

demodulator sensitivity VHS mode 0.23 0.3 0.37 V/MHz

SQPB mode 0.14 0.19 0.24 V/MHz

LIN1 demodulator linearity 1 VHS mode 0.97 1.0 1.03

LIN2 demodulator linearity 2 SQPB mode 0.90 1.0 1.07

Main de-emphasis and peaking output (pin 9)

V

9

DC output voltage fi= 3.8 MHz at VHS 1.1 1.6 2.1 V

V

VR(p-p)

reverse video voltage level
(peak-to-peak value)

230 300 370 mV

α

DEM

suppression of
demodulated carrier

40 −−dB

FM output (pin 11)

V

11

DC mean value output
voltage

RL=1kΩ 2.9 3.2 3.5 V

V

11(p-p)

output voltage level
(peak-to-peak value)

RL=1kΩ 0.7 0.9 1.1 V

f

sync

sync output frequency V5=V

sync

; V43= 0 dB 3.75 3.8 3.85 MHz

∆f

sync

stability of sync output
frequency

∆VCC= ±0.25 V
or T

amb

= −10 to +70 °C

−20 − +20 kHz

f

dev

frequency deviation V5=V

white

; V43= 0 dB;

video/sync = 7/3

0.95 1.0 1.05 MHz

∆f

dev

stability of frequency
deviation

∆VCC= ±0.25 V
or T

amb

= −10 to +70 °C

−20 − +20 kHz

∆f

rot

carrier interleave frequency rotary pulse (pin 19) HIGH/LOW;

at SP and LP

6.8 7.8 8.8 kHz

H

2

second harmonic distortion fi= 3.8 MHz −−50 −42 dB

L

mod

modulator linearity 0.95 1.00 1.05

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V05 MHz()V

0

4MHz()–

V

0

4 MHz()V

0

3MHz()–

--------------------------------------------------------------------

V

0

9 MHz()V

0

7MHz()–

V

0

7 MHz()V

0

5MHz()–

--------------------------------------------------------------------

1996 Oct 14 11

Philips Semiconductors Product specification

Y/C automatic adjustment processor
(VHS standard)

TDA9725

Switch: PB/TRICK/REC (pin 12)

R

I

internal resistance to
ground

40 50 60 kΩ

V

PB

voltage range for active
playback mode

3.5 − 5V

V

TR

voltage range for active
trick mode

1.75 − 3V

V

REC

voltage range for active
record mode

0 − 1.25 V

Playback FM input (pin 13)

V

13

DC voltage 1.7 2.2 2.7 V

V

i(p-p)

input voltage level
(peak-to-peak value)

FM AGC active 63 200 632 mV
FM AGC not active; pin 14 HIGH − 350 − mV

V

iBO(p-p)

boundary input voltage
(peak-to-peak value)

fi= 3.8 MHz; pin 14 HIGH 10 − 1000 mV

G

DOC

DOC on level Vi= 350 mV (p-p); fi= 3.8 MHz;

pins 7 and 14 HIGH

−18 −15 −12 dB

∆G

hys

DOC on/off hysteresis Vi= 350 mV (p-p); fi= 3.8 MHz;

pins 7 and 14 HIGH

135dB

G

Eon

envelope detector
switch-on level

playback mode;
0dB=Vi= 350 mV (p-p);
fi= 3.8 MHz; pin 14 HIGH

−13 −10 −7dB

Storage capacitor for FM AGC (pin 14; playback mode)

V

14

DC voltage AGC on 2.6 3.1 3.6 V
DC input voltage AGC off 4.3 − 5.0 V

Switch LP C*/LP/SP at PAL; EP/LP/SP at NTSC (pin 15)

R

I

internal resistance to
ground

40 50 60 kΩ

V

C

input voltage for active C*
(conjugated complex
chrominance signal)

PAL 3.5 − 5V

V

E

input voltage for active EP NTSC 3.5 − 5V

V

L

input voltage for active LP 1.75 − 3V

V

S

input voltage for active SP 0 − 1.25 V

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1996 Oct 14 12

Philips Semiconductors Product specification

Y/C automatic adjustment processor
(VHS standard)

TDA9725

Colour killer terminal (pin 16)

V

NC

DC voltage black and white luminance input without

chrominance

1.6 1.8 2.0 V

V

16

input voltage forced colour off 0 − 1.5 V

forced colour on 3.0 − 4.3 V

V

th

threshold voltage colour on 2.0 2.2 2.4 V

CK

th

colour killer threshold relative to nominal input;

V30= 110 mV (p-p)

−25 −30 −35 dB

CK

hys

colour killer hysteresis relative to nominal input;

V30= 110 mV (p-p)

135dB

Frequency correction output (pin 17)

V

17

operating range 0.8 − 4.2 V

I

oSLD

SLD output current SLD ±12 ±17 ±22 µA

t

SLD

SLD pulse duration SLD − 1 − t

H

f

SLH

start of detection at positive
frequency deviation
(referenced to fsc+N×fH at
pin 35; −I17)

SLD/PAL 1.0 2.0 3.0 kHz
SLD/NTSC 2.0 4.0 5.0 kHz

f

SLL

start of detection at
negative frequency
deviation (referenced to
fsc+N×fH at pin 35; +I17)

SLD/PAL −3.0 −2.0 −1.0 kHz
SLD/NTSC −5.0 −4.0 −2.0 kHz

I

ofDET

output current of frequency
detector

FDET ±12 ±17 ±22 µA

t

fDET

frequency detector pulse
duration

FDET 68 73 78 µs

f

fDETH

start of detection at positive
frequency deviation
(referenced to fsc+N×fH at
pin 35; −I17)

record mode 40 70 100 kHz

f

fDETL

start of detection at
negative frequency
deviation (referenced to
fsc+N×fH at pin 35; +I17)

record mode −100 −70 −40 kHz

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1996 Oct 14 13

Philips Semiconductors Product specification

Y/C automatic adjustment processor
(VHS standard)

TDA9725

Burst gate pulse output (or sandcastle output; pin 18); note 5
t

BGP

burst gate pulse duration 4.2 4.45 4.7 µs

t

BGS

start of burst gate beyond
sync start at pin 45

3.25 3.5 3.75 µs

V

O(L)

LOW level DC output
voltage

inactive; I18=1mA −−0.7 V
inactive; I

18

=0mA −−0.5 V

V

O(M)

medium level DC output
voltage

horizontal blanking;
10 kΩ connected to V

CC

2.2 2.6 3.0 V

V

O(H)

HIGH level DC output
voltage

BGP; I18= −0.4 mA 4.0 4.4 − V
BGP; I

18

=0mA 4.6 −−V

t

VBL(start)

vertical blanking of BGP
start

referring to first equalisation
pulse in mid of line

− 0 − t

H

t

VBL(stop)

vertical blanking of BGP
stop

referring to rotary transition 23 −−t

H

referring to last equalisation pulse
in mid of line

1 −−t

H

Rotary pulse input (pin 19; open PNP base)

V

C2

voltage for −90° phase
rotation

channel 2 0 − 2.25 V

V

C1

voltage for non-rotation
(PAL) or +90° rotation
(NTSC)

channel 1 2.75 − 5V

Loop filter VXO (pin 20; record mode)

V

20

DC voltage 1 2.4 3.6 V

Φ

VXO

VXO sensitivity −1.6 −1.2 −0.8 Hz/mV

f

PI(U)

upper pull-in frequency 0.6 1.0 1.8 kHz

f

PI(L)

lower pull-in frequency −1.8 −1.0 −0.6 kHz

Loop filter VCO (pin 21)

V

21

DC voltage 1.3 2.1 2.9 V

Φ

VCO

VCO sensitivity fH related; record mode −34 −38 −42 kHz/V

f

sc

related; playback mode −1.3 −1.5 −1.7 MHz/V

f

sc

output (pin 23)

V

23

DC output voltage 1.8 2.3 2.8 V

V

o(p-p)

output signal voltage
(peak-to-peak value)

no load 500 600 700 mV

H

2

second harmonic distortion −−−25 dB

H

3

third harmonic distortion −−−20 dB
VXO input from crystal (pin 24); note 6
V

24

DC voltage 2.6 3.0 3.4 V

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1996 Oct 14 14

Philips Semiconductors Product specification

Y/C automatic adjustment processor
(VHS standard)

TDA9725

VXO output to crystal (pin 25)

V

25

DC output voltage 2.9 3.3 3.7 V
∆f

osc

deviation of oscillator

frequency

due to internal spread;
playback mode

−50 − +50 Hz

video signal without burst;
record mode

−1.4 − +1.4 kHz

no video signal; record mode −100 − +100 Hz
V

CC

= 4.75 to 5.25 V;

T

amb

= −10 to +70 °C;

playback mode

−100 − +100 Hz

2f

sc

output (pin 26)

V

26

DC output voltage 4.5 4.9 − V
V

o

output signal voltage 1.2 kΩ connected to VCC and

emitter follower (EF)

40 55 70 mV

tuned LC circuit to V

CC

and EF 400 550 700 mV

H

2

second harmonic distortion tuned LC circuit (Q > 20) and EF −−−30 dB

f

H/2

output; coupled to burst sequence (pin 27)

V

O(L)

LOW level DC output

voltage

burst phase = +135°−−0.5 V

V

O(H)

HIGH level DC output

voltage

burst phase = −135° 4.5 −−V

V

NTSC4.43

input level for forced

NTSC 4.43 mode (no NAP)

NTSC; playback mode −−1.5 V

Chrominance output to tape (pin 28); see Table 2
V

28

DC output voltage colour on 2.1 2.4 2.7 V

colour killer active − 0.1 0.3 V

V

o(p-p)

chrominance output signal

voltage (N × fH)

(peak-to-peak value)

record mode; PAL 467 660 932 mV

G

UP

SECAM-fOR burst related

to PAL burst

SECAM 0.2 1.0 1.8 dB

H

2

second harmonic distortion V33=0dB −−−40 dB

V

33

=+6dB −−−35 dB

H

3

third harmonic distortion V33=0dB −−−40 dB

V

33

=+6dB −−−35 dB

α

CK

colour killer suppression 40 −−dB

Playback chrominance input from tape (pin 30)

V

30

DC voltage 1.7 2.2 2.7 V
V

i(p-p)

input signal voltage

(peak-to-peak value)

chrominance + FM −−310 mV
chrominance 11 110 220 mV

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT