INTEGRATED CIRCUITS
DATA SHEET
TDA 9321H
I2C-bus controlled TV Input
Processor
Final Device Specification |
June 30, 1998 |
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Previous version: December 19, 1997 |
Philips Semiconductors
Philips Semiconductors |
Final Device Specification |
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I2C-bus controlled TV Input Processor |
TDA 9321H |
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FEATURES
∙Multi-standard vision IF circuit with PLL demodulator
∙Sound IF amplifier with separate input for single reference QSS mode and separate AGC circuit
∙AM demodulator without extra reference circuit
∙Switchable group delay correction circuit which can be used to compensate the group delay pre-correction of the BG-standard in multi-standard TV receivers
∙Several (I2C-bus controlled) switch outputs which can be used to switch external circuits like sound traps etc.
∙Flexible source selection circuit with 2 external CVBS inputs, 2 Y/C (or additional CVBS) inputs and 2 (independently switchable) outputs
∙Comb filter interface with CVBS output and Y/C input
∙Integrated chrominance trap circuit
∙Integrated luminance delay line with adjustable delay time
∙Integrated chroma band-pass filter with switchable centre frequency
∙Multi-standard colour decoder with 4 separate X-tal pins and automatic search system
∙PALplus helper demodulator
∙Possible blanking of the “helper signals” for PALplus and EDTV-2
∙Internal base-band delay line
∙2 linear RGB inputs with fast blanking. The RGB signals are converted to YUV before they are supplied to the outputs. One of the RGB inputs can also be used as YUV input.
∙Horizontal synchronisation circuit with switchable time-constant for the PLL and Macrovision/subtitle gating
∙HA synchronisation pulse output or clamping pulse input/output
∙Vertical count-down circuit
∙VA synchronisation pulse output
∙Two-level sandcastle pulse output
∙I2C-bus control of various functions
∙Low dissipation
GENERAL DESCRIPTION
The TDA 9321H is an input processor for “High-end” television receivers which contains the following functions:
∙Multi-standard IF amplifier with PLL demodulator
∙QSS-IF amplifier and AM sound demodulator
∙Flexible CVBS and Y/C switch with various inputs and outputs
∙Multi-standard colour decoder which can also decode the PALplus helper signal
∙Integrated base-band delay line (64 μs)
∙Sync processor which generates the horizontal and vertical drive pulses for the feature box (100 Hz applications) or Display Processor (50 Hz applications)
The supply voltage of the IC is 8 Volts. It is mounted in a QFP envelope with 64 pins.
June 30, 1998 |
2 |
Philips Semiconductors |
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Final Device Specification |
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I2C-bus controlled TV Input Processor |
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TDA 9321H |
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QUICK REFERENCE DATA |
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SYMBOL |
PARAMETER |
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UNIT |
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Supply |
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VP |
supply voltage |
7.2 |
8.0 |
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8.8 |
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IP |
supply current |
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120 |
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mA |
Input voltages |
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ViVIFrms) |
video IF amplifier sensitivity (RMS value) |
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35 |
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μV |
ViSIF(rms) |
sound IF amplifier sensitivity (RMS value) |
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30 |
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μV |
ViCVBS(p-p) |
external CVBS/Y input (peak-to-peak value) |
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1.0 |
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V |
ViCHROMA(p-p) |
external chroma input voltage (burst amplitude) |
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0.3 |
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V |
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(peak-to-peak value) |
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ViRGB(p-p) |
RGB inputs (peak-to-peak value) |
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0.7 |
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V |
Output signals |
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VoCVBS(p-p) |
demodulated CVBS output (peak-to-peak value) |
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2.5 |
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V |
IoTUNER |
tuner AGC output current range |
0 |
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5 |
mA |
VoINT.(rms) |
sound IF intercarrier output (RMS value) |
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100 |
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mV |
VoAM(rms) |
demodulated AM sound output (RMS value) |
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500 |
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mV |
VoVIDSW(p-p) |
CVBS output voltage (peak-to-peak value) |
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1.0/2.0 |
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V |
VoB-Y(p-p) |
−(R−Y) output voltage (peak-to-peak value) |
− |
1.05 |
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V |
VoR-Y(p-p) |
−(B−Y) output voltage (peak-to-peak value) |
− |
1.33 |
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V |
VoY(BL-WH) |
Y output voltage (black-to-white value) |
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1.0 |
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V |
VoHorizontal |
HA output voltage |
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5 |
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V |
VoVertical |
VA output voltage |
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5 |
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V |
VoSubc.(p-p) |
Subcarrier output amplitude (peak-to-peak value) |
− |
200 |
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mV |
June 30, 1998 |
3 |
1998 30,June |
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DIAGRAMBLOCK |
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VIF-IN |
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SIF-IN |
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8V |
HA/CLP |
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controlled bus-C |
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VA |
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SCL |
SDA |
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R1 G1 |
B1 BL1 |
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R2 |
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VIF AMPLIFIER |
SIF AMPLIFIER |
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PULSE |
VERTICAL |
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I2C-BUS |
RGB-MATRIX |
G2 |
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SUPPLY |
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B2 |
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PLL DEMOD |
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QSS/AM |
GENERATOR |
DIVIDER |
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TRANSCEIVER |
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AGC |
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BL2 |
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TUNER |
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AGC/AFC |
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SW-OUT |
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Y-DELAY |
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Y |
U |
V |
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TOP |
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TV |
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AFC |
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Y |
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VERTICAL |
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Y |
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Y/U/V |
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SOUND |
VIDEO AMPL. |
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QSS MIXER |
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VCO+H-PLL |
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U |
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SYNC |
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Y-DELAY |
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SWITCH |
V |
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Input |
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TRAP |
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MUTE |
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AM DEMOD. |
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SEPARATOR |
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MUTE |
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IDENT |
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Y |
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U |
V |
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GROUP DELAY |
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SYNC |
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Y-SWITCH |
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BASE-BAND |
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Processor |
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VIDEO IDENT |
VIDEO IDENT |
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CORRECTION |
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SEPARATOR |
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+ TRAPS |
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DELAY LINE |
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AVCVBSINT-1 |
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SWITCH |
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CONTROL |
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Y/CVBS |
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HELPER |
R-Y |
B-Y |
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4 |
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CLOCHE |
FILTER |
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SECAM |
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PAL(NTSC) |
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CVBS-1 |
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ACC |
FILTER |
TUNING |
FSC |
DECODER |
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/SECAM |
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AV-2 |
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SWITCH |
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CVBS-2 |
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VIDEO SWITCH + CONTROL |
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HUE |
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SW-OUT |
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Y(CVBS)-3 |
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PAL/NTSC |
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C-3 |
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AUTO- |
BANDPASS |
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SYSTEM |
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PAL/NTSC |
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PLL |
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Y(CVBS)-4 |
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CHROMA |
FILTER |
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IDENT |
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DEMOD. |
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HUE CONTR. |
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C-4 |
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AS |
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CVBS(TXT) |
CVBS(PIP) |
CVBS |
SYS1 |
SYS2 |
Y |
C |
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11-12-96/AC |
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COMB FILTER |
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SUBCARRIER |
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Final |
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9321H TDA |
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Fig.1 BLOCK DIAGRAM TDA 9321H |
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Specification Device |
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Philips Semiconductors |
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Final Device Specification |
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I2C-bus controlled TV Input Processor |
TDA 9321H |
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PINNING |
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SYMBOL |
PIN |
DESCRIPTION |
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AGCSIF |
1 |
SIF AGC decoupling capacitor |
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IFIN1 |
2 |
IF input 1 |
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IFIN2 |
3 |
IF input 2 |
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AGCVIF |
4 |
VIF AGC decoupling capacitor |
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SIFOUT/AMOUT |
5 |
combined QSS and AM sound output |
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PLLIF |
6 |
IF-PLL loop filter |
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IFVCO1 |
7 |
IF VCO tuned circuit 1 |
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IFVCO2 |
8 |
IF VCO tuned circuit 2 |
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GND1 |
9 |
main ground |
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IFVO |
10 |
IF video output |
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VP1 |
11 |
main supply voltage 1 (+8 V) |
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GDIN |
12 |
group delay correction input |
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GDOUT |
13 |
group delay correction output |
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CVBSINT |
14 |
internal CVBS input |
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AV1 |
15 |
AV-1 input |
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CVBS1 |
16 |
CVBS-1 input |
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AV2 |
17 |
AV-2 input |
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CVBS2 |
18 |
CVBS-2 input |
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SW0 |
19 |
output switch (I2C) |
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CVBS/Y3 |
20 |
CVBS/Y-3 input |
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CHROMA3 |
21 |
chrominance-3 input |
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SW1 |
22 |
output switch (I2C) |
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CVBS/Y4 |
23 |
CVBS/Y-4 input |
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CHROMA4 |
24 |
chrominance-4 input |
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COMBSYS1 |
25 |
SYS-1 output for comb filter |
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COMBCVBS |
26 |
CVBS output for comb filter |
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COMBSYS2 |
27 |
SYS-2 output for comb filter |
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COMBY |
28 |
luminance input (from comb filter) |
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COMBC |
29 |
chrominance input (from comb filter) |
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REFO |
30 |
subcarrier output |
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GND2 |
31 |
digital ground |
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CVBSOPIP |
32 |
CVBS (PIP) output |
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DECDIG |
33 |
digital supply decoupling |
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CVBSOTXT |
34 |
CVBS (TXT) output |
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DECBG |
35 |
bandgap decoupling |
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RI1 |
36 |
R-1 input |
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GI1 |
37 |
G-1 input |
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BI1 |
38 |
B-1 input |
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RGBIN1 |
39 |
RGB-1 insertion input |
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RGBIN2 |
40 |
RGB-2 insertion input |
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June 30, 1998 |
5 |
Philips Semiconductors |
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Final Device Specification |
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I2C-bus controlled TV Input Processor |
TDA 9321H |
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SYMBOL |
PIN |
DESCRIPTION |
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RI2 |
41 |
R-2 input |
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GI2 |
42 |
G-2 input |
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BI2 |
43 |
B-2 input |
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GND3 |
44 |
ground |
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VP2 |
45 |
positive supply |
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SCL |
46 |
serial clock input |
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SDA |
47 |
serial data input/output |
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AS |
48 |
address select |
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YO |
49 |
luminance output |
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UO |
50 |
U-output |
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VO |
51 |
V-output |
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DET |
52 |
loop filter burst phase detector |
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SECPLL |
53 |
SECAM PLL decoupling |
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XTALA |
54 |
X-tal A (4.433619 MHz) |
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XTALB |
55 |
X-tal B (3.582056 MHz, PAL-N) |
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XTALC |
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X-tal C (3.575611 MHz, PAL-M) |
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XTALD |
57 |
X-tal D (3.579545 MHz, NTSC-M) |
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PH1LF |
58 |
phase-1 filter |
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SO |
59 |
sandcastle pulse output |
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HACLP |
60 |
HA/CLP output/input |
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VA |
61 |
VA output |
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AGCOUT |
62 |
tuner AGC output |
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SIFIN1 |
63 |
SIF input 1 |
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SIFIN2 |
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SIF input 2 |
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June 30, 1998 |
6 |
Philips Semiconductors |
Final Device Specification |
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I2C-bus controlled TV Input Processor |
TDA 9321H |
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handbook, full pagewidth
AGCSIF 1
IFIN1 2
IFIN2 3
AGCVIF 4
SIFO/AMO 5
PLLIF 6
IFVCO1 7
IFVCO2 8
GND1 9
IFVO 10
VP1 11
GDIN 12
GDOUT 13
CVBSINT 14
AV1 15
CVBS1 16
AV2 17
CVBS2
18
SW0 19
SIFIN2 |
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SIFIN1 |
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AGCOUT |
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VA |
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HACLP |
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SO |
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PH1LF |
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XTALD |
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XTALC |
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XTALB |
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XTALA |
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SECPLL |
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DET |
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TDAXXX9321H
20 |
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CVBS/Y3 |
CHROMA3 |
SW1 |
CVBS/Y4 |
CHROMA4 |
COMBSYS1 |
COMBCVBS |
COMBSYS2 |
COMBY |
COMBC |
REFO |
GND2 |
CVBSO |
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PIP |
51 VO
50 UO
49 YO
48 AS
47 SDA
46 SCL
45 VP2
44 GND3
43 BI2
42 GI2
41 RI2
40 RGBIN2
39 RGBIN1
38 BI1
37 GI1
36 RI1
35 DECBG
34 CVBSOTXT
33 DECDIG
MXXxxx
Fig.2 Pin configuration.
June 30, 1998 |
7 |
Philips Semiconductors |
Final Device Specification |
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I2C-bus controlled TV Input Processor |
TDA 9321H |
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FUNCTIONAL DESCRIPTION
Vision IF amplifier
The IF-amplifier contains 3 AC-coupled control stages with a total gain control range which is higher than 66 dB. The sensitivity of the circuit is comparable with that of modern IF-IC’s.
The video signal is demodulated by means of a PLL carrier regenerator. This circuit contains a frequency detector and a phase detector. During acquisition the frequency detector will tune the VCO to the right frequency. The initial adjustment of the oscillator is realised via the I2C-bus. The switching between SECAM L and L’ can also be realised via the I2C-bus. After lock-in the phase detector controls the VCO so that a stable phase relation between the VCO and the input signal is achieved. The VCO is running at the double IF frequency. The reference signal for the demodulator is obtained by means of a frequency divider circuit. To get a good performance for phase modulated carrier signals the control speed of the PLL can be increased by means of the FFI bit.
The AFC output is obtained by using the VCO control voltage of the PLL and can be read via the I2C-bus. For fast search tuning systems the window of the AFC can be increased with a factor 3. The setting is realised with the AFW bit.
The AGC-detector operates on top sync and top whitelevel. The demodulation polarity is switched via the I2C-bus. The AGC detector time-constant capacitor is connected externally. This mainly because of the flexibility of the application. The time-constant of the AGC system during positive modulation is rather long to avoid visible variations of the signal amplitude. To improve the speed of the AGC system a circuit has been included which detects whether the AGC detector is activated every frame period. When during 3 field periods no action is detected the speed of the system is increased. For signals without peak white information the system switches automatically to a gated black level AGC. Because a black level clamp pulse is required for this way of operation the circuit will only switch to black level AGC in the internal mode.
The circuit contains a video identification circuit which is independent of the synchronisation circuit. Therefore search tuning is possible when the display section of the receiver is used as a monitor. However, this ident circuit cannot be made as sensitive as the slower sync ident circuit (SL) and we recommend to use both ident outputs to obtain a reliable search system. The ident output is supplied to the tuning system via the I2C-bus.
The input of the identification circuit is connected to pin 14, the “internal” CVBS input (see Fig.3). This has the advantage that the ident circuit can also be made operative when a scrambled signal is received (descrambler connected between the IF video output (pin 10) and pin 14). A second advantage is that the ident circuit can be used when the IF amplifier is not used (e.g. with built-in satellite tuners).
The video ident circuit can also be used to identify the selected CBVS or Y/C signal. The switching between the 2 modes can be realised with the VIM bit.
The TDA 9321H contains a group delay correction circuit which can be switched between the BG and a flat group delay response characteristic. This has the advantage that in multi-standard receivers no compromise has to be made for the choice of the SAW filter. Both the input and output of the group delay correction circuit are externally available so that the sound trap can be connected between the IF video output and the group delay correction input. The output signal of the correction circuit can be supplied to the video processing circuit and to the SCART plug.
The IC has several (I2C-bus controlled) output ports which can be used to switch sound traps or other external components.
When the IF amplifier is not used the complete IF amplifier can be switched-off via the I2C-bus by means of the IFO bit.
Sound circuit
The sound IF amplifier is similar to the vision IF amplifier and has a gain control range of about 66 dB. The AGC circuit is related to the SIF carrier levels (average level of AM or FM carriers) and ensures a constant signal amplitude of the AM demodulator and the QSS mixer.
The single reference QSS mixer is realised by a multiplier. In this multiplier the SIF signal is converted to the intercarrier frequency by mixing it with the regenerated picture carrier from the VCO. The mixer output signal is supplied to the output via a high-pass filter for attenuation of the residual video signals. With this system a high performance hi-fi stereo sound processing can be achieved.
The AM sound demodulator is realised by a multiplier. The modulated sound IF signal is multiplied in phase with the limited SIF signal. The demodulator output signal is supplied to the output via a low-pass filter for attenuation of the carrier harmonics.
June 30, 1998 |
8 |
Philips Semiconductors |
Final Device Specification |
|
|
I2C-bus controlled TV Input Processor |
TDA 9321H |
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VIM |
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VIDEO |
IDENT |
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IDENT |
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TO LUMA/SYNC PROCESSING |
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TO CHROMA PROCESSING |
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+ |
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+ |
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+ |
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CVBS-INT |
CVBS |
CVBS |
Y/CVBS |
C |
Y/CVBS |
C |
COMB Y-IN |
COMB C-IN |
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COMB OUT |
TXT |
PIP |
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EXT. 1 |
EXT. 2 |
EXT. 3 |
EXT. 3 |
EXT. 4 |
EXT. 4 |
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CVBS |
CVBSO |
CVBSO |
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Fig.3 CVBS switch and interfacing of video ident |
Video switches
The circuit has 3 CVBS inputs (1 internal and 2 external inputs) and 2 Y/C inputs. The Y/C inputs can also be used as additional CVBS inputs. The switch configuration is given in Fig.3. The selection of the various sources is made via the I2C-bus.
The circuit can be set in a mode in which it automatically detects whether a CVBS or a Y/C signal is supplied to the Y/C inputs. In this mode the TV-standard identification first takes place on the added Y/CVBS and the C input signal. Then both chroma input signal amplitudes are checked once and the input signal with the highest burst signal amplitude is selected. The result of the detection can be read via the I2C-bus.
The IC has 2 inputs (AV-1 and AV-2) which can be used to read the status levels of pin 8 of the SCART plug. The information is available in the output status byte 02 in the bits D0-D3.
The 3 outputs of the video switch (CVBSOTXT, CVBSOPIP and COMBCVBS) can be independently switched to the various
input signals. The names are just arbitrary and it is for instance possible to use the COMBCVBS signal to drive the Comb-filter and the teletext decoder in parallel and to supply the CVBSOTXT signal to the SCART plug (via an emitter follower).
For comb filter interfacing the circuit has the COMBCVBS output, a 3rd Y/C input, a reference signal output (fsc) and 2 control pins which switch the comb filter to the standard of the incoming signal (as detected by the ident circuit of the colour decoder). When a signal is recognised which can be combed and the comb filter is enabled by the ECMB-bit the Y/C signals coming from the comb filter are automatically selected. This is indicated via the CMB-bit in output status byte 02 (D5).For signals which cannot be combed (like SECAM or Black-to-White signals) the Y/C signals coming from the comb filter are not selected.
Chroma and luminance processing
The circuits contain a chroma bandpass, the SECAM cloche filter and chroma trap circuit. The filters are realised by means of gyrator circuits and they are automatically calibrated by comparing the tuning frequency with the X-tal frequency of the decoder. The luminance delay line is also realised by means of gyrator circuits. The centre frequency of the chroma bandpass filter is switchable via the I2C-bus so that the performance can be optimised for “front-end” signals and external CVBS signals.
The luminance output signal which is derived from the incoming CVBS or Y/C signal can be varied in amplitude by means of a separate gain setting control via the I2C-bus control bits GAI1 and GAI0. The gain variation which can be realised with these bits is -1 to +2 dB.
June 30, 1998 |
9 |
Philips Semiconductors |
Final Device Specification |
|
|
I2C-bus controlled TV Input Processor |
TDA 9321H |
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Colour decoder
The colour decoder can decode PAL, NTSC and SECAM signals. The PAL/NTSC decoder contains an alignment-free X-tal oscillator with 4 separate X-tal pins, a killer circuit and two colour difference demodulators. The 90° phase shift for the reference signal is made internally.
Because it is possible to connect 4 different X-tals to the colour decoder, all colour standards can be decoded without external switching circuits. Which X-tals are connected to the decoder must be indicated via the I2C-bus. X-tal pins which are not used must be left open.
The horizontal oscillator is calibrated by means of the X-tal frequency of the colour PLL. For a reliable calibration it is very important that the X-tal indication bits (XA to XD) are not corrupted. For this reason the X-tal bits can be read in the output bytes so that the software can check the I2C transmission.
The IC’s contain an Automatic Colour Limiting (ACL) circuit which is switchable via the I2C-bus and which prevents that oversaturation occurs when signals with a high chroma-to-burst ratio are received. The ACL circuit is designed such that it only reduces the chroma signal and not the burst signal. This has the advantage that the colour sensitivity is not affected by this function. The ACL function is mainly intended for NTSC signals and it can also be used for PAL signals. For SECAM signals the ACL function should be switched-off.
The SECAM decoder contains an auto-calibrating PLL demodulator which has two references, viz: the 4.43 MHz sub-carrier frequency which is obtained from the X-tal oscillator which is used to tune the PLL to the desired free-running frequency and the bandgap reference to obtain the correct absolute value of the output signal. The VCO of the PLL is calibrated during each vertical blanking period, when the IC is in search or SECAM mode.
The circuit can also decode the PALplus helper signal and can insert the various reference signals, set-ups and timing signals which are required for the PALplus decoder IC’s.
The base-band delay line (TDA 4665 function) is integrated.
RGB switch and matrix
The IC has 2 RGB inputs with fast switching. The switching of the various sourcing is controlled via the I2C-bus and the condition of the switch inputs can be read from the I2C-bus status bytes. If the RGB signals are not synchronous with the selected decoder input signal, an external clamp pulse has to be supplied to the HA/CLP input. The IC must be set in this mode via the I2C-bus. In that case the VA pulse is suppressed by switching the VA output in a high impedance OFF-state.
When an external RGB signal is mixed into the internal YUV signal it is necessary to switch-off the PALplus demodulation. To detect the presence of a fast blanking a circuit is added which forces the MACP and HD bit to zero if a blanking pulse is detected in 2 consecutive lines. This system is chosen to prevent switching-off at every spike which is detected on the fast blanking input.
The IC has the possibility to use the RGB1 input as YUV input. This function can be enabled by means of the YUV bit in subaddress 0A (D3). When switched to the YUV input the input signals must have the same amplitude and polarity as the YUV output signals. The Y signal has to be supplied to the G1 input, the U signal to the B1 input and the V signal to the R1 input.
Synchronisation circuit
The sync separator is preceded by a controlled amplifier which adjusts the sync pulse amplitude to a fixed level. These pulses are fed to the slicing stage which is operating at 50% of the amplitude. The separated sync pulses are fed to the phase detector and to the coincidence detector. This coincidence detector is used to detect whether the line oscillator is synchronised and can also be used for transmitter identification. This circuit can be made less sensitive by means of the STM bit. This mode can be used during search tuning to avoid that the tuning system stops at very weak input signals. The PLL has a very high statical steepness so that the phase of the picture is independent of the line frequency.
For the horizontal output pulse 2 conditions are possible, viz.:
∙An HA pulse which has a phase and width which is identical to the incoming horizontal sync pulse
∙A clamp pulse (CLP) which has a phase and width which is identical to the clamp pulse in the sandcastle pulse
June 30, 1998 |
10 |
Philips Semiconductors |
Final Device Specification |
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I2C-bus controlled TV Input Processor |
TDA 9321H |
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The HA/CLP signal is generated by means of an oscillator which is running at a frequency of 440 x fH. Its frequency is divided by 440 to lock the first loop to the incoming signal. The time-constant of the loop can be forced by the I2C-bus (fast or slow). If required the IC can select the time-constant depending on the noise content of the incoming video signal.
The free-running frequency of the oscillator is determined by a digital control circuit which is locked to the reference signal of the colour decoder. When the IC is switched-on the HA/CLP is suppressed and the oscillator is calibrated as soon as all sub-address bytes have been sent. When the frequency of the oscillator is correct the HA/CLP signal is switched-on again.
When the coincidence detector indicates an out-of-lock situation the calibration procedure is repeated.
The VA pulse is obtained via a vertical count down circuit. The countdown circuit has various windows depending on the incoming signal (50 Hz or 60 Hz standard or no standard). The countdown circuit can be forced in various modes by means of the I2C-bus. To obtain short switching times of the countdown circuit during a channel change the divider can be forced in the search window by means of the NCIN bit.
I2C-BUS SPECIFICATION
The slave addresses of the IC’s is given in the table below. The circuit operates up to clock frequencies of 400 kHz.
Slave addresses
A6 |
A5 |
A4 |
A3 |
A2 |
A1 |
A0 |
R/W |
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1 |
0 |
0 |
0 |
1 |
A1 |
1 |
1/0 |
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The bit A1 is controlled via the pin 48 (AS), when the pin is connected to ground it is a 0 and when connected to the positive supply line it is a 1. When this pin is left open it is connected to ground via an internal resistor.
Start-up procedure
Read the status bytes until POR = 0 and send all subaddress bytes. It is advised to check the bus transmission by reading the output status bits SXA to SXD. This ensures a good operation of the calibration system of the horizontal oscillator. The horizontal output signal is switched-on when the oscillator is calibrated.
Each time before the data in the IC is refreshed, the status bytes must be read. If POR = 1, the procedure mentioned above must be carried out to restart the IC.When this procedure is not followed the horizontal frequency may be incorrect after power-up or after a power dip.
Valid subaddresses: 00 to 0E, subaddresses FE and FF are reserved for test purposes. Auto-increment mode available for subaddresses.
June 30, 1998 |
11 |
Philips Semiconductors |
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Final Device Specification |
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I2C-bus controlled TV Input Processor |
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TDA 9321H |
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Inputs |
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Table 1 Input status bits. |
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FUNCTION |
SUBADDRESS |
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DATA BYTE |
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(HEX) |
D7 |
D6 |
D5 |
D4 |
D3 |
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D2 |
D1 |
D0 |
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Colour decoder 0 |
00 |
CM3 |
CM2 |
CM1 |
CM0 |
XD |
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XC |
XB |
XA |
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Colour decoder 1 |
01 |
MACP |
HOB |
HBC |
HD |
0 |
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ACL |
CB |
BPS |
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Luminance |
02 |
0 |
0 |
GAI1 |
GAI0 |
YD3 |
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YD2 |
YD1 |
YD0 |
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Hue control |
03 |
0 |
0 |
A5 |
A4 |
A3 |
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A2 |
A1 |
A0 |
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Spare |
04 |
0 |
0 |
0 |
0 |
0 |
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0 |
0 |
0 |
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Synchronisation 0 |
05 |
FORF |
FORS |
FOA |
FOB |
0 |
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VIM |
POC |
VID |
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Synchronisation 1 |
06 |
0 |
0 |
0 |
0 |
BSY |
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HO |
EMG |
NCIN |
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Spare |
07 |
0 |
0 |
0 |
0 |
0 |
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0 |
0 |
0 |
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Video switches 0 |
08 |
0 |
0 |
0 |
ECMB |
DEC3 |
DEC2 |
DEC1 |
DEC0 |
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Video switches 1 |
09 |
0 |
PIP2 |
PIP1 |
PIP0 |
0 |
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TXT2 |
TXT1 |
TXT0 |
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RGB switch |
0A |
0 |
0 |
0 |
0 |
YUV |
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ECL |
IE2 |
IE1 |
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Output switches |
0B |
0 |
0 |
0 |
0 |
0 |
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0 |
OS1 |
OS0 |
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Vision IF |
0C |
FFI |
IFO |
GD |
MOD |
AFW |
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IFS |
STM |
VSW |
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Tuner take-over |
0D |
0 |
0 |
A5 |
A4 |
A3 |
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A2 |
A1 |
A0 |
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Adjustment IF PLL |
0E |
L’FA |
A6 |
A5 |
A4 |
A3 |
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A2 |
A1 |
A0 |
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Table 2 Output status bits. |
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SUBADDRESS |
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DATA BYTE |
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(HEX) |
D7 |
D6 |
D5 |
D4 |
D3 |
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D2 |
D1 |
D0 |
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Output status bytes |
00 |
POR |
x |
x |
x |
SNR |
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FSI |
SL |
IVW |
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01 |
CD3 |
CD2 |
CD1 |
CD0 |
SXD |
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SXC |
SXB |
SXA |
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02 |
IN1 |
IN2 |
CMB |
YC |
S2A |
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S2B |
S1A |
S1B |
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03 |
ID3 |
ID2 |
ID1 |
ID0 |
IFI |
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PL |
AFA |
AFB |
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June 30, 1998 |
12 |
Philips Semiconductors |
Final Device Specification |
|
|
I2C-bus controlled TV Input Processor |
TDA 9321H |
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INPUT CONTROL BITS
Table 3 Colour decoder mode
CM3 |
CM2 |
CM1 |
CM0 |
DECODER MODE |
X-TAL |
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0 |
0 |
0 |
0 |
PAL/NTSC/SECAM |
A |
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0 |
0 |
0 |
1 |
PAL/NTSC |
A |
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0 |
0 |
1 |
0 |
PAL |
A |
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0 |
0 |
1 |
1 |
NTSC |
A |
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0 |
1 |
0 |
0 |
SECAM |
A |
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0 |
1 |
0 |
1 |
PAL/NTSC |
B |
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|
0 |
1 |
1 |
0 |
PAL |
B |
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0 |
1 |
1 |
1 |
NTSC |
B |
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1 |
0 |
0 |
0 |
PAL/NTSC/SECAM |
ABCD |
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1 |
0 |
0 |
1 |
PAL/NTSC |
C |
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1 |
0 |
1 |
0 |
PAL |
C |
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1 |
0 |
1 |
1 |
NTSC |
C |
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1 |
1 |
0 |
0 |
spare |
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1 |
1 |
0 |
1 |
PAL/NTSC |
D |
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1 |
1 |
1 |
0 |
PAL |
D |
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1 |
1 |
1 |
1 |
NTSC |
D |
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Table 4 X-tal indication |
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XA-XD |
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CONDITION |
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0 |
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X-tal not present |
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1 |
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X-tal present, note1 |
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Note
1.When a comb filter is used the various X-tals must be connected to the IC as indicated in the pinning diagram. This is required because the ident system switches automatically to the comb filter when a signal is identified which can be combed (right combination of colour standard and X-tal frequency). For applications without comb filter only XA is important (4.43 MHz), the other pins can then have an arbitrary 3.5 MHz X-tal.
Table 5 Motion Adaptive Colour Plus, note1
MACP |
MODE |
0internal 4.43 MHz trap used
1external MACP chroma filtering used, 4.43 MHz trap bypassed, black set-up 200 mV
Note
1.The black set-up will only be present in a norm sync condition.
Table 6 Helper output blanking (PALplus/EDTV-2)
HOB |
HBC |
SNR |
BLANKING |
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0 |
- |
- |
off |
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1 |
0 |
- |
on |
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1 |
1 |
0 |
off |
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1 |
1 |
1 |
on |
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Table 7 PALplus helper demodulation active, note1
HD |
CONDITION |
0off
1on, PALplus mode with helper set-up 400 mV and black set-up 200 mV
Note
1.Black and helper set-up will only be present in a norm sync condition.
Table |
8 Automatic colour limiting |
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ACL |
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COLOUR LIMITING |
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0 |
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not active |
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1 |
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active |
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Table |
9 Chroma bandpass centre frequency |
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CB |
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CENTRE FREQUENCY |
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0 |
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FSC |
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1 |
|
1.1 x FSC |
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Table |
10 Bypass of chroma base-band delay line |
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BPS |
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DELAY LINE MODE |
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0 |
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active |
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1 |
|
bypassed |
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Table |
11 Gain luminance channel |
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GAI1 |
GAI0 |
|
GAIN SETTING |
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0 |
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0 |
|
-1 dB |
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0 |
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1 |
|
0 dB |
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1 |
|
0 |
|
+1 dB |
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1 |
|
1 |
|
+2 dB |
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June 30, 1998 |
13 |
Philips Semiconductors |
Final Device Specification |
|
|
I2C-bus controlled TV Input Processor |
TDA 9321H |
|
|
Table 12 Y-delay adjustment; note 1
YD0 to YD3 |
Y-DELAY |
|
|
YD3 |
YD3 160 ns + |
|
|
YD2 |
YD2 160 ns + |
|
|
YD1 |
YD1 80 ns + |
|
|
YD0 |
YD0 40 ns |
|
|
Note
1.For an equal delay of the luminance and chrominance signal the delay must be set at a value of 280 ns (YD3...YD0 = 1011). This is only valid for a CVBS signal without group delay distortions.
Table 13 Forced field frequency
FORF |
FORS |
FIELD FREQUENCY |
|
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|
0 |
0 |
auto (60 Hz when line not |
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|
synchronized) |
|
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|
0 |
1 |
forced 60 Hz; note 1 |
|
|
|
1 |
0 |
keep last detected field frequency |
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|
1 |
1 |
auto (50 Hz when line not |
|
|
synchronized) |
|
|
|
Note
1.When switched to this mode the divider will directly switch to forced 60 Hz only.
Table 14 Phase 1 (ϕ1) time constant, see also table 55
FOA |
FOB |
MODE |
|
|
|
0 |
0 |
normal |
|
|
|
0 |
1 |
slow |
|
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|
1 |
0 |
slow/fast |
|
|
|
1 |
1 |
fast |
|
|
|
Table 15 Video ident mode
VIM |
MODE |
|
|
0 |
ident coupled to internal CVBS (pin 14) |
|
|
1 |
ident coupled to selected CVBS |
|
|
Table 16 Synchronization mode
POC |
MODE |
0active
1not active
Table 17 Video ident mode
VID |
VIDEO IDENT MODE |
0ϕ1 loop switched on and off
1not active
Table 18 Blanked sync on Yout
BSY |
CONDITION |
|
|
0 |
unblanked sync, note1 |
|
|
1 |
blanked sync |
|
|
Note
1. Except for PALplus with black set-up.
Table 19 Condition of horizontal output
HO |
CONDITION |
|
|
0 |
clamp pulse available at HOUT |
1 |
HA pulse available at HOUT |
Table 20 Enable “Macrovision/subtitle” gating
EMG |
MODE |
0disable gating
1enable gating
Table 21 Vertical divider mode
NCIN |
VERTICAL DIVIDER MODE |
|
|
0 |
normal operation |
|
|
1 |
switched to search window |
|
|
June 30, 1998 |
14 |