Objective specification
File under Integrated Circuits, IC02
2000 Nov 22
Philips SemiconductorsObjective specification
Integrated multistandard comb filterTDA9181
FEATURES
• One-chip multistandard adaptive comb filter
• Cross luminance reduction
• Cross colour reduction
• No chroma trap, therefore sharper vertical luminance
transients
• Analog discrete-time signal processing, therefore no
quantization noise
• Anti-aliasing and reconstruction filters are included
• Input switch selects between two Y/CVBS inputs
• Output switch selects between combed CVBS and an
external Y/C source
• fSC as well as 2 × fSC colour subcarrier signal may be
applied
• Alignment free
• Few external components
• Low power.
QUICK REFERENCE DATA
GENERAL DESCRIPTION
The TDA9181is a an adaptive PAL/NTSC comb filter with
two internal delay lines, filters, clock control and input
clamps. Video standards PAL B, G, H, D, I, M and N and
NTSC M are supported.
Two CVBS input signals can be selected by means of an
input switch.
The selected CVBS input signal is filtered to obtain
a combed luminance output signal and a combed
chrominance output signal. Switched capacitor circuit
techniques are used, requiring an internal clock, locked on
to the colour subcarrier frequency.
Thecoloursubcarrierfrequencyaswellastwicethecolour
subcarrier frequency may be applied to the IC.
In addition to the comb filter the circuit contains an output
switch so that a selection can be made between the
combed CVBS signal and an external Y/C signal.
The IC is available in a DIP16 and SO16 package.
The supply voltage is 5 V.
SYMBOLPARAMETERMIN.TYP.MAX.UNIT
V
CCA
I
CCA
V
DDD
I
DDD
V
i(Y/CVBS)(p-p)
V
i(CIN)(p-p)
V
i(FSC)(p-p)
V
o(Y/CVBS)(p-p)
V
o(CIN)(p-p)
analog supply voltage4.55.05.5V
analog supply current−25−mA
digital supply voltage4.55.05.5V
digital supply current−10−mA
luminance or CVBS input signal voltage (peak-to-peak value)0.71.01.4V
chrominance input signal voltage (peak-to-peak value)−0.71.0V
colour subcarrier input signal voltage (peak-to-peak value)100200400mV
luminance or CVBS output signal voltage (peak-to-peak value)0.61.01.54V
chrominance output signal voltage (peak-to-peak value)−0.71.1V
ORDERING INFORMATION
TYPE
NUMBER
NAMEDESCRIPTIONVERSION
PACKAGE
TDA9181PDIP16plastic dual in-line package; 16 leads (300 mil); long bodySOT38-4
TDA9181TSO16plastic small outline package; 16 leads; body width 7.5 mmSOT162-1
2000 Nov 222
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2000 Nov 223
BLOCK DIAGRAM
Philips SemiconductorsObjective specification
Integrated multistandard comb filterTDA9181
handbook, full pagewidth
INPSEL
Y/CVBS
1
Y/CVBS
2
C
IN
SC
2
12
3
1
7
CLAMP
CLAMP
SANDCASTLE
DETECTOR
TDA9181
FILTER
TUNING
(LPFs)
LPF
9
FSC FSCSEL
V
2H/4H
DELAY
CLOCK GENERATOR
8
V
CCA
6
ADAPTIVE
4 × f
sc
11
SYS110SYS2
DDD
5
COMB
FILTER
LPF
LPF
13
AGND4DGND
15
OUTSEL
14
Y/CVBS
OUT
16
C
OUT
MGT518
Fig.1 Block diagram.
Philips SemiconductorsObjective specification
Integrated multistandard comb filterTDA9181
PINNING
SYMBOLPINDESCRIPTION
C
IN
INPSEL2input switch select input
Y/CVBS
2
DGND4digital ground
V
DDD
V
CCA
SC7sandcastle signal input
FSCSEL8colour subcarrier select input
FSC9colour subcarrier input signal
SYS210standard select 2 input
SYS111standard select 1 input
Y/CVBS
1
AGND13analog ground (signal reference)
Y/CVBS
OUT
OUTSEL15output switch select input
C
OUT
1chrominance signal input
3luminance or CVBS signal 2 input
5digital supply voltage
6analog supply voltage
12luminance or CVBS signal 1 input
14luminance or CVBS signal output
16chrominance signal output
handbook, halfpage
C
INPSEL
Y/CVBS
DGND
V
DDD
V
CCA
FSCSEL
SC
IN
2
1
2
3
4
TDA9181P
5
6
7
8
MGT519
16
15
14
13
12
11
10
9
C
OUT
OUTSEL
Y/CVBS
AGND
Y/CVBS
SYS1
SYS2
FSC
OUT
1
Fig.2 Pin configuration (DIP16).
2000 Nov 224
handbook, halfpage
Y/CVBS
C
INPSEL
DGND
V
DDD
V
CCA
SC
FSCSEL
1
IN
2
3
2
4
TDA9181T
5
6
7
8
MGT520
16
15
14
13
12
11
10
9
C
OUT
OUTSEL
Y/CVBS
AGND
Y/CVBS
SYS1
SYS2
FSC
Fig.3 Pin configuration (SO16).
OUT
1
Philips SemiconductorsObjective specification
Integrated multistandard comb filterTDA9181
FUNCTIONAL DESCRIPTION
Input configuration
The Y/CVBS1and Y/CVBS2input signals are clamped by
means of an internally generated clamp pulse which is
derived from the sandcastle input signal (pin SC). If no
sandcastlesignalisavailable,aclamppulsesignalmaybe
applied to pin SC. External clamp capacitors are needed.
The buffered and clamped Y/CVBS1and Y/CVBS2signals
arethenappliedtotheinputswitch.Theinputswitchselect
signal (INPSEL) determines whether Y/CVBS1 or
Y/CVBS2ispassedthroughtotheanti-aliaslow-passfilter.
This 3rd-order low-pass filter is optimized for best
performance with respect to step response and clock
suppression. The filtered signal is sampled at a clock
frequency of four times the colour subcarrier frequency
(fSC).
A colour subcarrier frequency signal is applied to pin FSC.
The colour subcarrier select input signal (FSCSEL)
indicates whether the colour subcarrier frequency (fSC)or
twice the colour subcarrier frequency (2 × fSC) is being
applied at the FSC input. An external coupling capacitor is
needed for the colour subcarrier input signal.
Comb filter
The sampled CVBS signal is applied to two delay lines.
Depending on the applied standard, one delay line delays
the signal over 1 or 2H for NTSC and PAL respectively
(1H = oneline-time).ThestandardselectinputsSYS1and
SYS2 indicate which standard, PAL B, G, H, D, I, M, N or
NTSC M, is being applied.
Output configuration
The luminance output switch selects between the
reconstructed combed luminance signal and one of the
bufferedandclampedinputsignals,Y/CVBS1orY/CVBS2.
The chrominance output switch selects between the
reconstructed combed chrominance signal and the
chrominance input signal (CIN). An external coupling
capacitor is needed for CIN. The selected signals are
applied to the outputs Y/CVBS
OUT
and C
respectively
OUT
via a buffer stage. The output switch signal (OUTSEL)
determines whether the output switches selectthe internal
combed signals or the external Y/C signals.
Clock generation and filter tuning
The clock generator is driven by a Phase-Locked Loop
(PLL)circuitwhichgeneratesareferencefrequencyoffour
times the colour subcarrier frequency. This PLL circuit is
phase-locked to the colour subcarrier input signal (FSC).
Several internal clock signals are derived from the 4 × f
SC
reference.
The filter tuning ensures the automatic alignment of the
anti-alias and the reconstruction low-pass filters. A 4 × f
SC
clock signal is used as a reference for the alignment. The
tuning takes place each line during the line blanking and is
initiated by means of an internally generated signal which
is derived from the sandcastle input signal.
If the output switches select external Y/C signals the
oscillator of the PLL circuit is stopped regardless of the
FSCinputandnointernalclocksignalsaregenerated.The
filter tuning is also stopped.
The direct and delayed signals are applied to an adaptive
comb filter. The adaptive comb filter performs band-pass
filtering around the colour subcarrier frequency and
compares the contents of adjacent lines. In this way the
combing of signals with different information is prevented
and artifacts such as hanging dots are avoided.
Boththecombedchrominanceandthecombedluminance
signalsare passed through a reconstruction low-pass filter
to obtain continuous-time signals. These low-pass filters
are3rd-order, optimized for best performance with respect
to step response and clock suppression. The
reconstructed signals are applied to the output switches.
2000 Nov 225
Philips SemiconductorsObjective specification
Integrated multistandard comb filterTDA9181
Mode definitions
Table 1 General mode definitions; note 1
PIN OUTSELMODE
LOWCOMB
HIGHYC
Note
1. If the OUTSEL pin is left open-circuit, the pin is pulled
LOW by means of an internal pull-down resistor to
analog ground (AGND). Thus the COMB mode can
also be selected by not connecting the OUTSEL pin.
Table 2 Y/CVBS
MODEY/CVBS
output signal definitions
OUT
OUT
OUTPUT SIGNAL
COMBcomb filtered luminance signal
YCY/CVBS
Table 3 C
output signal definitions
OUT
MODEC
or Y/CVBS2 signal
1
OUTPUT SIGNAL
OUT
COMBcomb filtered chrominance
signal
YCC
signal
IN
Table 4 Input switch mode definitions; note 1
PIN INPSELINPUT SWITCH MODE
LOWY/CVBS
HIGHY/CVBS
input selected
1
input selected
2
Table 5 FSC mode definitions; note 1
PIN FSCSELFSC INPUT SIGNAL FREQUENCY
LOWf
HIGH2 × f
SC
SC
Note
1. If the FSCSEL pin is left open-circuit, the pin is pulled
LOW by means of an internal pull-down resistor to
analog ground (AGND). Thus the f
mode can also
SC
be selected by not connecting the FSCSEL pin.
Table 6 Video standard mode definitions; note 1
PIN SYS1PIN SYS2
VIDEO
STANDARD
LOWLOWPAL M
LOWHIGHPAL B, G, H, D or I
HIGHLOWNTSC M
HIGHHIGHPAL N
Note
1. If the SYS1 and SYS2 pins are left open-circuit, the
SYS1 pin is pulled HIGH by means of an internal
pull-up resistor to analog supply (V
) and the SYS2
CCA
pin is pulled LOW by means of an internal pull-down
resistor to analog ground (AGND). Thus the NTSC M
videostandard can also be selected bynot connecting
pins SYS1 and SYS2.
Note
1. If the INPSEL pin is left open-circuit, the pin is pulled
LOW by means of an internal pull-down resistor to
analog ground (AGND). Thus the Y/CVBS
input can
1
also be selected by not connecting the INPSEL pin.
2000 Nov 226
Philips SemiconductorsObjective specification
Integrated multistandard comb filterTDA9181
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOLPARAMETERCONDITIONSMIN.MAX.UNIT
V
DDD
V
CCA
V
i(prot)(th)
T
stg
T
amb
T
sol
T
j
V
es
Notes
1. All pins are protected against ESD by means of internal clamping diodes.
2. Human Body Model (HBM): R = 1.5 kΩ; C = 100 pF.
3. Pin 5 (V
4. Machine Model (MM): R = 0 Ω; C = 200 pF.
5. Pin 5 (V
digital supply voltage−5.5V
analog supply voltage−5.5V
input voltage protection threshold−0.3VDD+ 0.3V
storage temperature−25+150°C
ambient temperature−25+70°C
soldering temperaturefor 5 s−260°C
junction temperature−150°C
electrostatic handling voltageHBM; all pins, except
−3000+3000V
pins 5 and 6; notes 1, 2 and 3
MM; all pins, except
−300+300V
pins 5 and 6; notes 1, 4 and 5
) and pin 6 (V
DDD
) and pin 6 (V
DDD
): HBM: −1500V<Ves< +1500 V.
CCA
): MM: −150V<Ves< +150 V.
CCA
THERMAL CHARACTERISTICS
SYMBOLPARAMETERCONDITIONSVALUEUNIT
R
th(j-a)
thermal resistance from junction to ambientin free air
TDA9181P75K/W
TDA9181T95K/W
QUALITY SPECIFICATION
In accordance with
“SNW-FQ-611E”
.
Latch-up
At an ambient temperature of 70 °C all pins meet the following specification:
• I
• I
≥ 100 mA or ≥ 1.5 V
trigger
≤−100 mA or ≤−0.5 V
trigger
DD(max)
DD(max)
.
2000 Nov 227
Philips SemiconductorsObjective specification
Integrated multistandard comb filterTDA9181
CHARACTERISTICS
V
CCA=VDDD
C
= 0.7 V (p-p); input signal FSC = 200 mV (p-p) sine wave at fSC; input signal SC=5V (p-p) sandcastle signal; test
IN
signal: 100/0/75/0 EBU colour bar for PAL B, G, H, D,I and N, 100% white 75% amplitude FCC colour bar for NTSC M
and PAL M; source impedance for Y/CVBS
FSC = 75 Ω, coupled with 100 nF; load impedance for CVBS/Y
voltages are related to analog ground (pin AGND); unless otherwise specified.
SYMBOLPARAMETERCONDITIONSMIN.TYP.MAX.UNIT
Supplies
V
CCA
I
CCA
V
DDD
I
DDD
Ppower dissipation−175−mW
Luminance or CVBS input 1 and input 2; pins Y/CVBS
V
i(Y/CVBS)(p-p)
t
clamp(Y/CVBS)
I
i(Y/CVBS)
Chrominance input; pin C
V
i(CIN)(p-p)
R
i(CIN)
Colour subcarrier input; pin FSC
V
i(FSC)(p-p)
Dduty cyclesquare wave405060%
R
i(FSC)
Sandcastle input; pin SC
V
i(SC)
t
W
t
W(rep)
R
i(SC)
C
i(SC)
Input switch select input; pin INPSEL
V
IL
V
IH
R
i(INPSEL)
C
i(INPSEL)
=5V; T
=25°C; input signal Y/CVBS1= 1 V (p-p); input signal Y/CVBS2= 1 V (p-p); input signal
amb
and Y/CVBS2=75Ω, coupled with 10 nF; source impedance for CIN and
1
OUT
and C
= 15 pF to analog ground (pin AGND); all
OUT
analog supply voltage4.55.05.5V
analog supply current−25−mA
digital supply voltage4.55.05.5V
digital supply current−10−mA
and Y/CVBS
luminance or CVBS input
1
including sync0.71.01.4V
2
voltage (peak-to-peak value)
clamp time constant−20−lines
input currentduring clamping−100+10µA
during active video−100+10nA
IN
chrominance input voltage
−0.71.0V
(peak-to-peak value)
input resistance30−−kΩ
subcarrier input voltage
100200400mV
(peak-to-peak value)
input resistance30−−kΩ
sandcastle input voltageno clamping−−3.3V
clamping3.7−−V
pulse widthclamping; note 12.6−−µs
pulse rising edge positionwith respect to end of