Philips tda9144 DATASHEETS

INTEGRATED CIRCUITS
DATA SH EET
TDA9144
2
I
Preliminary specification File under Integrated Circuits, IC02
1996 Jan 17
Philips Semiconductors Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor with PALplus helper demodulator
FEATURES
Multi-standard colour decoder and sync processor for PAL, NTSC and SECAM
PALplus helper demodulator
PALplus helper blanking and EDTV-2 blanking
I2C-bus controlled
I2C-bus addresses hardware selectable
Pin compatible with TDA9141
Alignment free
Few external components
Designed for use with baseband delay lines
Integrated video filters
Adjustable luminance delay
2
Noise detector with I
Norm/no_norm detector with I2C-bus read-out
CVBS or Y/C input, with automatic detection possibility
CVBS output provided I2C-bus address 8A is used
Vertical divider system
Two-level sandcastle signal
VA synchronization pulse (3-state)
HA synchronization pulse or clamping pulse CLP
input/output
Line-locked clock output (6.75 MHz or 6.875 MHz) or stand-alone I2C-bus output port
Stand-alone I2C-bus input/output port
Colour matrix and fast YUV switch
Comb filter enable input/output with subcarrier
frequency
Internal bypass mode of external delay line for PALplus and NTSC applications
Low power standby mode with 3-state YUV outputs
Fast blanking detector with I2C-bus read-out
Blanked or unblanked sync on Y
internal MACROVISION gating for the horizontal PLL
enabled by bus bit EMG.
C-bus read-out
out
by I2C-bus bit BSY
GENERAL DESCRIPTION
The TDA9144 is an I PAL/NTSC/SECAM decoder/sync processor with helper demodulator for PALplus signals and blanking facilities for PALplus and EDTV-2 signals. The TDA9144 has been designed for use with baseband chrominance delay lines, and has a combined subcarrier frequency/comb filter enable signal for communication with a PAL/NTSC comb filter.
The IC can process both CVBS input signals and Y/C input signals. The input signal is available on an output pin, in the event of a Y/C signal, it is added into a CVBS signal.
The sync processor provides a two-level sandcastle, a horizontal pulse (CLP or HA pulse, bus selectable) and a vertical (VA) pulse. When the HA pulse is selected, a line-locked clock (LLC) signal is available at the output port pin (6.75 MHz or 6.875 MHz).
A fast switch can select either the internal Y signal with the UV input signals, or YUV signals made of the RGB input signals. The RGB input signals can be clamped with either the internal or an external clamping signal.
Two pins with an input/output port and an output port of the
2
C-bus are available.
I The I2C-bus address of the TDA9144 is hardware
programmable. The TDA9144 is pin compatible with the TDA9141
(multistandard decoder/sync processor).
2
C-bus controlled, alignment-free
TDA9144
ORDERING INFORMATION
TYPE
NUMBER
TDA9144 SDIP32 plastic shrink dual in-line package; 32 leads (400 mil) SOT232-1
1996 Jan 17 2
NAME DESCRIPTION VERSION
PACKAGE
Philips Semiconductors Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM
TDA9144
decoder/sync processor with PALplus helper demodulator
QUICK REFERENCE DATA
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
CC
I
CC
V
CVBS(p-p)
V
Y(p-p)
V
C(p-p)
V
Y(out)
V
Y(out)
V
Y(out)(p-p)
V
U(out)(p-p)
V
V(out)(p-p)
V
SC(bl)
V
SC(clamp)
V
VA
V
HA
V
LLC(p-p)
V
R,G,B(p-p)
V
clamp(I/O)
V
sub(p-p)
V
OPORT
positive supply voltage 7.2 8.0 8.8 V supply current 50 60 70 mA CVBS input voltage (peak-to-peak value) top sync-white 1.0 1.43 V luminance input voltage
top sync-white 1.0 1.43 V
(peak-to-peak value) chrominance burst input voltage
0.3 0.6 V
(peak-to-peak value) luminance black-white output voltage 1.0 V luminance PALplus output voltage black-white 0.8 V maximum luminance helper signal output
686 mV
voltage (peak-to-peak value) U output voltage (peak-to-peak value) standard colour bar 1.33 V V output voltage (peak-to-peak value) standard colour bar 1.05 V sandcastle blanking voltage level 2.2 2.5 2.8 V sandcastle clamping voltage level 4.2 4.5 4.8 V VA output voltage 4.0 5.0 5.5 V HA output voltage 4.0 5.0 5.5 V LLC output voltage amplitude
250 500 mV
(peak-to-peak value) RGB input voltage (peak-to-peak value) 0 to 100% saturation 0.7 1.0 V clamping pulse input/output voltage 5.0 V subcarrier output voltage amplitude
150 200 300 mV
(peak-to-peak value) port output voltage 4.0 5.0 5.5 V
1996 Jan 17 3
Philips Semiconductors Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor with PALplus helper demodulator
BLOCK DIAGRAM
in
UinV
4
3
BPS
out
Y
out
V
out
U
18 14 13 12
21 20 19
YD3YD0YH1YH0
SWITCH
TB
MATRIX
DELAY
DELAY
ref
SEC
(RY)
(BY)
1322
2
2
SWITCH
SECAM
DEMOD
helper
DEMOD
PAL/NTSC
HUE
IDENT
SYSTEM
FSC
BUFFER
MBG897
Fscomb
TDA9144
handbook, full pagewidth
VA
SC CLP/HA R G B F
HPLL
CC
V
SDA SCL
17 11
VA
HA
10
TIMING
GENERATOR
SYNC
VERTICAL
57 24
C-BUS
6
2
I
ECL
ECL
CLP
SEPARATOR
TRAP
PLL
HORIZONTAL
SYNC
SEPARATOR
LCA
FILTER
TUNING
SECAM
CLOCHE
Y CLAMP
PLL
CHROMA
CHROMA
BANDPASS
ACC
SWITCH
CHROMA
INA-INB
ECMB
Fig.1 Block diagram.
TDA9144
AGND CPLL XTAL XTAL2
ref
FILT
BIAS
92728 29 30 31 23
DGND
1996 Jan 17 4
22
15
ADDR (CVBS)
I/O PORT
16
O PORT/LLC
26
Y/CVBS
25
C
8
DEC
Philips Semiconductors Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor with PALplus helper demodulator
PINNING
SYMBOL PIN DESCRIPTION
(RY) 1 output signal for (RY)
(BY) 2 output signal for (BY)
U
in
V
in
SCL 5 serial clock input SDA 6 serial data input/output V
CC
DEC 8 digital supply decoupling DGND 9 digital ground SC 10 sandcastle output VA 11 vertical acquisition
Y
out
V
out
U
out
I/O PORT 15 input/output port O PORT/LLC 16 output port/line-locked clock
CLP/HA 17 clamping pulse/HA
F 18 fast switch select input B 19 BLUE input G 20 GREEN input R 21 RED input ADDR (CVBS) 22 I
Fscomb 23 comb filter status input/output HPLL 24 horizontal PLL filter C 25 chrominance input Y/CVBS 26 luminance/CVBS input AGND 27 analog ground FILT
ref
CPLL 29 colour PLL filter XTAL 30 reference crystal input XTAL2 31 second crystal input SEC
ref
3 chrominance U input 4 chrominance V input
7 positive supply voltage
synchronization pulse 12 luminance output 13 chrominance V output 14 chrominance U output
output
synchronization pulse
input/output
2
C-bus address input (CVBS
output)
28 filter reference decoupling
32 SECAM reference decoupling
handbook, halfpage
O PORT/LLC
(RY)
(BY)
U
in
V
in
SCL SDA V
CC
DEC
DGND
SC
10
VA
11
Y
12
out
V
13
out
U
14
out
I/O PORT
15 16
Fig.2 Pin configuration.
1 2 3 4 5 6 7 8 9
TDA9144
MBG896
TDA9144
SEC
32
ref
XTAL2
31
XTAL
30
CPLL
29
FILT
28
ref
AGND
27
Y/CVBS
26
C
25
HPLL
24
Fscomb
23
ADDR (CVBS)
22
R
21
G
20
B
19
F
18
CLP/HA
17
1996 Jan 17 5
Philips Semiconductors Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor with PALplus helper demodulator
FUNCTIONAL DESCRIPTION
The TDA9144 is an I2C-bus controlled, alignment-free PAL/NTSC/SECAM colour decoder/sync processor which has been designed for use with baseband chrominance delay lines. For PALplus signals, helper demodulation and blanking facilities are included; for EDTV-2 (60 Hz) signals only blanking facilities are included.
In the standard operating mode the I2C-bus address is 8A. If the address input is connected to the positive supply rail the address will change to 8E.
Input switch
CAUTION
The voltage on the chrominance pin must never exceed
5.5 V. If it does, the IC enters a test mode.
The TDA9144 has a two pin input for CVBS or Y/C signals which can be selected via the I also has a position in which it automatically detects whether a CVBS or Y/C signal is on the input. In this input selector position, standard identification first takes place on an added Y/CVBS and C input signal. After that, both chrominance signal input amplitudes are checked once and the input with the strongest chrominance burst signal is selected. The input switch status is read out by the I2C-bus via output bit YC. The auto input detect mode indicates YC = 1 for a VBS input signal (no chrominance component).
CVBS output
In the standard operating mode with I a CVBS output signal is available on the address pin, which represents either the CVBS input signal or the Y/C input signal, added into a CVBS signal.
RGB colour matrix
The voltage on the Uin pin must never exceed 5.5 V. If it does, the IC enters a test mode.
The TDA9144 has a colour matrix to convert RGB input signals into YUV signals. A fast switch, controlled by the signal on pin F and enabled by I fast switch), can select between these YUV signals and the YUV signals of the decoder. Mode FRGB = 1 (forced RGB) overrules EFS and forces the matrixed RGB inputs to the YUV outputs.
2
C-bus. The input selector
CAUTION
2
2
C-bus address 8A,
C-bus via EFS (enable
The Y signal is internally connected to the switch. The
(RY) and(BY) output signals of the decoder first have to be delayed in external baseband chrominance delay lines. The outputs of the delay lines must be connected to the UV input pins. If the RGB signals are not synchronous with the selected decoder input signal, clamping of the RGB input signals is possible by I2C-bus selection of ECL (external RGB clamp mode) and by feeding an external clamping signal to the CLP pin. Also in external RGB clamp mode the VA output will be in a high impedance OFF-state. The YUV outputs can be put in 3-state mode by bus bit LPS (low power standby mode).
Standard identification
The standards which the TDA9144 can decode depend upon the choice of external crystals. If a 4.4 MHz and a
3.6 MHz crystal are used then SECAM, PAL 4.4/3.6 and NTSC 4.4/3.6 can be decoded. If two 3.6 MHz crystals are used then only PAL 3.6 and NTSC 3.6 can be decoded.
Which 3.6 MHz standards can be decoded depends upon the exact frequencies of the 3.6 MHz crystals. In an application where not all standards are required only one crystal is sufficient; in this instance the crystal must be connected to the reference crystal input (pin 30). If a
4.4 MHz crystal is used it must always be connected to the reference crystal input. Both crystals are used to provide a reference for the filters and the horizontal PLL, however, only the reference crystal is used to provide a reference for the SECAM demodulator. To enable the calibrating circuits to be adjusted exactly, two bits from I 00 are used to indicate which crystals are connected to the IC.
The standard identification circuit is a digital circuit without external components. The search loop is illustrated in Fig.3. The decoder (via the I2C-bus) can be forced to decode either SECAM or PAL/NTSC (but not PAL or NTSC). Crystal selection can also be forced. Information concerning standard and which crystal is selected and whether the colour killer is ON or OFF is provided by the read out.
Using the forced-mode does not affect the search loop, it does however, prevent the decoder from reaching or staying in an unwanted state. The identification circuit skips impossible standards (e.g. SECAM when no
4.4 MHz crystal is fitted) and illegal standards (e.g. in forced mode). To reduce the risk of wrong identification PAL has priority over SECAM. Only line identification is used for SECAM. For a vertical frequency of 60 Hz SECAM can be blocked to prevent wrong identification by means of bus bit SAF.
TDA9144
2
C-bus subaddress
1996 Jan 17 6
Philips Semiconductors Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor with PALplus helper demodulator
handbook, full pagewidth
SECAM
c
c
PAL
KILLED
NTSC
SECAM
KILLED
NTSC
KILLED
c
c
c
PAL
KILLED
c
c
TDA9144
PAL
c
c
Reference crystal Second crystal
PAL
KILLED
Fig.3 Search loop of the identification circuit.
Integrated filters
All chrominance bandpass and notch filters, including the luminance delay line, are an integral part of the IC. The filters are gyrator-capacitor type filters. The resonant frequency of the filters is controlled by a circuit that uses the active crystal to tune the SECAM Cloche filter during the vertical flyback time. The remaining filters and the luminance delay line are matched to this filter. The filters can be switched to either 4.43 MHz, 4.29 MHz or
3.58 MHz. The switching is controlled by the standard identification circuit. The luminance notch used for SECAM has a lower Q-factor than the notch used for PAL/NTSC. The notches are provided with a little preshoot to obtain a symmetrical step response. In Y/C mode the chrominance notch filters are bypassed, to preserve full signal bandwidth. For a CVBS signal the chrominance notch filters can be bypassed by bus selection of bit TB (trap bypass).
c
c
NTSC
KILLED
NTSCPAL
MGE040 
The luminance to helper delay difference can be adjusted
2
C-bus, to achieve a correct fitting for the delay in the
by I PALplus helper demodulation signal path and the luminance path (not for helper only with trap). The delay of the colour difference signals (RY) and (BY) in the chrominance signal path and the external chrominance delay lines when used, can be fitted to the luminance signal delay control via I2C-bus in 40 ns steps.
The typical luminance delay can be calculated: delay 90 + SAKSBK {170 + 40(FRQTB)} + 160(YD3) +
160(YD2) + 80(YD1) + 40(YD0) [ns].
1996 Jan 17 7
Philips Semiconductors Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor with PALplus helper demodulator
Colour decoder
The PAL/NTSC demodulator employs an oscillator that can operate with either crystal (3.6 MHz or 4.4 MHz). If the I2C-bus indicates that only one crystal is connected it will always connect to the crystal on the reference crystal input (pin 30). The Hue signal which is adjustable by I2C-bus, is gated during the burst for NTSC signals.
The SECAM demodulator is an auto-calibrating PLL demodulator which has two references. The reference crystal, to force the PLL to the desired free-running frequency and the bandgap reference, to obtain the correct absolute value of the output signal. The VCO of the PLL is calibrated during each vertical blanking period, when the IC is in search mode or SECAM mode.
If the reference crystal is not 4.4 MHz the decoder will not produce the correct SECAM signals. Especially for PALplus and NTSC applications, an internal bypass mode of the external baseband delay line (for instance TDA4665) is added, controlled by bus bit BPS (bypass mode) and has a gain of 2. The bypass mode is not available for SECAM.
Comb filter interfacing
The frequency of the active crystal is fed to the Fscomb output, which can be connected to an external comb filter IC (e.g. SAA4961). When bus bit ECMB is LOW, the subcarrier frequency is suppressed and its DC value is LOW. With ECMB HIGH, the DC value is HIGH with the
2
subcarrier frequency present, and I
C-bus output bit YC and the input switch are always forced in the Y/C mode, unless an external current sink (e.g. from the comb filter) prevents this, as pin Fscomb also acts as input pin. In this event the subcarrier frequency is still present on the same DC HIGH level
PALplus helper demodulation PALplus has been introduced to come to an evolutionary
introduction of wide screen transmissions with backward
compatibility with PAL 4 : 3 TV sets. A PALplus signal has the format of a standard analog PAL composite signal containing 430 PAL picture lines in letter box format (lines 60 to 274 and 372 to 586), together with helper information contained in the black bands above and below the visible letter box area (lines 24 to 59, 336 to 371, 275 to 310, and 587 to 622).
A viewer with a 4 : 3 TV set will see a letter box picture: black bars of
1
⁄8 picture height at the top as well as at the
bottom with a 16 : 9 picture in between (see left-hand side picture of Fig.4).
A wide screen viewer without PALplus decoder will only see the centre picture of Fig.4, or the right hand side picture when a zoom option is available, however with only 430 lines of vertical resolution.
When a wide screen viewer has a PALplus decoder, it expands the letter box format to a full-size wide screen picture with a vertical resolution of 574 lines. The decoder uses the helper lines information, hidden within the black bars. See the right-hand side picture of Fig.4.
Furthermore a PALplus signal will deliver full luminance bandwidth by an Y/C separation technique called ‘Motion Adaptive Colour Plus’ (MACP). Using this technique, the signal becomes free from cross colour and cross luminance. This algorithm requires MACP pre-processing in the PALplus encoder at the studio output.
The PALplus parts which the TDA9144 processes are in short:
Helper demodulation and multiplexing helper with letter box luminance signal
Chrominance trap bypassing if necessary
Creation of reference line 22 (see Fig.5)
Creation of black set-up and helper set-up
Correct blanking and timing reference for the necessary
post processing ICs.
TDA9144
dbook, full pagewidth
1996 Jan 17 8
helper lines
430
picture
lines
helper lines
Fig.4 Possible PALplus picture displays.
574
picture
lines
MBG903
Philips Semiconductors Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor with PALplus helper demodulator
In case of a PALplus input signal, the standard identification system of the TDA9144 only determines PAL and needs additional I2C-bus information for PALplus, via bus bits MACP, HD, HOB and HBC.
Bus bit MACP determines whether the 4.43 chrominance signal component of the CVBS input signal should be suppressed by a 4.43 trap or not. For MACP = 1 the chrominance suppression takes place outside the TDA9144.
The HD bit (helper demodulation) enables PALplus helper demodulation on the U phase (i.e. the BY demodulation axis). As there is only a 4.43 notch for the demodulated helper, an external notch filter is necessary to suppress the
8.86 MHz demodulation product and resolve the baseband helper signal. The demodulated helper luminance signal is always led to a notch filter (4.43 MHz, no bypass here), then multiplexed with the regular 430 letter box lines luminance signal and led to the output Y The black level of the luminance signal is internally clamped with a large time constant to the black level generated by the helper demodulator.
Also bus bits HD and MACP determine the presence of a black set-up voltage (with luminance scaling of a factor
0.8) and a helper set-up voltage for the demodulated helper signal on the output signal Y voltages are necessary for PALplus signal post processing outside the TDA9144. The set-up voltages are also multiplexed into a reference line 22, combined with the demodulated helper reference of line 23 and luminance reference of line 623, both present in every PALplus signal for correct PALplus reference post processing (see Fig.5).
Additional helper blanking bits (HOB, HBC) determine whether the helper signal has to be blanked or blanked conditionally depending on the signal-to-noise ratio bit SNR. Helper blanking can only take place on a norm sync signal, indicated by output bit NRM = 1. Table 1 is valid in 50 Hz or 60 Hz mode.
Table 1 Helper blanking modes
. These set-up
out
230 to 312 and 493 to 49 activated.
The TDA9144 can handle PALplus signals in either CVBS or Y/C format. In case of a Y/C signal, the modulated helper must be available on the chrominance input pin (C). The use of the 4.43 trap will not be necessary, as the chrominance and luminance components of a Y/C signal are already separated, so the 4.43 trap for the letter box luminance is bypassed (not for the demodulated helper signal). During helper demodulation, the internal chroma bandpass filter is bypassed.
For PALplus the I2C-bus Hue bits HU0 to HU5 are used to adjust for a correct helper demodulator phase. This has no effect on the RY and BY demodulator phase for PAL.
Table 2 gives an overview of the possible PALplus modes and their effects in the TDA9144. The table is only valid for a 50 Hz system. In 60 Hz system mode the columns for
.
out
line 22, 23b and 623a do not exist, and using the MACP and HD bits has no effect on the 60 Hz signal.
Mode 1 normal PAL
Mode 2 PAL with MACP processing
Mode 3 full PALplus
Mode 4 PALplus without MACP processing (helper
only)
Mode 5 near_norm or no_norm sync condition
Mode 6 norm sync condition with fast blanking active
Mode 7 system ident not identified as PAL.
The indications a and b for the lines 22, 23 and 623 respectively stand for the first half and the second half of a line.
The signalling bits in line 23 (see Fig.5) are processed in the same manner as letter box luminance lines in the TDA9144. Signalling bit decoding and PALplus identification is done externally with I2C-bus as communication link to the TDA9144 for bus bits MACP, HD, HOB, and HBC.
TDA9144
(1)
when helper blanking is
HOB HBC SNR
0 X X OFF 10XON 110OFF 111ON
For EDTV-2 (system M, 60 Hz, 525 lines) outside the letter box area, blanking is possible and takes place on lines
1996 Jan 17 9
HELPER
BLANKING
(1) For system M the line numbers start with the first equalizing
pulse in field 1, but the internal line counter starts counting at the first vertical sync pulse in field 1. This line number notation is used here and in Fig.9.
Philips Semiconductors Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor with PALplus helper demodulator
white level reference
PALplus CVBS in
black
helper reference
level
reference
burst U phase
10.83 µs
1.00
(V)
0.30
1.00
(V)
0.45
0.30
0.15
0
10.5 µs
0
EBU colour bar
max. modulated helper line
input
signals
1.00 (V)
0.30
0
1.00
0.80 (V)
0.45
0.30
0.15
0
handbook, full pagewidth
line 623
20 µs
10.5 µs
line 23
10 µs
32 µs
PALplus signalling bits
41 µs
51 µs
TDA9144
52 µs
output
signals
1.00 (V)
0.60
0.20
0
1.00 (V)
0.77
0.60
0.20
0
1.00 (V)
0.60
0.20
0
line 623
Y black
0.4 µs black
(clamp level)
line 23
0.4 µs PALplus signalling bits
line 22 reference line
212 LLC pulses
11.2 µs
black set-up
0.15 µs
white level reference
Y
(pin 12)
out
black set-up
black level offset
helper set-up
demodulated
helper reference
mid-grey offset = A B
helper set-up
(mid-grey)
151 LLC pulses
52 µs
(1)
22 µs30.8 µs
B
0.65 µs
1.00 (V)
0.60
0.20
1.00 (V)
0.60
0.20
(3)
A
(1) See Y output parameter Vos in Section “Characteristics”
800
mV
0
0
delay CLP to set up
(2)
686 mV
0.15 µs
(4)
demodulated helper
area limits
52 µs
baseband helper line with
black and helper set-up
EBU colour bar
with black set-up
0.65 µs
MBG904
(2) See demodulated helper parameter td in Section “Characteristics” (3) See demodulated helper parameter Vos in Section “Characteristics” (4) See CLP output/HA output parameter td in Section “Characteristics”
Figures drawn when using subaddress 8A and an Y LLC frequency equals 6.875 MHz; 440 LLC pulses per horizontal line. Demodulated helper shown when using an external 8.8 notch filter.
1996 Jan 17 10
of 440 ns.
delay
Fig.5 PALplus CVBS input and Y output signals.
Philips Semiconductors Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor with PALplus helper demodulator
(9)
black black black
(4)
luma
(5)
set-up helper
(4)
(4)
set-up helper luma
(4)
set-up helper luma
black black black
(4)
black black black
(4)
623a
LINE
23b
LINE
22
LINE
LINES
HELPER
(2)
(mV)
HELPER
SET-UP
(1)
TDA9144
BLACK
SET-UP
AMPL
LUMA
DELAY
COMB
4.43
(mV)
(V)
(b-w)
LINE
ECMB BPS 1 0 0 luma
ENABLE
(3)
TRAP
(8)
disabled bypass 0.8 200 400 helper
(6)
(7)
bypass 0.8 200 400 helper
ECMB BPS 1 0 0 luma black black luma
disabled
(3)
(3)
ECMB BPS 1 0 0 luma
(3)
ECMB BPS 1 0 0 luma
100101TB
Table 2 PALplus modes for 50 Hz
MODE MACP HD NRM FBA PAL
1996 Jan 17 11
2 1 0 1 0 1 bypass disabled BPS 0.8 200 0 luma
401101TB
3 1 1 1 0 1 bypass
5XX0XXTB
6XX11XTB
7XX1X0TB
Notes
1. When activated, the black set-up is added to the full frame.
2. When activated, the helper set-up is added to line 22b, 23b, 24 to 59, 275 to 310, 336 to 371, 587 to 622.
3. The 4.43 MHz trap is active in CVBS input mode and TB = 0, otherwise the trap is bypassed.
4. When helper blanking is active (see Table 1) lines 24 to 59, 275 to 310, 336 to 371, 587 to 622 are blanked.
5. Demodulated helper with 400 mV set-up and 4.43 MHz trap active.
6. The 4.43 MHz trap is bypassed during the letter box lines, but activated during helper lines and line 23b to reduce 4.43 MHz rest carrier.
7. The 4.43 MHz trap is active during helper lines and line 23b, during the letter box lines the trap is active when TB = 0.
8. In principle the comb filter should be enabled during letter box lines, when ECMB = 1. It depends on the comb filter if this will be implemented.
9. Line 623a contains luminance in NO_NORM, line 623a is black in a NEAR_NORM sync condition.
Philips Semiconductors Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor with PALplus helper demodulator
Fast blanking detector
For PALplus it is necessary to switch-off PALplus as soon as an external RGB input signal is mixed into a PALplus signal via a switching signal on the fast blanking input (F). To detect the presence of a fast blanking signal, a circuit is added which forces the MACP and HD bit to zero if in more than one line per field a blanking pulse is detected. More than one line per field is chosen to prevent switching-off at every spike detected on the fast blanking input. The detector output FBA (fast blanking active) can be read-out
2
by the I
C-bus.
Blanked/unblanked sync
2
By means of the I signal Y
will be presented with or without its composite
out
C-bus bit BSY (blanked sync), output
sync part. At BSY = 0 the composite sync is present on Y
. When activated, helper blanking takes place only
out
during helper lines scan. At BSY = 1 the black level is filled in during the line blanking interval and vertical blanking interval. When activated, the helper blanking extends the vertical blanking. For PALplus modes with black set-up no composite sync will be present on Y
, independent of the
out
BSY condition.
Sync processor (ϕ
loop)
1
The main part of the sync circuit is an oscillator running at 440 × f
(6.875 MHz), provided that I2C-bus address 8A is
H
used or 432 × fH (6.75 MHz) for 8E. Its frequency is divided by 440 or 432 to lock the ϕ1 loop to the incoming signal.
The time-constant of the loop can be selected by the I2C-bus (fast, auto or slow). In the fast mode the fast time-constant is chosen independent of signal conditions. In auto mode the medium time-constant is present with a fast time constant during the vertical retrace period ('field boost'). If the noise detector indicates a noisy video signal the time-constant switches to slow with a smaller field boost, which is also the time-constant for the slow mode. In case of a slow time constant sync gating takes place in a 6 µs window around the separated sync pulse. In case of no sync lock, both the auto and the slow mode have a medium time constant, to ensure reliable catching.
When a power-on-reset pulse is detected the frequency of the oscillator is switched to a frequency of about 10 MHz (23 kHz horizontal frequency) to protect the horizontal output transistor. The oscillator frequency is calibrated to
6.875 MHz or 6.75 MHz after receiving data on subaddress 01 for the first time after power-on-reset detection.
To ensure that this procedure does not fail it is absolutely necessary to send subaddress 00 before subaddress 01. Subaddress 00 contains the crystal indication bits and when subaddress 01 is received the line oscillator calibration will be initiated (for the start-up procedure after power-on-reset detection, see the I calibration is terminated when the oscillator frequency reaches 6.875 MHz or 6.75 MHz.
The ϕ1 loop can be opened using the I2C-bus. This is to facilitate On Screen Display (OSD) information. If there is no input signal or a very noisy input signal, the ϕ1 loop can be opened to provide a stable line frequency, and thus a stable picture.
The sync part also delivers a two-level sandcastle signal, which provides a combined horizontal and vertical blanking signal and a clamping pulse for the display section of the TV.
MACROVISION sync gating
A dedicated gating signal for the separated sync pulses, starting 11 lines after the detection of a vertical sync pulse until picture scan starts, can be used to improve the behaviour of the horizontal PLL with respect to the unwanted disturbances caused by the pseudo-sync pulses in video signals with MACROVISION anti-copy guard signals. This sync gating excludes the pseudo-sync pulses and can only take place in the auto and fast ϕ constant mode, provided I2C-bus bit SNR = 0 and I2C-bus
TDA9144
2
C-bus protocol). The
time
1
The noise content of the video signal is determined by a noise detector circuit. This circuit measures the noise at top sync during a 15 line period every field (65 lines after start VA pulse). When the noise level supersedes the detector threshold in two consecutive fields, noise is indicated and bus bit SNR is set.
The free-running frequency of the oscillator is determined by a digital control circuit that is locked to the active crystal.
1996 Jan 17 12
Philips Semiconductors Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor with PALplus helper demodulator
bit EMG = 1. I2C-bus bit EMG = 1 enables and EMG = 0 disables this sync gating in the horizontal PLL.
Vertical divider system
The vertical divider system has a fully integrated vertical sync separator. The divider can accommodate both 50 Hz and 60 Hz systems; it can either determine the field frequency automatically or it can be forced to the desired
2
system via the I
C-bus. A block diagram of the vertical
divider system is illustrated in Fig.6. The divider system operates at twice the horizontal
frequency. The line counter receives enable pulses at this frequency, thereby counting two pulses per line. A state diagram of the controller is shown in Fig.7. Because it is symmetrical only the right-hand part will be described.
handbook, halfpage
LINE COUNTER
When the controller returns to the COUNT state, the line counter will be reset half a line after the start of the vertical sync pulse of the video input signal. The NORM window normally looks within one line width and a sudden half line delay of the vertical sync pulse change can therefore be neglected, but for PALplus conditions every half line shift of the vertical sync pulse must be detected. In this case a half line window is used.
When the controller is in the NEAR_NORM state it will move to the COUNT state if it detects the vertical sync pulse within the NEAR_NORM window (i.e. 622 < LC < 628). If no vertical sync pulse is detected the controller will move back to the COUNT state when the line counter reaches LC = 628. The line counter will then be reset.
When the controller is in the NO_NORM state, it will move to the COUNT state when it detects a vertical sync pulse and reset the line counter. If a vertical sync pulse is not detected before LC = 722 (if the ϕ1 loop is locked, even in forced mode) it will move to the COUNT state and reset the line counter. If the ϕ1 loop is not locked the controller will return to the COUNT state when LC = 628.
TDA9144
CONTROLLER
NORM COUNTER
TIMING
GENERATOR
MGE043
Fig.6 Block diagram of the vertical divider system.
Depending on the previously found vertical frequency, the controller will be in one of the COUNT states. When the line counter has counted 488 pulses (i.e. 244 lines of the video input signal), the controller will move to the next state depending on the output of the norm counter. This can be either NORM, NEAR_NORM or NO_NORM, depending on the position of the vertical sync pulse in the previous fields. When the controller is in the NORM state it generates the vertical sync pulse (VSP) automatically and then, when the line counter is at LC = 626, moves to the WAIT state. In this condition it waits for the next pulse of the double line frequency signal, and then moves to the COUNT state of the current field frequency.
The forced mode option keeps the controller in either the left-hand side (60 Hz) or the right-hand side (50 Hz) of the state diagram.
Figure 8 illustrates the state diagram of the norm counter which is an up/down counter that increases its counter value by 1 if it finds a vertical sync pulse within the selected window. If not it decreases the counter value by 1 (or 2, see Fig.8). In the NEAR_NORM and NORM states the first correct vertical sync pulse after one or more incorrect vertical sync pulses is processed as an incorrect pulse. This procedure prevents the system from staying in the NEAR_NORM or NORM state if the vertical sync pulse is correct in the first field and incorrect in the second field.
In case of no sync lock (SLN = 1) the norm counter is reset to NO_NORM (wide search window), for fast vertical catching when switching between video sources. Fast switching between different channels however can still result in a continuous horizontal sync lock situation, when the channel is changed before the norm counter has reached the NORM state. To provide faster vertical catching in this case, measures have been taken to prevent the norm counter to count down to zero before reaching the NO_NORM state (see left-hand of Fig.8). Bus bit FWW (forced wide window) enables the norm counter to stay in the NO_NORM state if desired. The norm/no_norm status is read out by bus bit NRM.
1996 Jan 17 13
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