Philips TDA9109 Service Manual

TDA9109/N

LOW-COST DEFLECTIONPROCESSOR

FOR MULTISYNC MONITORS

HORIZONTAL

.

SELF-ADAPTATIVE

.

DUALPLLCONCEPT

.

150kHzMAXIMUM FREQUENCY

.

X-RAYPROTECTIONINPUT

.

I2C CONTROLS : H-POSITION, FREQUENCY
GENERATORFOR BURN-IN MODE

VERTICAL

.

VERTICALRAMP GENERATOR

.

50 TO165Hz AGC LOOP

.

GEOMETRYTRACKINGWITHVPOS& VAMP

.

I2C CONTROLS:
VAMP, VPOS, S-CORR, C-CORR

.

DC BREATHING COMPENSATION

2

C GEOMETRYCORRECTIONS

I

.

VERTICALPARABOLAGENERATOR
(Pincushion,Keystone)

.

HORIZONTALDYNAMICPHASE
(SidePin Balance& Parallelogram)

.

HORIZONTALAND VERTICALDYNAMIC FO­CUS (Horizontal Focus Amplitude, Horizontal
FocusSymmetry,VerticalFocus Amplitude)

GENERAL

.

SYNCPROCESSOR

.

12V SUPPLYVOLTAGE

.

8V REFERENCEVOLTAGE

.

HOR.& VERT. LOCK/UNLOCK OUTPUTS

.

READ/WRITEI2C INTERFACE

.

VERTICALMOIRE

.

B+REGULATOR

- INTERNAL PWM GENERATOR FOR B+
CURRENT MODE STEP-UP CONVERTER

- S WITCHABL E TO STEP-DOWN CON­VERTER

2

CADJUSTABLEB+REFERENCE VOLTAGE

-I

- OUTPUT PULSES SYNCHRONIZED ON
HORIZONTALFREQUENCY

- INTERNALMAX. CURRENT LIMITATION

.

COMPARED WITH THE TDA9109,
THE TDA9109/NHAS:

2

-NOI

- FIXED HORIZONTALDUTY CYCLE (48%)

- INCREASEDMAX.STORAGETIME OF THE

C FREE RUNNING FREQUENCY AD-

JUSTMENT

HORIZONTALSCANNING TRANSISTOR

DESCRIPTION

The TDA9109/N is a monolithic integrated circuit
assembledin32-pinshrinkdual in lineplasticpack­age.ThisIC controlsall thefunctionsrelatedtothe
horizontal and vertical deflection in multimode or
multi-frequencycomputerdisplaymonitors.

The internal sync processor, combined with the
very powerful geometrycorrection block makethe
TDA9109/N suitable for very high performance
monitors,using very few externalcomponents.

Thehorizontaljitter levelisverylow.Itisparticularly
well suited forhigh-end 15” and 17” monitors.

Combined with the ST7275Microcontroller family,
TDA9206 (Video preamplifier) and STV942x (On­Screen Display controller) the TDA9109/N allows

2

Cbus controlled computer display monitors

fullyI
to be built with a reduced number of external
components.

SHRINK32

(Plastic Package)

ORDER CODE : TDA9109/N

June 1998

1/32

TDA9109/N

PIN CONNECTIONS

H/HVIN

VSYNCIN

HLOCKOUT

PLL2C

C0
R0

PLL1F

HPOSITION

HFOCUSCAP

FOCUS-OUT

HGND

HFLY

HREF

COMP

REGIN

SENSE

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

5V
SDA
SCL
V

CC

BOUT
GND
HOUT
XRAY
EWOUT
VOUT
VCAP
V

REF

VAGCCAP
VGND
BREATH
B+GNDI

9109N-01.EPS

2/32

TDA9109/N

PIN CONNECTIONS

Pin Name Function

1 H/HVIN TTL compatible Horizontal sync Input (separate or composite)
2 VSYNCIN TTL compatible Vertical sync Input (for separated H&V)
3 HLOCKOUT First PLL Lock/Unlock Output (0V unlocked - 5V locked)
4 PLL2C Second PLL LoopFilter
5 C0 Horizontal Oscillator Capacitor
6 R0 Horizontal Oscillator Resistor
7 PLL1F First PLL Loop Filter
8 HPOSITION HorizontalPosition Filter (capacitor to be connected to HGND)

9 HFOCUSCAP Horizontal Dynamic Focus Oscillator Capacitor
10 FOCUSOUT Mixed Horizontal and Vertical Dynamic Focus Output
11 HGND Horizontal Section Ground
12 HFLY Horizontal Flyback Input (positivepolarity)
13 HREF Horizontal Section ReferenceVoltage (to be filtered)
14 COMP B+ Error Amplifier Output for frequency compensation and gain setting
15 REGIN Regulation Input of B+ control loop
16 I

SENSE

17 B+GND Ground (related toB+ reference adjustment)
18 BREATH DC Breathing Input Control (compensation of vertical amplitude against EHV variation)
19 VGND Vertical Section Ground
20 VAGCCAP Memory Capacitor for Automatic Gain Control Loop in Vertical Ramp Generator
21 V

REF

22 VCAP Vertical Sawtooth Generator Capacitor
23 VOUT Vertical Ramp Output(withfrequencyindependantamplitude and S or C Correctionsif any).

24 EWOUT Pin Cushion - E/W Correction Parabola Output
26 HOUT Horizontal Drive Output (internal transistor, open collector)
25 XRAY X-RAY protection input (with internal latch function)
27 GND General Ground (referenced to V
28 BOUT B+ PWMRegulator Output
29 V

CC

30 SCL I
31 SDA I
32 5V Supply Voltage (5V typ.)

Sensing ofexternal B+ switching transistor current, or switch for step-down converter

Vertical Section Reference Voltage (to be filtered)

It is mixed with vertical position voltage and vertical moiré.

)

CC

Supply Voltage (12V typ)

2

C Clock Input

2

C Data Input

9109N-01.TBL

3/32

TDA9109/N

QUICK REFERENCE DATA

Parameter Value Unit

Horizontal Frequency 15 to 150 kHz
Autosynch Frequency (for given R0 and C0) 1 to 4.5 f0
æ Horizontal Sync Polarity Input YES
Polarity Detection (on bothHorizontal and Vertical Sections) YES
TTL Composite Sync YES
Lock/Unlock Identification (on both Horizontal 1st PLL and Vertical Section) YES

2

C Control for H-Position

I
XRAY Protection YES

2

C Horizontal Duty Cycle 48 %

Fixed I

2

C Free Running Frequency Adjustment NO

I
Stand-by Function YES
Dual Polarity H-Drive Outputs NO
Supply Voltage Monitoring YES
PLL1 Inhibition Possibility NO
Blanking Outputs NO
Vertical Frequency 35 to 200 Hz
Vertical Autosync (for 150nF on Pin 22 and 470nF on Pin 20) 50 to 165 Hz
Vertical S-Correction YES
Vertical C-Correction YES
Vertical Amplitude Adjustment YES
DC Breathing Control on VerticalAmplitude YES
Vertical Position Adjustment YES
East/West (E/W) Parabola Output (also known as Pin Cushion Output) YES
E/W Correction Amplitude Adjustment YES
Keystone Adjustment YES
Internal Dynamic Horizontal Phase Control YES
Side Pin Balance Amplitude Adjustment YES
Parallelogram Adjustment YES
Tracking of Geometric Corrections with Vertical Amplitude and Position YES
Reference Voltage (both on Horizontal and Vertical) YES
Dynamic Focus (both Horizontal and Vertical) YES

2

C Horizontal Dynamic Focus Amplitude Adjustment YES

I

2

C Horizontal Dynamic Focus Symmetry Adjustment YES

I

2

C Vertical Dynamic Focus Amplitude Adjustment YES

I
Detection of Input Sync Type (biased from 5V alone) YES
Vertical Moiré Output YES

2

C Controlled V-Moiré Amplitude YES

I
Frequency Generator for Burn-in YES

2

C Read/Write 400 kHz

Fast I
B+ Regulation adjustable by I

2

C YES

10 %

±

9109N-02.TBL

4/32

BLOCKDIAGRAM

TDA9109/N

HOUT

PLL2C

HFLY

C0
R0

HLOCKOUT

4

5
67 26

3

HOUT

BUFFER

(48%)

H-DUTY

PHASE

SHIFTER

PHASE

COMPARATOR

VCO

2 bits

Forced

Frequency

28 B+OUT

14 COMP

B+

B+ Adjust

CC

XRAY

V

SAFETY

PROCESSOR

SENSE

BGND

I

17

16

15 REGIN

CONTROLLER

7 bits

2

X

Spin Bal

HFOCUSCAP

9

2

6 bits

X

VSYNC

2

X

2 x 5 bits

Amp & Symmetry

6 bits

Parallelogram

MOIRE

CANCEL

VERTICAL

5 BITS+ON/OFF

10 FOCUS

VAMPVDF

E/W

7 bits

TRACKING

GEOMETRY

VAMP

6 bits

2

X

7 bits

X

6 bits

Keyst.

VERTICAL

OSCILLATOR

RAMP GENERATOR

TDA9109/N

EWOUT

V

OUT

BREATH

18

7 bits

VPOS

V

AGCCAP

20

V

CAP

22 23

HPOSITION

PLL1F

LOCK/UNLOCK

IDENTIFICATION

6 bits 6 bits

S AND C

CORRECTION

8

COMPARATOR

H-PHASE(7 bits)

PHASE/FREQUENCY

SYNC

PROCESSOR

RESET

REF

V

131211

HREF

HGND

SELECT

SYNC INPUT

1

H/HVIN

(1 bit)

2

VSYNCIN

29

V

REF

V

21

25

CC

XRAY

REF

V

GENERATOR

192432

5V

VGND

C INTERFACE

2

I

30

31

SCL

SDA

27

GND

9109N-02.EPS

5/32

TDA9109/N

ABSOLUTE MAXIMUMRATINGS

Symbol Parameter Value Unit

V
V

V

VESD

T

T

THERMAL DATA

Symbol Parameter Value Unit

R

th (j-a)

SYNC PROCESSOR
OperatingConditions (V

Symbol Parameter Test Conditions Min. Typ. Max. Unit

HsVR Voltage on H/HVIN Input Pin 1 0 5 V

MinD Minimum Horizontal Input Pulses Duration Pin 1 0.7 µs

Mduty Maximum Horizontal Input Signal Duty Cycle Pin 1 25 %

VsVR Voltage on VSYNCIN Pin2 0 5 V

VSW Minimum Vertical Sync Pulse Width Pin 2 5 µs

VSmD Maximum Vertical SyncInput Duty Cycle Pin 2 15 %
VextM Maximum Vertical Sync Widthon TTLH/Vcomposite Pin 1 750

I

HLOCKOUT

Supply Voltage (Pin 29) 13.5 V

CC

Supply Voltage (Pin 32) 5.7 V

DD

Max Voltage on Pin 4

IN

Pin 9
Pin 5
Pins 6, 7, 8, 14, 15, 16, 20, 22
Pin 10, 18, 23, 24, 25, 26,28
Pins 1, 2, 3, 30, 31

ESD susceptibility Human Body Model,100pF Dischargethrough 1.5kΩ

EIAJ Norm,200pF Discharge through 0Ω

Storage Temperature -40, +150

stg

T

Junction Temperature +150

j

Operating Temperature 0, +70

oper

4.0

5.5

6.4

8.0

V

CC

V

DD

2

300

Junction-Ambient Thermal Resistance Max. 65

DD

=5V,T

amb

=25oC)

Sink and Source Current Pin3 250 µA

kV

o
o
o

o

C/W

V
V
V
V
V
V

V

C
C
C

9109N-03.TBL

9109N-04.TBL

s

µ

ElectricalCharacteristics(VDD=5V,T

amb

=25oC)

Symbol Parameter Test Conditions Min. Typ. Max. Unit

VINTH Horizontal and Vertical Input Logic Level

(Pins 1, 2)

Low Level
High Level 2.2

0.8 V

RIN Horizontal and Vertical Pull-Up Resistor Pins 1, 2 200 k

TfrOut Fall and Rise Time, Output CMOS Buffer Pin 3, C

VHlock Horizontal1st PLLLock OutputStatus (Pin 3) Locked, I

Unlocked, I

VoutT Extracted Vsync Integration Time (% of T

on H/V Composite (see Note 1)

Note 1 : THisthe horizontal period.

)

C0 = 820pF 26 35 %

H

= 20pF 200 ns

OUT

LOCKOUT

LOCKOUT

= -250µA

= +250µA 4.405

0.5 V

I2C READ/WRITE (see Note 2)
ElectricalCharacteristics(V

Symbol Parameter Test Conditions Min. Typ. Max. Unit

2

C PROCESSOR

I

Fscl Maximum Clock Frequency Pin 30 400 kHz

Tlow Low period of the SCLClock Pin30 1.3

Thigh High period of the SCL Clock Pin30 0.6

Vinth SDA and SCL Input Threshold Pins 30,31 2.2 V

VACK Acknowledge Output Voltage on SDA input with 3mA Pin 31 0.4 V

Note 2 : See also I2C Table Control and I2C Sub Address Control.

6/32

DD

=5V,T

amb

=25oC)

V

Ω

V

s

µ

s

µ

9109N-05.TBL

TDA9109/N

HORIZONTAL SECTION
OperatingConditions

Symbol Parameter Test Conditions Min. Typ. Max. Unit

VCO

R

0(Min.)

C

0(Min.)

F

(Max.)

OUTPUT SECTION

I12m Maximum Input Peak Current Pin 12 5 mA

HOI Horizontal Drive Output Maximum Current Pin 26, Sunk current 30 mA

Minimum Oscillator Resistor Pin 6 6 k
Minimum Oscillator Capacitor Pin 5 390 pF
Maximum Oscillator Frequency 150 kHz

Ω

ElectricalCharacteristics(VCC=12V,T

amb

=25oC)

Symbol Parameter Test Conditions Min. Typ. Max. Unit

SUPPLY AND REFERENCE VOLTAGES

V
V

V

REF-H

V

I

REF-H

I

REF-V

Supply Voltage Pin 29 10.8 12 13.2 V

CC

Supply Voltage Pin 32 4.5 5 5.5 V

DD

Supply Current Pin 29 50 mA

I

CC

Supply Current Pin 32 5 mA

I

DD

Horizontal Reference Voltage Pin 13, I = -2mA 7.4 8 8.6 V
Vertical Reference Voltage Pin 21, I = -2mA 7.4 8 8.6 V

REF-V

Max. Sourced Current on V
Max. Sourced Current on V

REF-H
REF-V

Pin 13 5 mA
Pin 21 5 mA

1st PLL SECTION

HpolT Delay Time for detecting polarity change

Pin 1 0.75 ms

(see Note 3)

V

VCO Control Voltage (Pin 7) V

VCO

Vcog VCO Gain (Pin 7) R

=8V f

REF-H

= 6.49kΩ,C0= 820pF,

0

dF/dV = 1/11R

0C0

0

fH(Max.)

1.3

6.2

17.1 kHz/V

Hph Horizontal Phase Adjustment(see Note 4) % of Horizontal Period ±10 %

Vbmin

Vbtyp

Vbmax

IPll1U

Minimum Value
Typical Value
Maximum Value

PLL1 Filter Current Charge PLL1is Unlocked

IPll1L

HorizontalPhaseSetting Value (Pin8) (seeNote4)

Free Running Frequency R0= 6.49kΩ,C0= 820pF,

f

0

df0/dT Free RunningFrequency Thermal Drift

Sub-Address 01

Byte x1111111
Byte x1000000
Byte x0000000

PLL1 is Locked

= 0.97/8R0C

f

0

2.8

3.4

4.0

±140

±1

22.8 kHz

0

-150 ppm/C

(No drift on external components) (see Note 5)

CR PLL1 Capture Range (see Note 6) R

FF Forced Frequency FF1 Byte 11xxxxxx

FF2 Byte 10xxxxxx

Notes: 3. This delay is mandatory to avoid a wrong detection of polarity change in the case of a composite sync.

4. See Figure 10 for explanation of referencephase.

5. These parameters are not tested on each unit. They are measured during our internal qualification.

6. This PLL capturerange may be obtained only if f0is adjusted (for instanceby adjusting R0) . If not, more marginmust be provided
between f

(Min.) and f0, to cope withthe components spread.

H

= 6.49kΩ,C0= 820pF,

0

+0.5kHz to 4.5f

from f

0

fH(Min.)

(Max.) 90

f

H

0

Sub-Address 02 2f0

3f0

25 kHz

V
V

V
V
V

µA

mA

kHz

9109N-05.TBL

7/32

TDA9109/N

HORIZONTAL SECTION (continued)
ElectricalCharacteristics(V

Symbol Parameter Test Conditions Min. Typ. Max. Unit

2nd PLL SECTION AND HORIZONTAL OUTPUT SECTION

FBth Flyback Input Threshold Voltage (Pin 12) 0.65 0.75 V

Hjit Horizontal Jitter At 31.4kHz 70 ppm
HD Horizontal Drive OutputDuty-Cycle Pin 26, see Note 7 48 %

XRAYth X-RAY Protection Input ThresholdVoltage Pin 25, see Note 8 8 V

Vphi2 Internal Clamping Levels on 2nd PLL

VSCinh Threshold Voltage to Stop H-Out,V-Out,

HDvd Horizontal Drive Output (low level) Pin 26, I

HORIZONTAL DYNAMIC FOCUS FUNCTION

HDFst HorizontalDynamic FocusSawtooth

HDFdis Horizontal Dynamic Focus Sawtooth

HDFDC Bottom DC Output Level R

TDHDF DC Output VoltageThermal Drift

HDFamp Horizontal Dynamic Focus Amplitude

HDFKeyst Horizontal Dynamic Focus Symmetry

VERTICAL DYNAMIC FOCUS FUNCTION (positiveparabola)

AMPVDF Vertical Dynamic Focus Parabola (added

VDFAMP Parabola Amplitude Function of VAMP

VHDFKeyt Parabola Asymetry Function of VPOS

Notes: 5. These parameters are not tested on each unit.They are measured during our internalqualification.

Loop Filter (Pin 4)

B-Out and Reset XRAY
when V

< VSCinh (see Note 8)

CC

MinimumLevel
MaximumLevel

Discharge Width

(see Note 5)

Min Byte xxx11111
Typ Byte xxx10000
Max Byte xxx00000

Min A/B Byte xxx11111
Typ Byte xxx10000
Max A/B Byte xxx00000

to horizontal)Amplitude with VAMP and
VPOS Typical

Min. Byte 000000
Typ. Byte 100000
Max. Byte 111111

(tracking between VAMP and VDF) with
VPOS Typ. (see Figure 1 andNote 9)

Control(tracking between VPOS andVDF)
with VAMP Max.

7. Duty Cycle is the ratio between the output transistor OFF time and the period. The power transistor is controlled OFF when the
output transistor is OFF.

8. See Figure 14.

9. S and C correction are inhibited so the output sawtooth has a linearshape.

CC

=12V,T

=25oC) (continued)

amb

Low Level
High Level

Pin 29 7.5 V

Pin 9, capacitor on
HFOCUSCAP and C0 = 820pF,

=20µs

T

H

Start by HFLY center 400 ns

LOAD

Sub-Address 03, Pin 10,

= 50kHz, Symmetry Typ. 1

f

H

Sub-Address 04, f
Typ. Amp

B/A
A/B
A/B

Sub-Address 0F

Sub-Address 05

Byte 10000000
Byte 11000000
Byte 11111111

Sub-Address 06

Byte x0000000
Byte x1111111

1.6

4.0

= 30mA 0.4 V

OUT

2

4.7

= 10kΩ, Pin10 2 V

200 ppm/C

1.5
3

= 50kHz,

H

223.5

1.0

3.5

0

0.5
1

0.6
1

1.5

0.52

0.52

V
V

V
V

V

PP

V

PP

V

PP

V

PP

V

PP

V

PP

V

PP

V

PP

V

PP

V

PP

V

PP

9109N-05.TBL

8/32

TDA9109/N

VERTICALSECTION
OperatingConditions

Symbol Parameter Test Conditions Min. Typ. Max. Unit

OUTPUTS SECTION

VEWM Maximum E/W OutputVoltage Pin 24 6.5 V
VEWm Minimum E/W Output Voltage Pin 24 1.8 V

R

LOAD

Minimum Load for less than 1% VerticalAmplitude Drift Pin 20 65 M

Ω

ElectricalCharacteristics(VCC=12V,T

amb

=25oC)

Symbol Parameter Test Conditions Min. Typ. Max. Unit

VERTICAL RAMP SECTION

VRB Voltage at Ramp Bottom Point V
VRT Voltage at Ramp Top Point (with Sync) V

= 8V, Pin 22 2 V

REF-V

= 8V, Pin 22 5 V

REF-V

VRTF Voltage at Ramp Top Point (without Sync) Pin 22 VRT-0.1 V
VSTD Vertical Sawtooth Discharge Time Pin 22, C
VFRF Vertical Free RunningFrequency

(see Note 10)

ASFR AUTO-SYNC Frequency (see Note 11) C

RAFD Ramp Amplitude Drift Versus Frequency at

Maximum Vertical Amplitude (see Note 5)

C

OSC (Pin 22)

Measured on Pin22

22

C

22

50Hz < f and f < 165Hz

Rlin Ramp Linearity on Pin 22 (see Note 10) 2.5V < V

VPOS Vertical Position Adjustment Voltage

(Pin 23 - VOUT mean value)

Sub Address 06

Byte x0000000
Byte x1000000
Byte x1111111 3.65

VOR Vertical Output Voltage

(peak-to-peak on Pin 23)

Sub Address 05

Byte x0000000
Byte x1000000
Byte x1111111 3.5

= 150nF 70 µs

22

= 150nF

100 Hz

= 150nF ±5% 50 165 Hz
= 150nF

and V27< 4.5V 0.5 %

27

200 ppm/Hz

3.2

3.5

3.8

2.25

3.75

3

3.3 V
V
V

2.5 V
V
V

VOI Vertical Output Maximum Current (Pin 23) ±5mA

dVS Max Vertical S-Correction Amplitude

Sub Address 07

(see Note 12)

x0xxxxxx inhibitsS-CORR
x1111111 givesmax S-CORR

Ccorr Vertical C-Corr Amplitude

x0xxxxxx inhibits C-CORR

Sub Address 08
∆V/V

at TV/4

∆V/V

PP

at 3TV/4

∆V/V

PP

@ TV/2

PP

Byte x1000000
Byte x1100000
Byte x1111111

Notes: 5. These parameters are not testedon each unit. They are measured during our internal qualification.

10. With Register 07 at Byte x0xxxxxx (S correctionis inhibited) and withRegister 08 at Bytex0xxxxxx (C correction is inhibited),the
sawtooth has a linear shape.

11. This is the frequencyrangefor which thevertical oscillatorwill automaticallysynchronize,using a single capacitorvalue on Pin22
and with a constant ramp amplitude.

12. TV is thevertical period.

-4

+4

-3
0
3

%
%

%
%
%

9109N-05.TBL

9/32

TDA9109/N

VERTICALSECTION(continued)
ElectricalCharacteristics(V

Symbol Parameter Test Conditions Min. Typ. Max. Unit

East/West (E/W) FUNCTION

EW

TDEW

EWpara Parabola Amplitude with Max. VAMP, Typ. VPOS,

EWtrack Parabola Amplitude Function of VAMP Control

KeyAdj Keystone Adjustment Capability with Typ. VPOS,

KeyTrack Intrinsic Keystone Function of VPOS Control

INTERNAL DYNAMIC HORIZONTAL PHASE CONTROL

SPBpara Side Pin Balance Parabola Amplitude(Figure 3)with

SPBtrack Side Pin Balance Parabola Amplitude function of

ParAdj Parallelogram Adjustment Capabilit y wit h

Partrack Intrinsic Parallelogram Function of VPOS Control

VERTICAL MOIRE

VMOIRE Vertical Moiré(measured on VOUT : Pin 23) Subaddress 0C

BREATHING COMPENSATION

BRRANG DC Breathing Control Range (see Note 15) V18 1 12 V

BRADj Vertical Output Variation versus DC Breathing

Notes: 10. With Register 07 at Byte x0xxxxxx (S correction is inhibited)and with Register 08at Byte x0xxxxxx (C correction is inhibited),the

DC Output Voltage with Typ. VPOS and Keystone

DC

inhibited
DC Output Voltage Thermal Drift See Note 13 100 ppm/C

DC

Keystone inhibited

(tracking between VAMPandE/W) with Typ. VPOS,
Typ. E/W Amplitude and Keystone inhibited(see
Note 10)

E/W inhibited and Max. Vertical Amplitude
(see Note 10 and Figure 4)

(tracking between VPOS and E/W) with Max. E/W
Amplitude and Max.VerticalAmplitude (see Note 13)

A/B Ratio
B/A Ratio

Max. VAMP, Typ.VPOSand Parallelograminhibited
(see Notes 10 & 14)

VAMP Control (tracking between VAMP and SPB)
with Max. SPB, Typ. VPOS and Parallelogram
inhibited (see Notes 10 & 14)

Max. VAMP, T yp. VPOS and Max. SPB
(see Notes 10 & 14)

(t racki ng between VPOS and DHP C) with
Max. VAMP, Max. SPB and Parallelogram inhibited
(see Notes 10 & 14)

A/B Ratio
B/A Ratio

Control (Pin 23)

sawtooth has a linear shape.

13. These parameters are not tested on each unit. They are measured during our internal qualification.
is the horizontal period.

14. T

H

15. When not used the DC breathingcontrol pin must be connected to 12V.

CC

=12V,T

=25oC) (continued)

amb

Pin 24, see Figure 2 2.5 V

Subaddress 0A

Byte 11111111
Byte 11000000
Byte 10000000

2.5

1.25
0

V
V
V

Subaddress 05

Byte 10000000
Byte 11000000
Byte 11111111

0.45

0.8

1.25

V
V
V

Subaddress 09

Byte 1x000000
Byte 1x111111

1
1

V
V

Subaddress 06

Byte x0000000
Byte x1111111

0.52

0.52

Subaddress 0D

Byte x1111111
Byte x1000000

+1.4

-1.4

%T
%T

Subaddress 05

Byte 10000000
Byte 11000000
Byte 11111111

0.5

0.9

1.4

%T
%T
%T

Subaddress 0E

Byte x1111111
Byte x1000000

+1.4

-1.4

%T
%T

Subaddress 06

Byte x0000000
Byte x1111111

0.52

0.52

Byte 01x11111 6 mV

≥ V

V

18

V18=4V

REF-V

0

-10

PP
PP
PP

PP
PP
PP

PP
PP

H
H

H
H
H

H
H

%
%

9109N-05.TBL

10/32